WO2024005496A1 - Carte de circuit imprimé et boîtier semi-conducteur la comprenant - Google Patents

Carte de circuit imprimé et boîtier semi-conducteur la comprenant Download PDF

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Publication number
WO2024005496A1
WO2024005496A1 PCT/KR2023/008907 KR2023008907W WO2024005496A1 WO 2024005496 A1 WO2024005496 A1 WO 2024005496A1 KR 2023008907 W KR2023008907 W KR 2023008907W WO 2024005496 A1 WO2024005496 A1 WO 2024005496A1
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Prior art keywords
pad
layer
protective layer
circuit pattern
recess
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PCT/KR2023/008907
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English (en)
Korean (ko)
Inventor
성대현
정인호
권순규
황정호
Original Assignee
엘지이노텍 주식회사
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Publication of WO2024005496A1 publication Critical patent/WO2024005496A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB

Definitions

  • the embodiment relates to a circuit board and a semiconductor package including the same.
  • a typical semiconductor package has a structure in which multiple chips are arranged.
  • the size of semiconductor packages is increasing due to recent higher specifications of products to which the semiconductor packages are applied and the adoption of a large number of chips such as HBM (High Bandwidth Memory).
  • the semiconductor package includes an interposer to connect multiple chips.
  • high performance may include conditions such as high-speed transmission of signals, integration of semiconductor packages, and high allowable current for signals that can be transmitted.
  • the pad may be a mounting pad connected to a chip or a bump pad connected to various substrates.
  • various substrates may include additional packages such as memory substrates, interposers connecting chips and circuit boards, and main boards of electronic devices to which the semiconductor packages are applied.
  • the degree of integration of the semiconductor package can be improved.
  • the contact area between the pad and the solder bump decreases in response to a decrease in the size of the pad, and accordingly, there is a problem in that the adhesion between the pad and the solder bump decreases.
  • physical reliability and electrical reliability problems occur in which the solder bump is separated from the pad.
  • the embodiment provides a circuit board with a new structure and a semiconductor package including the same.
  • the embodiment provides a circuit board with improved integration and a semiconductor package including the same.
  • the embodiment provides a circuit board capable of improving adhesion between a pad and a connection member and a semiconductor package including the same.
  • the embodiment provides a circuit board capable of increasing the contact area between a pad and a connection member and a semiconductor package including the same.
  • a circuit board includes an insulating layer; a circuit pattern layer disposed on the insulating layer and including a pad; and a protective layer disposed on the insulating layer and including an opening that vertically overlaps the pad, wherein the pad includes a recess concave from an upper surface of the pad toward a lower surface of the pad, and the protective layer a first portion including the opening, a first region vertically overlapping with the pad, and a second region excluding the first region, the pad including the recess; and a second part connected to the first part and not including the recess, wherein the first part of the pad includes a first sub-part vertically overlapping with the opening of the protective layer, and the protective layer and a second sub-portion vertically overlapping with a lower surface of the first region, wherein the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.
  • the upper surface of the second sub-portion of the pad is spaced apart from the lower surface of the first region of the protective layer, and the upper surface of the second portion of the pad is in direct contact with the lower surface of the first region of the protective layer. do.
  • the upper surface of the first portion of the pad has a concavo-convex shape.
  • the width of the second sub-portion of the pad satisfies a range of 2 to 50 times the width of the second portion of the pad.
  • the vertical distance from the lower surface of the first region of the protective layer to the upper surface of the first portion of the pad is 5% to 5% of the vertical distance from the lower surface of the first region of the protective layer to the lower surface of the pad.
  • the range of 55% is satisfied.
  • the pad includes a side surface, and at least a portion of an upper surface of the first portion of the pad is connected to the side surface of the pad.
  • the recess of the pad is connected to a side of the pad.
  • the pad includes a first side and a second side opposite the first side, and the width of the second sub-portion of the pad adjacent to the first side of the pad is equal to the second side of the pad. different from the width of the second sub-portion of the adjacent pad.
  • the recess includes: a first part provided on the upper surface of the pad; and a second part connected to the first part and provided on a side of the pad.
  • the side of the pad including the second part is spaced apart from the protective layer.
  • the opening of the protective layer includes a region whose width changes in the vertical direction.
  • the circuit pattern layer further includes a trace disposed on the insulating layer, and the upper surface of the trace is positioned higher than the upper surface of the first portion of the pad.
  • a semiconductor package includes an insulating layer; a pad disposed on the insulating layer and having a recess on its upper surface; a protective layer disposed on the insulating layer and including an opening that vertically overlaps the pad; and a connection member disposed to fill the opening of the protective layer and the recess of the pad, wherein a concavo-convex interface is provided between the connection member and the pad, and the protective layer includes the opening.
  • a first portion including a first region vertically overlapping with the pad and a second region excluding the first region, wherein the pad includes the recess; and a second part connected to the first part and not including the recess, wherein the first part of the pad includes a first sub-part vertically overlapping with the opening of the protective layer, and the protective layer and a second sub-portion vertically overlapping with a lower surface of the first region, wherein the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.
  • connection member is disposed within the recess and includes a portion in direct contact with a lower surface of the first region of the protective layer and an upper surface of the second sub-portion of the pad.
  • the recess is connected to at least a portion of a side surface of the pad, and the connecting member is disposed in the recess connected to the side surface of the pad and has a portion in direct contact with the inner surface of the second region of the protective layer.
  • the recess includes a first part provided on the upper surface of the pad, and a second part connected to the first part and provided on a side of the pad, and the connection member is connected to the first part of the recess. disposed on the part and the second part, respectively, a lower surface of the first region of the protective layer, an inner surface of the second region of the protective layer, an upper surface of the first portion of the pad, and a side surface of the pad, respectively. Includes contact parts.
  • the semiconductor package further includes a semiconductor element disposed on the connection member.
  • connection member further includes a substrate disposed on the connection member.
  • the substrate includes at least one of an interposer connected to a semiconductor device, a memory substrate on which a memory chip is placed, a main board of an electronic device, and a bridge substrate connecting a plurality of semiconductor devices.
  • the circuit board and semiconductor package of the embodiment can improve adhesion and bonding force between the pad and the connection member. Therefore, the embodiment can solve the problem of cracks occurring in the connection member, thereby improving the physical reliability and electrical reliability of the connection member.
  • the circuit board of the embodiment includes an insulating layer, a pad, and a protective layer.
  • the protective layer includes an opening that vertically overlaps at least a portion of the pad.
  • the protective layer includes a first area adjacent to the opening and vertically overlapping the pad, and a second area excluding the first area.
  • the pad has a recess.
  • the recess may be a concave portion concave from the upper surface of the pad toward the lower surface.
  • the pad includes an upper surface having a concavo-convex shape corresponding to the recess.
  • the pad includes a first part including the recess and a second part not including the recess.
  • the first portion of the pad includes a first sub-portion that vertically overlaps the opening of the protective layer, and a second sub-portion that vertically overlaps the first region of the protective layer.
  • a connection member is disposed on the pad.
  • the connection member is disposed to fill the recess of the pad.
  • the connecting member is disposed not only on the first sub-portion but also on the second sub-portion of the pad.
  • a portion of the connection member disposed in the second sub-portion may have a structure positioned between a lower surface of the first region of the protective layer and an upper surface of the second sub-portion of the pad.
  • the connecting member of the embodiment includes a first part disposed on the second sub-part.
  • the first part of the connection member may function as an anchor that improves adhesion and adhesion to the pad.
  • embodiments may improve the contact area between the pad and the connection member through the anchor structure of the connection member. Through this, the embodiment does not need to increase the size of the pad to improve the contact area. As a result, the embodiment can reduce the size of the pad and thereby improve circuit integration. Furthermore, embodiments can reduce the overall volume of the circuit board and semiconductor package.
  • the recess provided in the pad of the embodiment may include a plurality of parts.
  • the recess may include a first part provided on the top of the pad and a second part connected to the first part and provided on a side of the pad.
  • connection member may be disposed in the second part of the recess of the pad.
  • the connection member may be disposed within the first part of the recess and contact a lower surface of the first area of the protective layer and an upper surface of the pad.
  • the connection member may be disposed within the second part of the recess and contact the inner surface of the second region of the protective layer and the side surface of the pad.
  • 1A is a cross-sectional view showing a circuit board according to a comparative example.
  • FIG. 1B is a diagram showing a scanning electron microscope photograph of the actual product of FIG. 1A.
  • FIG. 2A is a diagram showing a semiconductor package according to a first embodiment.
  • Figure 2b is a diagram showing a semiconductor package according to a second embodiment.
  • Figure 2c is a diagram showing a semiconductor package according to a third embodiment.
  • FIG. 2D is a diagram showing a semiconductor package according to a fourth embodiment.
  • Figure 2e is a diagram showing a semiconductor package according to a fifth embodiment.
  • Figure 2f is a diagram showing a semiconductor package according to the sixth embodiment.
  • Figure 3 is a cross-sectional view showing a circuit board according to an embodiment.
  • Figure 4a is an enlarged cross-sectional view of a partial area of the circuit board according to the first embodiment.
  • Figure 4b is a top view of the circuit board of Figure 4a.
  • FIG. 4C is a cross-sectional view showing a state in which a connection member is disposed on the circuit board of FIG. 4A.
  • FIG. 5A is a diagram showing a first modified example of the circuit board of FIG. 4A.
  • FIG. 5B is a diagram showing a second modified example of the circuit board of FIG. 4A.
  • Figure 6 is a cross-sectional view showing the circuit board of the second embodiment.
  • Figure 7 is a cross-sectional view showing the circuit board of the third embodiment.
  • Figure 8a is a diagram showing a circuit board according to a fourth embodiment.
  • FIG. 8B is a cross-sectional view showing a state in which a connection member is disposed on the circuit board of FIG. 8A.
  • Figure 9 is a cross-sectional view showing a circuit board according to the fifth embodiment.
  • FIGS. 10A to 10D are cross-sectional views illustrating the method of manufacturing the circuit board shown in FIG. 3 in process order.
  • the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and as long as it is within the scope of the technical idea of the present invention, one or more of the components may be optionally used between the embodiments. It can be used by combining and replacing.
  • top or bottom refers not only to cases where two components are in direct contact with each other, but also to one component. This also includes cases where another component described above is formed or placed between two components.
  • top (above) or bottom (bottom) it may include not only the upward direction but also the downward direction based on one component.
  • FIG. 1A is a cross-sectional view showing a circuit board according to a comparative example
  • FIG. 1B is a scanning electron microscope photograph of the actual product of FIG. 1A.
  • the circuit board of the comparative example includes an insulating layer 10, a pad 20, a protective layer 30, and a connection member 40.
  • the pad 20 is disposed on the insulating layer 10.
  • the pad 20 is one of a first pad on which a chip is mounted and a second pad coupled to an external substrate.
  • a protective layer 30 including an opening that vertically overlaps the pad 20 is disposed on the insulating layer 10 .
  • the protective layer 30 includes an opening formed to correspond to the area where the connection member 40 is to be placed.
  • connection member 40 is disposed on the pad 20. Specifically, the connection member 40 is disposed on the pad 20 that overlaps perpendicularly to the opening of the protective layer 30.
  • the contact area between the connection member 40 of the comparative example and the pad 20 corresponds to the area of the opening of the protective layer 30.
  • the contact area between the connection member 40 of the comparative example and the pad 20 is determined by the area of the opening of the protective layer 30 vertically overlapping the pad 20.
  • the contact area between the connection member 40 and the pad 20 is equal to the area of the opening of the protective layer 30 vertically overlapping the pad 20.
  • the area of the opening of the protective layer 30 was increased to increase the contact area between the connection member 40 and the pad 20.
  • the size of the pad 20 must increase correspondingly.
  • the circuit integration decreases.
  • the size of the pad 20 is reduced to improve the circuit integration, and the opening area of the protective layer 30 is correspondingly reduced.
  • connection member 40 when the area of the opening of the protective layer 30 decreases, the contact area between the connection member 40 and the pad 20 decreases correspondingly. In addition, when the contact area between the connection member 40 and the pad 20 decreases, problems with the physical reliability or electrical reliability of the connection member 40 occur in the semiconductor package manufacturing environment or the semiconductor package use environment. do.
  • connection member 40 when the contact area between the connection member 40 and the pad 20 decreases, a crack occurs at the interface CR between the connection member 40 and the pad 20. There is a problem that arises. Additionally, the connection member 40 may be separated from the pad 20 due to the crack, which may cause problems with the physical and electrical reliability of the semiconductor package.
  • thermal stress occurs in a use environment or manufacturing environment of the semiconductor package, and the generated thermal stress may be concentrated at the interface between the connection member 40 and the pad 20. And, when the thermal stress is concentrated at the interface, the crack occurrence rate at the interface may increase.
  • the electronic device includes a main board (not shown).
  • the main board may be physically and/or electrically connected to various components.
  • the main board may be connected to the semiconductor package of the embodiment.
  • Various semiconductor devices may be mounted on the semiconductor package.
  • the semiconductor device may include active devices and/or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one chip.
  • Semiconductor devices may be logic chips, memory chips, etc.
  • the logic chip may be a central processor (CPU), a graphics processor (GPU), or the like.
  • the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.
  • AP application processor
  • the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.
  • volatile memory eg, DRAM
  • non-volatile memory eg, ROM
  • flash memory e.g., NAND
  • Chip Scale Package (CSP), Flip Chip-Chip Scale Package (FC-CSP), Flip Chip Ball Grid Array (FC-BGA), Package On Package (POP), and SIP ( System In Package), but is not limited to this.
  • CSP Chip Scale Package
  • FC-CSP Flip Chip-Chip Scale Package
  • FC-BGA Flip Chip Ball Grid Array
  • POP Package On Package
  • SIP System In Package
  • the electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, and network systems. ), computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive It may be, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.
  • the semiconductor package of the embodiment may have various package structures including a circuit board, which will be described later.
  • FIG. 2A is a diagram showing a semiconductor package according to a first embodiment.
  • the semiconductor package of the first embodiment includes a first substrate 100.
  • the first substrate 100 may refer to a package substrate.
  • the first substrate 100 may provide a space where at least one external substrate is coupled.
  • the first substrate 100 may provide a space where a main board included in an electronic device is coupled.
  • the first substrate 100 includes at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, a penetrating electrode penetrating the at least one insulating layer, the insulating layer, and a circuit. It may include a protective layer that protects the pattern layer.
  • the first substrate 100 may include a plurality of pads.
  • the plurality of pads may refer to a portion of the circuit pattern layer disposed on the outermost layer of the first substrate 100.
  • the pad may refer to a portion of the circuit pattern layer disposed on the uppermost side of the first substrate 100.
  • the pad may refer to a portion of the circuit pattern layer disposed on the lowermost side of the first substrate 100.
  • the protective layer may include an opening exposing the surface (eg, top or bottom) of the pad.
  • the semiconductor package may include a plurality of connection members.
  • the first substrate 100 may include a plurality of pads, and the plurality of connection members may be respectively disposed on the plurality of pads.
  • the first substrate 100 may include a plurality of first pads.
  • the semiconductor package may include first connection members 110 disposed on the plurality of first pads.
  • the first substrate 100 may include a plurality of second pads. Additionally, the semiconductor package may include second connection members 140 disposed on the plurality of second pads.
  • the first substrate 100 may include a plurality of third pads. Additionally, the semiconductor package may include a third connection member 160 disposed on the plurality of third pads.
  • the first pad may be disposed on the top surface of the first substrate 100. Additionally, the second and third pads may be disposed on the lower surface of the first substrate 100.
  • a semiconductor package may include a plurality of semiconductor devices.
  • a semiconductor package may include a first semiconductor device 120 disposed on the first connection member 110.
  • the first pad of the first substrate 100 may be divided into a plurality of groups.
  • the first connection member 110 may be disposed on each of the first pads of the plurality of groups.
  • the first semiconductor devices 120 may each be mounted on the first pads of the plurality of groups.
  • a plurality of first semiconductor devices 120 may be mounted on the top of the first substrate 100 at a certain distance from each other.
  • the first semiconductor device 120 may refer to a semiconductor device mounted on the top of the first substrate 100.
  • a plurality of first semiconductor devices spaced apart from each other may be disposed on the first substrate 100 .
  • the semiconductor package may include a second semiconductor device 140 disposed under the second connection member 140.
  • the second semiconductor device 140 may refer to a semiconductor device mounted on the lower side of the first substrate 100 among semiconductor devices included in a semiconductor package. Additionally, a plurality of second semiconductor devices may be disposed on the lower side of the first substrate 100 and spaced apart from each other.
  • At this time, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a logic chip.
  • at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an application processor chip.
  • at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an analog-to-digital converter or an application-specific IC (ASIC).
  • ASIC application-specific IC
  • at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a memory chip.
  • the memory chip may be a stack memory such as HBM.
  • memory chips may include volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, etc.
  • At least one of the first semiconductor device 120 and the second semiconductor device 140 is a drive IC chip, a diode chip, a power IC chip, a touch sensor IC chip, and a multi layer ceramic condenser (MLCC). It may include at least one of a chip, a BGA (Ball Grid Array) chip, and a chip capacitor.
  • MLCC multi layer ceramic condenser
  • the semiconductor package may include a third connection member 160.
  • the third connection member 160 may be disposed under the third pad of the first substrate 100.
  • the third connection member 160 may connect the first substrate 100 and the main board of the electronic device.
  • the third connection member 160 may have a larger diameter than the first connection member 110 and the second connection member 140.
  • the diameter of the third connection member 160 may satisfy a range of 10 to 200 times the diameter of at least one of the first connection member 110 and the second connection member 140.
  • the diameter of the third connection member 160 may be within a range of 20 to 180 times the diameter of at least one of the first connection member 110 and the second connection member 140.
  • the diameter of the third connection member 160 may be within a range of 40 to 150 times the diameter of at least one of the first connection member 110 and the second connection member 140. That is, the third connection member 160 is connected to the main board of the electronic device, and may have a larger diameter than the other connection members corresponding to the width of the pad portion of the main board. Additionally, the first connection member 110 and the second connection member 140 are connected to a semiconductor device and may have a diameter smaller than that of the third connection member 160 to correspond to a terminal of the semiconductor device.
  • the semiconductor package may include a molding layer.
  • the semiconductor package may include a first molding layer 130 disposed on the first substrate 100.
  • the first molding layer 130 may mold components disposed on the outermost layer of the first substrate 100.
  • the first molding layer 130 may mold the surface of the protective layer, the surface of the circuit pattern layer, and the surface of the insulating layer disposed on the uppermost side of the first substrate 100.
  • the first molding layer 130 may mold the first connection member 110 and the first semiconductor device 120 disposed on the first substrate 100.
  • the semiconductor package may further include an underfill (not shown) surrounding the first connection member 110 and the first semiconductor device 120. And when the semiconductor package includes the underfill, the first molding layer 130 may mold around the underfill.
  • the semiconductor package may include a second molding layer 170 disposed under the first substrate 100.
  • the second molding layer 170 may mold the surface of the protective layer, the surface of the circuit pattern layer, and the surface of the insulating layer disposed on the lowermost side of the first substrate 100. Additionally, the second molding layer 170 may mold the second connection member 140 and the second semiconductor device 140 disposed under the first substrate 100. Additionally, the second molding layer 170 may mold the third connection member 160.
  • the second molding layer 170 may expose at least a portion of the lower surface of the second semiconductor device 140.
  • the lower surface of the second molding layer 170 may be positioned no lower than the lower surface of the second semiconductor device 140.
  • the lower surface of the second molding layer 170 may be located on the same plane as the lower surface of the second semiconductor device 140.
  • the second molding layer 170 may be positioned no lower than the lower surface of the third connection member 160.
  • the lower surface of the second molding layer 170 may be located on the same plane as the lower surface of the third connection member 160, or may be located higher than the lower surface of the third connection member 160. Accordingly, the lower surface of the third connection member 160 may not be covered with the second molding layer 170. Additionally, at least a portion of the third connection member 160 may protrude downward from the second molding layer 170.
  • the first molding layer 130 and the second molding layer 170 may be EMC (Epoxy Mold Compound), but are not limited thereto.
  • the first molding layer 130 and the second molding layer 170 may have a low dielectric constant.
  • the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.2 to 10.
  • the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.5 to 8.
  • the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.8 to 5. Accordingly, in the embodiment, the first molding layer 130 and the second molding layer 170 have a low dielectric constant, so that the heat generated from the first semiconductor device 120 and the second semiconductor device 140 is reduced. Heat dissipation characteristics can be improved.
  • the semiconductor package of the first embodiment may have a double-sided molding structure as described above. That is, the semiconductor package of the first embodiment may have a structure in which at least one first semiconductor device 120 and at least one second semiconductor device 140 are mounted on the upper and lower sides of the first substrate 100, respectively.
  • Figure 2b is a diagram showing a semiconductor package according to a second embodiment.
  • the semiconductor package according to the second embodiment may be different from the semiconductor package according to the first embodiment of FIG. 2A in that it has a one-side molding structure.
  • the semiconductor package of the second embodiment includes a first substrate 100, a first connection member 110, a first semiconductor element 120, a first molding layer 130, and a third connection member 160. It can be included.
  • the semiconductor package of the second embodiment may have a structure in which semiconductor devices are mounted only on the top of the first substrate 100. Accordingly, the molding layer of the semiconductor package of the second embodiment may be disposed only on the top of the first substrate 100.
  • Figure 2c is a diagram showing a semiconductor package according to a third embodiment.
  • the semiconductor package according to the third embodiment is different from the semiconductor package according to the second embodiment of FIG. 2B in that it further includes an additional package.
  • the semiconductor package of the third embodiment may further include a fourth pad disposed on the first substrate 100. That is, a circuit pattern layer is disposed on the upper surface of the first substrate 100. Additionally, a portion of the circuit pattern layer may function as a first pad on which the first semiconductor device 120 is mounted, and another portion may function as a fourth pad.
  • the semiconductor package of the third embodiment may further include a fourth connection member 180 disposed on the fourth pad.
  • the upper surface of the fourth connection member 180 may not be covered with the first molding layer 130.
  • the semiconductor package of the third embodiment may include a second substrate 200 disposed on the fourth connection member 180.
  • the second substrate 200 may be a memory substrate, but is not limited thereto.
  • the semiconductor package of the third embodiment may include a third semiconductor device 210 mounted on the second substrate 200.
  • the third semiconductor device 210 may be a memory chip, but is not limited thereto.
  • the semiconductor package of the third embodiment may further include a connecting member 220 connecting the second substrate 200 and the third semiconductor device 210. That is, the semiconductor package of the third embodiment of FIG. 2C may have a package-on-package structure.
  • FIG. 2D is a diagram showing a semiconductor package according to a fourth embodiment.
  • the semiconductor package according to the fourth embodiment includes a first semiconductor device 120 including a plurality of logic chips and an additional component to the first substrate 100. 3 There is a difference in that the substrate 190 is disposed.
  • a plurality of logic chips may be disposed on the first substrate 100.
  • a plurality of logic chips of the same type may be disposed on the first substrate 100, or a plurality of logic chips of different types may be disposed on the first substrate 100.
  • a connecting member connecting the plurality of first semiconductor devices 120 may be disposed on the first substrate 100.
  • the connecting member may refer to the third substrate 190.
  • the third substrate 190 may be a bridge substrate.
  • the third substrate 190 may include a redistribution layer.
  • the third substrate 190 is disposed on the first substrate 100. Additionally, the third substrate 190 may electrically connect a plurality of first semiconductor devices 120 corresponding to a plurality of logic chips. At this time, although it is shown in the drawing that the third substrate 190 is embedded in the first substrate 100, it is not limited to this.
  • the third substrate 190 may be disposed on the first substrate 100.
  • the third substrate 190 may be a silicon bridge substrate.
  • the third substrate 190 may be an organic bridge containing an organic material.
  • Figure 2e is a diagram showing a semiconductor package according to a fifth embodiment.
  • the semiconductor package according to the fifth embodiment is different from the semiconductor package according to the previous embodiment in that the fourth substrate 300 is disposed between the first substrate and the first semiconductor device.
  • the semiconductor package according to the fifth embodiment may include a fourth substrate 300 disposed on the first substrate 100.
  • a first connection member 110 may be disposed on the first substrate 100 to connect the first substrate 100 and the fourth substrate 300.
  • the semiconductor package according to the fifth embodiment may include a fifth connection member 320 disposed on the fourth substrate 300. Additionally, the semiconductor package according to the fifth embodiment may include a semiconductor device 320 disposed on the fifth connection member 320.
  • the semiconductor device 320 may be one, or alternatively, it may be composed of a plurality of semiconductor devices 320 .
  • the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320.
  • the fourth substrate 300 may perform a function of connecting the first substrate 100 and the semiconductor device 320. Additionally, the fourth substrate 300 may function to connect a plurality of semiconductor devices 320.
  • the fourth substrate 300 may also be referred to as an interposer that connects the first substrate 100 and the semiconductor device 320.
  • the fourth substrate 300 may be an active interposer that functions as a semiconductor device.
  • the package of the fifth embodiment may have a vertical stacked structure on the first substrate 100 and a plurality of logic chips may be mounted. And among the logic chips, a first logic chip corresponding to the active interposer functions as the corresponding logic chip and performs a signal transmission function between the second logic chip disposed on top of the logic chip and the first substrate 100. You can.
  • the fourth substrate 300 may be a passive interposer.
  • the fourth substrate 300 may function as a signal relay between the semiconductor device 320 and the first substrate 100.
  • the number of terminals of the semiconductor device 320 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 320 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced.
  • the first substrate 100 is connected to the main board of the electronic device.
  • the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320.
  • the fourth substrate 300 may include a pad having a fine width and spacing corresponding to the terminal of the semiconductor device 320.
  • Figure 2f is a diagram showing a semiconductor package according to the sixth embodiment.
  • the semiconductor package according to the sixth embodiment is different from the semiconductor package according to the fifth embodiment in that the fifth substrate 330 is further disposed on the fourth substrate 300.
  • a plurality of semiconductor devices 320 may be disposed on the fourth substrate 300 while being spaced apart from each other in the horizontal direction. And the plurality of semiconductor devices 320 may be active devices of different types or the same type. By way of example, the plurality of semiconductor devices 320 may represent different types of AP chips. Additionally, one of the plurality of semiconductor devices 320 may be an AP chip, and the other may be a memory chip.
  • the semiconductor package of the sixth embodiment further includes a fifth substrate 330.
  • the fifth substrate 330 may be embedded in the fourth substrate 300, but is not limited thereto.
  • the fifth substrate 330 may be disposed on the fourth substrate 300 and perform a function of connecting the plurality of semiconductor devices 320.
  • the fifth substrate 330 may include a redistribution layer.
  • the fifth substrate 330 may be a bridge.
  • the fifth substrate 330 may include a silicon bridge.
  • the fifth substrate 330 may be an organic bridge containing an organic material.
  • each of the semiconductor packages of the first to sixth embodiments includes a connection member as described above.
  • connection member may be a member that functions to electrically connect a plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding.
  • connection member has the function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package can be understood as a part that is electrically connected, not solder or wire.
  • the wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu.
  • the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. .
  • the direct bonding method between metals may refer to a connection member connecting a substrate and a semiconductor device. At this time, the direct bonding connection member may refer to a metal layer formed between a plurality of components by recrystallization.
  • the circuit board described below may refer to any one of a plurality of substrates included in a previous semiconductor package.
  • the circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIGS. 2A to 2C. And, when the circuit board refers to the first board 100, the pad described below is the first pad on which the first connection member 110 is disposed, and the second pad on which the second connection member 140 is disposed. It may refer to either a pad or a third pad on which the third connection member 160 is disposed.
  • circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIG. 2D, and may alternatively refer to the second substrate 200, and alternatively, the third substrate 190. ) could also mean.
  • circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIG. 2E or, alternatively, may refer to the fourth substrate 300.
  • circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIG. 2F, and may alternatively refer to the fourth substrate 300, and alternatively, the fifth substrate 330. ) could mean.
  • the circuit board of the embodiment is characterized by the structure of the pad on which the connection member is disposed.
  • the pad on which the connection member is disposed may be a pad connected to a semiconductor device.
  • the pad on which the connection member is disposed may be a pad connected to the main board of the electronic device.
  • the pad on which the connection member is disposed may mean a pad connected to the fourth substrate 300.
  • the pad on which the connection member is disposed may mean a pad connected to the fifth substrate 330.
  • the pad of the circuit board described below may refer to one or more pads among the plurality of pads included in the first substrate 100.
  • the pad of the circuit board described below may refer to one or more pads among a plurality of pads included in the second substrate 200.
  • the pad of the circuit board described below may refer to one or more pads among the plurality of pads included in the third substrate 190.
  • the pad of the circuit board described below may refer to one or more pads among the plurality of pads included in the fourth substrate 300.
  • the pad of the circuit board described below may refer to one or more pads among the plurality of pads included in the fifth substrate 330.
  • circuit board of the embodiment is the first substrate 100 of the semiconductor package of the third embodiment shown in FIG. 2C.
  • the pad described below may refer to a first pad connected to the first semiconductor device 120, and the connection member described below may refer to the first semiconductor device 120 and the first semiconductor device 120. It may refer to the first connection member 110 connecting pads.
  • the pad described below may mean a second pad connected to the second substrate 200, and the connection member described below connects the second substrate 200 and the second pad. It may refer to the fourth connection member 180.
  • the pad described below may refer to a third pad connected to the main board of an electronic device, and the connection member described below may refer to a third pad connected between the main board and the third pad. It may mean absence (160).
  • Figure 3 is a cross-sectional view showing a circuit board according to an embodiment.
  • the circuit board 400 includes an insulating layer 410 .
  • the insulating layer 410 may have one or more layers. Preferably, the insulating layer 410 may have a multilayer structure.
  • the insulating layer 410 of the circuit board 400 is shown in the drawing as having a single-layer structure, it is not limited to this.
  • the insulating layer 410 may have a structure in which a plurality of layers are stacked in a vertical direction.
  • the circuit board 400 may have a multi-layer structure of at least two layers.
  • the insulating layer of the circuit board 400 consists of one layer.
  • the insulating layer 410 may be rigid or flexible.
  • the insulating layer 410 may include prepreg.
  • the insulating layer 410 may be a prepreg in which glass fibers are impregnated with resin.
  • the resin may be an epoxy resin, but is not limited thereto.
  • the insulating layer 410 may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass.
  • the insulating layer 410 includes reinforced or soft plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), and polycarbonate (PC). can do.
  • the insulating layer 410 may include sapphire.
  • the insulating layer 410 may include an optically isotropic film.
  • the insulating layer 410 may include Cyclic Olefin Copolymer (COC), Cyclic Olefin Polymer (COP), wide isotropic polycarbonate (PC), or wide isotropic polymethyl methacrylate (PMMA).
  • COC Cyclic Olefin Copolymer
  • COP Cyclic Olefin Polymer
  • PC wide isotropic polycarbonate
  • PMMA wide isotropic polymethyl methacrylate
  • the insulating layer 410 may be formed of a material containing an inorganic filler and an insulating resin.
  • the insulating layer 410 may have a structure in which an inorganic filler of silica or alumina is disposed on a thermosetting resin or thermoplastic resin.
  • the insulating layer 410 may be made of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imageable Dielectric Resin (PID), or BT.
  • the insulating layer 410 may include resin coated copper (RCC).
  • the insulating layer 410 may have a thickness ranging from 10 ⁇ m to 60 ⁇ m.
  • the thickness of each of the plurality of layers may be within the range of 10 ⁇ m to 60 ⁇ m.
  • the insulating layer 410 may have a thickness ranging from 15 ⁇ m to 55 ⁇ m. More preferably, the insulating layer 410 may satisfy a thickness ranging from 18 ⁇ m to 52 ⁇ m.
  • the thickness of the insulating layer 410 may refer to the vertical distance between a plurality of circuit pattern layers arranged adjacent to each other in the thickness direction.
  • the thickness of the insulating layer 410 may refer to the vertical distance between the first circuit pattern layer 420 and the second circuit pattern layer 430.
  • the thickness of the insulating layer 410 may mean the vertical distance between the lower surface of the first circuit pattern layer 420 and the upper surface of the second circuit pattern layer 430.
  • the thickness of the insulating layer 410 is less than 10 ⁇ m, the bending characteristics of the circuit board 400 may be reduced. For example, if the thickness of the insulating layer 410 is less than 10 ⁇ m, the first circuit pattern layer 420 and the second circuit pattern layer 430 disposed on the surface of the insulating layer 410 are stably protected. This may not be possible, and electrical reliability and/or physical reliability problems may occur accordingly. In addition, if the thickness of the insulating layer 410 is less than 10 ⁇ m, fairness in the process of forming the first circuit pattern layer 420 or the second circuit pattern layer 430 on the insulating layer 410 is low. may deteriorate.
  • the thickness of the insulating layer 410 exceeds 60 ⁇ m, the overall thickness of the circuit board 400 may increase, and thus the thickness of the semiconductor package may increase. Additionally, if the thickness of the insulating layer 410 exceeds 60 ⁇ m, it may be difficult to miniaturize the first circuit pattern layer and/or the second circuit pattern layer 430. For example, when the thickness of the insulating layer 410 exceeds 60 ⁇ m, the width of the first circuit pattern layer and/or the second circuit pattern layer 430 and the gap between adjacent patterns are 12 ⁇ m or less, 10 It may be difficult to form it to ⁇ m or less, 8 ⁇ m or less, or 6 ⁇ m or less. In addition, if it is difficult to miniaturize the first circuit pattern layer and/or the second circuit pattern layer 430, circuit integration may decrease, and the signal transmission distance may increase accordingly, resulting in increased signal transmission loss.
  • At least one of the plurality of insulating layers may include an insulating material different from at least the other one.
  • at least one insulating layer may be an insulating layer containing reinforcing fibers
  • at least another insulating layer may be an insulating layer that does not include reinforcing fibers. You can.
  • the insulating layer containing the reinforcing fibers may be a core layer.
  • the circuit board 400 may be a core board including a core layer, but is not limited thereto.
  • the thickness of the insulating layer 410 described above may mean the thickness of the insulating layer that does not include the reinforcing fibers.
  • the circuit board 400 includes a circuit pattern layer disposed on the insulating layer 410 .
  • the circuit board 400 includes a first circuit pattern layer 420 disposed on the upper surface of the insulating layer 410. Additionally, the circuit board 400 includes a second circuit pattern layer 430 disposed on the lower surface of the insulating layer 410.
  • the first circuit pattern layer 420 may be divided into a plurality of circuit patterns depending on location or function.
  • the first circuit pattern layer 420 may include at least one pad.
  • the first circuit pattern layer 420 may include a pad on which a semiconductor device is mounted.
  • the first circuit pattern layer 420 may include a pad to which an external substrate is coupled.
  • the first circuit pattern layer 420 may include a pad coupled to an interposer.
  • the first circuit pattern layer 420 may include a pad coupled to a bridge substrate.
  • the first circuit pattern layer 420 may include a pad coupled to a memory substrate including a memory chip.
  • the first circuit pattern layer 420 may refer to the first outermost circuit pattern layer of the circuit board 400. Specifically, when the circuit board 400 has a multi-layer structure including a plurality of insulating layers, the first circuit pattern layer 420 is disposed on the upper surface of the uppermost insulating layer among the plurality of insulating layers. It may refer to a circuit pattern layer.
  • the first circuit pattern layer 420 may include a plurality of metal layers.
  • the first circuit pattern layer 420 may include a first metal layer disposed on the upper surface of the insulating layer 410 and a second metal layer disposed on the first metal layer.
  • the first metal layer of the first circuit pattern layer 420 may be a seed layer for electroplating the second metal layer of the first circuit pattern layer 420.
  • the thickness of the first metal layer of the first circuit pattern layer 420 may be within the range of 0.2 ⁇ m to 3.0 ⁇ m.
  • the thickness of the first metal layer of the first circuit pattern layer 420 may be within the range of 0.3 ⁇ m to 2.8 ⁇ m. More preferably, the thickness of the first metal layer of the first circuit pattern layer 420 may be within the range of 0.5 ⁇ m to 2.5 ⁇ m.
  • the first metal layer of the first circuit pattern layer 420 may not function as a seed layer. If the thickness of the first metal layer of the first circuit pattern layer 420 is less than 0.2 ⁇ m, it may be difficult to form a first metal layer of uniform thickness on the upper surface of the insulating layer 410.
  • the process time for forming the first metal layer of the first circuit pattern layer 420 increases, and the yield decreases accordingly. can do. Additionally, when the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 ⁇ m, the etching time of the first metal layer in the forming process of the first circuit pattern layer 420 may increase. . Additionally, when the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 ⁇ m, the first circuit pattern layer 420 may be damaged when etching the first metal layer of the first circuit pattern layer 420. Deformation of the second metal layer may occur.
  • the deformation of the second metal layer of the first circuit pattern layer 420 is caused by etching the sides of the second metal layer at the time of etching the first metal layer, so that the width of the upper surface and the width of the lower surface of the second metal layer This may mean that the difference is increasing.
  • deformation of the second metal layer of the first circuit pattern layer 420 may mean that the vertical cross-sectional shape of the second metal layer changes from a square to a trapezoid.
  • the etching amount in the etching process of the first metal layer increases, and accordingly, the side of the first metal layer and the second metal layer
  • the depth of depressions (eg, undercuts) formed on the sides of the metal layer may increase.
  • the difference between the width of the first metal layer and the width of the second metal layer may increase.
  • electrical characteristics may deteriorate due to increased signal transmission loss.
  • dendrites may be formed by electromigration, thereby forming the first circuit pattern layer 420. Electrical and/or physical properties may be deteriorated.
  • the second metal layer of the first circuit pattern layer 420 may be an electrolytic plating layer obtained by electrolytically plating the first metal layer as a seed layer.
  • the second metal layer of the first circuit pattern layer 420 may be formed on the first metal layer to have a certain thickness.
  • the second metal layer of the first circuit pattern layer 420 may include the same metal as the first metal layer of the first circuit pattern layer 420, but is not limited thereto.
  • the first metal layer and the second metal layer of the first circuit pattern layer 420 may each include copper.
  • the thickness of the second metal layer of the first circuit pattern layer 420 may be greater than the thickness of the first metal layer of the first circuit pattern layer 420.
  • the thickness of the second metal layer of the first circuit pattern layer 420 may be within the range of 3.5 ⁇ m to 25 ⁇ m. Preferably, the thickness of the second metal layer of the first circuit pattern layer 420 may be within the range of 4.0 ⁇ m to 23 ⁇ m. More preferably, the thickness of the second metal layer of the first circuit pattern layer 420 may be within the range of 4.5 ⁇ m to 22 ⁇ m.
  • the etching of the second metal layer may also be performed during the etching process of the first metal layer. If the thickness of the second metal layer of the first circuit pattern layer 420 is less than 3.5 ⁇ m, the allowable current of the signal transmitted through the first circuit pattern layer decreases, and thus the electrical characteristics may deteriorate. If the thickness of the second metal layer of the first circuit pattern layer 420 exceeds 25 ⁇ m, it may be difficult to miniaturize the first circuit pattern layer 420. For example, if the thickness of the second metal layer of the first circuit pattern layer 420 exceeds 25 ⁇ m, the width and spacing of the patterns constituting the first circuit pattern layer 420 may not meet the requirements. You can. As a result, the degree of circuit integration may decrease or the volume of the circuit board and semiconductor package may increase.
  • the circuit board 400 of the embodiment may include a second circuit pattern layer 430 disposed on the lower surface of the insulating layer 410.
  • the second circuit pattern layer 430 may have a structure corresponding to the first circuit pattern layer 420.
  • the second circuit pattern layer 430 may include at least one pad.
  • the second circuit pattern layer 430 may include a pad on which a semiconductor device is mounted.
  • the second circuit pattern layer 430 may include a pad to which an external substrate is coupled.
  • the second circuit pattern layer 430 may include a pad to which the main board of the electronic device is coupled.
  • the second circuit pattern layer 430 may refer to the second outermost circuit pattern layer of the circuit board 400.
  • the second circuit pattern layer 430 is formed on the lower surface of the insulating layer disposed on the lowest side among the plurality of insulating layers. It may refer to an arranged circuit pattern layer.
  • Each of the first circuit pattern layer 420 and the second circuit pattern layer 430 may include a recess.
  • the first circuit pattern layer 420 may include a first recess 420-1.
  • the first circuit pattern layer 420 includes a pad and a trace connected to the pad. And, the pad of the first circuit pattern layer 420 has a first recess 420-1.
  • the first recess 420-1 may be formed concavely from the upper surface of the pad of the first circuit pattern layer 420 toward the lower surface of the pad of the first circuit pattern layer 420.
  • the first recess 420-1 may refer to a concave portion formed on the upper surface of the pad of the first circuit pattern layer 420.
  • the first recess 420-1 may have different depths along the horizontal direction.
  • the bottom surface of the first recess 420-1 may have a concave-convex shape.
  • the top surface of the pad of the first circuit pattern layer 420 may have a concave-convex shape corresponding to the bottom surface of the first recess 420-1.
  • the first recess 420-1 may be provided entirely on the upper surface of the pad of the first circuit pattern layer 420, or, alternatively, may be provided on a portion of the upper surface of the pad of the first circuit pattern layer 420. It can be provided in .
  • At least a portion of the first recess 420 - 1 vertically overlaps the first protective layer 450 disposed on the insulating layer 410 . Accordingly, at least a portion of the upper surface of the pad of the first circuit pattern layer 420 may vertically overlap the first protective layer 450 and may not contact the first protective layer 450 . For example, a crevice corresponding to the first recess 420-1 may be provided between the upper surface of the pad of the first circuit pattern layer 420 and the lower surface of the first protective layer 450. there is.
  • the first circuit pattern layer 420 includes patterns other than pads.
  • the pad of the first circuit pattern layer 420 is a pattern that vertically overlaps the opening 440-1 of the first protective layer 450, which will be described below, among the first circuit pattern layer 420. It can mean.
  • the pad of the first circuit pattern layer 420 includes a region of the first circuit pattern layer 420 that vertically overlaps the opening 440-1 of the first protective layer 450. It can mean a pattern.
  • the pattern other than the pad of the first circuit pattern layer 420 is a pattern that does not vertically overlap the opening 440-1 of the first protective layer 450 among the first circuit pattern layer 420. It can mean.
  • the upper surface of the pattern of the first circuit pattern layer 420 other than the pad may be entirely covered by the first protective layer 450.
  • patterns other than the pad of the first circuit pattern layer 420 may include traces.
  • the first recess may not be provided on the upper surface of the trace of the first circuit pattern layer 420. That is, the first recess 420-1 is a first circuit pattern layer exposed through the opening 440-1 of the first protective layer 450 when the first protective layer 450 is formed ( 420) can be formed by processing a part of it. At this time, the traces of the first circuit pattern layer 420 are not exposed through the opening 440-1 of the first protective layer 450. That is, the traces of the first circuit pattern layer 420 may be entirely covered with the first protective layer 450. Accordingly, the first recess may not be formed on the upper surface of the trace of the first circuit pattern layer 420.
  • the first circuit pattern layer 420 may include patterns having different heights. For example, at least a portion of the upper surface of the pad of the first circuit pattern layer 420 may be located lower than the upper surface of the trace of the first circuit pattern layer 420. For example, the top surface of the pad of the first circuit pattern layer 420 provided with the first recess 420-1 may be positioned lower than the top surface of the trace without the first recess 420-1. . For example, the top surface of the pad of the first circuit pattern layer 420 may be located lower than the top surface of the trace of the first circuit pattern layer 420 by the depth of the first recess 420-1. .
  • the second circuit pattern layer 430 may include a second recess 430-1.
  • the second circuit pattern layer 430 includes a pad and a trace connected to the pad. And, the pad of the second circuit pattern layer 430 has a second recess 430-1.
  • the second recess 430-1 may be formed to be convex from the lower surface of the pad of the second circuit pattern layer 430 toward the upper surface of the pad of the second circuit pattern layer 430.
  • the second recess 430-1 may refer to a convex portion formed on the lower surface of the pad of the second circuit pattern layer 430.
  • the second recess 430-1 may have different depths along the horizontal direction.
  • the bottom surface of the second recess 430-1 may have a concave-convex shape.
  • the bottom surface of the pad of the second circuit pattern layer 430 may have a concave-convex shape corresponding to the bottom surface of the second recess 430-1.
  • the second recess 430-1 may be provided entirely on the lower surface of the pad of the second circuit pattern layer 430, or, alternatively, may be provided on a portion of the lower surface of the pad of the second circuit pattern layer 430. It can be provided in .
  • At least a portion of the second recess 430-1 vertically overlaps the second protective layer 460 disposed under the insulating layer 410. Accordingly, at least a portion of the lower surface of the pad of the second circuit pattern layer 430 may vertically overlap the second protective layer 460 and may not contact the second protective layer 460 . For example, a crevice corresponding to the second recess 430-1 may be provided between the lower surface of the pad of the second circuit pattern layer 430 and the upper surface of the second protective layer 460. there is.
  • the second circuit pattern layer 430 includes patterns other than pads.
  • the pad of the second circuit pattern layer 430 is a pattern that vertically overlaps the opening 460-1 of the second protective layer 460, which will be described below. It can mean.
  • the pad of the second circuit pattern layer 430 includes a region of the second circuit pattern layer 430 that vertically overlaps the opening 460-1 of the second protective layer 460. It can mean a pattern.
  • the pattern other than the pad of the second circuit pattern layer 430 is a pattern that does not vertically overlap the opening 460-1 of the second protective layer 460 among the second circuit pattern layer 430. It can mean.
  • the lower surface of the pattern of the second circuit pattern layer 430 other than the pad may be entirely covered by the second protective layer 460.
  • patterns other than the pad of the second circuit pattern layer 430 may include traces.
  • the second recess may not be provided on the lower surface of the trace of the second circuit pattern layer 430. That is, the second recess 430-1 is a portion of the second circuit pattern layer 430 exposed through the opening of the second protective layer 460 when the second protective layer 460 is formed. It can be formed by processing. At this time, the traces of the second circuit pattern layer 430 are not exposed through the opening 460-1 of the second protective layer 460. That is, the traces of the second circuit pattern layer 430 may be entirely covered with the second protective layer 460. Accordingly, the second recess may not be formed on the lower surface of the trace of the second circuit pattern layer 430.
  • the second circuit pattern layer 430 may include patterns having different heights. For example, at least a portion of the lower surface of the pad of the second circuit pattern layer 430 may be positioned higher than the lower surface of the trace of the second circuit pattern layer 430. For example, the lower surface of the pad of the second circuit pattern layer 430 provided with the second recess 430-1 may be positioned higher than the lower surface of the trace not provided with the second recess. . For example, the lower surface of the pad of the second circuit pattern layer 430 may be located lower than the lower surface of the trace of the second circuit pattern layer 430 by the depth of the second recess 430-1. .
  • each pad of the first circuit pattern layer 420 and the second circuit pattern layer 430 will be described in more detail below.
  • the circuit board 400 of the embodiment may include a through electrode 440.
  • the penetrating electrode 440 may penetrate the insulating layer 410.
  • the through electrode 440 may penetrate the insulating layer 410 to electrically connect the first circuit pattern layer 420 and the second circuit pattern layer 430.
  • the through electrodes 440 can be spaced apart in the vertical direction and electrically connect adjacent circuit pattern layers.
  • the through electrode 440 can be formed by filling the inside of a through hole penetrating the insulating layer 410 with a conductive material.
  • the through hole may be formed by any one of mechanical, laser, and chemical processing.
  • methods such as milling, drilling, and routing can be used.
  • laser processing UV or CO 2 laser methods can be used.
  • chemical processing chemicals containing aminosilanes, ketones, etc. can be used.
  • the through electrode 440 includes a plurality of metal layers.
  • the through electrode 440 may include a first metal layer and a second metal layer corresponding to the first circuit pattern layer 420 and the second circuit pattern layer 430.
  • the first circuit pattern layer 420 and the second circuit pattern layer 430 of the embodiment include a first metal layer and a second metal layer as they are manufactured through the SAP process, but are not limited thereto.
  • the first circuit pattern layer 420 and the second circuit pattern layer 430 may be manufactured through the MSAP process. Accordingly, each of the first circuit pattern layer 420 and the second circuit pattern layer 430 may have a third metal layer additionally disposed between the first metal layer and the insulating layer.
  • the third metal layer may refer to a copper foil layer attached when the insulating layer is laminated, but is not limited thereto.
  • each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may include a conductive material.
  • the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 each include gold (Au), silver (Ag), platinum (Pt), titanium (Ti), It may include at least one metal material selected from tin (Sn), copper (Cu), and zinc (Zn).
  • each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.
  • Each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 is manufactured using an additive process or a subtractive process, which are typical circuit board manufacturing processes.
  • MSAP Modified Semi Additive Process
  • SAP Semi Additive Process
  • the circuit board 400 of the embodiment may include a protective layer.
  • the circuit board 400 may include a first protective layer 450 disposed on the insulating layer 410 .
  • the circuit board 400 may include a second protective layer 460 disposed under the insulating layer 410 .
  • the first protective layer 450 and the second protective layer 460 may be resist layers.
  • the first protective layer 450 and the second protective layer 460 may be a solder resist layer containing an organic polymer material.
  • the first protective layer 450 and the second protective layer 460 may include an epoxy acrylate-based resin.
  • the first protective layer 450 and the second protective layer 460 may include resin, hardener, pigment, solvent, filler, additive, acrylic monomer, etc.
  • each of the first protective layer 450 and the second protective layer 460 may be greater than the respective thickness of the first circuit pattern layer 420 and the second circuit pattern layer 430.
  • the total thickness may refer to the vertical distance between the lower surface and the upper surface of the first protective layer 450 and the second protective layer 460.
  • the total thickness of the first protective layer 450 may satisfy the range of 6.7 ⁇ m to 35.0 ⁇ m. Preferably, the total thickness of the first protective layer 450 may satisfy the range of 7.3 ⁇ m to 32 ⁇ m. More preferably, the total thickness of the first protective layer 450 may satisfy the range of 8.0 ⁇ m to 30 ⁇ m.
  • the thickness of the circuit board and the thickness of the semiconductor package may increase. Additionally, if the total thickness of the first protective layer 450 is less than 6.7 ⁇ m, the first circuit pattern layer may not be stably protected, which may reduce electrical or physical reliability.
  • the second protective layer 460 may have a thickness corresponding to the thickness of the first protective layer 450, but is not limited thereto.
  • the first protective layer 450 and the second protective layer 460 may each include an opening.
  • the first protective layer 450 may include a first opening 450-1.
  • the first opening 450-1 may vertically overlap at least a portion of the first circuit pattern layer 420.
  • the first opening 450-1 of the first protective layer 450 may expose at least a portion of the upper surface of the first circuit pattern layer 420.
  • the first protective layer 450 may include a first opening 450-1 that vertically overlaps the pad of the first circuit pattern layer 420. At this time, the width of the first opening 450-1 may be smaller than the width of the pad of the first circuit pattern layer 420.
  • At least a portion of the pad of the first circuit pattern layer 420 may vertically overlap the first opening 450-1 of the first protective layer 450, and the remaining portion may overlap the first protective layer 450. It may not overlap vertically with the first opening 450-1 of the layer 450.
  • At least a portion of the first protective layer 450 may vertically overlap the pad of the first circuit pattern layer 420 and may not contact the pad of the first circuit pattern layer 420 .
  • the first protective layer 450 may include an overlapping area that vertically overlaps the pad of the first circuit pattern layer 420.
  • at least a portion of the lower surface of the overlapping area of the first protective layer 450 may not be in contact with the pad of the first circuit pattern layer 420 .
  • at least a portion of the lower surface of the overlapping area of the first protective layer 450 is perpendicular to the first recess 420-1 formed on the upper surface of the pad of the first circuit pattern layer 420. May overlap. Accordingly, a crevice may be provided between at least a portion of the lower surface of the overlapping area of the first protective layer 450 and the upper surface of the pad of the first circuit pattern layer 420.
  • the second protective layer 460 may include a second opening 460-1.
  • the second opening 460-1 may vertically overlap at least a portion of the second circuit pattern layer 430.
  • the second opening 460-1 of the second protective layer 460 may expose at least a portion of the lower surface of the second circuit pattern layer 430.
  • the second protective layer 460 may include a second opening 460-1 that vertically overlaps the pad of the second circuit pattern layer 430.
  • the width of the second opening 460-1 may be smaller than the width of the pad of the second circuit pattern layer 430. Accordingly, at least a portion of the pad of the first circuit pattern layer 430 may vertically overlap the second opening 460-1 of the second protective layer 460, and the remaining portion may overlap the second protective layer 460. It may not vertically overlap the second opening 460-1 of layer 460.
  • At least a portion of the second protective layer 460 may vertically overlap the pad of the second circuit pattern layer 430 and may not contact the pad of the second circuit pattern layer 430 .
  • the second protective layer 460 may include an overlapping area that vertically overlaps the pad of the second circuit pattern layer 430.
  • at least a portion of the upper surface of the overlapping area of the second protective layer 460 may not be in contact with the pad of the second circuit pattern layer 430.
  • at least a portion of the upper surface of the overlapping area of the second protective layer 460 is perpendicular to the second recess 430-1 formed on the lower surface of the pad of the second circuit pattern layer 430. May overlap. Accordingly, a crevice may be provided between at least a portion of the upper surface of the overlapping area of the second protective layer 460 and the lower surface of the pad of the second circuit pattern layer 430.
  • FIG. 4A is an enlarged cross-sectional view of a portion of the circuit board according to the first embodiment
  • FIG. 4B is a plan view of the circuit board of FIG. 4A
  • FIG. 4C is a cross-sectional view showing a state in which a connection member is disposed on the circuit board of FIG. 4A. am.
  • a protective layer including a pad provided on the circuit board of the first embodiment, a recess formed in the pad, and an opening will be described in detail with reference to FIGS. 4A to 4C.
  • the pad described below may refer to the pad of the first circuit pattern layer 420, or, alternatively, may refer to the pad of the second circuit pattern layer 430. However, hereinafter, for convenience of explanation, the pad will be given the same reference number as that of the first circuit pattern layer 420.
  • the circuit board of the first embodiment includes an insulating layer 410 and a pad 420 disposed on the insulating layer 410.
  • the pad 420 may refer to a pad of one of the first circuit pattern layer and the second circuit pattern layer.
  • the pad 420 is disposed on the insulating layer 410.
  • the upper surface of the pad 420 may have a step.
  • the pad 420 may have a concave recess 420-1 formed from the upper surface of the pad 420 toward the lower surface of the pad 420.
  • the recess 420-1 may also be referred to as a concave depression extending from the upper surface of the pad 420 toward the lower surface.
  • the recess 420-1 may be provided in a portion of the upper surface of the pad 420.
  • the pad 420 may include a first part (P1) including the recess (420-1) and a second part (P2) that does not include the recess (420-1). there is.
  • the top surface of the first part (P1) of the pad 420 may be located lower than the top surface of the second part (P2) of the pad 420.
  • the top surface of the first part (P1) of the pad 420 is located lower than the top surface of the second part (P2) of the pad 420 by a depth corresponding to the recess 420-1. can do.
  • the pad 420 may have a first thickness T1.
  • the first thickness T1 may refer to the thickness of the portion with the greatest thickness among the entire area of the pad 420.
  • the first thickness T1 of the pad 420 may mean the thickness of the second portion P2 of the pad 420.
  • the first thickness T1 of the pad 420 may mean a value obtained by adding the thickness of the first portion P1 of the pad 420 and the depth of the recess 420-1. .
  • the first thickness T1 of the pad 420 may satisfy the range of 3.7 ⁇ m to 28 ⁇ m.
  • the first thickness T1 of the pad 420 may satisfy the range of 4.3 ⁇ m to 25.8 ⁇ m.
  • the first thickness T1 of the pad 420 may satisfy the range of 5 ⁇ m to 24.5 ⁇ m.
  • the first thickness T1 of the pad 420 may mean the sum of the thicknesses of the first metal layer and the second metal layer of the first circuit pattern layer 420 described above. Additionally, if the first thickness T1 of the pad 420 is outside the above range, the previously described problem may occur.
  • the recess 420-1 may be provided to have a certain depth on the upper surface of the first portion P1 of the pad 420.
  • the recess 420-1 may have a first depth T2.
  • the first depth T2 may mean the difference between the thickness of the first part P1 and the second part P2 of the pad 420.
  • the first portion (P1) of the pad 420 has a concave-convex shape. Accordingly, the first portion P1 of the pad 420 has different thicknesses or heights in the horizontal direction. Accordingly, the thickness of the first part (P1) of the pad 420 may mean the thickness of the area with the smallest thickness among the entire areas of the first part (P1). Alternatively, the thickness of the first part P1 of the pad 420 may mean the average thickness of the entire area of the first part P1.
  • the first depth T2 of the recess 420-1 and the difference value are calculated from the lower surface of the first region R1 of the protective layer 450 described below. It may mean the vertical separation distance to the upper surface of the part (P1).
  • the vertical separation distance may mean the maximum vertical separation distance.
  • the vertical separation distance refers to the vertical distance from the upper surface of the first portion (P1) of the pad 420, which has the lowest height, to the lower surface of the first region (R1) of the protective layer 450. can do.
  • the embodiment is not limited to this, and the vertical separation distance may mean the average separation distance.
  • the first depth T2 of the recess 420-1 has the same meaning as the thickness difference value and the vertical separation distance between the first part P1 and the second part P2 of the pad 420. You can have
  • the first depth T2 may range from 5% to 55% of the first thickness T1. Preferably, the first depth T2 may range from 7% to 52% of the first thickness T1. More preferably, the first depth T2 may range from 8% to 50% of the first thickness T1.
  • the effect that can be achieved by the recess 420-1 may be insufficient. That is, the recess 420-1 is provided to improve bonding and adhesion between the connection member 500 and the pad 420.
  • the first depth T2 is less than 5% of the first thickness T1
  • the effect of improving the bonding force or adhesion may be insufficient.
  • cracks may occur in the connection member 500 or physical and/or electrical reliability problems may occur in which the connection member 500 is separated from the pad 420.
  • the amount of the connection member 500 filled in the recess 420-1 may increase. Additionally, when the amount of the connection member 500 increases, the rigidity of the connection member 500 weakens, and cracks may occur accordingly. Additionally, if the first depth T2 exceeds 55% of the first thickness T1, the thickness deviation of the connection member 500 may increase, and connection reliability may decrease accordingly. In addition, if the first depth T2 exceeds 55% of the first thickness T1, the thickness deviation for each region of the pad 420 increases, which may cause electrical reliability problems. For example, when the thickness deviation for each region increases, the transmission loss of the signal flowing through the pad 420 may increase, or the allowable current of the signal that can be provided through the pad 420 may decrease.
  • the protective layer 450 may include multiple regions.
  • the protective layer 450 includes a first region R1 adjacent to the opening 450-1. That is, the protective layer 450 includes the opening 450-1 and a first region R1 that vertically overlaps the pad 420. Additionally, the protective layer 450 may include a second region excluding the first region R1.
  • the lower surface of the first region R1 of the protective layer 450 may be divided into a plurality of lower surfaces.
  • the lower surface of the first region R1 of the protective layer 450 has a first lower surface that does not contact the upper surface of the pad 420, and a second lower surface that contacts the upper surface of the pad 420. may include.
  • the lower surface of the first region (R1) of the protective layer 450 vertically overlaps the first portion (P1) of the pad 420 and is connected to the pad by the recess 420-1. It includes a first lower surface that is not in contact with the first portion (P1) of 420.
  • the lower surface of the first region (R1) of the protective layer 450 vertically overlaps the second portion (P2) of the pad 420 and contacts the upper surface of the second portion (P2). 2 Includes lower surface.
  • a crevice is formed by the recess 420-1 between the upper surface of the first portion P1 of the pad 420 and the first lower surface of the first region R1 of the protective layer 450. It can be. Additionally, the upper surface of the second portion P2 of the pad 420 and the second lower surface of the first region R1 of the protective layer 450 may directly contact each other.
  • the protective layer 450 may have a third thickness T3.
  • the third thickness T3 may mean the thickness of the first region R1 of the protective layer 450.
  • the third thickness T3 of the protective layer 450 may mean the vertical distance between the uppermost surface of the pad 420 and the uppermost surface of the protective layer 450.
  • the third thickness T3 of the protective layer 450 may satisfy the range of 1 ⁇ m to 25 ⁇ m.
  • the third thickness T3 of the protective layer 450 may satisfy the range of 3 ⁇ m to 18.5 ⁇ m. More preferably, the third thickness T3 of the protective layer 450 may satisfy the range of 3 ⁇ m to 16.5 ⁇ m.
  • the third thickness T3 of the protective layer 450 is outside the above range, problems such as the circuit pattern layer not being stably protected or the overall thickness of the circuit board increasing as described above may occur. there is.
  • the first part P1 of the pad 420 may be divided into a plurality of sub-parts. This can be distinguished based on a plurality of regions of the protective layer 450.
  • the upper surface of the first portion P1 of the pad 420 does not contact the protective layer 450.
  • the upper surface of the first portion (P1) of the pad 420 includes a first sub-portion (P1-1) that does not vertically overlap the first protective layer 450, and a first sub-portion (P1) -1) and may include a second sub-part (P1-2) that does not vertically overlap the first part (P1).
  • the first sub-portion (P1-1) of the pad 420 may vertically overlap the opening 450-1 provided in the protective layer 450. Additionally, the second sub-portion P1-2 of the pad 420 may vertically overlap the first region R1 of the protective layer 450 adjacent to the opening 450-1.
  • the pad 420 includes a first sub-portion (P1-1) of the first portion (P1) that vertically overlaps the opening 450-1 of the protective layer 460.
  • the pad 420 includes the second part P2 vertically overlapping the first region R1 of the protective layer 450 and the second sub-part P1 of the first part P1. 2) Includes.
  • the second sub-part (P1-2) and the second part (P2) of the first part (P1) vertically overlap the first region (R1) of the protective layer 450.
  • the second sub-part (P1-2) of the first part (P1) includes the recess (420-1). Accordingly, the upper surface of the second sub-part (P1-2) of the first part (P1) does not contact the lower surface of the first region (R1) of the protective layer 450. And the second portion P2 of the pad 420 does not have the recess 420-1. Accordingly, the upper surface of the second portion (P2) of the pad 420 directly contacts the lower surface of the first region (R1) of the protective layer 450.
  • the second sub-portion (P1-2) and the second portion (P2) of the pad 420 of the embodiment vertically overlap the first region (R1) of the protective layer 450. At this time, the second sub-portion (P1-2) of the pad is spaced apart from the protective layer 450, and the second portion (P2) of the pad 420 is in direct contact with the protective layer 450.
  • the width W1 of the second sub-part P1-2 of the pad 420 may be different from the width W2 of the second part P2 of the pad 420.
  • the width W1 of the second sub-part P1-2 of the pad 420 may be greater than the width W2 of the second part P2 of the pad 420.
  • the width W1 of the second sub-part P1-2 of the pad 420 satisfies the range of 2 to 50 times the width W2 of the second part P2 of the pad 420. You can.
  • the width W1 of the second sub-part P1-2 of the pad 420 is 3 to 48 times the width W2 of the second part P2 of the pad 420. range can be satisfied. More preferably, the width W1 of the second sub-part P1-2 of the pad 420 is 5 to 40 times the width W2 of the second part P2 of the pad 420. range can be satisfied.
  • the width W1 of the second sub-part P1-2 of the pad 420 is less than twice the width W2 of the second part P2 of the pad 420, the connection member 500 ), the effect of increasing the adhesion and adhesion strength is insufficient, and as a result, a reliability problem may occur in which the connection member 500 is separated from the pad 420.
  • the overall width of the pad 420 may increase. Additionally, when the overall width of the pad 420 increases, circuit integration may decrease and the overall volume of the circuit board may increase accordingly.
  • the second sub portion of the pad 420 may have corresponding widths in the entire area. and.
  • the second portion P2 of the pad 420 may also have widths corresponding to each other in the entire area.
  • having the corresponding width may mean that the width deviation in the entire area is 30% or less, 20% or less, 15% or less, 10% or less, 5% or less, or 2% or less.
  • having the corresponding width may mean that the difference between the maximum width and the minimum width in the entire area is 3 ⁇ m or less, 2 ⁇ m or less, 1 ⁇ m or less, or 0.5 ⁇ m or less.
  • the second sub portion of the pad 420 may vary in width over the entire area.
  • the width W1 of the second sub-part P1-2 and the width W2 of the second part P2 may mean the width at one side adjacent to each other based on the vertical cross-section.
  • the width W1 of the second sub-part P1-2 may mean the width of the area adjacent to the first side of the first sub-part P1-1 in the vertical cross-section
  • the width W2 of the second part P2 may mean the width of the area adjacent to the first side of the second sub-part P1-2.
  • connection member 500 is disposed in the recess 420-1 and the opening 450-1.
  • connection member 500 may be divided into a plurality of parts.
  • connection member 500 may include a first part disposed in the recess 420-1 of the pad 420.
  • the first part of the connection member 500 may be located between the first region (R1) of the first protective layer 450 and the first part (P1) of the pad 420.
  • the first part of the connection member 500 is a portion 450LS of the lower surface of the first region R1 of the protective layer 450 and the first portion P1 of the pad 420. It can be in contact with the upper surface.
  • connection member 500 may be located on the first part and include a part disposed in the opening 450-1 of the protective layer 450.
  • the second part of the connection member 500 may have a shape corresponding to the shape of the opening 450-1.
  • the second part of the connection member 500 may contact the inner surface 450IS of the first region R1 of the protective layer 450 constituting the opening 450-1.
  • the opening 450-1 may have the same width at the portion adjacent to the upper surface of the protective layer 450 and the same width at the portion adjacent to the lower surface of the protective layer 450.
  • the second part of the connection member 500 may have a pillar shape with the upper and lower surfaces having the same width.
  • the connection member 500 may include a third part disposed on the second part.
  • the third part of the connection member 500 may protrude above the top surface of the protective layer 450.
  • the upper surface of the third part of the connection member 500 may have a curved surface that is convex in the upward direction. At least a portion of the third part of the connection member 500 may be located on the first region R1 of the protective layer 450. Accordingly, the third part of the connection member 500 may contact the upper surface 450US of the first region R1 of the protective layer 450.
  • a concavo-convex interface may be provided between the connection member 500 and the pad 420.
  • the uneven-shaped interface may refer to the lower surface of the connection member 500.
  • the uneven-shaped interface may correspond to the upper surface of the first portion P1 of the pad 420.
  • the uneven-shaped interface may have a structure of the first sub-portion (P1-1) and the second sub-portion (P1-2) of the first portion (P1) of the pad 420.
  • the pad 420 is provided with a recess 420-1 as described above. Additionally, the provided recess 420-1 can be used to improve adhesion between the pad 420 and the connection member 500. Specifically, the embodiment uses the recess 420-1 to allow the connection member 500 to have an anchor structure and be coupled to the pad 420. Accordingly, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board.
  • the recess 420-1 is applied to all pads of the first circuit pattern layer 420 and the second circuit pattern layer 430, it is not limited thereto.
  • only some pads that are relatively small in size or have low adhesion to the connection member 500 may have an anchor structure including the recess 420-1.
  • the circuit board and semiconductor package of the embodiment can improve adhesion and bonding force between the pad and the connection member. Therefore, the embodiment can solve the problem of cracks occurring in the connection member, thereby improving the physical reliability and electrical reliability of the connection member.
  • the circuit board of the embodiment includes an insulating layer, a pad, and a protective layer.
  • the protective layer includes an opening that vertically overlaps at least a portion of the pad.
  • the protective layer includes a first area that includes the opening and vertically overlaps the pad, and a second area excluding the first area.
  • the pad has a recess.
  • the recess may be a concave portion concave from the upper surface of the pad toward the lower surface.
  • the pad includes an upper surface having a concavo-convex shape corresponding to the recess.
  • the pad includes a first part including the recess and a second part not including the recess.
  • the first portion of the pad includes a first sub-portion that vertically overlaps the opening of the protective layer, and a second sub-portion that vertically overlaps the first region of the protective layer.
  • a connection member is disposed on the pad.
  • the connection member is disposed to fill the recess of the pad.
  • the connecting member is disposed not only on the first sub-portion but also on the second sub-portion of the pad.
  • a portion of the connection member disposed in the second sub-portion may have a structure positioned between a lower surface of the first region of the protective layer and an upper surface of the second sub-portion of the pad.
  • the connecting member of the embodiment includes a first part disposed on the second sub-part.
  • the first part of the connection member may function as an anchor that improves adhesion and adhesion to the pad.
  • embodiments may improve the contact area between the pad and the connection member through the anchor structure of the connection member. Through this, the embodiment does not need to increase the size of the pad to improve the contact area. As a result, the embodiment can reduce the size of the pad and thereby improve circuit integration. Furthermore, embodiments can reduce the overall volume of the circuit board and semiconductor package.
  • FIG. 5A is a diagram showing a first modified example of the circuit board of FIG. 4A
  • FIG. 5B is a diagram showing a second modified example of the circuit board of FIG. 4A.
  • the protective layer 450 of the circuit board of the first embodiment included an opening 450-1 that vertically overlaps the pad 420.
  • the opening 450-1 had a shape with no change in width in the vertical direction.
  • the width of the adjacent opening 450-1 on the upper surface of the protective layer 450 was the same as the width of the adjacent opening 450-1 on the lower surface of the protective layer 450.
  • the opening of the protective layer 450 may have a width change in the vertical direction.
  • the opening of the protective layer 450 is formed through exposure and development processes.
  • the shape of the change in width of the opening may vary depending on the exposure conditions.
  • the exposure conditions include positive conditions and negative conditions.
  • the opening of the protective layer 450 may have different shapes depending on the exposure conditions.
  • the protective layer 450 may include an opening 450-1a.
  • the opening 450-1a of the protective layer 450 may include a region whose width varies.
  • the width of the opening 450-1a of the protective layer 450 may change from an area adjacent to the upper surface of the protective layer 450 to an area adjacent to the lower surface of the protective layer 450.
  • the width of the opening 450-1a of the protective layer 450 may decrease from an area adjacent to the upper surface of the protective layer 450 to an area adjacent to the lower surface of the protective layer 450.
  • the pad 420 in the first modified example includes a first part (P1) including a recess (420-1) and a second part (P2) that does not include the recess.
  • the first part (P1) of the pad 420 includes a first sub-part (P1-1) and a second sub-part (P1-2).
  • the width of the opening 450-1a changes vertically. Accordingly, in the first modified example, the first sub-portion (P1-1) and the second sub-portion (P1-2) of the pad 420 are divided into the first region (R1) of the protective layer 450. It can be done based on the lower surface of .
  • the second sub-part (P1-2) of the pad 420 includes the recess 420-1 and vertically overlaps the lower surface of the first region R1 of the protective layer 450. It can mean.
  • the first sub-portion (P1-1) of the pad 420 vertically overlaps the opening 450-1a of the protective layer 450 and forms a first region (R1) of the protective layer 450. It may mean a part that does not overlap vertically with the lower surface of .
  • the protective layer 450 may include an opening 450-1b.
  • the opening 450-1b of the protective layer 450 may include a region whose width varies.
  • the width of the opening 450-1b of the protective layer 450 may change from an area adjacent to the upper surface of the protective layer 450 to an area adjacent to the lower surface of the protective layer 450.
  • the width of the opening 450-1b of the protective layer 450 may increase from an area adjacent to the upper surface of the protective layer 450 to an area adjacent to the lower surface of the protective layer 450.
  • the pad 420 in the second modified example includes a first part (P1) including a recess (420-1) and a second part (P2) that does not include the recess.
  • the first part (P1) of the pad 420 includes a first sub-part (P1-1) and a second sub-part (P1-2).
  • the width of the opening 450-1a changes vertically. Accordingly, in the first modified example, the first sub-portion (P1-1) and the second sub-portion (P1-2) of the pad 420 are divided into the first region (R1) of the protective layer 450. It can be done based on the lower surface of .
  • the second sub-part (P1-2) of the pad 420 includes the recess 420-1 and vertically overlaps the lower surface of the first region R1 of the protective layer 450. It can mean.
  • the first sub-portion (P1-1) of the pad 420 vertically overlaps the opening 450-1b of the protective layer 450 and forms a first region (R1) of the protective layer 450. It may mean a part that does not overlap vertically with the lower surface of .
  • the circuit board described below is similar to the structure of the circuit board of the first embodiment, but there may be differences in the recesses provided in the pads.
  • Figure 6 is a cross-sectional view showing the circuit board of the second embodiment.
  • the circuit board of the second embodiment includes an insulating layer 410, a pad 420a disposed on the insulating layer 410, and an opening 450-1 disposed on the insulating layer 410. It includes a protective layer 450 containing.
  • the pad 420a includes a recess 420-1a.
  • the recess 420-1a may be provided entirely on the upper surface of the pad 420a.
  • the pad 420 of the circuit board of the first embodiment included a first part P1 having a recess and a second part not having the recess.
  • the pad 420a of the circuit board of the second embodiment may include only the first portion P1 including the recess 420-1a.
  • the pad 420a includes a first sub-part (P1-1) that vertically overlaps the opening 450-1 of the protective layer 450, and a first region (R1) of the protective layer 450. It may include a second sub-part (P1-2) that vertically overlaps the lower surface of .
  • the lower surface of the first region R1 of the protective layer 450 may vertically overlap the pad 420a and not contact the pad 420a.
  • the entire upper surface area of the pad 420a may not be in contact with the protective layer 450.
  • Figure 7 is a cross-sectional view showing the circuit board of the third embodiment.
  • the circuit board of the third embodiment includes an insulating layer 410, a pad 420b disposed on the insulating layer 410, and an opening 450-1 disposed on the insulating layer 410. It includes a protective layer 450 containing.
  • the pad 420b includes a recess 420-1b.
  • the recess 420-1b may be partially provided on the upper surface of the pad 420b.
  • the pad 420b includes a first part P1 having a recess 420-1b and a second part P2 not having the recess 420-1b. At this time, the second part (P2) of the pad (420b) may be located only on one side of the first part (P1) of the pad (420b).
  • it may include a first side of the pad 420b and a second side opposite to the first side.
  • the second portion P2 of the pad 420b may not exist in an area adjacent to the first side of the pad 420b.
  • the first portion P1 of the pad 420b may be located in an area adjacent to the first side of the pad 420b.
  • the first side of the pad 420b may be connected to the recess 420-1b.
  • the first side of the pad 420b may be directly connected to the second sub-part P1-2 of the first part P1 of the pad 420b. That is, the second part P2 may not be located between the first side of the pad 420b and the second sub-part P1-2.
  • the second portion P2 of the pad 420b may exist in an area adjacent to the second side opposite to the first side of the pad 420b.
  • a second part P2 connected to the second sub-part P1-2 of the pad 420b may exist in an area adjacent to the second side of the pad 420b.
  • the second side of the pad may not be connected to the recess 420-1b.
  • the second side of the pad 420b may not be directly connected to the first portion P1 of the pad 420b.
  • FIG. 8A is a diagram showing a circuit board according to a fourth embodiment
  • FIG. 8B is a cross-sectional view showing a state in which a connection member is disposed on the circuit board of FIG. 8A.
  • the circuit board of the fourth embodiment includes an insulating layer 410, a pad 420c disposed on the insulating layer 410, and an opening 450 disposed on the insulating layer 410. It includes a protective layer 450 containing -1).
  • the pad 420c includes a recess.
  • the recess may be provided entirely on the upper surface of the pad 420c.
  • the recess may include a first part 420-1c1 provided entirely on the upper surface of the pad 420c.
  • the pad 420c of the circuit board of the fourth embodiment includes the first part 420-1c1 of the recess, and accordingly, the pad 420c may include only the first part P1. Accordingly, the upper surface of the pad 420c may not entirely contact the lower surface of the first region R1 of the protective layer 450.
  • the recess may include a second part (420-1c2) connected to the first part (420-1c1).
  • the second part 420-1c2 may be connected to the first part 420-1c1 and may be formed on the side of the pad 420c.
  • the recess in the previous embodiment was provided only on the top surface of the pad.
  • the recess of the fourth embodiment includes a first part 420-1c1 provided on the upper surface of the pad 420c and a second part 420-1c2 provided on the side of the pad 420c.
  • the recess of the fourth embodiment may be provided on the entire side surface of the pad 420c.
  • the side surface of the pad 420c is not in contact with the first region R1 and the second region R2 of the protective layer 450, respectively, by the second part 420-1c2 of the recess. It may not be possible.
  • connection member 500 is disposed in the first part 420-1c1 and the second part 420-1c2 of the recess 420-1b, respectively.
  • the connection member 500 may contact the upper surface of the pad 420c and at least a portion of the side surface of the pad 420c.
  • connection member 500 may contact the upper surface of the pad 420c and the lower surface of the first region R1 of the protective layer 450. Additionally, the connection member 500 may contact the side surface of the pad 420c and the inner surface of the second region R2 of the protective layer 450. Through this, the embodiment can further improve the adhesion and bonding force between the pad and the connection member.
  • the recess provided in the pad of the embodiment may include a plurality of parts.
  • the recess may include a first part provided on the top of the pad and a second part connected to the first part and provided on a side of the pad.
  • connection member may be disposed in the second part of the recess of the pad.
  • the connection member may be disposed within the first part of the recess and contact a lower surface of the first area of the protective layer and an upper surface of the pad.
  • the connection member may be disposed within the second part of the recess and contact the inner surface of the second region of the protective layer and the side surface of the pad.
  • Figure 9 is a cross-sectional view showing a circuit board according to the fifth embodiment.
  • the circuit board of the fifth embodiment includes an insulating layer 410, a pad 420d disposed on the insulating layer 410, and an opening 450-1 disposed on the insulating layer 410. It includes a protective layer 450 containing.
  • the pad 420d includes a recess.
  • the recess may be partially provided on the upper surface of the pad 420d.
  • the recess may be provided on a side of the pad 420d.
  • the pad 420d has a first part 420-1d1 partially provided on the upper surface of the pad 420d, and is connected to the first part 420-1d1 and located on the side of the pad 420d. It may include a second part (420-1d2) provided.
  • the circuit board of the embodiment may be provided with a plurality of pads, and the plurality of pads may be provided with recesses having different shapes.
  • the circuit board of the embodiment may include recesses of different shapes described in at least two of the first to fifth embodiments.
  • the circuit board may include a first pad and a second pad.
  • the first pad of the circuit board may be provided with the recess 420-1 of the first embodiment, and the second pad may be provided with the recesses 420-1d1 and 420-1d2 of the fifth embodiment. there is.
  • FIGS. 10A to 10D are cross-sectional views illustrating the method of manufacturing the circuit board shown in FIG. 3 in process order.
  • an insulating layer 410 is prepared.
  • VH through hole
  • a through electrode 440 may be formed on the insulating layer 410 to fill the through hole (VH). Additionally, in the embodiment, a first circuit pattern layer 420 including at least one pad may be formed on the upper surface of the insulating layer 410. Additionally, in the embodiment, a second circuit pattern layer 430 including at least one pad may be formed on the lower surface of the insulating layer 420.
  • a first protective layer 450 may be formed on the upper surface of the insulating layer 410. Additionally, in the embodiment, a second protective layer 460 may be formed on the lower surface of the insulating layer 410.
  • the embodiment may expose and develop each of the first protective layer 450 and the second protective layer 460. Through this, the embodiment can form an opening 450-1 in the first protective layer 450 that vertically overlaps the pad of the first circuit pattern layer 420. Additionally, in the embodiment, an opening 460-1 that vertically overlaps the pad of the second circuit pattern layer 430 may be formed in the second protective layer 460.
  • a circuit board having the characteristics of the above-described invention when used in IT devices such as smartphones, server computers, TVs, or home appliances, functions such as signal transmission or power supply can be stably performed.
  • a circuit board having the characteristics of the present invention when a circuit board having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems such as leakage current or electrical short circuits between terminals. Alternatively, the problem of electrical opening of the terminal supplying the semiconductor chip can be solved. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved.
  • the circuit board having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.
  • a circuit board having the characteristics of the above-mentioned invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of signals transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside and prevent leakage.
  • the stability of the transport device can be further improved by solving the problem of electrical short-circuiting between currents or terminals, or the problem of electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Une carte de circuit imprimé selon un mode de réalisation comprend : une couche isolante ; une couche de circuit imprimé disposée sur la couche isolante et comprenant un plot ; et une couche protectrice disposée sur la couche isolante et comprenant une ouverture chevauchant verticalement le plot. Le plot comprend un renfoncement concave à partir de la surface supérieure du plot vers la surface inférieure du plot ; la couche protectrice comprend une première région qui inclut l'ouverture et chevauche verticalement le plot et une seconde région qui exclue la première région ; le plot comprend une première partie qui inclut le renfoncement et une seconde partie qui est connectée à la première partie et qui exclue le renfoncement ; la première partie du plot comprend une première sous-partie qui chevauche verticalement l'ouverture de la couche protectrice et une seconde sous-partie qui chevauche verticalement la surface inférieure de la première région de la couche protectrice ; et la largeur de la seconde sous-partie du plot est supérieure à la largeur de la seconde partie du plot.
PCT/KR2023/008907 2022-06-27 2023-06-27 Carte de circuit imprimé et boîtier semi-conducteur la comprenant WO2024005496A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2022-0078535 2022-06-27
KR1020220078535A KR20240001627A (ko) 2022-06-27 2022-06-27 회로 기판 및 이를 포함하는 반도체 패키지

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WO2024005496A1 true WO2024005496A1 (fr) 2024-01-04

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KR (1) KR20240001627A (fr)
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060035453A1 (en) * 2004-08-14 2006-02-16 Seung-Woo Kim Method of forming a solder ball on a board and the board
JP2009065114A (ja) * 2008-05-12 2009-03-26 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板
KR20100060402A (ko) * 2008-11-27 2010-06-07 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20150007986A (ko) * 2013-07-11 2015-01-21 신꼬오덴기 고교 가부시키가이샤 배선 기판 및 그 제조 방법
US20200161272A1 (en) * 2017-07-01 2020-05-21 International Business Machines Corporation Lead-free solder joining of electronic structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060035453A1 (en) * 2004-08-14 2006-02-16 Seung-Woo Kim Method of forming a solder ball on a board and the board
JP2009065114A (ja) * 2008-05-12 2009-03-26 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板
KR20100060402A (ko) * 2008-11-27 2010-06-07 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20150007986A (ko) * 2013-07-11 2015-01-21 신꼬오덴기 고교 가부시키가이샤 배선 기판 및 그 제조 방법
US20200161272A1 (en) * 2017-07-01 2020-05-21 International Business Machines Corporation Lead-free solder joining of electronic structures

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