WO2024027574A1 - 阳极短路横向绝缘栅双极晶体管模型及其建模方法 - Google Patents

阳极短路横向绝缘栅双极晶体管模型及其建模方法 Download PDF

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WO2024027574A1
WO2024027574A1 PCT/CN2023/109757 CN2023109757W WO2024027574A1 WO 2024027574 A1 WO2024027574 A1 WO 2024027574A1 CN 2023109757 W CN2023109757 W CN 2023109757W WO 2024027574 A1 WO2024027574 A1 WO 2024027574A1
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transistor
voltage
ligbt
insulated gate
gate bipolar
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PCT/CN2023/109757
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English (en)
French (fr)
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沈丽君
刘新新
韩晓婷
李新红
张心凤
杨洋
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无锡华润上华科技有限公司
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Publication of WO2024027574A1 publication Critical patent/WO2024027574A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to an anode short-circuited lateral insulated gate bipolar transistor model, and also relates to a modeling method of an anode short-circuited lateral insulated gate bipolar transistor model.
  • Lateral Insulated Gate Bipolar Transistor is widely used in integrated circuits (IC) due to its advantages such as reduced conduction voltage, high input impedance, high current density and easy integration. Among them, the anode is short-circuited
  • the lateral insulated gate bipolar transistor Shorted Anode LIGBT, SA-LIGBT
  • SA-LIGBT has the characteristics of high withstand voltage, high power density, fast switching speed, etc.
  • the anode short-circuited lateral insulated gate bipolar transistor has many effects that are difficult to characterize. These effects are difficult to characterize using conventional methods.
  • the Insulated Gate Bipolar Transistor (IGBT) model is difficult to accurately characterize. Therefore, there is a need for an anode short-circuited lateral insulated gate bipolar transistor model and its modeling method with high simulation accuracy.
  • An anode short-circuited lateral insulated gate bipolar transistor model suitable for an anode short-circuited lateral insulated gate bipolar transistor (SA-LIGBT) with an NPN transistor in the anode, and the SA-LIGBT includes a base region, a first body region and a second body region located in the base region, a first doping region of the first conductivity type and a second doping region of the second conductivity type located in the first body region, and a third doping region of the first conductivity type and a fourth doping region of the second conductivity type in the second body region, a field oxide layer located on the base region, and a gate; the first conductivity The first doping region of the type and the second doping region of the second conductivity type are drawn out as the collector of the SA-LIGBT; the anode short-circuit lateral insulated gate bipolar transistor model includes: NMOS transistor M1, NPN transistor QN1, PNP transistor QP1, and second controlled current source G2.
  • the source of the NMOS transistor M1 is connected to the emitter of the SA-LIGBT, and the gate of the NMOS transistor M1 is connected to the gate of the SA-LIGBT.
  • the emitter of the NPN transistor QN1 is connected to the drain of the NMOS transistor M1, and the collector of the NPN transistor QN1 is connected to the collector of the SA-LIGBT.
  • the emitter of the PNP transistor QP1 is connected to the collector of the SA-LIGBT and the base of the NPN transistor QN1.
  • the collector of tube QP1 is connected to the emitter of the SA-LIGBT, and the base of the PNP transistor QP1 is connected to the emitter of the NPN transistor QN1.
  • the second controlled current source G2 has one end connected to the emitter of the NPN transistor QN1 and the other end connected to the source of the NMOS transistor M1.
  • the current generated by the second controlled current source G2 is controlled by the The current of NMOS tube M1.
  • the above-mentioned anode short-circuited lateral insulated gate bipolar transistor model is suitable for IGBT devices with an NPN structure as the anode, which has a smaller tail current and no forward voltage foldback phenomenon.
  • the model matches the structure.
  • the second controlled current source G2 is set up to simulate the tail current, which can fit the switching characteristics of the device well and has high simulation accuracy.
  • the anode short-circuited lateral insulated gate bipolar transistor model also includes a first controlled current source G1.
  • One end of the first controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the emitter of the PNP transistor QP1.
  • One end is connected to the collector of the PNP transistor QP1, and the current generated by the first controlled current source G1 is controlled by the current of the PNP transistor QP1.
  • the first controlled current source G1 includes a first current source, a first capacitor and a first resistor connected in parallel, the first capacitor generates a first capacitance based on the current of the PNP transistor QP1 terminal voltage, thereby forming a controlled current source related to the terminal voltage of the capacitor.
  • the second controlled current source G2 includes a second current source, a second capacitor and a second resistor connected in parallel, and the second capacitor generates a second capacitance based on the current of the NMOS transistor M1 terminal voltage, thereby forming a controlled current source related to the terminal voltage of the capacitor, and the second resistor is used to adjust the size of the tail current by selecting an appropriate resistance value.
  • the anode short-circuited lateral insulated gate bipolar transistor model further includes: a drain resistor Rd1, one end connected to the drain of the NMOS transistor M1, and the other end connected to the second controlled current source G2 and The common end of the emitter of the NPN transistor QN1; the base resistor Rb1, one end is connected to the base of the PNP transistor QP1, and the other end is connected to the second controlled current source G2 and the emitter of the NPN transistor QN1 Common terminal; external capacitor C0, one end is connected to the gate of the NMOS transistor M1, and the other end is connected to the collector of the NPN transistor QN1.
  • the NPN transistor QN1 and the PNP transistor QP1 are characterized using the G-P BJT model
  • the NMOS transistor M1 is characterized using the BSIM3 model or the BSIM4 model
  • the model used by the NMOS transistor M1 separates the internal drain terminal Capacitance parameter is off.
  • the drain resistor Rd1 and the base resistor Rb1 are voltage-controlled resistors
  • the drain terminal resistance Rd1 represents the drain terminal drift region resistance of the NMOS transistor M1;
  • the base resistor Rb1 represents the modulation resistance in the base region of the PNP transistor QP1.
  • Rd_tfac (1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25));
  • V d,e represents the voltage between the drain d of the NMOS transistor M1 and the emitter e of the NPN transistor QN1.
  • Rcdw1 represents represents the resistance value of the drain terminal resistor Rd1 when the voltage is zero
  • Crd is the first voltage coefficient of the drain terminal resistor Rd1
  • Erdd is the power exponent coefficient of the first voltage of the drain terminal resistor Rd1
  • Prwge1 is The second voltage coefficient of the drain resistance Rd1
  • W is the channel width of the SA-LIGBT
  • wrd1 is the correction parameter of the channel width W
  • V g,e represents the gate and emitter of the SA-LIGBT voltage between;
  • TEMP is the system temperature
  • Td1 is the temperature coefficient of the first-order exponential term of the drain terminal resistance Rd1
  • Td2 is the temperature coefficient of the second-order exponential term of the drain terminal resistance Rd1.
  • Rb_tfac (1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25));
  • V b1,e represents the voltage between the base b 1 of the PNP transistor QP1 and the emitter e of the NPN transistor QN1
  • Rbw1 represents the resistance value of the base resistor Rb1 when the voltage is zero
  • Prwge2 is the first voltage coefficient of the base resistor Rb1 when the voltage is zero
  • V g,e represents the voltage between the gate and the emitter of the SA-LIGBT
  • Erge2 is the power exponential term coefficient of the first voltage of the base resistor Rb1
  • Prwbd2 is the second voltage coefficient of the base resistor Rb1
  • Erbd is the power exponent coefficient of the second voltage of the base resistor Rb1
  • wrd2 is the correction parameter of the channel width W
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the drain resistor Rd1 is a voltage-controlled resistor.
  • the base resistor Rb1 is a voltage-controlled resistor.
  • the anode short-circuited lateral insulated gate bipolar transistor model also includes a base resistor Rp. One end of the base resistor Rp is connected to the base of the NPN transistor QN1, and the other end is connected to the PNP transistor. The emitter of QP1.
  • a modeling method for an anode short-circuited lateral insulated gate bipolar transistor model including: step A, establishing the anode short-circuited lateral insulated gate bipolar transistor model as claimed in claim 1, and setting device parameters of the SA-LIGBT; Step B, adjust the capacitance-voltage parameters of the NMOS tube M1 to fit the capacitance-voltage curve; Step C, adjust the threshold voltage parameters of the NMOS tube M1 to fit the turn-on voltage of the SA-LIGBT; Step D, Adjust the device parameters of the NPN transistor QN1 to fit the transfer characteristic curve of the minimum V CE of the SA-LIGBT when the SA-LIGBT is turned on; Step E, adjust the linear region parameters of the NMOS transistor M1 and the PNP The device parameters of the transistor QP1 are used to fit the transfer characteristic curve when the V CE of the SA-LIGBT is in the first voltage value interval; step F, adjust the saturation zone parameters of the NMOS transistor M1 and the device parameters of the PNP transistor QP1
  • the anode short-circuited lateral insulated gate bipolar transistor model further includes: a drain resistor Rd1, One end is connected to the drain of the NMOS transistor M1, and the other end is connected to the common end of the second controlled current source G2 and the emitter of the NPN transistor QN1; the base resistor Rb1 is connected to the base of the PNP transistor QP1.
  • the step B includes: adjusting the capacitance-voltage parameters of the NMOS transistor M1 and The parameters of the external capacitor C0 are used to fit the capacitance-voltage curve;
  • the step D includes: adjusting the device parameters of the NPN transistor QN1 and the resistance value of the base resistor Rp to fit the transfer of the minimum V CE Characteristic curve;
  • the step E includes: adjusting the linear region parameters of the NMOS transistor M1, the device parameters of the PNP transistor QP1 and the parameters of the base resistor Rb1 to fit the V CE in the first voltage value interval The transfer characteristic curve
  • the anode short-circuited lateral insulated gate bipolar transistor model also includes a first controlled current source G1.
  • One end of the first controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the emitter of the PNP transistor QP1.
  • One end is connected to the collector of the PNP transistor QP1, and the current generated by the first controlled current source G1 is controlled by the current of the PNP transistor QP1; after the step F1, a step F2 is also included: adjusting the first The parameters of the current source G1 are controlled to fit the self-heating effect of the SA-LIGBT.
  • step G is only executed when the fitting accuracy of steps B, step C, step D, step F, step F1, and step F2 all meet the requirements, Otherwise, return to step B; after step G and before step H, if the fitting accuracy of the temperature characteristic curve does not meet the requirements, return to step G.
  • Figure 1 is a schematic cross-sectional view of an SA-LIGBT with an NPN transistor on the anode according to an embodiment of the present application
  • Figure 2 is an equivalent circuit schematic diagram of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment of the present application, and the figure corresponds to the device structure corresponding to the anode;
  • Figure 3a is an equivalent circuit of the first controlled current source G1 in an embodiment of the present application.
  • Figure 3b is an equivalent circuit of the second controlled current source G2 in an embodiment of the present application.
  • Figure 4 is a flow chart of a modeling method of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment of the present application
  • Figure 5 is a flow chart of a modeling method of an anode short-circuited lateral insulated gate bipolar transistor model in another embodiment of the present application
  • Figure 6 shows the current of an insulated gate bipolar transistor device using a model of an embodiment of the present application at normal temperature (25 degrees Celsius). -Voltage characteristic fitting curve;
  • Figure 7 is a current-voltage characteristic fitting curve of an insulated gate bipolar transistor device using a model of an embodiment of the present application at low temperature (minus 40 degrees Celsius);
  • Figure 8 is a current-voltage characteristic fitting curve of an insulated gate bipolar transistor device using a model according to an embodiment of the present application under high temperature (180 degrees Celsius);
  • Figure 9 shows the transient characteristics test circuit of this application as well as the test data and model simulation fitting curve.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.
  • P+ type simply represents P type with heavy doping concentration
  • P type represents medium doping concentration
  • P-type with doping concentration P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type N-type with medium doping concentration
  • N-type represents lightly doped concentration.
  • IGBT Insulated Gate Bipolar Transistor
  • an IGBT with an NPN transistor on the anode also called the collector
  • This application proposes an anode short-circuited lateral insulated gate bipolar transistor model, which is suitable for a semi-anode structure with an anode short circuit.
  • IGBT that is, it is suitable for SA-LIGBT with NPN transistor on the anode.
  • the SA-LIGBT includes a base region 110, a first body region 132 located in the base region 110, a second body region 134 located in the base region 110, and a first conductivity type located in the first body region 132.
  • the first doping region 142 of the first conductivity type and the second doping region 148 of the second conductivity type are led out as collectors of the SA-LIGBT.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • Figure 2 is an equivalent circuit schematic diagram of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment of the present application.
  • the anode short-circuited lateral insulated gate bipolar transistor model includes: NMOS transistor M1, NPN transistor QN1, PNP transistor QP1, and second controlled current source G2.
  • the source s of the NMOS transistor M1 is connected to the emitter E of the SA-LIGBT, and the gate g of the NMOS transistor M1 is connected to the gate G of the SA-LIGBT.
  • the emitter e of the NPN transistor QN1 is connected to the drain d of the NMOS transistor M1, and the collector c of the NPN transistor QN1 is connected to the collector C of the SA-LIGBT.
  • the emitter e 1 of the PNP transistor QP1 is connected to the collector C of the SA-LIGBT and the NPN transistor QN1
  • the base b of the PNP transistor QP1 is connected to the emitter E of the SA-LIGBT, and the base b 1 of the PNP transistor QP1 is connected to the emitter e of the NPN transistor QN1.
  • the second controlled current source G2 has one end connected to the emitter e of the NPN transistor QN1 and the other end connected to the source s of the NMOS transistor M1.
  • the current generated by the second controlled current source G2 is controlled by the The current of NMOS tube M1.
  • the applicable SA-LIGBT device anode has an NPN structure, which has a smaller tail current and no forward voltage foldback phenomenon.
  • the model matches the structure.
  • the second controlled current source G2 is set up to simulate the tail current, which can fit the switching characteristics of the device well and has high simulation accuracy.
  • FIG. 2 is an equivalent circuit schematic diagram of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment of the present application, and the figure shows the device structure corresponding to the anode.
  • the anode short-circuited lateral insulated gate bipolar transistor model further includes a first controlled current source G1.
  • One end of the first controlled current source G1 is connected to the emitter of the PNP transistor QP1, and the other end is connected to the collector of the PNP transistor QP1.
  • the current generated by the first controlled current source G1 is controlled by the current of the PNP transistor QP1.
  • the first controlled current source G1 is used to characterize the self-heating effect of SA-LIGBT, so the model can fit the static characteristics of the device well.
  • the equivalent circuit of the first controlled current source G1 can be seen in Figure 3a, which includes a first current source g1, a first capacitor C1 and a first resistor R1 connected in parallel with each other.
  • the first capacitor C1 generates a first capacitor terminal voltage based on the current of the PNP transistor QP1, thereby generating a first controlled current source G1 related to the first capacitor terminal voltage, that is, the first controlled current source is generated through an RC circuit.
  • the equivalent circuit of the second controlled current source G2 can be seen in Figure 3b.
  • the second controlled current source G2 includes a second current source g2, a second capacitor C2 and a second resistor R2 connected in parallel with each other.
  • the second capacitor generates a second capacitor terminal voltage based on the current of the NMOS transistor M1, so that A second controlled current source G2 related to the second capacitor terminal voltage is formed, and the influence of the subcircuit when the device is turned on and SA- when the device is turned off can be controlled by adjusting the resistance of the second resistor R in the subcircuit.
  • the size of the LIGBT tail current is provided.
  • the NPN transistor QN1 and the PNP transistor QP1 are characterized using the Gummel-poon (G-P) BJT model, and the NMOS transistor M1 is characterized using the BSIM3 model or BSIM4 model.
  • G-P Gummel-poon
  • the anode short-circuited lateral insulated gate bipolar transistor model also includes a drain resistor Rd1, a base resistor Rb1 and an external capacitor C0.
  • One end of the drain resistor Rd1 is connected to the drain d of the NMOS transistor M1, and the other end is connected to the common end of the second controlled current source G2 and the emitter e of the NPN transistor QN1.
  • One end of the base resistor Rb1 is connected to the base b 1 of the PNP transistor QP1, and the other end is connected to the common end of the second controlled current source G2 and the emitter e of the NPN transistor QN1.
  • One end of the external capacitor C0 is connected to the gate g of the NMOS transistor M1, and the other end is connected to the collector c of the NPN transistor QN1.
  • the capacitive characteristics of NPN transistor QN1 and PNP transistor QP1 are characterized by the GP BJT model. Due to the existence of the drain terminal resistance Rd1, the expression for calculating the drain terminal capacitance in the MOS model cannot correctly correspond to the terminal voltage, so that the capacitance of the drain terminal cannot be reasonably represented. Therefore, the MOS model (the model used by the NMOS tube M1) is closed in the model of the embodiment. The capacitance parameter of the internal drain terminal is represented by the external capacitance C0. The capacitance characteristics of the source end of the NMOS transistor M1 are still characterized by corresponding parameters in the MOS model.
  • the anode short-circuited lateral insulated gate bipolar transistor model also includes a base resistor Rp.
  • One end of the base resistor Rp is connected to the base b of the NPN transistor QN1, and the other end is connected to the emitter e 1 of the PNP transistor QP1.
  • the drain resistor Rd1 and the base resistor Rb1 are voltage-controlled resistors.
  • the drain terminal resistance Rd1 represents the resistance of the drain terminal drift region of the NMOS transistor M1.
  • the base resistor Rb1 represents the modulation resistance in the base area of the PNP transistor QP1.
  • V d, e represents the voltage between the two nodes of the drain d of the NMOS transistor M1 and the emitter e of the NPN transistor QN1 (that is, both ends of the drain resistance Rd1)
  • Rcdw1 represents the drain resistance Rd1 when the voltage is zero.
  • Resistance value Crd is the first voltage coefficient of the drain resistance Rd1
  • Erdd is the power exponential coefficient of the first voltage of the drain resistance Rd1
  • Prwge1 is the second voltage coefficient of the drain resistance Rd1
  • W is the channel of SA-LIGBT Track width
  • wrd1 is the correction parameter of W
  • V g,e represents the voltage between the gate and emitter of SA-LIGBT.
  • Rd_tfac (1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25))
  • TEMP is the system temperature
  • Td1 is the temperature coefficient of the first-order exponential term of the drain-end resistance Rd1
  • Td2 is the temperature coefficient of the second-order exponential term of the drain-end resistance Rd1.
  • V b1,e represents the voltage between the two nodes of the base b 1 of the PNP transistor QP1 and the emitter e of the NPN transistor QN1 (i.e., both ends of the base resistor Rb1)
  • Rbw1 represents the base resistance Rb1 when the voltage is zero.
  • Prwbd2 is the second voltage coefficient of the base resistor Rb1
  • Erbd is the power exponential term coefficient of the second voltage of the base resistor Rb1
  • wrd2 is the correction parameter of W.
  • Rb_tfac (1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25))
  • Tb1 is the temperature coefficient of the first-order exponential term of the base resistor Rb1
  • Tb2 is the temperature coefficient of the second-order exponential term of the base resistor Rb1.
  • the simulation model of the first controlled current source G1 (self-heating effect controlled current source subcircuit) is implemented as follows:
  • the simulation model of the second controlled current source G2 (tail current controlled current source sub-circuit) is implemented as follows:
  • the above-mentioned anode short-circuited lateral insulated gate bipolar transistor model can accurately simulate the static characteristics and switching characteristics of the SA-LIGBT of this application.
  • the model includes self-heating effects and can simulate tail current.
  • the model is composed of the industry-wide standard model BSIM3/BSIM4MOS model. , G-P BJT model, voltage-controlled resistance model, capacitance model and controlled current source. It is compatible with standard circuit simulators HSPICE and SPECTER. Through format conversion, the simulation results on different simulators can be kept consistent.
  • FIG. 4 is a flow chart of a modeling method of an anode short-circuited lateral insulated gate bipolar transistor model in an embodiment of the present application, including the following steps S410 to S480.
  • S410 Establish an anode short-circuited lateral insulated gate bipolar transistor (SA-LIGBT) model with an NPN structure in the anode, and set device parameters of the SA-LIGBT.
  • SA-LIGBT lateral insulated gate bipolar transistor
  • step S420 includes adjusting the CV parameters of the NMOS transistor M1 and the external capacitor C0 parameters to fit the CV curve.
  • step S420 includes adjusting at least one of the gate-collector overlap capacitance Cgdo, the lightly doped region overlap capacitance Cgdl, and the lightly doped region overlap capacitance coefficient Ckappad to fit CV curve.
  • step S440 includes adjusting the device parameters and base of the NPN transistor QN1 The resistance value of resistor Rp is used to fit the transfer characteristic curve of the minimum V CE when the SA-LIGBT device is turned on.
  • the device parameters of the NPN transistor QN1 adjusted in step S440 include at least one of the transmission saturation current Is, the forward current emission coefficient Nf, and the forward amplification factor Bf.
  • a base resistor Rb1 is set in the model between the base b 1 of the PNP transistor QP1 and the common terminal of the second controlled current source G2 and the emitter e of the NPN transistor QN1. Based on this, step S450 This includes adjusting the linear region parameters of the NMOS transistor M1, the device parameters of the PNP transistor QP1, and the parameters of the base resistor Rb1 to fit the transfer characteristic curve of the SA-LIGBT in the first voltage range of V CE .
  • the linear region parameters of the NMOS transistor M1 adjusted in step S450 include low electric field mobility U0, first-order mobility degradation coefficient Ua, second-order mobility degradation coefficient Ub, drain parasitic resistance Rdw, drain At least one of the gate bias coefficients Prwg of the terminal parasitic resistance.
  • the device parameters of the PNP transistor QP1 adjusted in step S450 include the transmission saturation current Is, the forward current emission coefficient Nf, the forward amplification factor Bf, and the forward amplification factor roll-off angle under large current. Ikf, and at least one of the exponential parameters Nkf of the forward amplification roll-off under large current.
  • the saturation region parameters of the NMOS transistor M1 adjusted in step S460 include at least one of the substrate charge effect coefficient A0, the gate bias coefficient Ags, and the carrier saturation velocity Vsat.
  • the device parameters of the PNP transistor QP1 adjusted in step S460 include the transmission saturation current Is, the forward current emission coefficient Nf, the forward amplification factor Bf, and the forward amplification factor roll-off angle under large current. Ikf, and at least one of the exponential parameters Nkf of the forward amplification roll-off under large current.
  • a drain resistance Rd1 is set between the drain d of the NMOS transistor M1 and the common terminal of the second controlled current source G2 and the emitter e of the NPN transistor QN1. Based on this, in step S460 After that (before step S470), step S462 is also included: adjusting the drain resistance Rd1 to fit the linear region part of the output characteristic curve of the SA-LIGBT.
  • the first controlled current source G1 is set between the emitter e 1 of the PNP transistor QP1 and the collector c 1 of the PNP transistor QP1 in the model. Based on this, after step S462 and before step S470, It also includes step S464: adjusting the parameters of the first controlled current source G1 to fit the self-heating effect of the SA-LIGBT.
  • step S464 it also includes determining whether the fitting accuracy of steps S420, S430, S440, S450, S460, S462, and S464 meets the requirements (that is, whether the model simulation data is better fitted than the actual test data).
  • (Good) step if the curve fitted in any of the above steps S420 to S464 does not meet the accuracy requirements, the parameters involved in this step are adjusted again, and step S470 is not executed until the curves of each step meet the requirements.
  • step S470 and before step S480 there is also a step of determining whether the fitting accuracy of the temperature characteristic curve meets the requirements. If the accuracy does not meet the requirements, return to step S470.
  • FIG. 5 is a flow chart of a modeling method of an anode short-circuited lateral insulated gate bipolar transistor model in another embodiment. The following provides an example of an IGBT model built according to the above modeling method:
  • Figure 6 is the current-voltage characteristic fitting curve of the SA-LIGBT device using the above model under normal temperature (25 degrees Celsius) of this application.
  • the current I ds tends to 0.
  • Figure 7 shows the application's low temperature (minus 40 degrees Celsius)
  • Figure 8 shows the current-voltage characteristic fitting curve of the above model for the SA-LIGBT device under high temperature (180 degrees Celsius) conditions.
  • the solid lines in Figures 6 to 8 are model simulation data, and the dots are actual test data of SA-LIGBT devices.
  • d corresponds to the collector C (collector) of IGBT
  • s corresponds to the emitter E (emitter) of IGBT.
  • FIG 9 shows the transient characteristics test circuit as well as the test data and model simulation fitting curve (actual measurement and fitting of the tail current under the transient characteristics of the device).
  • the resistor is labeled R1
  • the power source is labeled DC
  • the ground is labeled GND1.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种阳极短路横向绝缘栅双极晶体管模型，适用于阳极具有NPN三极管的阳极短路横向绝缘栅双极晶体管(Shorted Anode Lateral Insulated Gate Bipolar Transistor,SA-LIGBT)，包括：NMOS管(M1)，NPN三极管(QN1)，PNP三极管(QP1)，和第二受控电流源(G2)。所述NMOS管(M1)的源极连接所述SA-LIGBT的发射极，所述NMOS管(M1)的栅极连接所述SA-LIGBT的栅极；所述NPN三极管(QN1)的发射极连接所述NMOS管(M1)的漏极，所述NPN三极管(QN1)的集电极连接所述SA-LIGBT的集电极；所述PNP三极管(QP1)的发射极连接所述SA-LIGBT的集电极和所述NPN三极管(QN1)的基极，所述PNP三极管(QP1)的集电极连接所述SA-LIGBT的发射极，所述PNP三极管(QP1)的基极连接所述NPN三极管(QN1)的发射极；所述受控电流源G2，一端连接所述NPN三极管(QN1)的发射极，另一端连接所述NMOS管(M1)的源极，所述第二受控电流源(G2)产生的电流受控于所述NMOS管(M1)的电流。

Description

阳极短路横向绝缘栅双极晶体管模型及其建模方法
相关申请
本申请要求2022年8月3日申请的，申请号为202210927589.4，名称为“阳极短路横向绝缘栅双极晶体管模型及其建模方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本公开涉及半导体制造领域，特别是涉及一种阳极短路横向绝缘栅双极晶体管模型，还涉及一种阳极短路横向绝缘栅双极晶体管模型的建模方法。
背景技术
横向绝缘栅双极晶体管(Lateral Insulated Gate Bipolar Transistor，LIGBT)因其导通压降低、输入阻抗高、电流密度大和易于集成等优点被广泛应用在集成电路(Integrated Circuit，IC)中，其中阳极短路横向绝缘栅双极晶体管(Shorted Anode LIGBT，SA-LIGBT)有着高耐压、高功率密度、开关速度快等特点，但是阳极短路横向绝缘栅双极晶体管有着很多难以表征的效应，这些效应用常规的绝缘栅双极晶体管(Insulated Gate Bipolar Transistor，IGBT)模型难以准确地表征。因此需要一种仿真准确度高的阳极短路横向绝缘栅双极晶体管模型及其建模方法。
发明内容
基于此，有必要提供一种仿真准确度高的阳极短路横向绝缘栅双极晶体管模型及其建模方法。
一种阳极短路横向绝缘栅双极晶体管模型，适用于阳极具有NPN三极管的阳极短路横向绝缘栅双极晶体管(Shorted Anode Lateral Insulated Gate Bipolar Transistor，SA-LIGBT)，所述SA-LIGBT包括基区，位于所述基区中的第一体区和第二体区，位于所述第一体区中的第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，以及位于所述第二体区中的第一导电类型的第三掺杂区和第二导电类型的第四掺杂区，位于所述基区上的场氧层，以及栅极；所述第一导电类型的第一掺杂区和所述第二导电类型的第二掺杂区引出作为所述SA-LIGBT的集电极；所述阳极短路横向绝缘栅双极晶体管模型包括：NMOS管M1，NPN三极管QN1，PNP三极管QP1，和第二受控电流源G2。所述NMOS管M1的源极连接所述SA-LIGBT的发射极，所述NMOS管M1的栅极连接所述SA-LIGBT的栅极。所述NPN三极管QN1的发射极连接所述NMOS管M1的漏极，所述NPN三极管QN1的集电极连接所述SA-LIGBT的集电极。所述PNP三极管QP1的发射极连接所述SA-LIGBT的集电极和所述NPN三极管QN1的基极，所述PNP三极 管QP1的集电极连接所述SA-LIGBT的发射极，所述PNP三极管QP1的基极连接所述NPN三极管QN1的发射极。所述第二受控电流源G2，一端连接所述NPN三极管QN1的发射极，另一端连接所述NMOS管M1的源极，所述第二受控电流源G2产生的电流受控于所述NMOS管M1的电流。
上述阳极短路横向绝缘栅双极晶体管模型，适用的IGBT器件阳极具有NPN结构，从而具有较小的拖尾电流，没有正向电压折回现象。模型与该结构匹配，设置第二受控电流源G2来模拟拖尾电流，能够很好地拟合器件的开关特性，仿真准确度高。
在其中一个实施例中，所述阳极短路横向绝缘栅双极晶体管模型还包括第一受控电流源G1，所述第一受控电流源G1的一端连接所述PNP三极管QP1的发射极，另一端连接所述PNP三极管QP1的集电极，所述第一受控电流源G1产生的电流受控于所述PNP三极管QP1的电流。
在其中一个实施例中，所述第一受控电流源G1包括相互并联的第一电流源、第一电容及第一电阻，所述第一电容基于所述PNP三极管QP1的电流产生第一电容端电压，从而构成与所述电容端电压相关的受控电流源。
在其中一个实施例中，所述第二受控电流源G2包括相互并联的第二电流源、第二电容及第二电阻，所述第二电容基于所述NMOS管M1的电流产生第二电容端电压，从而构成与所述电容端电压相关的受控电流源，所述第二电阻用于通过选择合适的电阻值来调整拖尾电流的大小。
在其中一个实施例中，所述阳极短路横向绝缘栅双极晶体管模型还包括：漏端电阻Rd1，一端连接所述NMOS管M1的漏极，另一端连接所述第二受控电流源G2与所述NPN三极管QN1的发射极的公共端；基极电阻Rb1，一端连接所述PNP三极管QP1的基极，另一端连接所述第二受控电流源G2与所述NPN三极管QN1的发射极的公共端；外部电容C0，一端连接所述NMOS管M1的栅极，另一端连接所述NPN三极管QN1的集电极。
在其中一个实施例中，所述NPN三极管QN1和PNP三极管QP1使用G-P BJT模型来表征，所述NMOS管M1使用BSIM3模型或BSIM4模型进行表征，且所述NMOS管M1使用的模型将内部漏端电容参数关闭。
在其中一个实施例中，所述漏端电阻Rd1和所述基极电阻Rb1为压控电阻；
所述漏端电阻Rd1表征所述NMOS管M1漏端漂移区电阻；
所述基极电阻Rb1表征所述PNP三极管QP1基区内的调制电阻。
在其中一个实施例中，所述漏端电阻Rd1的压控数学表达式为：
Rd1＝Rd_tfac×Rcdw1×(Crd*Vd,e Erdd×(1/(1+Prwge1×Vg,e))+1)/(W×1E6)wrd1
其中，Rd_tfac＝(1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25))；
Vd,e表示NMOS管M1的漏极d与NPN三极管QN1的发射极e两节点之间的电压，Rcdw1表 示电压为零时的所述漏端电阻Rd1的电阻值，Crd为所述漏端电阻Rd1的第一电压系数，Erdd为所述漏端电阻Rd1的第一电压的幂指数项系数，Prwge1为所述漏端电阻Rd1的第二电压系数，W为所述SA-LIGBT的沟道宽度，wrd1为所述沟道宽度W的修正参数，Vg,e表示SA-LIGBT的栅极与发射极之间的电压；TEMP为系统温度，Td1为所述漏端电阻Rd1的一阶指数项的温度系数，Td2为所述漏端电阻Rd1的二阶指数项的温度系数。
在其中一个实施例中，所述基极电阻Rb1的压控数学表达式为：
Rb1＝Rb_tfac×Rbw1×(1+Prwge2×Vg,e Erge2+Prwbd2×Vb1,e Erbd)/(W×1E6)wrd2
其中，Rb_tfac＝(1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25))；
Vb1,e表示所述PNP三极管QP1的基极b1与所述NPN三极管QN1的发射极e两节点之间的电压，Rbw1表示电压为零时的所述基极电阻Rb1的电阻值，Prwge2为所述基极电阻Rb1的第一电压系数，Vg,e表示SA-LIGBT的栅极与发射极之间的电压，Erge2为所述基极电阻Rb1的第一电压的幂指数项系数，Prwbd2为所述基极电阻Rb1的第二电压系数，Erbd为所述基极电阻Rb1的第二电压的幂指数项系数，wrd2为所述沟道宽度W的修正参数；Tb1为所述基极电阻Rb1的一阶指数项的温度系数，Tb2为所述基极电阻Rb1的二阶指数项的温度系数。
在其中一个实施例中，所述第一导电类型为N型，所述第二导电类型为P型。
在其中一个实施例中，所述漏端电阻Rd1是压控电阻。
在其中一个实施例中，所述基极电阻Rb1是压控电阻。
在其中一个实施例中，所述阳极短路横向绝缘栅双极晶体管模型还包括基极电阻Rp，所述基极电阻Rp的一端连接所述NPN三极管QN1的基极，另一端连接所述PNP三极管QP1的发射极。
还有必要提供一种阳极短路横向绝缘栅双极晶体管模型的建模方法。
一种阳极短路横向绝缘栅双极晶体管模型的建模方法，包括：步骤A，建立如权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，并设置所述SA-LIGBT的器件参数；步骤B，调节所述NMOS管M1的电容-电压参数以拟合电容-电压曲线；步骤C，调节所述NMOS管M1的阈值电压参数以拟合所述SA-LIGBT的开启电压；步骤D，调节所述NPN三极管QN1的器件参数以拟合所述SA-LIGBT开启时所述SA-LIGBT的最小VCE的转移特性曲线；步骤E，调节所述NMOS管M1的线性区参数和所述PNP三极管QP1的器件参数以拟合所述SA-LIGBT的VCE处于第一电压值区间时的转移特性曲线；步骤F，调节所述NMOS管M1的饱和区参数和所述PNP三极管QP1的器件参数以拟合所述SA-LIGBT的VCE处于第二电压值区间时的转移特性曲线，以及拟合所述SA-LIGBT的输出特性曲线；所述第二电压值区间的左端点的电压值大于所述第一电压值区间的右端点的电压值；步骤G，调节温度系数以拟合所述SA-LIGBT的温度特性曲线；步骤H，调节所述第二受控电流源G2的参数以拟合所述SA-LIGBT的开关特性。
在其中一个实施例中，所述阳极短路横向绝缘栅双极晶体管模型还包括：漏端电阻Rd1， 一端连接所述NMOS管M1的漏极，另一端连接所述第二受控电流源G2与所述NPN三极管QN1的发射极的公共端；基极电阻Rb1，一端连接所述PNP三极管QP1的基极，另一端连接所述第二受控电流源G2与所述NPN三极管QN1的发射极的公共端；外部电容C0，一端连接所述NMOS管M1的栅极，另一端连接所述NPN三极管QN1的集电极；基极电阻Rp，一端连接所述NPN三极管QN1的基极，另一端连接所述PNP三极管QP1的发射极；所述步骤B包括：调节所述NMOS管M1的电容-电压参数以及所述外部电容C0的参数以拟合电容-电压曲线；所述步骤D包括：调节所述NPN三极管QN1的器件参数和所述基极电阻Rp的电阻值以拟合所述最小VCE的转移特性曲线；所述步骤E包括：调节所述NMOS管M1的线性区参数、所述PNP三极管QP1的器件参数以及所述基极电阻Rb1的参数以拟合所述VCE处于第一电压值区间时的转移特性曲线；在所述步骤F之后还包括步骤F1：调整所述漏端电阻Rd1以拟合所述输出特性曲线的线性区部分。
在其中一个实施例中，所述阳极短路横向绝缘栅双极晶体管模型还包括第一受控电流源G1，所述第一受控电流源G1的一端连接所述PNP三极管QP1的发射极，另一端连接所述PNP三极管QP1的集电极，所述第一受控电流源G1产生的电流受控于所述PNP三极管QP1的电流；在所述步骤F1之后还包括步骤F2：调整所述第一受控电流源G1的参数以拟合所述SA-LIGBT的自热效应。
在其中一个实施例中，所述步骤F2之后只在所述步骤B、步骤C、步骤D、步骤F、步骤F1、步骤F2的拟合精度均满足要求的情况下才执行所述步骤G，否则返回所述步骤B；在所述步骤G之后以及所述步骤H之前，若所述温度特性曲线的拟合精度不满足要求，则返回所述步骤G。
附图说明
为了更好地描述和说明本公开的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对本公开目前描述的实施例和/或示例以及目前理解的本公开的最佳模式中的任何一者的范围的限制。
图1是本申请一实施例中阳极具有NPN三极管的SA-LIGBT的剖面示意图；
图2是本申请一实施例中阳极短路横向绝缘栅双极晶体管模型的等效电路原理图，并且图中对应示出了阳极对应的器件结构；
图3a是本申请一实施例中第一受控电流源G1的等效电路；
图3b是本申请一实施例中第二受控电流源G2的等效电路；
图4是本申请一实施例中阳极短路横向绝缘栅双极晶体管模型的建模方法的流程图；
图5是本申请另一实施例中阳极短路横向绝缘栅双极晶体管模型的建模方法的流程图；
图6为本申请常温(25摄氏度)下采用一实施例的模型对绝缘栅双极晶体管器件的电流 -电压特性拟合曲线；
图7为本申请低温(负40摄氏度)下采用一实施例的模型对绝缘栅双极晶体管器件的电流-电压特性拟合曲线；
图8为本申请高温(180摄氏度)下采用一实施例的模型对绝缘栅双极晶体管器件的电流-电压特性拟合曲线；
图9为本申请瞬态特性测试电路以及测试数据与模型仿真拟合曲线。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整 数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
对于阳极短路的全阳结构的绝缘栅双极晶体管(Insulated Gate Bipolar Transistor，IGBT)器件，其工作时会在MOS工作状态和IGBT工作状态之间转换，该结构会存在正向电压折回现象。为了改善拖尾效应和正向电压折回现象，设计得到阳极(也称作集电极)具有NPN三极管的IGBT，本申请提出一种阳极短路横向绝缘栅双极晶体管模型，适用于阳极短路的半阳结构的IGBT，即适用于阳极具有NPN三极管的SA-LIGBT。如图1所示，SA-LIGBT包括基区110，位于基区110中的第一体区132，位于基区110中的第二体区134，位于第一体区132中的第一导电类型的第一掺杂区142，位于第一体区132中的第二导电类型的第二掺杂区148，位于第二体区134中的第一导电类型的第三掺杂区144，位于第二体区134中的第二导电类型的第四掺杂区146，位于基区110上的场氧层150，以及栅极160。第一导电类型的第一掺杂区142和第二导电类型的第二掺杂区148引出作为SA-LIGBT的集电极。在图1所示的实施例中，第一导电类型为N型，第二导电类型为P型。
图2是本申请一实施例中阳极短路横向绝缘栅双极晶体管模型的等效电路原理图，如图2所示，阳极短路横向绝缘栅双极晶体管模型包括：NMOS管M1，NPN三极管QN1，PNP三极管QP1，和第二受控电流源G2。
所述NMOS管M1的源极s连接所述SA-LIGBT的发射极E，所述NMOS管M1的栅极g连接所述SA-LIGBT的栅极G。
所述NPN三极管QN1的发射极e连接所述NMOS管M1的漏极d，所述NPN三极管QN1的集电极c连接所述SA-LIGBT的集电极C。
所述PNP三极管QP1的发射极e1连接所述SA-LIGBT的集电极C和所述NPN三极管QN1 的基极b，所述PNP三极管QP1的集电极c1连接所述SA-LIGBT的发射极E，所述PNP三极管QP1的基极b1连接所述NPN三极管QN1的发射极e。
第二受控电流源G2，一端连接所述NPN三极管QN1的发射极e，另一端连接所述NMOS管M1的源极s，所述第二受控电流源G2产生的电流受控于所述NMOS管M1的电流。
上述阳极短路横向绝缘栅双极晶体管模型，适用的SA-LIGBT器件阳极具有NPN结构，从而具有较小的拖尾电流，没有正向电压折回现象。模型与该结构匹配，设置第二受控电流源G2来模拟拖尾电流，能够很好地拟合器件的开关特性，仿真准确度高。
图2是本申请一实施例中阳极短路横向绝缘栅双极晶体管模型的等效电路原理图，并且该图中对应示出了阳极对应的器件结构。在图2所示的实施例中，阳极短路横向绝缘栅双极晶体管模型还包括第一受控电流源G1。第一受控电流源G1的一端连接PNP三极管QP1的发射极，另一端连接PNP三极管QP1的集电极。第一受控电流源G1产生的电流受控于PNP三极管QP1的电流。第一受控电流源G1用于表征SA-LIGBT的自热效应，因此模型能够很好地拟合器件的静态特性。
第一受控电流源G1的等效电路可以参见图3a，包括相互并联的第一电流源g1、第一电容C1及第一电阻R1。第一电容C1基于PNP三极管QP1的电流产生第一电容端电压，从而产生与第一电容端电压相关的第一受控电流源G1，即通过RC电路产生第一受控电流源。
第二受控电流源G2的等效电路可以参见图3b。所述第二受控电流源G2包括相互并联的第二电流源g2、第二电容C2及第二电阻R2，所述第二电容基于所述NMOS管M1的电流产生第二电容端电压，从而构成与所述第二电容端电压相关的第二受控电流源G2，并且可以通过调整子电路中的第二电阻R的阻值来控制器件开启时子电路的影响和器件关断时SA-LIGBT的拖尾电流的大小。
在本申请的一个实施例中，NPN三极管QN1和PNP三极管QP1使用根梅尔-普恩(Gummel-poon，G-P)BJT模型来表征，NMOS管M1使用BSIM3模型或BSIM4模型来表征。
在图2所示的实施例中，阳极短路横向绝缘栅双极晶体管模型还包括漏端电阻Rd1、基极电阻Rb1及外部电容C0。漏端电阻Rd1一端连接NMOS管M1的漏极d，另一端连接第二受控电流源G2与NPN三极管QN1的发射极e的公共端。基极电阻Rb1一端连接PNP三极管QP1的基极b1，另一端连接第二受控电流源G2与NPN三极管QN1的发射极e的公共端。外部电容C0一端连接NMOS管M1的栅极g，另一端连接NPN三极管QN1的集电极c。
NPN三极管QN1和PNP三极管QP1的电容特性通过G-P BJT模型来表征。由于漏端电阻Rd1的存在，MOS模型中计算漏端电容的表达式不能正确对应端点电压，从而不能合理表征其漏端的电容，因此实施例的模型中关闭MOS模型(NMOS管M1使用的模型)内部漏端的电容参数，通过外部电容C0来表征。NMOS管M1的源端的电容特性仍然通过MOS模型中相应的参数来表征。
在图2所示的实施例中，阳极短路横向绝缘栅双极晶体管模型还包括基极电阻Rp。基极电阻Rp的一端连接NPN三极管QN1的基极b，另一端连接PNP三极管QP1的发射极e1。
在图2所示的实施例中，漏端电阻Rd1和基极电阻Rb1为压控电阻。漏端电阻Rd1表征NMOS管M1漏端漂移区电阻。基极电阻Rb1表征PNP三极管QP1基区内的调制电阻。
在本申请的一个实施例中，漏端电阻Rd1的压控数学表达式如下：
Rd1＝Rd_tfac×Rcdw1×(Crd*Vd,e Erdd×(1/(1+Prwge1×Vg,e))+1)/(W×1E6)wrd1
其中，Vd,e表示NMOS管M1的漏极d与NPN三极管QN1的发射极e两节点之间(即漏端电阻Rd1两端)的电压，Rcdw1表示电压为零时的漏端电阻Rd1的电阻值，Crd为漏端电阻Rd1的第一电压系数，Erdd为漏端电阻Rd1的第一电压的幂指数项系数，Prwge1为漏端电阻Rd1的第二电压系数，W为SA-LIGBT的沟道宽度，wrd1为W的修正参数，Vg,e表示SA-LIGBT的栅极与发射极之间的电压。并且：
Rd_tfac＝(1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25))
其中，TEMP为系统温度，Td1为漏端电阻Rd1的一阶指数项的温度系数，Td2为漏端电阻Rd1的二阶指数项的温度系数。
在本申请的一个实施例中，基极电阻Rb1的压控数学表达式如下：
Rb1＝Rb_tfac×Rbw1×(1+Prwge2×Vg,e Erge2+Prwbd2×Vb1,e Erbd)/(W×1E6)wrd2
其中，Vb1,e表示PNP三极管QP1的基极b1与NPN三极管QN1的发射极e两节点(即基极电阻Rb1两端)之间的电压，Rbw1表示电压为零时的基极电阻Rb1的电阻值，Prwge2为基极电阻Rb1的第一电压系数，Vg,e表示SA-LIGBT的栅极与发射极之间的电压，Erge2为基极电阻Rb1的第一电压的幂指数项系数，Prwbd2为基极电阻Rb1的第二电压系数，Erbd为基极电阻Rb1的第二电压的幂指数项系数，wrd2为W的修正参数。并且：
Rb_tfac＝(1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25))
其中，Tb1为基极电阻Rb1的一阶指数项的温度系数，Tb2为基极电阻Rb1的二阶指数项的温度系数。
在本申请的一个实施例中，第一受控电流源G1(自热效应受控电流源子电路)的仿真模型实现如下：
rth t1 0 rth m＝multi
cth t1 0 cth m＝multi
grth2 0 t1 vccs cur＝'abs(i(q1)*v(c,e))'m＝multi
grth1 c e vccs cur＝'(pwr((1+v(t1,0)/t0),-k)-1)*(-i(q1))'m＝multi
在本申请的一个实施例中，第二受控电流源G2(拖尾电流受控电流源子电路)的仿真模型实现如下：
gsen 0 a cur＝'(i(m1))'m＝multi
rt1 a 0'pwr(ttail,max(1,((i(m1)*ttail))/(0.01+v(a,0))))'m＝multi
ct1 a 0 cap1 m＝multi
gfsen d e cur＝'(cap1*(abs(v(a,0)))/tt)-i(m1)'m＝multi
上述阳极短路横向绝缘栅双极晶体管模型可以准确地仿真本申请的SA-LIGBT的静态特性和开关特性，模型包含自热效应、能够仿真拖尾电流，同时模型由业界通用的标准模型BSIM3/BSIM4MOS模型、G-P BJT模型、电压控制电阻模型、电容模型和受控电流源组成，能够与标准电路仿真器HSPICE、SPECTRE兼容，通过格式转化可以保持在不同仿真器上仿真结果一致。
本申请还提供一种阳极短路横向绝缘栅双极晶体管模型的建模方法，所述建模方法基于前述任一实施例所述的阳极短路横向绝缘栅双极晶体管模型进行建模仿真。图4是本申请一实施例中阳极短路横向绝缘栅双极晶体管模型的建模方法的流程图，包括下列步骤S410至S480。
S410，建立阳极具有NPN结构的阳极短路横向绝缘栅双极晶体管(SA-LIGBT)模型，并设置SA-LIGBT的器件参数。
建立前述任一实施例所述的模型，并设置SA-LIGBT的沟道宽度、沟道长度、原胞数等器件工艺参数。
S420，调节NMOS管M1的电容-电压(CV)参数以拟合电容-电压(CV)曲线。
调节NMOS管M1的CV参数。在一些实施例中，模型中在NMOS管M1的栅极g和NPN三极管QN1的集电极c之间设置了外部电容C0，基于此，步骤S420包括调节NMOS管M1的CV参数和外部电容C0的参数以拟合CV曲线。在本申请的一个实施例中，步骤S420包括调节栅极-集电极交叠电容Cgdo，轻掺杂区域交叠电容Cgdl，以及轻掺杂区域交叠电容系数Ckappad中的至少一项以拟合CV曲线。
S430，调节NMOS管M1的阈值电压参数以拟合SA-LIGBT的开启电压。
S440，调节NPN三极管QN1的器件参数以拟合SA-LIGBT开启时SA-LIGBT的最小VCE的转移特性曲线。
调节NPN三极管QN1的器件参数以拟合SA-LIGBT开启时最小VCE(集电极C和发射极E之间的电压)的转移特性曲线。在一些实施例中，模型中在NPN三极管QN1的基极b和PNP三极管QP1的发射极e1之间设置了基极电阻Rp，基于此，步骤S440包括调节NPN三极管QN1的器件参数和基极电阻Rp的电阻值以拟合SA-LIGBT器件开启时最小VCE的转移特性曲线。在本申请的一个实施例中，步骤S440调节的NPN三极管QN1的器件参数包括传输饱和电流Is，正向电流发射系数Nf，以及正向放大倍数Bf中的至少一项。
S450，调节NMOS管M1的线性区参数和PNP三极管QP1的器件参数以拟合SA-LIGBT的 VCE处于第一电压值区间时的转移特性曲线。
在一些实施例中，模型中在PNP三极管QP1的基极b1和第二受控电流源G2与NPN三极管QN1的发射极e的公共端之间设置了基极电阻Rb1，基于此，步骤S450包括调节NMOS管M1的线性区参数、PNP三极管QP1的器件参数以及基极电阻Rb1的参数以拟合SA-LIGBT的VCE第一电压值区间时的转移特性曲线。在本申请的一个实施例中，步骤S450调节的NMOS管M1的线性区参数包括低电场迁移率U0，一阶迁移率退化系数Ua，二阶迁移率退化系数Ub，漏端寄生电阻Rdw，漏端寄生电阻的栅偏压系数Prwg中的至少一项。在本申请的一个实施例中，步骤S450调节的PNP三极管QP1的器件参数包括传输饱和电流Is，正向电流发射系数Nf，正向放大倍数Bf，正向放大倍数在大电流下roll-off角Ikf，以及正向放大倍数在大电流下roll-off的指数参数Nkf中的至少一项。
S460，调节NMOS管M1的饱和区参数和PNP三极管QP1的器件参数以拟合SA-LIGBT的VCE处于第二电压值区间时的转移特性曲线和SA-LIGBT的输出特性曲线。其中，所述第二电压值区间的左端点的电压值大于所述第一电压值区间的右端点的电压值。
在本申请的一个实施例中，步骤S460调节的NMOS管M1的饱和区参数包括衬底电荷效应系数A0，栅偏压系数Ags，以及载流子饱和速度Vsat中的至少一项。在本申请的一个实施例中，步骤S460调节的PNP三极管QP1的器件参数包括传输饱和电流Is，正向电流发射系数Nf，正向放大倍数Bf，正向放大倍数在大电流下roll-off角Ikf，以及正向放大倍数在大电流下roll-off的指数参数Nkf中的至少一项。
在一些实施例中，模型中在NMOS管M1的漏极d和第二受控电流源G2与NPN三极管QN1的发射极e的公共端之间设置了漏端电阻Rd1，基于此，在步骤S460之后(步骤S470之前)还包括步骤S462：调整漏端电阻Rd1以拟合SA-LIGBT的输出特性曲线的线性区部分。
在一些实施例中，模型中在PNP三极管QP1的发射极e1与PNP三极管QP1的集电极c1之间设置了第一受控电流源G1，基于此，在步骤S462之后和步骤S470之前，还包括步骤S464：调整第一受控电流源G1的参数以拟合SA-LIGBT的自热效应。
在本申请的一个实施例中，在步骤S464之后还包括判断步骤S420、S430、S440、S450、S460、S462、S464的拟合精度是否满足要求(即模型仿真数据是否与实际测试数据拟合较好)的步骤，若以上步骤S420～S464任一步骤拟合的曲线不满足精度要求，则再次调整该步骤涉及的参数，直到各步骤的曲线均满足要求后才执行步骤S470。具体地，可以在步骤S464之后返回步骤S420，判断每一个步骤拟合的曲线是否满足精度要求，如果任一步骤拟合的曲线不满足精度要求，则再次调整该步骤涉及的参数至满足要求，然后继续验证下一步骤拟合的曲线是否满足精度要求，直到所有拟合曲线均满足精度要求。
S470，调节温度系数以拟合SA-LIGBT的温度特性曲线。
调节前述各步骤中涉及的各项参数对应的温度系数，以拟合SA-LIGBT的温度特性曲线。
S480，调节第二受控电流源G2的参数以拟合SA-LIGBT的开关特性。
在本申请的一个实施例中，在步骤S470之后、步骤S480之前，还包括判断温度特性曲线的拟合精度是否满足要求的步骤，若精度不满足要求，则返回步骤S470。
图5是另一实施例中阳极短路横向绝缘栅双极晶体管模型的建模方法的流程图。以下提供一种按照上述建模方法搭建的IGBT模型实例：

图6为本申请常温(25摄氏度)下采用上述模型对SA-LIGBT器件的电流-电压特性拟合曲线，其中电压Vgs分别为3V和0V时电流Ids都趋于0。图7为本申请低温(负40摄氏度)、图8为高温(180摄氏度)条件下上述模型对SA-LIGBT器件的电流-电压特性拟合曲线。图6至图8中实线是模型仿真数据，圆点是对SA-LIGBT器件的实际测试数据，d对应IGBT的集电极C(collector)，s对应IGBT的发射极E(emitter)。图9为瞬态特性测试电路以及测试数据与模型仿真拟合曲线(器件瞬态特性下拖尾电流的实测与拟合情况)，图9中电阻的标号为R1，电源的标号为DC，地线的标号为GND1。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行 并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种阳极短路横向绝缘栅双极晶体管模型，其特征在于，适用于阳极具有NPN三极管的阳极短路横向绝缘栅双极晶体管(Shorted Anode Lateral Insulated Gate Bipolar Transistor，SA-LIGBT)，所述SA-LIGBT包括基区，位于所述基区中的第一体区和第二体区，位于所述第一体区中的第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，以及位于所述第二体区中的第一导电类型的第三掺杂区和第二导电类型的第四掺杂区，位于所述基区上的场氧层，以及栅极；所述第一导电类型的第一掺杂区和所述第二导电类型的第二掺杂区引出作为所述SA-LIGBT的集电极；所述阳极短路横向绝缘栅双极晶体管模型包括：
    NMOS管(M1)，所述NMOS管(M1)的源极连接所述SA-LIGBT的发射极，所述NMOS管(M1)的栅极连接所述SA-LIGBT的栅极；
    NPN三极管(QN1)，所述NPN三极管(QN1)的发射极连接所述NMOS管(M1)的漏极，所述NPN三极管(QN1)的集电极连接所述SA-LIGBT的集电极；
    PNP三极管(QP1)，所述PNP三极管(QP1)的发射极连接所述SA-LIGBT的集电极和所述NPN三极管(QN1)的基极，所述PNP三极管(QP1)的集电极连接所述SA-LIGBT的发射极，所述PNP三极管(QP1)的基极连接所述NPN三极管(QN1)的发射极；
    第二受控电流源(G2)，一端连接所述NPN三极管(QN1)的发射极，另一端连接所述NMOS管(M1)的源极，所述第二受控电流源(G2)产生的电流受控于所述NMOS管(M1)的电流。
  2. 根据权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，还包括第一受控电流源(G1)，所述第一受控电流源(G1)的一端连接所述PNP三极管(QP1)的发射极，另一端连接所述PNP三极管(QP1)的集电极，所述第一受控电流源(G1)产生的电流受控于所述PNP三极管(QP1)的电流。
  3. 根据权利要求2所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述第一受控电流源(G1)包括相互并联的第一电流源、第一电容及第一电阻，所述第一电容基于所述PNP三极管(QP1)的电流产生第一电容端电压。
  4. 根据权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述第二受控电流源(G2)包括相互并联的第二电流源、第二电容及第二电阻，所述第二电容基于所述NMOS管(M1)的电流产生第二电容端电压。
  5. 根据权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，还包括：
    漏端电阻(Rd1)，一端连接所述NMOS管(M1)的漏极，另一端连接所述第二受控电流源 (G2)与所述NPN三极管(QN1)的发射极的公共端；
    基极电阻(Rb1)，一端连接所述PNP三极管(QP1)的基极，另一端连接所述第二受控电流源(G2)与所述NPN三极管(QN1)的发射极的公共端；
    外部电容(C0)，一端连接所述NMOS管(M1)的栅极，另一端连接所述NPN三极管(QN1)的集电极。
  6. 根据权利要求5所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述NPN三极管(QN1)和PNP三极管(QP1)使用G-P BJT模型来表征，所述NMOS管(M1)使用BSIM3模型或BSIM4模型来表征，且所述NMOS管(M1)使用的模型将内部漏端电容参数关闭。
  7. 根据权利要求5所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述漏端电阻(Rd1)和所述基极电阻(Rb1)为压控电阻；
    所述漏端电阻(Rd1)表征所述NMOS管(M1)漏端漂移区电阻；
    所述基极电阻(Rb1)表征所述PNP三极管(QP1)基区内的调制电阻。
  8. 根据权利要求7所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述漏端电阻(Rd1)的压控数学表达式为：
    Rd1＝Rd_tfac×Rcdw1×(Crd*Vd,e Erdd×(1/(1+Prwge1×Vg,e))+1)/(W×1E6)wrd1
    其中，Rd_tfac＝(1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25))；
    Vd,e表示NMOS管M1的漏极(d)与NPN三极管(QN1)的发射极(e)两节点之间的电压，Rcdw1表示电压为零时的所述漏端电阻(Rd1)的电阻值，Crd为所述漏端电阻(Rd1)的第一电压系数，Erdd为所述漏端电阻(Rd1)的第一电压的幂指数项系数，Prwge1为所述漏端电阻(Rd1)的第二电压系数，W为所述SA-LIGBT的沟道宽度，wrd1为所述沟道宽度(W)的修正参数，Vg,e表示SA-LIGBT的栅极与发射极之间的电压；TEMP为系统温度，Td1为所述漏端电阻Rd1的一阶指数项的温度系数，Td2为所述漏端电阻Rd1的二阶指数项的温度系数。
  9. 根据权利要求8所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述基极电阻Rb1的压控数学表达式为：
    Rb1＝Rb_tfac×Rbw1×(1+Prwge2×Vg,e Erge2+Prwbd2×Vb1,e Erbd)/(W×1E6)wrd2
    其中，Rb_tfac＝(1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25))；
    Vb1,e表示所述PNP三极管(QP1)的基极(b1)与所述NPN三极管(QN1)的发射极(e)两节点之间的电压，Rbw1表示电压为零时的所述基极电阻(Rb1)的电阻值，Prwge2为所述基极电阻(Rb1)的第一电压系数，Vg,e是所述NMOS管(M1)的栅极(g)与所述NPN三极管(QN1) 的发射极(e)之间的电压的绝对值，Erge2为所述基极电阻(Rb1)的第一电压的幂指数项系数，Prwbd2为所述基极电阻(Rb1)的第二电压系数，Erbd为所述基极电阻(Rb1)的第二电压的幂指数项系数，wrd2为所述沟道宽度(W)的修正参数；Tb1为所述基极电阻(Rb1)的一阶指数项的温度系数，Tb2为所述基极电阻(Rb1)的二阶指数项的温度系数。
  10. 根据权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型。
  11. 根据权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，其特征在于，还包括基极电阻(Rp)，所述基极电阻(Rp)的一端连接所述NPN三极管(QN1)的基极，另一端连接所述PNP三极管(QP1)的发射极。
  12. 一种阳极短路横向绝缘栅双极晶体管模型的建模方法，包括：
    步骤A，建立如权利要求1所述的阳极短路横向绝缘栅双极晶体管模型，并设置所述SA-LIGBT的器件参数；
    步骤B，调节所述NMOS管(M1)的电容-电压参数以拟合电容-电压曲线；
    步骤C，调节所述NMOS管(M1)的阈值电压参数以拟合所述SA-LIGBT的开启电压；
    步骤D，调节所述NPN三极管(QN1)的器件参数以拟合所述SA-LIGBT开启时所述SA-LIGBT的最小VCE的转移特性曲线；
    步骤E，调节所述NMOS管(M1)的线性区参数和所述PNP三极管(QP1)的器件参数以拟合所述SA-LIGBT的VCE处于第一电压值区间时的转移特性曲线；
    步骤F，调节所述NMOS管(M1)的饱和区参数和所述PNP三极管(QP1)的器件参数以拟合所述SA-LIGBT的VCE处于第二电压值区间时的转移特性曲线，以及拟合所述SA-LIGBT的输出特性曲线；所述第二电压值区间的左端点的电压值大于所述第一电压值区间的右端点的电压值；
    步骤G，调节温度系数以拟合所述SA-LIGBT的温度特性曲线；
    步骤H，调节所述第二受控电流源(G2)的参数以拟合所述SA-LIGBT的开关特性。
  13. 根据权利要求12所述的阳极短路横向绝缘栅双极晶体管模型的建模方法，其特征在于，所述阳极短路横向绝缘栅双极晶体管模型还包括：
    漏端电阻(Rd1)，一端连接所述NMOS管(M1)的漏极，另一端连接所述第二受控电流源(G2)与所述NPN三极管(QN1)的发射极的公共端；
    基极电阻(Rb1)，一端连接所述PNP三极管(QP1)的基极，另一端连接所述第二受控电 流源(G2)与所述NPN三极管(QN1)的发射极的公共端；
    外部电容(C0)，一端连接所述NMOS管(M1)的栅极，另一端连接所述NPN三极管(QN1)的集电极；
    基极电阻(Rp)，一端连接所述NPN三极管(QN1)的基极，另一端连接所述PNP三极管(QP1)的发射极；
    所述步骤B包括：调节所述NMOS管(M1)的电容-电压参数以及所述外部电容(C0)的参数以拟合电容-电压曲线；
    所述步骤D包括：调节所述NPN三极管(QN1)的器件参数和所述基极电阻(Rp)的电阻值以拟合所述最小VCE的转移特性曲线；
    所述步骤E包括：调节所述NMOS管(M1)的线性区参数、所述PNP三极管(QP1)的器件参数以及所述基极电阻(Rb1)的参数以拟合所述VCE处于所述第一电压值区间时的所述转移特性曲线；
    在所述步骤F之后还包括步骤F1：调整所述漏端电阻(Rd1)以拟合所述输出特性曲线的线性区部分。
  14. 根据权利要求13所述的阳极短路横向绝缘栅双极晶体管模型的建模方法，其特征在于，所述阳极短路横向绝缘栅双极晶体管模型还包括第一受控电流源(G1)，所述第一受控电流源(G1)的一端连接所述PNP三极管(QP1)的发射极，另一端连接所述PNP三极管(QP1)的集电极，所述第一受控电流源(G1)产生的电流受控于所述PNP三极管(QP1)的电流；
    在所述步骤F1之后还包括步骤F2：调整所述第一受控电流源(G1)的参数以拟合所述SA-LIGBT的自热效应。
  15. 根据权利要求14所述的阳极短路横向绝缘栅双极晶体管模型的建模方法，其特征在于，所述步骤F2之后只在所述步骤B、步骤C、步骤D、步骤F、步骤F1、步骤F2的拟合精度均满足要求的情况下才执行所述步骤G，否则返回所述步骤B；
    在所述步骤G之后以及所述步骤H之前，若所述温度特性曲线的拟合精度不满足要求，则返回所述步骤G。
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