WO2024027218A1 - 开关绕组电机驱动系统及其控制方法、装置、存储介质 - Google Patents

开关绕组电机驱动系统及其控制方法、装置、存储介质 Download PDF

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Publication number
WO2024027218A1
WO2024027218A1 PCT/CN2023/090286 CN2023090286W WO2024027218A1 WO 2024027218 A1 WO2024027218 A1 WO 2024027218A1 CN 2023090286 W CN2023090286 W CN 2023090286W WO 2024027218 A1 WO2024027218 A1 WO 2024027218A1
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Prior art keywords
inverter
phase
target voltage
drive signal
share
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PCT/CN2023/090286
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English (en)
French (fr)
Inventor
张杰楠
冯君璞
龙谭
徐云松
胡斌
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广东美的制冷设备有限公司
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Publication of WO2024027218A1 publication Critical patent/WO2024027218A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
    • H02P21/14—Estimation or adaptation of machine parameters, e.g. flux, current or voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
    • H02P21/22—Current control, e.g. using a current control loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation

Definitions

  • the present disclosure relates to the field of motor control technology, and in particular to an open-winding motor drive system and its control method, device, and storage medium.
  • the open-winding motor drive system is a double-end power supply motor system topology formed by opening the neutral point of the winding of a conventional motor and connecting an IPM (Intelligent Power Module) in series at each end.
  • IPM Intelligent Power Module
  • the conventional space vector modulation algorithm needs to generate 12 drive signals to coordinately control the turn-on or turn-off of the 12 switching tubes of the two IPMs.
  • a single MCU (Micro Controller Unit) chip is generally used to output 12 driving signals to drive two IPMs.
  • the MCU chip not only needs to meet the ability to output 12 driving signals, but also generates 12 driving signals. It occupies a large amount of computing resources of the MCU chip.
  • the present disclosure aims to solve one of the technical problems in the related art, at least to a certain extent.
  • the first purpose of the present disclosure is to propose a control method for an open-winding motor drive system.
  • the first inverter and the second inverter share multiple drive signal lines, thereby reducing the use of the control chip interface. And it reduces the computing resources required to control the chip.
  • a second object of the present disclosure is to provide a computer-readable storage medium.
  • a third object of the present disclosure is to provide an open-winding motor drive system.
  • the fourth object of the present disclosure is to provide a control device for an open-winding motor drive system.
  • a fifth object of the present disclosure is to propose another open-winding motor drive system.
  • a control method for an open-winding motor drive system includes a first inverter and a second inverter arranged corresponding to both ends of the winding of the open-winding motor.
  • the first inverter and the second inverter share multiple drive signal lines.
  • the method includes: obtaining the target voltage vectors of the first inverter and the second inverter to obtain two target voltage vectors; according to the two target voltages Vector generates multiple drive signals; convert multiple drive signals into Input to multiple drive signal lines to drive and control the first inverter and the second inverter.
  • target voltage vectors of the first inverter and the second inverter are obtained, multi-channel drive signals are generated according to the two target voltage vectors, and the multi-channel drive signals are The signal is input to the multi-channel drive signal line to drive and control the first inverter and the second inverter, wherein the first inverter and the second inverter share the multi-channel drive signal line. Therefore, by sharing multiple drive signal lines between the first inverter and the second inverter, the use of the control chip interface is reduced, and due to the reduction in the use of the control chip interface, the drive signals that the control chip needs to generate are also reduced accordingly. This reduces the computing resources required to control the chip.
  • the first inverter and the second inverter share multiple drive signal lines, including: the a-phase upper bridge arm of the first inverter and the b-phase upper bridge arm of the second inverter.
  • the arms share a drive signal line; the b-phase upper arm of the first inverter and the c-phase upper arm of the second inverter share a drive signal line; the c-phase upper arm of the first inverter and the second inverter
  • the a-phase upper arm of the inverter shares the drive signal line; the a-phase lower arm of the first inverter and the b-phase lower arm of the second inverter share the drive signal line; the b-phase lower arm of the first inverter shares the drive signal line
  • the arm and the c-phase lower arm of the second inverter share a drive signal line; the c-phase lower arm of the first inverter shares a drive signal line with the a-phase lower arm of the second inverter.
  • the first inverter and the second inverter share multiple drive signal lines, including: the a-phase upper arm of the first inverter and the a-phase lower arm of the second inverter.
  • the bridge arms share a driving signal line; the b-phase upper bridge arm of the first inverter and the b-phase lower bridge arm of the second inverter share a driving signal line; the c-phase upper bridge arm of the first inverter and the second inverter
  • the C-phase lower arm of the inverter shares a drive signal line; the A-phase lower arm of the first inverter and the A-phase upper arm of the second inverter share a drive signal line; the B-phase lower arm of the first inverter shares a drive signal line.
  • the bridge arm and the b-phase upper bridge arm of the second inverter share a drive signal line; the c-phase lower bridge arm of the first inverter shares a drive signal line with the c-phase upper bridge arm of the second inverter.
  • generating a multi-channel driving signal based on two target voltage vectors includes: determining the location of the combined voltage vector of the two target voltage vectors based on the positions of the two target voltage vectors in a two-phase rotating coordinate system. sectors; generate multiple drive signals based on the sector and any one of the two target voltage vectors.
  • generating a multi-channel driving signal based on two target voltage vectors includes: determining the result of a composite voltage vector of the two target voltage vectors based on the positions of the two target voltage vectors in a two-phase stationary coordinate system. sector at; generate multiple drive signals based on the sector and any one of the two target voltage vectors.
  • generating a multi-channel driving signal according to the sector and any one of the two target voltage vectors includes: obtaining the action time of the basic voltage space vector corresponding to any target voltage vector according to the sector. ;Acquire the space voltage vector switching point based on the action time; generate multiple drive signals based on the voltage space vector switching point.
  • a computer-readable storage medium which stores a control program for an open-winding motor drive system.
  • the control program When the program is executed by a processor, the control program of any of the foregoing embodiments is implemented. Control method of open winding motor drive system.
  • the first inverter and the second inverter share multiple drive signal lines, thereby reducing the use of the control chip interface and reducing the computing resources required for the control chip.
  • an open-winding motor drive system including: a memory, a processor, and a control program of the open-winding motor drive system stored in the memory and executable on the processor. , when the processor executes the program, the control method of the open-winding motor drive system of any of the foregoing embodiments is implemented.
  • the processor executes the computer program of the above-mentioned control method of the open-winding motor drive system, and the first inverter and the second inverter share multiple drive signal lines, thereby reducing Control the use of chip interfaces and reduce the computing resources required to control the chip.
  • a control device for an open-winding motor drive system includes a first inverter and a second inverter arranged corresponding to both ends of the winding of the open-winding motor.
  • the first inverter and the second inverter share multiple drive signal lines
  • the device includes: an acquisition module, used to acquire the target voltage vectors of the first inverter and the second inverter, and obtain two target voltage vectors;
  • the generation module is used to generate multi-channel driving signals according to the two target voltage vectors;
  • the control module is used to input the multi-channel driving signals to the multi-channel driving signal lines to drive and control the first inverter and the second inverter.
  • the target voltage vectors of the first inverter and the second inverter are obtained through the acquisition module, and the multi-channel drive signals are generated according to the two target voltage vectors through the generation module. , and input multiple drive signals to the multiple drive signal lines through the control module to drive and control the first inverter and the second inverter, wherein the first inverter and the second inverter share multiple drive signals. drive signal lines. Therefore, by sharing multiple drive signal lines between the first inverter and the second inverter, the use of the control chip interface is reduced, and due to the reduction in the use of the control chip interface, the drive signals that the control chip needs to generate are also reduced accordingly. This reduces the computing resources required to control the chip.
  • another open-winding motor driving system including: an open-winding motor; a first inverter and a second inverter, and a first inverter and a second inverter.
  • the inverter is arranged at both ends of the winding of the open-winding motor, and the first inverter and the second inverter share multiple drive signal lines.
  • the first inverter and the second inverter share multiple drive signal lines, thereby reducing the use of the control chip interface, and due to the reduction in the use of the control chip interface, the control chip The number of drive signals that need to be generated is correspondingly reduced, thereby reducing the computing resources required to control the chip.
  • Figure 1 is a topology diagram of an open-winding motor drive system according to an embodiment of the present disclosure
  • Figure 2 is a topology diagram of an open-winding motor drive system according to another embodiment of the present disclosure.
  • Figure 3 is a control block diagram of an open-winding motor drive system according to one embodiment of the present disclosure
  • Figure 4 is a schematic flowchart of a control method of an open-winding motor drive system according to an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the sectors corresponding to the open winding motor drive system shown in Figure 1;
  • Figure 6 is a schematic diagram of the sectors corresponding to the open winding motor drive system shown in Figure 2;
  • Figure 7 is a driving signal timing diagram corresponding to the open winding motor drive system shown in Figure 1;
  • Figure 8 is a driving signal timing diagram corresponding to the open winding motor drive system shown in Figure 2;
  • Figure 9 is a waveform comparison diagram of the three-phase current and zero-sequence current corresponding to the open-winding motor drive system shown in Figure 1 and the three-phase current and zero-sequence current corresponding to the traditional open-winding motor drive system;
  • Figure 10 is a waveform diagram of the three-phase current and zero sequence current corresponding to the open winding motor drive system shown in Figure 2;
  • Figure 11 is a schematic structural diagram of an open-winding motor drive system according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a control device of an open-winding motor drive system according to an embodiment of the present disclosure.
  • the open-winding motor driving system includes: a first inverter 10 , a second inverter 20 , an open-winding motor 30 and an electronic control system.
  • the DC sides of the first inverter 10 and the second inverter 20 are both connected to the DC power supply DC, and the AC sides of the first inverter 10 and the second inverter 20 are respectively connected to the windings of the open-winding motor 30
  • the neutral point of a conventional Y-shaped motor is opened, and an inverter (such as an IPM module) is connected to both ends of the motor winding.
  • the first inverter 10 and the second inverter 20 share a multi-channel drive. signal line.
  • the electronic control system includes a control chip 40 and a sampling unit 50. The electronic control system coordinates and controls the two inverters to drive the open-winding motor 30 to work.
  • the first inverter 10 and the second inverter 20 share multiple drive signal lines, including:
  • the a-phase upper arm of the first inverter 10 and the b-phase upper arm of the second inverter 20 share a driving signal line, and the first pin of the control chip 40 is used to provide the a-phase upper arm of the first inverter 10
  • the upper arm input drive signal PWM_A1+ is the same as the b-phase upper arm input drive signal PWM_B2+ of the second inverter 20, and the drive signal PWM_A1+ is the same as the drive signal PWM_B2+;
  • the b-phase upper arm of the first inverter 10 and the c-phase upper arm of the second inverter 20 share a driving signal line, and the second pin of the control chip 40 is used to provide the b-phase of the first inverter 10
  • the upper arm inputs the driving signal PWM_B1+ and supplies it to the second inverter 20
  • the c-phase upper bridge arm inputs the drive signal PWM_C2+, and the drive signal PWM_B1+ is the same as the drive signal PWM_C2+;
  • the c-phase upper arm of the first inverter 10 and the a-phase upper arm of the second inverter 20 share a driving signal line, and the third pin of the control chip 40 is used to provide the c-phase upper arm of the first inverter 10
  • the upper arm input drive signal PWM_C1+ is the same as the drive signal PWM_A2+ supplied to the a-phase upper arm of the second inverter 20, and the drive signal PWM_C1+ is the same as the drive signal PWM_A2+;
  • the phase a lower arm of the first inverter 10 and the phase b lower arm of the second inverter 20 share a driving signal line, and the fourth pin of the control chip 40 is used to provide the phase a of the first inverter 10
  • the lower arm input drive signal PWM_A1- is the same as the b-phase lower arm input drive signal PWM_B2- of the second inverter 20, and the drive signal PWM_A1- is the same as the drive signal PWM_B2-;
  • the b-phase lower arm of the first inverter 10 and the c-phase lower arm of the second inverter 20 share a driving signal line, and the fifth pin of the control chip 40 is used to provide the b-phase of the first inverter 10
  • the lower arm input drive signal PWM_B1- is the same as the c-phase lower arm input drive signal PWM_C2- of the second inverter 20, and the drive signal PWM_B1- is the same as the drive signal PWM_C2-;
  • the c-phase lower arm of the first inverter 10 and the a-phase lower arm of the second inverter 20 share a driving signal line, and the sixth pin of the control chip 40 is used to provide the c-phase lower arm of the first inverter 10
  • the lower arm input drive signal PWM_C1- is the same as the drive signal PWM_A2- input to the a-phase lower arm of the second inverter 20, and the drive signal PWM_C1- is the same as the drive signal PWM_A2-.
  • the first inverter 10 and the second inverter 20 share multiple drive signal lines, including:
  • the a-phase upper arm of the first inverter 10 and the a-phase lower arm of the second inverter 20 share a driving signal line, and the first pin of the control chip 40 is used to provide the a-phase signal of the first inverter 10
  • the upper arm input drive signal PWM_A1+ and the a-phase lower arm input drive signal PWM_A2- to the second inverter 20, and the drive signal PWM_A1+ and the drive signal PWM_A2- are the same;
  • the b-phase upper arm of the first inverter 10 and the b-phase lower arm of the second inverter 20 share a driving signal line, and the second pin of the control chip 40 is used to provide the b-phase of the first inverter 10
  • the upper arm input drive signal PWM_B1+ and the b-phase lower arm input drive signal PWM_B2- to the second inverter 20, and the drive signal PWM_B1+ and the drive signal PWM_B2- are the same;
  • the c-phase upper arm of the first inverter 10 and the c-phase lower arm of the second inverter 20 share a driving signal line, and the third pin of the control chip 40 is used to provide the c-phase
  • the upper arm input drive signal PWM_C1+ and the c-phase lower arm input drive signal PWM_C2- to the second inverter 20, and the drive signal PWM_C1+ and the drive signal PWM_C2- are the same;
  • the phase a lower arm of the first inverter 10 and the phase a upper arm of the second inverter 20 share a driving signal line, and the fourth pin of the control chip 40 is used to provide the phase a of the first inverter 10
  • the lower arm input drive signal PWM_A1- and the a-phase upper arm input drive signal PWM_A2+ of the second inverter 20 are the same, and the drive signal PWM_A1- is the same as the drive signal PWM_A2+;
  • the b-phase lower arm of the first inverter 10 and the b-phase upper arm of the second inverter 20 share a driving signal line, and the fifth pin of the control chip 40 is used to provide the b-phase signal of the first inverter 10
  • the lower arm input drive signal PWM_B1- is input to the b-phase upper arm drive signal PWM_B2+ of the second inverter 20, and the drive signal PWM_B1- is the same as the drive signal PWM_B2+;
  • the c-phase lower arm of the first inverter 10 and the c-phase upper arm of the second inverter 20 share a driving signal line, and the sixth pin of the control chip 40 is used to provide the c-phase of the first inverter 10
  • the lower arm input drive signal PWM_C1- and is given to the second inverter 20
  • the c-phase upper bridge arm inputs the drive signal PWM_C2+, and the drive signal PWM_C1- is the same as the drive signal PWM_C2+.
  • the control chip 40 includes a zero-sequence current control unit 41 , a three-phase current control unit 42 and a drive signal generation unit 43 , where the zero-sequence current control unit 41 is used to obtain the three-phase current Ia according to the sampling unit 50 , Ib and Ic reconstruct the zero-sequence current I0, and implement relevant control based on the zero-sequence current I0 according to the zero-sequence current I0; the three-phase current control unit 42 is used to implement relevant control based on the three-phase currents Ia, Ib and Ic; drive The signal generation unit 43 is used to generate 6-channel drives based on the signals output by the zero-sequence current control unit 41 and the three-phase current control unit 42, using a certain algorithm, such as SVPWM (Space Vector Pulse Width Modulation, Space Vector Pulse Width Modulation) algorithm. signals, and input 6 channels of driving signals to the first inverter 10 and the second inverter
  • SVPWM Space Vector
  • the sampling unit 50 includes current sensing resistors R1, R2 and R3.
  • the current sensing resistors R1, R2 and R3 can be connected in series between the lower bridge arms of phase a, phase b and phase c of the second inverter 20 and the negative pole of the direct current power supply DC, respectively.
  • the current of the three-phase bridge arm of the second inverter 20 is sampled through the current sensing resistors R1, R2 and R3.
  • the current sensing resistors R1, R2 and R3 can also be connected in series between the lower arms of the a-phase, b-phase and c-phase of the first inverter 10 and the negative pole of the direct current power supply DC.
  • the current sensing resistor can be a single resistor, and the sampling unit 50 can also be a current transformer, etc. There is no specific limitation here.
  • the first inverter and the second inverter share multiple drive signal lines, which reduces the use of control chip interfaces.
  • the original 12 interfaces are reduced to 6 interfaces, and because the control chip interface With the reduction of use, the driving signals that the control chip needs to generate are also reduced accordingly, thereby reducing the computing resources required by the control chip; and, this embodiment only uses one control chip, compared with using two control chips to drive two inverters respectively.
  • the inverter can effectively reduce the cost and design difficulty of the electronic control board.
  • FIG. 4 is a schematic flowchart of a control method of an open-winding motor drive system according to an embodiment of the present disclosure. As shown in Figure 4, the control method of the open-winding motor drive system includes the following steps:
  • S101 Obtain the target voltage vectors of the first inverter and the second inverter, and obtain two target voltage vectors.
  • two target voltage vectors denoted as the first target voltage vector VA and the second target voltage vector VB, can be output by coordinating the driving signals of the first inverter and the second inverter.
  • the sector in which the composite voltage vector is located can be determined first based on the two target voltage vectors, and then the multi-channel driving signal is generated based on the sector and any one of the two target voltage vectors.
  • both the first inverter and the second inverter include six switching tubes. At any time, only three switching tubes of each inverter are turned on, and the upper and lower arms of the same bridge arm are switched on. The switch tubes of the bridge arms are interlocked, so each inverter has eight basic switching states. If the number "1" is used to indicate that the corresponding upper bridge arm is in the on state, and the lower bridge arm is in the off state, use The number “0" means that the corresponding upper bridge arm is in a disconnected state, while the lower bridge arm is in a conductive state.
  • the eight switch states correspond to eight switch values, which are "000”, "100", "110”,...
  • these eight switch values correspond to eight voltage space vectors, specifically including six basic voltage space vectors A to F with equal amplitude and mutual phase difference of ⁇ /3, and two zero voltage space vectors.
  • the six basic voltage space vectors divide the complex plane into six sectors, namely sectors I, II,...,VI, with two zero-voltage space vectors located in the center.
  • the sector in which the synthesized voltage vector VOEW is located can be determined based on the first target voltage vector VA and the second target voltage vector VB, and then based on A multi-channel drive signal is generated based on the sector where the sector is located and the first target voltage vector VA, or a multi-channel drive signal is generated based on the sector where the sector is located and the second target voltage vector VB.
  • generating a multi-channel driving signal based on two target voltage vectors includes: determining the sector where the composite voltage vector of the two target voltage vectors is located based on the positions of the two target voltage vectors in the two-phase rotating coordinate system. ; Generate multiple drive signals based on the sector and any one of the two target voltage vectors.
  • the required synthetic voltage vector VOEW is the voltage vector under the two-phase rotating coordinate system ( ⁇ - ⁇ coordinate system)
  • the first target voltage vector Both VA and the second target voltage vector VB are voltage vectors in a two-phase stationary coordinate system ( ⁇ - ⁇ coordinate system).
  • the coordinate system is transformed from a two-phase stationary coordinate system ( ⁇ - ⁇ coordinate system) to a two-phase rotating coordinate system ( ⁇ - ⁇ coordinate system), and then based on the mathematics of the two target voltage vectors VA and VB and the two-phase rotating coordinate system
  • the geometric relationship determines the sector where the composite voltage vector VOEW is located, and then generates multiple drive signals based on the sector and one of the target voltage vectors VA or VB.
  • the second target voltage vector VB is first reversely processed, and then the two target voltage vectors are The coordinates of vectors VA and VB are converted from two-phase stationary coordinates to two-phase rotating coordinates, and then the sector where the synthetic voltage vector VOEW is located is determined based on the mathematical relationship between the two converted target voltage vectors VA and VB and the two-phase rotating coordinate system. , if it is in sector I, then multiple drive signals are generated according to the sector I and one of the target voltage vectors VA or VB.
  • generating a multi-channel driving signal based on two target voltage vectors includes: determining the sector where the combined voltage vector of the two target voltage vectors is located based on the positions of the two target voltage vectors in a two-phase stationary coordinate system. area; generate multiple drive signals according to the sector and any one of the two target voltage vectors.
  • the required synthetic voltage vector VOEW is the voltage vector in the two-phase stationary coordinate system
  • the first target voltage vector VA and the second target voltage vector VB is also a voltage vector in a two-phase stationary coordinate system. Therefore, after obtaining the two target voltage vectors VA and VB, there is no need to perform coordinate conversion. It is directly based on the mathematics of the two target voltage vectors VA and VB and the two-phase stationary coordinate system. The geometric relationship determines the sector where the composite voltage vector VOEW is located, and then generates multiple drive signals based on the sector and one of the target voltage vectors VA or VB.
  • two target voltage vectors VA and When VB first perform reverse processing on the second target voltage vector VB, and then determine the sector where the synthetic voltage vector VOEW is located based on the mathematical relationship between the two target voltage vectors VA and VB and the two-phase stationary coordinate system. I, and then generate multiple driving signals according to the sector I and one of the target voltage vectors VA or VB.
  • the method of sharing the drive signal lines is determined based on coordinated control of the first inverter and the second inverter. Therefore, after obtaining the sector where the composite voltage vector is located, the multi-channel driving signals generated based on the sector and one of the target voltage vectors VA or VB can satisfy the requirements of the first inverter and the second inverter at the same time. The control requirements of the inverter are greatly reduced, thereby greatly reducing the occupation of computing resources of the control chip.
  • generating multiple drive signals according to the sector and any one of the two target voltage vectors includes: obtaining the action time of the basic voltage space vector corresponding to any target voltage vector according to the sector; The voltage space vector switching point is obtained based on the action time; multi-channel driving signals are generated based on the voltage space vector switching point.
  • a multi-channel driving signal can be generated based on sector I and the first target voltage vector VA. Specifically, it is determined based on sector I first.
  • Two basic voltage space vectors (1,0,0) and (1,1,0) and based on the amplitude and position of the first target voltage vector VA, use the volt-second balance principle to calculate the two basic voltage space vectors (1 ,0,0) and (1,1,0), and thus obtain the action time of two zero-voltage space vectors (0,0,0) and (1,1,1); then, based on 7
  • the segmented SVPWM algorithm determines the order of action of two basic voltage space vectors and two zero voltage space vectors.
  • the two basic voltage space vectors and two zero voltage space vectors are The order of action of the voltage space vector is (0,0,0), (1,0,0), (1,1,0), (1,1,1), (1,1,0), (1 ,0,0), (0,0,0).
  • the 7-segment voltage space vector includes 3 segments of zero voltage space vector and 4 segments of basic voltage space vector, and the 3 segments of zero voltage space vector are located at the beginning, middle and end of the driving signal waveform respectively.
  • the space voltage vector switching point can be determined.
  • the first space voltage vector switching point is the first inverse The a-phase upper arm of the inverter switches from off to on, and the corresponding switching time is T0/4;
  • the second space voltage vector switching point is when the b-phase upper arm of the first inverter switches from off to On, the corresponding switching time is T0/4+T1/2;
  • the third space voltage vector switching point is when the c-phase upper arm of the first inverter switches from off to on, and the corresponding switching time is T0 /4+T1/2+T2/2;
  • the fourth space voltage vector switching point is when the c-phase upper arm of the first inverter switches from on to off, and the corresponding switching time is T0/4+T1/ 2+T2/2+T7/4+T7/4; and so on.
  • T0 represents the action time of the zero voltage space vector (0,0,0)
  • T1 represents the action time of the basic voltage space vector (1,0,0)
  • T2 represents the action time of the basic voltage space vector (1,1,0).
  • Action time represents the action time of zero voltage space vector (1,1,1)
  • Ts T1+T2+T0+T7, Ts is the control period.
  • multi-channel driving signals can also be generated based on the 5-segment SVPWM algorithm, but it inserts zero-voltage vectors intensively and has larger harmonic components. Therefore, the sampling 5-segment SVPWM algorithm has lower harmonic components.
  • S103 Input multiple drive signals to multiple drive signal lines to drive and control the first inverter and the second inverter.
  • the 6 drive signals when generating 6 drive signals based on the sector where the composite voltage vector VOEW is located and the first target voltage vector VA, the 6 drive signals are passed through the 6 drive signal lines shown in Figure 1 Input to the first inverter and the second inverter to drive the open winding motor to work.
  • the drive signal waveforms of the first inverter and the second inverter are shown in Figure 7.
  • the drive signal of the second inverter The waveform is determined based on the driving signal waveform of the first inverter and the connection mode of the driving signal lines.
  • the drive signal is shared based on the phase a upper arm of the first inverter and the phase b upper arm of the second inverter. line, the b-phase upper bridge arm of the second inverter is turned on.
  • the 6 drive signals are passed through the 6 drive signals shown in Figure 2
  • the input line is input to the first inverter and the second inverter to drive the open winding motor to work.
  • the drive signal waveforms of the first inverter and the second inverter are shown in Figure 8.
  • the drive signal of the second inverter The signal waveform is determined based on the driving signal waveform of the first inverter and the connection mode of the driving signal lines.
  • the drive signal is shared based on the phase a upper arm of the first inverter and the phase a lower arm of the second inverter. line, the lower bridge arm of phase a of the second inverter is turned on.
  • the use of the control chip interface is reduced, and due to the reduction in the use of the control chip interface, the control chip needs to generate corresponding drive signals. Reduce, thereby reducing the computing resources required to control the chip.
  • the common mode voltage generated by the common bus of the first inverter and the second inverter can also be effectively eliminated, thereby eliminating the common mode voltage caused by Zero sequence current.
  • the common mode voltage generated by the first inverter is shown in formula (1):
  • U com1 represents the common mode voltage generated by the first inverter
  • U a1o1 represents the voltage between the midpoint O1 of the two series-connected bus capacitors C1 and C2 in Figure 1 and the midpoint a1 of the phase a bridge arm
  • U b1o1 represents the voltage between the midpoint O1 of the bus capacitors C1 and C2 and the midpoint b1 of the b-phase bridge arm
  • U c1o1 represents the voltage between the midpoint O1 of the bus capacitors C1 and C2 and the midpoint c1 of the c-phase bridge arm. Voltage.
  • the common mode voltage generated by the second inverter is shown in formula (2):
  • U com2 represents the common mode voltage generated by the second inverter
  • U a2o2 represents the voltage between the midpoint O2 of the two series-connected bus capacitors C3 and C4 in Figure 1 and the midpoint a2 of the phase a bridge arm
  • U b2o2 represents the voltage between the midpoint O2 of the bus capacitors C3 and C4 and the midpoint b2 of the b-phase bridge arm
  • U c2o2 represents the voltage between the midpoint O2 of the bus capacitors C3 and C4 and the midpoint c2 of the c-phase bridge arm. Voltage.
  • U o1o2 represents the system common mode voltage, that is, the voltage between the midpoint O1 of the bus capacitors C1 and C2 and the midpoint O2 of the bus capacitors C3 and C4.
  • U dc represents the DC power supply voltage, that is, the bus voltage
  • Sa1, Sb1 and Sc1 represent the driving signals of the a-phase upper arm, b-phase upper arm and c-phase upper arm of the first inverter respectively
  • Sa2, Sb2 and Sc2 respectively represent the driving signals of the a-phase upper arm, b-phase upper arm and c-phase upper arm of the second inverter.
  • Figure 9 shows a comparison diagram of the three-phase current and zero-sequence current obtained by using the traditional open-winding motor drive system and the three-phase current and zero-sequence current obtained by using the open-winding motor drive system shown in Figure 1. It can be seen from Figure 9 It can be seen that the zero-sequence current peak value obtained by using the traditional open-winding motor drive system is around 2A. The sinusoidality of the three-phase current becomes worse due to the influence of the zero-sequence current. The control difficulty increases and the device loss also increases. Using Figure 1 The zero-sequence current peak of the open-winding motor drive system shown is 2.5*10 ⁇ -6A, which is approximately zero. The sinusoidality of the three-phase current is good, and the system disturbance and device loss are reduced.
  • Figure 10 shows the waveform diagrams of the three-phase current and zero-sequence current obtained by using the open-winding motor drive system shown in Figure 2. It can be seen from Figure 10 that although the open-winding motor drive system shown in Figure 2 cannot eliminate system common Mode voltage, but it can achieve the maximum output effect and improve the output capability of the system.
  • the first inverter and the second inverter share multiple drive signal lines, which reduces the use of the control chip interface, and due to the control With the reduction in the use of chip interfaces, the drive signals that need to be generated by the control chip are also reduced accordingly, thereby reducing the computing resources required for the control chip and reducing the difficulty and cost of hardware design.
  • embodiments of the present disclosure also provide a computer-readable storage medium on which a control program for an open-winding motor drive system is stored.
  • a control program for an open-winding motor drive system is stored.
  • the program is executed by a processor, the open-winding method of any of the foregoing embodiments is implemented. Control method of motor drive system.
  • the first inverter and the second inverter share multiple drive signal lines, thereby reducing the use of the control chip interface and reducing the computing resources required for the control chip.
  • embodiments of the present disclosure also provide an open winding motor driving system.
  • the open-winding motor drive system 200 includes a memory 210, a processor 220, and a control program for the open-winding motor drive system that is stored in the memory 210 and can be run on the processor 220.
  • the processor 220 executes the program, Implement the control method of the open-winding motor drive system of any of the aforementioned embodiments.
  • the processor executes the computer program of the above-mentioned control method of the open-winding motor drive system, and the first inverter and the second inverter share multiple drive signal lines, thereby reducing Control the use of chip interfaces and reduce the computing resources required to control the chip.
  • embodiments of the present disclosure also provide a control device for an open winding motor drive system.
  • the system includes a first inverter and a second inverter arranged corresponding to two ends of the winding of the open-winding motor, and the first inverter and the second inverter share multiple drive signal lines.
  • the control device includes: an acquisition module 310, a generation module 320 and a control module 330.
  • the acquisition module 310 is used to acquire the target voltage vectors of the first inverter and the second inverter, and obtain two target voltage vectors; the generation module 320 is used to generate multi-channel driving signals according to the two target voltage vectors; the control module 330 is used to input multiple drive signals to multiple drive signal lines to drive and control the first inverter and the second inverter.
  • the first inverter and the second inverter share multiple drive signal lines, including: the a-phase upper bridge arm of the first inverter shares the b-phase upper bridge arm of the second inverter.
  • Drive signal line; the b-phase upper arm of the first inverter and the c-phase upper arm of the second inverter share the drive signal line; the c-phase upper arm of the first inverter and the second inverter
  • the a-phase upper arm shares a drive signal line;
  • the a-phase lower arm of the first inverter shares a drive signal line with the second inverter's b-phase lower arm;
  • the first inverter's b-phase lower arm and the second inverter share a drive signal line.
  • the c-phase lower arm of the second inverter shares a drive signal line; the c-phase lower arm of the first inverter and the a-phase lower arm of the second inverter share a drive signal line.
  • the first inverter and the second inverter share multiple drive signal lines, including: the phase a upper bridge arm of the first inverter shares the phase a lower bridge arm of the second inverter.
  • the drive signal line; the b-phase upper arm of the first inverter and the b-phase lower arm of the second inverter share the drive signal line; the c-phase upper arm of the first inverter and the second inverter’s
  • the c-phase lower arm shares a drive signal line; the a-phase lower arm of the first inverter and the second inverter share a drive signal line; the b-phase lower arm of the first inverter and the second inverter share a drive signal line.
  • the b-phase upper arm of the second inverter shares a drive signal line; the c-phase lower arm of the first inverter and the c-phase upper arm of the second inverter share a drive signal line.
  • the generation module 320 is specifically configured to: determine the sector where the composite voltage vector of the two target voltage vectors is located based on the positions of the two target voltage vectors in the two-phase rotating coordinate system; Any target voltage vector among the target voltage vectors generates multiple drive signals.
  • the generation module 320 is specifically configured to: according to two target voltage vectors in a two-phase stationary coordinate system position, determine the sector where the composite voltage vector of the two target voltage vectors is located; generate a multi-channel drive signal based on the sector and any one of the two target voltage vectors.
  • the generation module 320 is specifically configured to: obtain the action time of the basic voltage space vector corresponding to any target voltage vector according to the sector; obtain the voltage space vector switching point according to the action time; generate multiple voltage space vector switching points according to the voltage space vector. road drive signal.
  • control device of the open-winding motor drive system in the embodiment of the present disclosure corresponds to the specific implementation of the control method of the open-winding motor drive system in the aforementioned embodiment of the present disclosure, and will not be described again here. .
  • the target voltage vectors of the first inverter and the second inverter are obtained through the acquisition module, and the multi-channel drive signals are generated according to the two target voltage vectors through the generation module. , and input multiple drive signals to the multiple drive signal lines through the control module to drive and control the first inverter and the second inverter, wherein the first inverter and the second inverter share multiple drive signals. drive signal lines. Therefore, by sharing multiple drive signal lines between the first inverter and the second inverter, the use of the control chip interface is reduced, and due to the reduction in the use of the control chip interface, the drive signals that the control chip needs to generate are also reduced accordingly. This reduces the computing resources required to control the chip.
  • embodiments of the present disclosure also provide another open winding motor driving system.
  • the driving system includes: an open-winding motor 30 , a first inverter 10 and a second inverter 20 .
  • the first inverter 10 and the second inverter 20 are arranged corresponding to the two ends of the winding of the open-winding motor 30 , and the first inverter 10 and the second inverter 20 share multiple drive signal lines.
  • the first inverter 10 and the second inverter 20 share multiple drive signal lines, including: the a-phase upper arm of the first inverter 10 and the b-phase of the second inverter 20
  • the upper bridge arms share a drive signal line;
  • the b-phase upper arm of the first inverter 10 and the c-phase upper arm of the second inverter 20 share a drive signal line;
  • the drive signal line is shared with the a-phase upper arm of the second inverter 20;
  • the a-phase lower arm of the first inverter 10 shares the drive signal line with the b-phase lower arm of the second inverter 20;
  • the first The b-phase lower arm of the inverter 10 and the c-phase lower arm of the second inverter 20 share a driving signal line;
  • the c-phase lower arm of the first inverter 10 and the a-phase of the second inverter 20 The lower arms share the drive signal line.
  • the first inverter 10 and the second inverter 20 share multiple drive signal lines, including: the a-phase upper bridge arm of the first inverter 10 and the a-phase upper arm of the second inverter 20 The phase lower bridge arms share a drive signal line; the b-phase upper bridge arm of the first inverter 10 and the b-phase lower bridge arm of the second inverter 20 share a drive signal line; the c-phase upper bridge of the first inverter 10 The arm and the c-phase lower arm of the second inverter 20 share a drive signal line; the a-phase lower arm of the first inverter 10 and the a-phase upper arm of the second inverter 20 share a drive signal line; The b-phase lower arm of one inverter 10 and the b-phase upper arm of the second inverter 20 share a driving signal line; the c-phase lower arm of the first inverter 10 and the c-phase arm of the second inverter 20 The upper phase bridge arms share the drive signal line.
  • the driving system also includes a control chip 40, which is used to: obtain the target voltage vectors of the first inverter 10 and the second inverter 20, and obtain two target voltage vectors; according to the two targets The voltage vector generates multiple drive signals; the multiple drive signals are input to the multiple drive signal lines to drive and control the first inverter 10 and the second inverter 20 .
  • a control chip 40 which is used to: obtain the target voltage vectors of the first inverter 10 and the second inverter 20, and obtain two target voltage vectors; according to the two targets The voltage vector generates multiple drive signals; the multiple drive signals are input to the multiple drive signal lines to drive and control the first inverter 10 and the second inverter 20 .
  • control chip 40 is also used to: determine the sector where the combined voltage vector of the two target voltage vectors is located based on the positions of the two target voltage vectors in the two-phase rotating coordinate system; Any target voltage vector among the target voltage vectors generates multiple drive signals.
  • control chip 40 is also used to: determine the sector where the combined voltage vector of the two target voltage vectors is located based on the positions of the two target voltage vectors in the two-phase stationary coordinate system; Multiple drive signals are generated from either target voltage vector of the two target voltage vectors.
  • control chip 40 is also used to: obtain the action time of the basic voltage space vector corresponding to any target voltage vector according to the sector; obtain the voltage space vector switching point according to the action time; and generate multiple voltage space vector switching points according to the voltage space vector. road drive signal.
  • the first inverter and the second inverter share multiple drive signal lines, thereby reducing the use of the control chip interface, and due to the reduction in the use of the control chip interface, the control chip The number of drive signals that need to be generated is correspondingly reduced, thereby reducing the computing resources required to control the chip.
  • a "computer-readable medium” may be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
  • Non-exhaustive list of computer readable media include the following: electrical connections with one or more wires (electronic device), portable computer disk cartridges (magnetic device), random access memory (RAM), Read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM).
  • the computer-readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, and subsequently edited, interpreted, or otherwise suitable as necessary. process to obtain the program electronically and then store it in computer memory.
  • various parts of the present disclosure may be implemented in hardware, software, firmware, or combinations thereof.
  • steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system.
  • a logic gate circuit with a logic gate circuit for implementing a logic function on a data signal.
  • Discrete logic circuits application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.
  • first and second used in the embodiments of the present disclosure are only used for descriptive purposes and may not be understood to indicate or imply relative importance, or to implicitly indicate what is indicated in this embodiment. number of technical features. Therefore, features defined by terms such as “first” and “second” in the embodiments of the present disclosure may explicitly or implicitly indicate that the embodiment includes at least one of the features.
  • the word "plurality” means at least two or two and more, such as two, three, four, etc., unless otherwise clearly and specifically limited in the embodiment.
  • connection can It can be a fixed connection, or it can be a detachable connection, or it can be integrated. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be directly connected, or indirectly connected through an intermediate medium, or it can be two The internal connection between components, or the interaction between two components.
  • connection can It can be a fixed connection, or it can be a detachable connection, or it can be integrated. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be directly connected, or indirectly connected through an intermediate medium, or it can be two The internal connection between components, or the interaction between two components.

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Abstract

一种开绕组电机驱动系统及其控制方法、装置、存储介质，其中，系统包括对应开绕组电机（30）的绕组两端设置的第一逆变器（10）和第二逆变器（20），第一逆变器（10）和第二逆变器（20）共用多路驱动信号线，方法包括：获取第一逆变器（10）和第二逆变器（20）的目标电压矢量，得到两个目标电压矢量(S101)；根据两个目标电压矢量生成多路驱动信号(S102)；将多路驱动信号输入至多路驱动信号线，以对第一逆变器（10）和第二逆变器（20）进行驱动控制(S103)。

Description

开关绕组电机驱动系统及其控制方法、装置、存储介质
相关申请的交叉引用
本公开要求于2022年08月05日提交的申请号为202210939742.5，名称为“开关绕组电机驱动系统及其控制方法、装置、存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及电机控制技术领域，特别涉及一种开绕组电机驱动系统及其控制方法、装置、存储介质。
背景技术
开绕组电机驱动系统是将常规电机的绕组中性点打开，两端各串接一个IPM(Intelligent Power Module，智能功率模块)而形成的一种双端供电的电机系统拓扑结构。在对开绕组电机控制时，常规的空间矢量调制算法需要生成12路驱动信号，以协调控制两个IPM的12个开关管导通或关断。
相关技术中，一般使用单个MCU(Micro Controller Unit，微控制单元)芯片输出12路驱动信号来驱动两个IPM，该MCU芯片不仅需要满足输出12路驱动信号的能力，而且产生12路驱动信号需要占用MCU芯片大量的计算资源。
公开内容
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的第一个目的在于提出一种开绕组电机驱动系统的控制方法，第一逆变器和第二逆变器通过共用多路驱动信号线，减少了控制芯片接口的使用，并且减少了控制芯片所需的计算资源。
本公开的第二个目的在于提出一种计算机可读存储介质。
本公开的第三个目的在于提出一种开绕组电机驱动系统。
本公开的第四个目的在于提出一种开绕组电机驱动系统的控制装置。
本公开的第五个目的在于提出另一种开绕组电机驱动系统。
为达到上述目的，根据本公开第一方面实施例提出了一种开绕组电机驱动系统的控制方法，系统包括对应开绕组电机的绕组两端设置的第一逆变器和第二逆变器，第一逆变器和第二逆变器共用多路驱动信号线，方法包括：获取第一逆变器和第二逆变器的目标电压矢量，得到两个目标电压矢量；根据两个目标电压矢量生成多路驱动信号；将多路驱动信号 输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制。
根据本公开实施例的开绕组电机驱动系统的控制方法，获取第一逆变器和第二逆变器的目标电压矢量，并根据两个目标电压矢量生成多路驱动信号，以及将多路驱动信号输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制，其中，第一逆变器和第二逆变器共用多路驱动信号线。由此，通过第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源。
根据本公开的一个实施例，第一逆变器和第二逆变器共用多路驱动信号线，包括：第一逆变器的a相上桥臂与第二逆变器的b相上桥臂共用驱动信号线；第一逆变器的b相上桥臂与第二逆变器的c相上桥臂共用驱动信号线；第一逆变器的c相上桥臂与第二逆变器的a相上桥臂共用驱动信号线；第一逆变器的a相下桥臂与第二逆变器的b相下桥臂共用驱动信号线；第一逆变器的b相下桥臂与第二逆变器的c相下桥臂共用驱动信号线；第一逆变器的c相下桥臂与第二逆变器的a相下桥臂共用驱动信号线。
根据本公开的另一个实施例，第一逆变器和第二逆变器共用多路驱动信号线，包括：第一逆变器的a相上桥臂与第二逆变器的a相下桥臂共用驱动信号线；第一逆变器的b相上桥臂与第二逆变器的b相下桥臂共用驱动信号线；第一逆变器的c相上桥臂与第二逆变器的c相下桥臂共用驱动信号线；第一逆变器的a相下桥臂与第二逆变器的a相上桥臂共用驱动信号线；第一逆变器的b相下桥臂与第二逆变器的b相上桥臂共用驱动信号线；第一逆变器的c相下桥臂与第二逆变器的c相上桥臂共用驱动信号线。
根据本公开的一个实施例，根据两个目标电压矢量生成多路驱动信号，包括：根据两个目标电压矢量在两相旋转坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量，生成多路驱动信号。
根据本公开的另一个实施例，根据两个目标电压矢量生成多路驱动信号，包括：根据两个目标电压矢量在两相静止坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量生成多路驱动信号。
根据本公开的一个实施例，根据扇区和两个目标电压矢量中的任一目标电压矢量生成多路驱动信号，包括：根据扇区获取任一目标电压矢量对应的基本电压空间矢量的作用时间；根据作用时间获取空间电压矢量切换点；根据电压空间矢量切换点生成多路驱动信号。
为达到上述目的，根据本公开第二方面实施例提出了一种计算机可读存储介质，其上存储有开绕组电机驱动系统的控制程序，该程序被处理器执行时实现前述任一个实施例的开绕组电机驱动系统的控制方法。
根据本公开实施例的计算机可读存储介质，通过执行上述开绕组电机驱动系统的控制方 法的计算机程序，第一逆变器和第二逆变器通过共用多路驱动信号线，减少了控制芯片接口的使用，并且减少了控制芯片所需的计算资源。
为达到上述目的，根据本公开第三方面实施例提出了一种开绕组电机驱动系统，包括：存储器、处理器及存储在存储器上并可在处理器上运行的开绕组电机驱动系统的控制程序，处理器执行程序时，实现前述任一个实施例的开绕组电机驱动系统的控制方法。
根据本公开实施例的开绕组电机驱动系统，通过处理器执行上述开绕组电机驱动系统的控制方法的计算机程序，第一逆变器和第二逆变器通过共用多路驱动信号线，减少了控制芯片接口的使用，并且减少了控制芯片所需的计算资源。
为达到上述目的，根据本公开第四方面实施例提出了一种开绕组电机驱动系统的控制装置，系统包括对应开绕组电机的绕组两端设置的第一逆变器和第二逆变器，第一逆变器和第二逆变器共用多路驱动信号线，装置包括：获取模块，用于获取第一逆变器和第二逆变器的目标电压矢量，得到两个目标电压矢量；生成模块，用于根据两个目标电压矢量生成多路驱动信号；控制模块，用于将多路驱动信号输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制。
根据本公开实施例的开绕组电机驱动系统的控制装置，通过获取模块获取第一逆变器和第二逆变器的目标电压矢量，并通过生成模块根据两个目标电压矢量生成多路驱动信号，以及通过控制模块将多路驱动信号输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制，其中，第一逆变器和第二逆变器共用多路驱动信号线。由此，通过第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源。
为达到上述目的，根据本公开第五方面实施例提出了另一种开绕组电机驱动系统，包括：开绕组电机；第一逆变器和第二逆变器，第一逆变器和第二逆变器对应开绕组电机的绕组两端设置，第一逆变器和第二逆变器共用多路驱动信号线。
根据本公开实施例的开绕组电机驱动系统，通过第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
图1是根据本公开一个实施例的开绕组电机驱动系统的拓扑图；
图2是根据本公开另一个实施例的开绕组电机驱动系统的拓扑图；
图3是根据本公开一个实施例的开绕组电机驱动系统的控制框图；
图4是根据本公开一个实施例的开绕组电机驱动系统的控制方法的流程示意图；
图5是图1所示开绕组电机驱动系统对应的扇区示意图；
图6是图2所示开绕组电机驱动系统对应的扇区示意图；
图7是图1所示开绕组电机驱动系统对应的驱动信号时序图；
图8是图2所示开绕组电机驱动系统对应的驱动信号时序图；
图9是图1所示开绕组电机驱动系统对应的三相电流、零序电流与传统开绕组电机驱动系统对应的三相电流、零序电流的波形对比图；
图10是图2所示开绕组电机驱动系统对应的三相电流、零序电流的波形图；
图11是根据本公开一个实施例的开绕组电机驱动系统的结构示意图；
图12是根据本公开一个实施例的开绕组电机驱动系统的控制装置的结构示意图。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下面参考附图描述本公开实施例的开绕组电机驱动系统及其控制方法、装置、存储介质。
参考图1-图3所示，在本公开的一些实施例中，开绕组电机驱动系统包括：第一逆变器10、第二逆变器20、开绕组电机30以及电控系统。其中，第一逆变器10和第二逆变器20的直流侧均与直流电源DC相连，第一逆变器10和第二逆变器20的交流侧对应连接在开绕组电机30的绕组两端，即将常规的Y型电机的中性点打开，并在电机绕组两端分别连接一个逆变器(如IPM模块)，第一逆变器10和第二逆变器20共用多路驱动信号线。电控系统包括控制芯片40和采样单元50，通过电控系统协调控制两个逆变器来驱动开绕组电机30工作。
作为一种示例，如图1所示，第一逆变器10和第二逆变器20共用多路驱动信号线，包括：
第一逆变器10的a相上桥臂与第二逆变器20的b相上桥臂共用驱动信号线，控制芯片40的第一引脚用于给第一逆变器10的a相上桥臂输入驱动信号PWM_A1+和给第二逆变器20的b相上桥臂输入驱动信号PWM_B2+，且驱动信号PWM_A1+和驱动信号PWM_B2+相同；
第一逆变器10的b相上桥臂与第二逆变器20的c相上桥臂共用驱动信号线，控制芯片40的第二引脚用于给第一逆变器10的b相上桥臂输入驱动信号PWM_B1+和给第二逆变器20 的c相上桥臂输入驱动信号PWM_C2+，且驱动信号PWM_B1+和驱动信号PWM_C2+相同；
第一逆变器10的c相上桥臂与第二逆变器20的a相上桥臂共用驱动信号线，控制芯片40的第三引脚用于给第一逆变器10的c相上桥臂输入驱动信号PWM_C1+和给第二逆变器20的a相上桥臂输入驱动信号PWM_A2+，且驱动信号PWM_C1+和驱动信号PWM_A2+相同；
第一逆变器10的a相下桥臂与第二逆变器20的b相下桥臂共用驱动信号线，控制芯片40的第四引脚用于给第一逆变器10的a相下桥臂输入驱动信号PWM_A1-和给第二逆变器20的b相下桥臂输入驱动信号PWM_B2-，且驱动信号PWM_A1-和驱动信号PWM_B2-相同；
第一逆变器10的b相下桥臂与第二逆变器20的c相下桥臂共用驱动信号线，控制芯片40的第五引脚用于给第一逆变器10的b相下桥臂输入驱动信号PWM_B1-和给第二逆变器20的c相下桥臂输入驱动信号PWM_C2-，且驱动信号PWM_B1-和驱动信号PWM_C2-相同；
第一逆变器10的c相下桥臂与第二逆变器20的a相下桥臂共用驱动信号线，控制芯片40的第六引脚用于给第一逆变器10的c相下桥臂输入驱动信号PWM_C1-和给第二逆变器20的a相下桥臂输入驱动信号PWM_A2-，且驱动信号PWM_C1-和驱动信号PWM_A2-相同。
作为另一种示例，如图2所示，第一逆变器10和第二逆变器20共用多路驱动信号线，包括：
第一逆变器10的a相上桥臂与第二逆变器20的a相下桥臂共用驱动信号线，控制芯片40的第一引脚用于给第一逆变器10的a相上桥臂输入驱动信号PWM_A1+和给第二逆变器20的a相下桥臂输入驱动信号PWM_A2-，且驱动信号PWM_A1+和驱动信号PWM_A2-相同；
第一逆变器10的b相上桥臂与第二逆变器20的b相下桥臂共用驱动信号线，控制芯片40的第二引脚用于给第一逆变器10的b相上桥臂输入驱动信号PWM_B1+和给第二逆变器20的b相下桥臂输入驱动信号PWM_B2-，且驱动信号PWM_B1+和驱动信号PWM_B2-相同；
第一逆变器10的c相上桥臂与第二逆变器20的c相下桥臂共用驱动信号线，控制芯片40的第三引脚用于给第一逆变器10的c相上桥臂输入驱动信号PWM_C1+和给第二逆变器20的c相下桥臂输入驱动信号PWM_C2-，且驱动信号PWM_C1+和驱动信号PWM_C2-相同；
第一逆变器10的a相下桥臂与第二逆变器20的a相上桥臂共用驱动信号线，控制芯片40的第四引脚用于给第一逆变器10的a相下桥臂输入驱动信号PWM_A1-和给第二逆变器20的a相上桥臂输入驱动信号PWM_A2+，且驱动信号PWM_A1-和驱动信号PWM_A2+相同；
第一逆变器10的b相下桥臂与第二逆变器20的b相上桥臂共用驱动信号线，控制芯片40的第五引脚用于给第一逆变器10的b相下桥臂输入驱动信号PWM_B1-和给第二逆变器20的b相上桥臂输入驱动信号PWM_B2+，且驱动信号PWM_B1-和驱动信号PWM_B2+相同；
第一逆变器10的c相下桥臂与第二逆变器20的c相上桥臂共用驱动信号线,控制芯片40的第六引脚用于给第一逆变器10的c相下桥臂输入驱动信号PWM_C1-和给第二逆变器20 的c相上桥臂输入驱动信号PWM_C2+，且驱动信号PWM_C1-和驱动信号PWM_C2+相同。
如图3所示，控制芯片40包括零序电流控制单元41、三相电流控制单元42以及驱动信号生成单元43，其中，零序电流控制单元41用于根据采样单元50获得的三相电流Ia、Ib和Ic重构零序电流I0，并根据零序电流I0实现基于零序电流I0的相关控制；三相电流控制单元42用于实现基于三相电流Ia、Ib和Ic的相关控制；驱动信号生成单元43用于根据零序电流控制单元41和三相电流控制单元42输出的信号，采用一定的算法，如SVPWM(Space Vector Pulse Width Modulation，空间矢量脉宽调制)算法，生成6路驱动信号，并将6路驱动信号输入至第一逆变器10和第二逆变器20，以对第一逆变器10和第二逆变器20中的开关管进行驱动控制，以使开绕组电机30运行。
采样单元50包括检流电阻R1、R2和R3，检流电阻R1、R2和R3可分别串联在第二逆变器20的a相、b相和c相的下桥臂与直流电源DC的负极之间，通过检流电阻R1、R2和R3采样第二逆变器20的三相桥臂的电流。当然，检流电阻R1、R2和R3也可以分别串联在第一逆变器10的a相、b相和c相的下桥臂与直流电源DC的负极之间。或者，检流电阻可以为单电阻，采样单元50也可以为电流互感器等，具体这里不做限制。
由上述实施例可知，第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，如由原来的12个接口减少为6个接口，且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源；并且，本实施例只采用了一个控制芯片，相比采用两个控制芯片分别驱动两个逆变器，能够有效降低成本和电控板的设计难度。
图4是根据本公开一个实施例的开绕组电机驱动系统的控制方法的流程示意图，如图4所示，该开绕组电机驱动系统的控制方法包括以下步骤：
S101，获取第一逆变器和第二逆变器的目标电压矢量，得到两个目标电压矢量。
具体地，可通过协调控制第一逆变器和第二逆变器的驱动信号来输出两个目标电压矢量，记为第一目标电压矢量VA和第二目标电压矢量VB。
S102，根据两个目标电压矢量生成多路驱动信号。
具体地，可先根据两个目标电压矢量确定合成电压矢量所处的扇区，然后根据扇区和两个目标电压矢量中的任一目标电压矢量，生成多路驱动信号。
需要说明的是，第一逆变器和第二逆变器均包括六个开关管，任何时刻每个逆变器有且仅有三个开关管导通，且同一桥臂的上桥臂和下桥臂的开关管是互锁的，因此每个逆变器具有八个基本的开关状态，若用数字“1”表示相应上桥臂处于导通状态，而下桥臂处于断开状态，用数字“0”表示相应上桥臂处于断开状态，而下桥臂处于导通状态，则八个开关状态对应八个开关量，分别为“000”、“100”、“110”、...、“111”，这八个开关量对应八 个电压空间矢量，具体包括六个幅值相等、相位互差π/3的基本电压空间矢量A至F，以及两个零电压空间矢量，其中，六个基本电压空间矢量将复平面划分为六个扇区，分别为扇区I、II、...、VI，两个零电压空间矢量位于中心。
在获得第一目标电压矢量VA和第二目标电压矢量VB后，可基于第一目标电压矢量VA和第二目标电压矢量VB确定两者合成后的合成电压矢量VOEW所处的扇区，然后根据所处的扇区和第一目标电压矢量VA生成多路驱动信号，或者根据所处的扇区和第二目标电压矢量VB生成多路驱动信号。
作为一种示例，根据两个目标电压矢量生成多路驱动信号，包括：根据两个目标电压矢量在两相旋转坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量，生成多路驱动信号。
需要说明的是，在采用图1所示的开绕组电机驱动系统时，所需的合成电压矢量VOEW为两相旋转坐标系(γ-δ坐标系)下的电压矢量，而第一目标电压矢量VA和第二目标电压矢量VB均为两相静止坐标系(α-β坐标系)下的电压矢量，因此在获得两个目标电压矢量VA和VB后，需要将两个目标电压矢量VA和VB的坐标系由两相静止坐标系(α-β坐标系)转化为两相旋转坐标系(γ-δ坐标系)，而后再基于两个目标电压矢量VA和VB与两相旋转坐标系的数学几何关系确定合成电压矢量VOEW所处的扇区，进而根据所处的扇区和其中一个目标电压矢量VA或VB，生成多路驱动信号。
如图5所示，在采用图1所示开绕组电机驱动系统时，在获得两个目标电压矢量VA和VB时，先对第二目标电压矢量VB做反向处理，然后将两个目标电压矢量VA和VB的坐标由两相静止坐标转换为两相旋转坐标，接着根据转换后的两个目标电压矢量VA和VB与两相旋转坐标系的数学关系判断合成电压矢量VOEW所处的扇区，如处于扇区I，进而根据所处的扇区I和其中一个目标电压矢量VA或VB，生成多路驱动信号。
作为另一种示例，根据两个目标电压矢量生成多路驱动信号，包括：根据两个目标电压矢量在两相静止坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量生成多路驱动信号。
需要说明的是，在采用图2所示的开绕组电机驱动系统时，所需的合成电压矢量VOEW为两相静止坐标系下的电压矢量，而第一目标电压矢量VA和第二目标电压矢量VB也均为两相静止坐标系下的电压矢量，因此在获得两个目标电压矢量VA和VB后，无需进行坐标转换，直接基于两个目标电压矢量VA和VB与两相静止坐标系的数学几何关系确定合成电压矢量VOEW所处的扇区，进而根据所处的扇区和其中一个目标电压矢量VA或VB，生成多路驱动信号。
如图6所示，在采用图2所示开绕组电机驱动系统时，在获得两个目标电压矢量VA和 VB时，先对第二目标电压矢量VB做反向处理，然后根据两个目标电压矢量VA和VB与两相静止坐标系的数学关系判断合成电压矢量VOEW所处的扇区，如处于扇区I，进而根据所处的扇区I和其中一个目标电压矢量VA或VB，生成多路驱动信号。
可以理解的是，由于第一逆变器和第二逆变器共用多路驱动信号线，而共用驱动信号线的方式是基于对第一逆变器和第二逆变器的协调控制所确定的，因此在获得合成电压矢量所处的扇区后，根据所处的扇区和其中一个目标电压矢量VA或VB生成的多路驱动信号，就可以同时满足第一逆变器和第二逆变器的控制需求，从而大大减少了控制芯片计算资源的占用。
在一些实施例中，根据扇区和两个目标电压矢量中的任一目标电压矢量生成多路驱动信号，包括：根据扇区获取任一目标电压矢量对应的基本电压空间矢量的作用时间；根据作用时间获取电压空间矢量切换点；根据电压空间矢量切换点生成多路驱动信号。
作为一种示例，如图5所示，在确定合成电压矢量VOEW处于扇区I时，可根据扇区I和第一目标电压矢量VA生成多路驱动信号，具体是，先根据扇区I确定两个基本电压空间矢量(1,0,0)和(1,1,0)，并根据第一目标电压矢量VA的幅值和位置，利用伏秒平衡原则计算两个基本电压空间矢量(1,0,0)和(1,1,0)的作用时间，并由此得到两个零电压空间矢量(0,0,0)和(1,1,1)的作用时间；接着，基于7段式SVPWM算法确定两个基本电压空间矢量和两个零电压空间矢量的作用顺序，如图7所示，在扇区I对应的驱动信号波形图中，两个基本电压空间矢量和两个零电压空间矢量的作用顺序依次为(0,0,0)、(1,0,0)、(1,1,0)、(1,1,1)、(1,1,0)、(1,0,0)、(0,0,0)。从图7可以看出，7段式电压空间矢量包括3段零电压空间矢量和4段基本电压空间矢量，且3段零电压空间矢量分别位于驱动信号波形的开始、中间和结尾。同时，根据两个基本电压空间矢量和两个零电压空间矢量的作用顺序以及作用时间，可以确定出空间电压矢量切换点，如图7所示，第一个空间电压矢量切换点为第一逆变器的a相上桥臂由断开切换至导通，对应的切换时间为T0/4；第二个空间电压矢量切换点为第一逆变器的b相上桥臂由断开切换至导通，对应的切换时间为T0/4+T1/2；第三个空间电压矢量切换点为第一逆变器的c相上桥臂由断开切换至导通，对应的切换时间为T0/4+T1/2+T2/2；第四个空间电压矢量切换点为第一逆变器的c相上桥臂由导通切换至断开，对应的切换时间为T0/4+T1/2+T2/2+T7/4+T7/4；依次类推。其中，T0表示零电压空间矢量(0,0,0)的作用时间，T1表示基本电压空间矢量(1,0,0)的作用时间，T2表示基本电压空间矢量(1,1,0)的作用时间，T7表示零电压空间矢量(1,1,1)的作用时间，且Ts＝T1+T2+T0+T7，Ts为控制周期。最后，根据电压空间矢量切换点，基于PWM调制技术，生成6路驱动信号。
需要说明的是，当合成电压矢量VOEW处于其它扇区时，生成多路驱动信号的过程与其 处于扇区I时的相同，具体参考前述，这里不再赘述。另外，也可以基于5段式SVPWM算法生成多路驱动信号，但是其将零电压矢量集中插入，谐波分量较大，因此采样5段式SVPWM算法具有更低的谐波分量。
作为另一种示例，如图6所示，在确定合成电压矢量VOEW处于扇区I时，可根据扇区I和第一目标电压矢量VA生成多路驱动信号，具体可参考图5所示示例，这里不再赘述。
S103，将多路驱动信号输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制。
作为一种示例，如图5所示，在根据合成电压矢量VOEW所处扇区以及第一目标电压矢量VA生成6路驱动信号时，将6路驱动信号通过图1所示6路驱动信号线输入至第一逆变器和第二逆变器，以驱动开绕组电机工作，第一逆变器和第二逆变器的驱动信号波形如图7所示，第二逆变器的驱动信号波形基于第一逆变器的驱动信号波形以及驱动信号线的连接方式确定。例如，在扇区I，当第一逆变器的a相上桥臂导通时，基于第一逆变器的a相上桥臂和第二逆变器的b相上桥臂共用驱动信号线，第二逆变器的b相上桥臂导通。
作为另一种示例，如图6所示，在根据合成电压矢量VOEW所处扇区以及第一目标电压矢量VA生成6路驱动信号时，将6路驱动信号通过图2所示6路驱动信号线输入至第一逆变器和第二逆变器，以驱动开绕组电机工作，第一逆变器和第二逆变器的驱动信号波形如图8所示，第二逆变器的驱动信号波形基于第一逆变器的驱动信号波形以及驱动信号线的连接方式确定。例如，在扇区I，当第一逆变器的a相上桥臂导通时，基于第一逆变器的a相上桥臂和第二逆变器的a相下桥臂共用驱动信号线，第二逆变器的a相下桥臂导通。
上述实施例中，由于第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源。
需要说明的是，在采用图1所示开绕组电机驱动系统时，还可以有效消除因第一逆变器和第二逆变器共母线产生的共模电压，从而消除因共模电压引起的零序电流。具体来说，第一逆变器产生的共模电压如公式(1)所示：
其中，Ucom1表示第一逆变器产生的共模电压，Ua1o1表示图1中两个串联连接的母线电容C1和C2的中点O1与a相桥臂的中点a1之间的电压，Ub1o1表示母线电容C1和C2的中点O1与b相桥臂的中点b1之间的电压，Uc1o1表示母线电容C1和C2的中点O1与c相桥臂的中点c1之间的电压。
第二逆变器产生的共模电压如公式(2)所示：
其中，Ucom2表示第二逆变器产生的共模电压，Ua2o2表示图1中两个串联连接的母线电容C3和C4的中点O2与a相桥臂的中点a2之间的电压，Ub2o2表示母线电容C3和C4的中点O2与b相桥臂的中点b2之间的电压，Uc2o2表示母线电容C3和C4的中点O2与c相桥臂的中点c2之间的电压。
第一逆变器和第二逆变器产生的系统共模电压如公式(3)所示：
其中，Uo1o2表示系统共模电压，也即母线电容C1和C2的中点O1与母线电容C3和C4的中点O2之间的电压。
由于第一逆变器和第二逆变器产生的系统共模电压同时满足公式(4)：
其中，Udc表示直流电源电压，即母线电压，Sa1、Sb1和Sc1分别表示第一逆变器的a相上桥臂、b相上桥臂和c相上桥臂的驱动信号，Sa2、Sb2和Sc2分别表示第二逆变器的a相上桥臂、b相上桥臂和c相上桥臂的驱动信号。
从图4可以看出，消除系统共模电压就是使系统共模电压为零，也即(Sa1+Sb1+Sc1)＝(Sa2+Sb2+Sc2)，其中Sa1、Sb1、Sc1、Sa2、Sb2和Sc2均用0和1进行计算。满足该公式的情况如表1所示：
表1

从表1可以看出，采用如图1所示的开绕组电机驱动系统可以有效消除共模电压，从而减少系统的零序电流，减少系统干扰。
图9示出了采用传统开绕组电机驱动系统得到的三相电流、零序电流与采用图1所示的开绕组电机驱动系统得到的三相电流、零序电流的对比图，从图9可以看出，采用传统开绕组电机驱动系统得到的零序电流峰值在2A左右，三相电流由于零序电流的影响正弦度变差，控制难度增大的同时器件损耗也增大；采用图1所示的开绕组电机驱动系统的零序电流峰值在2.5*10^-6A，近似为零，三相电流的正弦度较好，系统的扰动及器件损耗均降低。
图10示出了采用图2所示的开绕组电机驱动系统得到的三相电流、零序电流的波形图，从图10可以看出，虽然图2所示开绕组电机驱动系统无法消除系统共模电压，但是其可以达到最大输出效果，提高系统的输出能力。
综上所述，根据本公开实施例的开绕组电机驱动系统的控制方法，通过第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源，降低了硬件设计难度和成本。
对应上述实施例，本公开的实施例还提供了一种计算机可读存储介质，其上存储有开绕组电机驱动系统的控制程序，该程序被处理器执行时实现前述任一个实施例的开绕组电机驱动系统的控制方法。
根据本公开实施例的计算机可读存储介质，通过执行上述开绕组电机驱动系统的控制方 法的计算机程序，第一逆变器和第二逆变器通过共用多路驱动信号线，减少了控制芯片接口的使用，并且减少了控制芯片所需的计算资源。
对应上述实施例，本公开的实施例还提供了一种开绕组电机驱动系统。
如图11所示，开绕组电机驱动系统200包括存储器210、处理器220及存储在存储器210上并可在处理器220上运行的开绕组电机驱动系统的控制程序，处理器220执行程序时，实现前述任一个实施例的开绕组电机驱动系统的控制方法。
根据本公开实施例的开绕组电机驱动系统，通过处理器执行上述开绕组电机驱动系统的控制方法的计算机程序，第一逆变器和第二逆变器通过共用多路驱动信号线，减少了控制芯片接口的使用，并且减少了控制芯片所需的计算资源。
对应上述实施例，本公开的实施例还提供了一种开绕组电机驱动系统的控制装置。其中，系统包括对应开绕组电机的绕组两端设置的第一逆变器和第二逆变器，第一逆变器和第二逆变器共用多路驱动信号线。如图12所示，控制装置包括：获取模块310、生成模块320和控制模块330。
其中，获取模块310用于获取第一逆变器和第二逆变器的目标电压矢量，得到两个目标电压矢量；生成模块320用于根据两个目标电压矢量生成多路驱动信号；控制模块330用于将多路驱动信号输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制。
在一些实施例中，第一逆变器和第二逆变器共用多路驱动信号线，包括：第一逆变器的a相上桥臂与第二逆变器的b相上桥臂共用驱动信号线；第一逆变器的b相上桥臂与第二逆变器的c相上桥臂共用驱动信号线；第一逆变器的c相上桥臂与第二逆变器的a相上桥臂共用驱动信号线；第一逆变器的a相下桥臂与第二逆变器的b相下桥臂共用驱动信号线；第一逆变器的b相下桥臂与第二逆变器的c相下桥臂共用驱动信号线；第一逆变器的c相下桥臂与第二逆变器的a相下桥臂共用驱动信号线。
在一些实施例中，第一逆变器和第二逆变器共用多路驱动信号线，包括：第一逆变器的a相上桥臂与第二逆变器的a相下桥臂共用驱动信号线；第一逆变器的b相上桥臂与第二逆变器的b相下桥臂共用驱动信号线；第一逆变器的c相上桥臂与第二逆变器的c相下桥臂共用驱动信号线；第一逆变器的a相下桥臂与第二逆变器的a相上桥臂共用驱动信号线；第一逆变器的b相下桥臂与第二逆变器的b相上桥臂共用驱动信号线；第一逆变器的c相下桥臂与第二逆变器的c相上桥臂共用驱动信号线。
在一些实施例中，生成模块320具体用于：根据两个目标电压矢量在两相旋转坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量，生成多路驱动信号。
在一些实施例中，生成模块320具体用于：根据两个目标电压矢量在两相静止坐标系下 的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量生成多路驱动信号。
在一些实施例中，生成模块320具体用于：根据扇区获取任一目标电压矢量对应的基本电压空间矢量的作用时间；根据作用时间获取电压空间矢量切换点；根据电压空间矢量切换点生成多路驱动信号。
需要说明的是，本公开实施例的开绕组电机驱动系统的控制装置的具体实施方式与前述本公开实施例的开绕组电机驱动系统的控制方法的具体实施方式一一对应，在此不再赘述。
根据本公开实施例的开绕组电机驱动系统的控制装置，通过获取模块获取第一逆变器和第二逆变器的目标电压矢量，并通过生成模块根据两个目标电压矢量生成多路驱动信号，以及通过控制模块将多路驱动信号输入至多路驱动信号线，以对第一逆变器和第二逆变器进行驱动控制，其中，第一逆变器和第二逆变器共用多路驱动信号线。由此，通过第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源。
对应上述实施例，本公开的实施例还提供了另一种开绕组电机驱动系统。
如图1所示，驱动系统包括：开绕组电机30、第一逆变器10和第二逆变器20。其中，第一逆变器10和第二逆变器20对应开绕组电机30的绕组两端设置，第一逆变器10和第二逆变器20共用多路驱动信号线。
在一些实施例中，第一逆变器10和第二逆变器20共用多路驱动信号线，包括：第一逆变器10的a相上桥臂与第二逆变器20的b相上桥臂共用驱动信号线；第一逆变器10的b相上桥臂与第二逆变器20的c相上桥臂共用驱动信号线；第一逆变器10的c相上桥臂与第二逆变器20的a相上桥臂共用驱动信号线；第一逆变器10的a相下桥臂与第二逆变器20的b相下桥臂共用驱动信号线；第一逆变器10的b相下桥臂与第二逆变器20的c相下桥臂共用驱动信号线；第一逆变器10的c相下桥臂与第二逆变器20的a相下桥臂共用驱动信号线。
在另一些实施例中，第一逆变器10和第二逆变器20共用多路驱动信号线，包括：第一逆变器10的a相上桥臂与第二逆变器20的a相下桥臂共用驱动信号线；第一逆变器10的b相上桥臂与第二逆变器20的b相下桥臂共用驱动信号线；第一逆变器10的c相上桥臂与第二逆变器20的c相下桥臂共用驱动信号线；第一逆变器10的a相下桥臂与第二逆变器20的a相上桥臂共用驱动信号线；第一逆变器10的b相下桥臂与第二逆变器20的b相上桥臂共用驱动信号线；第一逆变器10的c相下桥臂与第二逆变器20的c相上桥臂共用驱动信号线。
在一些实施例中，驱动系统还包括控制芯片40，控制芯片40用于：获取第一逆变器10和第二逆变器20的目标电压矢量，得到两个目标电压矢量；根据两个目标电压矢量生成多路驱动信号；将多路驱动信号输入至多路驱动信号线，以对第一逆变器10和第二逆变器20进行驱动控制。
在一些实施例中，控制芯片40还用于：根据两个目标电压矢量在两相旋转坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量，生成多路驱动信号。
在另一些实施例中，控制芯片40还用于：根据两个目标电压矢量在两相静止坐标系下的位置，确定两个目标电压矢量的合成电压矢量所处的扇区；根据扇区和两个目标电压矢量中的任一目标电压矢量生成多路驱动信号。
在一些实施例中，控制芯片40还用于：根据扇区获取任一目标电压矢量对应的基本电压空间矢量的作用时间；根据作用时间获取电压空间矢量切换点；根据电压空间矢量切换点生成多路驱动信号。
需要说明的是，本公开实施例的开绕组电机驱动系统的具体实施方式与前述本公开实施例的开绕组电机驱动系统的控制方法的具体实施方式一一对应，在此不再赘述。
根据本公开实施例的开绕组电机驱动系统，通过第一逆变器和第二逆变器共用多路驱动信号线，减少了控制芯片接口的使用，并且由于控制芯片接口使用的减少，控制芯片需要产生的驱动信号也相应减少，从而减少了控制芯片所需的计算资源。
需要说明的是，在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，“计算机可读介质”可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或多个布线的电连接部(电子装置)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本公开的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施 方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
此外，本公开实施例中所使用的“第一”、“第二”等术语，仅用于描述目的，而不可以理解为指示或者暗示相对重要性，或者隐含指明本实施例中所指示的技术特征数量。由此，本公开实施例中限定有“第一”、“第二”等术语的特征，可以明确或者隐含地表示该实施例中包括至少一个该特征。在本公开的描述中，词语“多个”的含义是至少两个或者两个及以上，例如两个、三个、四个等，除非实施例中另有明确具体的限定。
在本公开中，除非实施例中另有明确的相关规定或者限定，否则实施例中出现的术语“安装”、“相连”、“连接”和“固定”等应做广义理解，例如，连接可以是固定连接，也可以是可拆卸连接，或成一体，可以理解的，也可以是机械连接、电连接等；当然，还可以是直接相连，或者通过中间媒介进行间接连接，或者可以是两个元件内部的连通，或者两个元件的相互作用关系。对于本领域的普通技术人员而言，能够根据具体的实施情况理解上述术语在本公开中的具体含义。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 一种开绕组电机驱动系统的控制方法，所述系统包括对应开绕组电机的绕组两端设置的第一逆变器和第二逆变器，所述第一逆变器和所述第二逆变器共用多路驱动信号线，所述方法包括：
    获取所述第一逆变器和所述第二逆变器的目标电压矢量，得到两个目标电压矢量；
    根据所述两个目标电压矢量生成多路驱动信号；
    将所述多路驱动信号输入至所述多路驱动信号线，以对所述第一逆变器和所述第二逆变器进行驱动控制。
  2. 根据权利要求1所述的方法，其中，所述第一逆变器和所述第二逆变器共用多路驱动信号线，包括：
    所述第一逆变器的a相上桥臂与所述第二逆变器的b相上桥臂共用驱动信号线；
    所述第一逆变器的b相上桥臂与所述第二逆变器的c相上桥臂共用驱动信号线；
    所述第一逆变器的c相上桥臂与所述第二逆变器的a相上桥臂共用驱动信号线；
    所述第一逆变器的a相下桥臂与所述第二逆变器的b相下桥臂共用驱动信号线；
    所述第一逆变器的b相下桥臂与所述第二逆变器的c相下桥臂共用驱动信号线；
    所述第一逆变器的c相下桥臂与所述第二逆变器的a相下桥臂共用驱动信号线。
  3. 根据权利要求1所述的方法，其中，所述第一逆变器和所述第二逆变器共用多路驱动信号线，包括：
    所述第一逆变器的a相上桥臂与所述第二逆变器的a相下桥臂共用驱动信号线；
    所述第一逆变器的b相上桥臂与所述第二逆变器的b相下桥臂共用驱动信号线；
    所述第一逆变器的c相上桥臂与所述第二逆变器的c相下桥臂共用驱动信号线；
    所述第一逆变器的a相下桥臂与所述第二逆变器的a相上桥臂共用驱动信号线；
    所述第一逆变器的b相下桥臂与所述第二逆变器的b相上桥臂共用驱动信号线；
    所述第一逆变器的c相下桥臂与所述第二逆变器的c相上桥臂共用驱动信号线。
  4. 根据权利要求2所述的方法，其中，所述根据所述两个目标电压矢量生成多路驱动信号，包括：
    根据所述两个目标电压矢量在两相旋转坐标系下的位置，确定所述两个目标电压矢量的合成电压矢量所处的扇区；
    根据所述扇区和所述两个目标电压矢量中的任一目标电压矢量，生成所述多路驱动信号。
  5. 根据权利要求3所述的方法，其中，所述根据所述两个目标电压矢量生成多路驱动 信号，包括：
    根据所述两个目标电压矢量在两相静止坐标系下的位置，确定所述两个目标电压矢量的合成电压矢量所处的扇区；
    根据所述扇区和所述两个目标电压矢量中的任一目标电压矢量生成所述多路驱动信号。
  6. 根据权利要求4或5所述的方法，其中，所述根据所述扇区和所述两个目标电压矢量中的任一目标电压矢量生成所述多路驱动信号，包括：
    根据所述扇区获取所述任一目标电压矢量对应的基本电压空间矢量的作用时间；
    根据所述作用时间获取空间电压矢量切换点；
    根据所述电压空间矢量切换点生成所述多路驱动信号。
  7. 一种计算机可读存储介质，其上存储有开绕组电机驱动系统的控制程序，该开绕组电机驱动系统的控制程序被处理器执行时实现根据权利要求1-6中任一项所述的开绕组电机驱动系统的控制方法。
  8. 一种开绕组电机驱动系统，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的开绕组电机驱动系统的控制程序，所述处理器执行所述程序时，实现根据权利要求1-6中任一项所述的开绕组电机驱动系统的控制方法。
  9. 一种开绕组电机驱动系统的控制装置，所述系统包括对应开绕组电机的绕组两端设置的第一逆变器和第二逆变器，所述第一逆变器和所述第二逆变器共用多路驱动信号线，所述装置包括：
    获取模块，用于获取所述第一逆变器和所述第二逆变器的目标电压矢量，得到两个目标电压矢量；
    生成模块，用于根据所述两个目标电压矢量生成多路驱动信号；
    控制模块，用于将所述多路驱动信号输入至所述多路驱动信号线，以对所述第一逆变器和所述第二逆变器进行驱动控制。
  10. 一种开绕组电机驱动系统，包括：
    开绕组电机；
    第一逆变器和第二逆变器，所述第一逆变器和所述第二逆变器对应所述开绕组电机的绕组两端设置，所述第一逆变器和所述第二逆变器共用多路驱动信号线。
PCT/CN2023/090286 2022-08-05 2023-04-24 开关绕组电机驱动系统及其控制方法、装置、存储介质 WO2024027218A1 (zh)

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JP2021002898A (ja) * 2019-06-19 2021-01-07 株式会社Ｓｏｋｅｎ 回転電機の制御装置
JP2021197889A (ja) * 2020-06-18 2021-12-27 株式会社アイシン 回転電機制御装置
CN114142787A (zh) * 2020-09-04 2022-03-04 现代自动车株式会社 电动机驱动装置
JP2022096905A (ja) * 2020-12-18 2022-06-30 株式会社Soken 回転電機の制御装置

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JPH11252986A (ja) * 1998-02-27 1999-09-17 Sanyo Denki Co Ltd 多重巻き電動機の制御装置
CN105577021A (zh) * 2016-01-07 2016-05-11 浙江大学 一种双逆变器的单svm方法
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