WO2024027047A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2024027047A1
WO2024027047A1 PCT/CN2022/133809 CN2022133809W WO2024027047A1 WO 2024027047 A1 WO2024027047 A1 WO 2024027047A1 CN 2022133809 W CN2022133809 W CN 2022133809W WO 2024027047 A1 WO2024027047 A1 WO 2024027047A1
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Prior art keywords
light
layer
substrate
electrode
emitting element
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PCT/CN2022/133809
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English (en)
French (fr)
Inventor
李泽尧
郑浩旋
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惠科股份有限公司
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Publication of WO2024027047A1 publication Critical patent/WO2024027047A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a preparation method thereof.
  • Micro LED Inorganic Micro Light Emitting Diode (Micro LED) display panels are one of the hot spots in the field of display panel research today. Compared with OLED display panels, Micro LED has high reliability, low power consumption, high brightness and fast response speed. Etc. Especially in the AR/VR/XR and wearable fields, due to its smaller demand for display size, combined with the current maturity of Micro LED display technology, Micro LED has received great attention and application.
  • a conductive layer needs to be deposited in the connection through holes to achieve electrical connections between components and/or signal lines; at the same time, a black matrix or light-shielding layer needs to be provided in the display panel to prevent pixels from interfering with each other. Mixed light or light leakage to the driving circuit layer causes abnormality in the driving elements.
  • the conductive layer in the connection through hole is easily prone to problems of poor conductivity due to uneven deposition of the conductive layer; and, due to its light absorption, the black matrix or light-shielding layer has a problem with the light transmittance of the display panel. Lower question.
  • the display panel and its preparation method provided by this application are intended to solve the problem of poor conductivity in existing display panels due to uneven deposition of conductive layers in connection through holes and the low transmittance of the display panel.
  • the display panel includes:
  • a driving circuit layer is provided on one side of the substrate, the driving circuit layer includes driving elements, common electrodes and signal traces;
  • a flat layer disposed on the side of the driving circuit layer facing away from the substrate, and covering the driving circuit layer;
  • a light-emitting element is provided on a side of the flat layer facing away from the substrate;
  • the light-emitting element includes a semiconductor layer, a first electrode and a second electrode; the first electrode is electrically connected to the driving element, and the The second electrode is electrically connected to the common electrode;
  • a first covering layer disposed on the side of the light-emitting element facing away from the substrate, and covering the light-emitting element;
  • the first electrode and the second electrode are located on a side of the semiconductor layer facing away from the substrate;
  • the first covering layer has a first through hole and a second through hole, and the first through hole Extend to the driving circuit layer to partially expose the driving element;
  • the second through hole extends to the driving circuit layer to partially expose the common electrode;
  • first through holes and the second through holes are spaced apart and arranged around the side wall of the light emitting element, and the first through holes and the second through holes are filled with metal to form
  • the first metal wall and the second metal wall allow part of the light emitted from the light-emitting element to be reflected from the first metal wall and the second metal wall and emitted from one side of the substrate; and the first metal wall
  • the first electrode is electrically connected to the driven element
  • the second metal wall is electrically connected to the second electrode and the common electrode.
  • the light-emitting element, the driving element, the common electrode and the signal trace are arranged in a staggered position, and the portion of the insulating dielectric layer of the driving circuit layer corresponding to the light-emitting element is made of light-transmitting material, so that the The light emitted by the light-emitting element is emitted from one side of the substrate.
  • the first electrode and the second electrode are spaced apart in a first direction parallel to the display panel, and the light-emitting element has a first side surface and a second side surface spaced apart along the first direction. , and a third side and a fourth side connecting the first side and the second side;
  • the first metal wall is spaced apart from one side of the first side and extends to one side of the third side and The fourth side surface;
  • the second metal wall is spaced apart from the second side surface and extends to the third side surface and the fourth side surface;
  • the first metal wall is located on The projection of the part on one side of the third side on the third side at least partially overlaps with the projection of the part of the second metal wall on one side of the third side on the third side;
  • the first The projection of the portion of the metal wall located on one side of the fourth side on the fourth side at least partially overlaps with the projection of the portion of the second metal wall located on one side of the fourth side on the fourth side.
  • the radial distance between the surface of the first metal wall and/or the second metal wall close to the light-emitting element and the central axis of the light-emitting element Gradually increase, so that part of the emitted light from the light-emitting element is reflected to the substrate through the first metal wall and/or the second metal wall.
  • a groove is formed on a surface of the side of the flat layer facing away from the substrate, and the light-emitting element is disposed in the groove.
  • the first covering layer also has a third through hole and a fourth through hole, the third through hole at least partially exposes the first electrode, and the fourth through hole at least partially exposes the second electrode;
  • the display panel also includes a conductive layer, the conductive layer includes a first connection line and a second connection line; the first connection line is provided on a side of the first covering layer facing away from the substrate and extends to the The third through hole, the second connection line is provided on the side of the first covering layer facing away from the substrate and extends to the fourth through hole; the first metal wall passes through the first connection The circuit is connected to the first electrode, and the second metal wall is connected to the second electrode through the second connection circuit.
  • the display panel also includes:
  • a second covering layer disposed on the side of the conductive layer facing away from the substrate and covering the conductive layer;
  • a reflective layer is provided on a side of the second covering layer facing away from the substrate and covers the second covering layer.
  • the first metal wall and the second metal wall are arranged around the side wall of the light-emitting element to form a sub-pixel opening; the first connection line and the The second connection lines are arranged at intervals and cover the sub-pixel opening.
  • the driving circuit layer includes a first driving element and a second driving element; the first driving element is located on a side of the second driving element close to the substrate, and the second driving element is electrically connected to The first driving element, the first electrode and the first driving element are electrically connected.
  • the preparation method of the display panel includes:
  • a driving circuit layer is produced on one side of the substrate; the driving circuit layer includes driving elements, common electrodes and signal traces;
  • the light-emitting element includes a semiconductor layer, a first electrode and a second electrode, the first electrode and the second electrode are located on the side of the light-emitting element away from the substrate. the surface of one side;
  • a first through hole and a second through hole are made on the first covering layer to partially expose the driving element and the common electrode respectively; wherein the first through hole and the second through hole are spaced apart and surround The side wall of the light-emitting element is provided;
  • first through hole and the second through hole with metal to form a first metal wall and a second metal wall; wherein the first metal wall and the second metal wall are used to reflect the Part of the light-emitting element emits light to the substrate;
  • a conductive layer is made on the first covering layer; wherein the conductive layer includes a first connection line and a second connection line, and the first connection line connects the first electrode and the first metal wall, so The second connection line connects the second electrode and the second metal wall.
  • the display panel provides a first covering layer on the side of the light-emitting element facing away from the substrate, and forms a first through hole and a second through hole on the first covering layer, and
  • the first through hole extends to the driving circuit layer to partially expose the driving element
  • the second through hole extends to the driving circuit layer to partially expose the common electrode, so that the first electrode and the second electrode of the light emitting element can pass through the first through hole and the second electrode respectively.
  • the two through holes are electrically connected to the driving element and the common electrode, so that the driving circuit layer drives the light-emitting element to emit light; at the same time, by filling the first through hole and the second through hole with metal, the first through hole and the second through hole are filled with metal respectively.
  • the first metal wall and the second metal wall are formed in the hole, thereby improving the conductive performance of the conductive structure in the through hole and avoiding the problem of poor conductivity; in addition, by arranging the first through hole and the second through hole at intervals and surrounding the light emitting element
  • the side walls are arranged such that the first metal wall and the second metal wall formed in the first through hole and the second through hole are spaced apart and surround the side wall of the light emitting element, so that the first metal wall and the second metal wall are also It can have both the functions and functions of the black matrix, and due to their metallic properties, the first metal wall and the second metal wall allow part of the emitted light from the light-emitting element to be reflected from the first metal wall and/or the second metal wall.
  • the light emits from one side of the substrate thereby effectively improving the luminous efficiency of the light-emitting element and improving the light transmittance of the display panel, greatly improving the brightness of the image during display and further reducing the power consumption of the display panel.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic top structural view of a single sub-pixel of the display panel shown in Figure 1 according to the first embodiment
  • Figure 3 is a schematic top structural view of another embodiment of a single sub-pixel of the display panel shown in Figure 1;
  • (a) in Figure 3 is a schematic top structural view of a second embodiment of a single sub-pixel shown in Figure 1;
  • Figure (b) in Figure 3 is a top view structural diagram of the third embodiment of a single sub-pixel shown in Figure 1;
  • (c) in Figure 3 is a top view of the fourth embodiment of a single sub-pixel shown in Figure 1 Structural schematic diagram;
  • Figure 3 (d) is a top structural schematic diagram of the fifth embodiment of the single sub-pixel shown in Figure 1;
  • Figure 3 (e) is the sixth embodiment of the single sub-pixel shown in Figure 1
  • a schematic top view of the structure is provided;
  • (f) in Figure 3 is a schematic top view of the structure of the seventh embodiment of the single sub-pixel shown in Figure 1;
  • Figure 4 is a schematic top structural view of another embodiment of the conductive layer, first metal wall, second metal wall and light-emitting element of a single sub-pixel of the display panel shown in Figure 1;
  • Figure 5a is a schematic top structural view of a single sub-pixel of the display panel shown in Figure 1 according to another embodiment
  • Figure 5b is a schematic top structural view of another embodiment of a single sub-pixel of the display panel shown in Figure 1;
  • Figure 6 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIGS 7a-7k are schematic process flow diagrams of the preparation method of the display panel shown in Figure 6;
  • FIG. 8 is a schematic flowchart of an embodiment of step S2 of the preparation method shown in FIG. 6 .
  • first”, “second” and “third” in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as “first”, “second”, and “third” may explicitly or implicitly include at least one of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise clearly and specifically limited. All directional indications (such as up, down, left, right, front, back%) in the embodiments of this application are only used to explain the relative positional relationship between components in a specific posture (as shown in the drawings). , sports conditions, etc., if the specific posture changes, the directional indication will also change accordingly.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • a display panel 100 is provided.
  • the display panel 100 includes a substrate 10 , a driving circuit layer 20 and a plurality of light-emitting elements 40 .
  • the substrate 10 is used to carry and protect the driving circuit layer 20 to prevent the driving circuit layer 20 from being exposed and damaged.
  • the driving circuit layer 20 is used to drive the light emitting element 40 to emit light, thereby displaying images.
  • the substrate 10 can be plate-shaped, and its shape and size can be set according to actual production requirements; for example, the size, shape, material, etc. of the substrate 10 can be set according to the size, shape and other factors of the display panel 100 .
  • the substrate 10 may be a flexible substrate or a rigid substrate.
  • the substrate 10 can be made of insulating material, such as glass, resin, organic polymer materials, etc.; the substrate 10 can also be made of metal, and an insulating layer needs to be provided on the metal substrate to avoid interference with the display panel 100 Problems such as short circuits occur in other metal layers.
  • the substrate 10 is made of transparent material, so that the light emitted from the light-emitting element 40 can be emitted through the substrate 10 .
  • the driving circuit layer 20 is disposed on one side of the substrate 10 and is used to provide driving signals to the light-emitting element 40 so that the light-emitting element 40 displays a corresponding image.
  • the driving circuit layer 20 includes driving elements, common electrodes 24 and signal traces. Among them, each driving element and the common electrode 24 are electrically connected through corresponding signal wiring to form an array driving circuit; specifically, the signal wiring may include VDD signal wiring, VSS signal wiring, Data signal wiring, Scan signal Routing etc.
  • the driving element 23 includes a first driving element 21 and a second driving element 22 .
  • the first driving element 21 is located on the side of the second driving element 22 close to the substrate 10.
  • the first driving element 21 can use a low-temperature polysilicon transistor.
  • the low-temperature polysilicon transistor As the first driving element 21, due to its low-temperature polysilicon Compared with traditional amorphous silicon semiconductors, the electron migration rate is higher, and its current passing capacity is higher, which makes the display panel 100 respond faster and can better meet the needs of the large size of the display panel 100 and the relatively large size of the LED display panel 100 Large current passing capacity; at the same time, by using low-temperature polysilicon transistors as the driving elements 23, the array driving circuit occupies a smaller area, thereby making the light-transmitting area of the display panel 100 larger and improving the brightness and pixel resolution of the image display. degree, and at the same time, the power consumption of the driving circuit layer 20 can be effectively reduced.
  • the second driving element 22 is disposed on a side of the first driving element 21 away from the substrate 10 , and an insulating dielectric layer is disposed between the second driving element 22 and the first driving element 21 to prevent the first driving element 21 from interfacing with the substrate 10 .
  • a short circuit problem occurs between the second driving elements 22; the insulating dielectric layer has a conductive connection hole, and the second driving element 22 is electrically connected to the first driving element 21 through the conductive connection hole for controlling the current of the first driving element 21. Control, therefore, the second driving element 22 has lower requirements for current passing capability, but higher requirements for leakage current in the off state.
  • the second driving element 22 by using an oxide semiconductor transistor as the second driving element 22, not only can The current size of the first driving element 21 is controlled, and the leakage current of the second driving element 22 in the off state is reduced, thereby further reducing the power consumption of the array driving circuit.
  • the drain of the second driving element 22 is electrically connected to the gate 211 of the first driving element 21 , so that the second driving element 22 controls the current magnitude of the first driving element 21 .
  • the driving circuit layer 20 effectively reduces the power consumption of the display panel 100 and improves the performance of the display panel 100 by using an array driving circuit formed by low-temperature polysilicon transistors with higher electron mobility and oxide semiconductors that generate smaller leakage currents.
  • the brightness and pixel resolution of the image display is a simple circuit that reduces the power consumption of the display panel 100 and improves the performance of the display panel 100 by using an array driving circuit formed by low-temperature polysilicon transistors with higher electron mobility and oxide semiconductors that generate smaller leakage currents.
  • a flat layer 30 is provided on the side of the driving circuit layer 20 facing away from the substrate 10 .
  • the flat layer 30 covers the driving circuit layer 20 to form a relatively flat layer on the side facing away from the substrate 10 .
  • the flat surface can not only be used as an insulating layer, but can also be used to set other components.
  • the material of the flat layer 30 may include an insulating transparent material, so that the flat layer 30 has insulation and light-transmitting properties; the thickness of the flat layer 30 may be set according to actual needs, and is not specifically limited.
  • the light-emitting element 40 is disposed on the side of the flat layer 30 facing away from the substrate 10 and is used to electrically connect with the driving circuit layer 20 to receive the driving signal of the array driving circuit and display corresponding image information.
  • the light-emitting element 40 includes a semiconductor layer 43, a first electrode 41 and a second electrode 42; wherein the first electrode 41 and the second electrode 42 are located on a side of the semiconductor layer 43 away from the substrate 10, so that the light-emitting element 40
  • the semiconductor layer 43 is located on the side close to the substrate 10, and the first electrode 41 and the second electrode 42 are located on the side away from the substrate 10; it can also be understood that the semiconductor layer 43 of the light-emitting element 40 is disposed toward the substrate 10,
  • the first electrode 41 and the second electrode 42 are arranged in a direction away from the substrate 10 , so that the emitting direction of the light emitted from the light-emitting element 40 is toward the substrate 10 and emitted outward through one side of the substrate 10 ; at the same time
  • the first electrode 41 of the light-emitting element 40 can be an anode, and the second electrode 42 can be a cathode; the first electrode 41 is electrically connected to the driving element 23 of the driving circuit layer 20 , and the second electrode 42 is connected to the common electrode of the driving circuit layer 20 24 electrical connections. Specifically, the first electrode 41 is electrically connected to the source/drain electrode 212 of the first driving element 21, and the second electrode 42 is electrically connected to the common electrode 24 (VSS common electrode 24) of the driving circuit layer 20, so that the driving circuit The layer 20 provides a driving signal to the light-emitting element 40 to cause the light-emitting element 40 to emit light and display a corresponding image.
  • the light-emitting element 40 can be a current-driven light-emitting element 40 such as an LED, such as a Micro LED, a Mini LED, etc.; the size of the Mini LED is between 50 microns and 200 microns, and the size of the Micro LED is less than 50 microns.
  • Micro LED is preferably used as the light-emitting element 40 to obtain the Micro LED display panel 100.
  • a groove 31 is formed on the surface of the side of the flat layer 30 facing away from the substrate 10, and the light-emitting elements 40 are disposed in the groove 31, so that the light-emitting elements 40 can be transferred in large quantities.
  • the light-emitting element 40 can be accurately transferred into the groove 31 , which effectively improves the transfer accuracy of the light-emitting element 40 and thus improves the product yield of the display panel 100 .
  • a first covering layer 50 is provided on the side of the light-emitting element 40 away from the substrate 10 , and the first covering layer 50 is used to cover the light-emitting element 40 .
  • the material of the first covering layer 50 includes an insulating material, thereby preventing a short circuit between the first electrode 41 and the second electrode 42 of the light-emitting element 40, resulting in abnormal image display.
  • the first covering layer 50 has a first through hole 51 and a second through hole 52 , and the first through hole 51 extends toward the substrate 10 to the driving circuit layer 20 to partially expose the driving element 23 , and the second through hole 52 It extends toward the substrate 10 to the driving circuit layer 20 so that the common electrode 24 is partially exposed.
  • the first through hole 51 extends toward the substrate 10 to the first driving element 21 so that the source/drain electrode 212 of the first driving element 21 is at least partially exposed
  • the second through hole 52 extends toward the substrate 10 Extend to the common electrode 24 (VSS common electrode 24), so that the common electrode 24 is partially exposed, so that the first electrode 41 and the second electrode 42 of the light-emitting element 40 can pass through the first through hole 51 and the second through hole 52 respectively.
  • the driving circuit layer 20 provides a driving signal to the light-emitting element 40, causing the light-emitting element 40 to emit light and display the corresponding image.
  • FIG. 2 is a schematic top structural view of a single sub-pixel of the display panel shown in FIG. 1 according to the first embodiment.
  • the first through holes 51 and the second through holes 52 are spaced apart and arranged around the side walls of the light emitting element 40 , and both the first through holes 51 and the second through holes 52 are filled with metal to form the first through hole 51 and the second through hole 52 .
  • the metal wall 511 and the second metal wall 521 not only improve the wire performance of the conductive structures in the first through hole 51 and the second through hole 52 and avoid the problem of poor conductivity in the through hole; moreover, the first metal wall 511 and The second metal wall 521 is arranged around the side wall of the light-emitting element 40 and can also function as a black matrix to prevent light mixing between pixels or light leakage to the driving circuit layer 20 causing abnormality of the driving element 23; at the same time, the second metal wall 521 Due to their metallic properties, the first metal wall 511 and the second metal wall 521 allow part of the light emitted from the light-emitting element 40 to be reflected by the first metal wall 511 and the second metal wall 521 and then emitted from the side of the substrate 10, thereby improving the efficiency.
  • the luminous efficiency of the light-emitting element 40 increases the light transmittance of the display panel 100 , so that the brightness of the image displayed by the display panel 100 is greatly improved, and the power consumption of the display panel 100 can be further reduced.
  • the first through hole 51 and the second through hole 52 are filled with metal, and the metal can be a metal with good electrical conductivity such as gold, silver, copper, aluminum, zinc, or an alloy thereof.
  • the metal can be a metal with good electrical conductivity such as gold, silver, copper, aluminum, zinc, or an alloy thereof.
  • Copper is filled into the first through hole 51 and the second through hole 52 to form the first metal wall 511 and the second metal wall 521 .
  • the first covering layer 50 also has third through holes 53 and fourth through holes 54 .
  • the third through hole 53 at least partially exposes the first electrode 41 of the light-emitting element 40
  • the fourth through hole 54 at least partially exposes the second electrode 42 , so that the first electrode 41 can communicate with the first electrode 41 through the third through hole 53 .
  • the metal wall 511 is electrically connected, and the second electrode 42 can be electrically connected to the common electrode 24 through the fourth through hole 54 .
  • the display panel 100 further includes a conductive layer 55 , which is disposed on a side of the first covering layer 50 facing away from the substrate 10 ; the conductive layer 55 includes a first connection line 551 and a second connection line 551 .
  • Connection line 552; the first connection line 551 is provided on a side of the first covering layer 50 facing away from the substrate 10 and extends to the third through hole 53, and the second connection line 552 is provided on a side of the first covering layer 50 facing away from the substrate 10 side and extends to the fourth through hole 54 .
  • the first metal wall 511 is connected to the first electrode 41 through the first connection line 551, and the second metal wall 521 is connected to the second electrode 42 through the second connection line 552, so that the first electrode 41 of the light-emitting element 40 passes through the first
  • the connection line 551 and the first metal wall 511 are electrically connected to the first driving element 21
  • the second electrode 42 is electrically connected to the common electrode 24 through the second connection line 552 and the second metal wall 521 .
  • the light-emitting element 40 is offset from the driving element 23 , the common electrode 24 and the signal wiring, and the portion of the insulating dielectric layer of the driving circuit layer 20 corresponding to the light-emitting element 40 is made of light-transmitting material, so that the light-emitting element 40 The emitted light can emerge from the substrate 10 side.
  • the array driving circuit in the driving circuit layer 20 is staggered with the light-emitting element 40 ; or it can also be understood that the array driving circuit in the driving circuit layer 20 is on the substrate 10
  • the orthographic projection does not overlap with the orthographic projection of the light-emitting element 40 on the substrate 10; thereby improving the pixel aperture ratio of the display panel 100, preventing the array driving circuit from blocking the emitted light of the light-emitting element 40, and reducing the light transmittance of the display panel 100 , resulting in the problem of low image brightness of the display panel 100, so that the display panel 100 uses the substrate 10 side as the light-emitting surface.
  • the first electrode 41 and the second electrode 42 of the light-emitting element 40 are spaced apart in the first direction A parallel to the display panel 100; the light-emitting element 40 has a structure along the first direction A.
  • the first side 401 and the second side 402 are spaced apart, and the third side 403 and the fourth side 404 are connected to the first side 401 and the second side 402;
  • the first metal wall 511 is spaced apart from the first side 401 and Extending to the third side 403 side and the fourth side 404 side;
  • the second metal walls 521 are spaced apart from the second side 402 side and extend to the third side 403 side and the fourth side 404 side;
  • the first metal wall The projection of the portion of the wall 511 located on the third side 403 on the third side 403 at least partially overlaps with the projection of the portion of the second metal wall 521 located on the third side 403 on the third side 403;
  • the first metal wall 511 is located on the third side 403.
  • the projection of the part on the fourth side 404 on the fourth side 404 at least partially overlaps with the projection of the part of the second metal wall 521 on the fourth side 404 on the fourth side 404, thereby ensuring that the first metal wall 511 and the
  • the two metal walls 521 can completely surround the side walls of the light-emitting element 40 to prevent the light emitted by the light-emitting element 40 from emitting from the gap between the first metal wall 511 and the second metal wall 521 and causing light leakage and light mixing between pixels.
  • the display effect is affected, and light leakage to the driving element 23 causes abnormal switching of the driving element 23 , thus affecting the driving signal of the driving circuit layer 20 , resulting in abnormal image display.
  • Figure 3 is a top structural schematic diagram of another embodiment of a single sub-pixel of the display panel shown in Figure 1; (a) in Figure 3 is a second embodiment of a single sub-pixel of the display panel shown in Figure 1. Top structural schematic diagram; Figure 3 (b) is a top structural schematic diagram of the third embodiment of a single sub-pixel shown in Figure 1; Figure 3 (c) is a fourth implementation of a single sub-pixel shown in Figure 1
  • (d) in Figure 3 is the top structural schematic diagram provided by the fifth embodiment of the single sub-pixel shown in Figure 1;
  • (e) in Figure 3 is the single sub-pixel shown in Figure 1
  • (f) in Figure 3 is a schematic top view of the structure provided by the seventh embodiment of the single sub-pixel shown in Figure 1 .
  • the cross-sections of the first metal wall 511 and the second metal wall 521 may be arc-shaped, unclosed polygons, or other irregular shapes, and may be arranged at intervals. , and are arranged around the side walls of the light-emitting element 40 to achieve the technical effects that the first metal wall 511 and the second metal wall 521 involved in the above embodiment can achieve.
  • the specific shapes and thicknesses of the first metal wall 511 and the second metal wall 521 can also be other shapes and thicknesses.
  • the embodiments of this application only show some examples, and do not mean that their structures are limited to this. In specific embodiments, the specific shapes and thicknesses of the first metal wall 511 and the second metal wall 521 can be set according to actual needs, and there are no specific restrictions on this.
  • FIG. 4 is a schematic top structural view of another embodiment of the conductive layer, the first metal wall, the second metal wall and the light-emitting element of a single sub-pixel of the display panel shown in FIG. 1 .
  • the first metal wall 511 and the second metal wall 521 are arranged around the side walls of the light-emitting element 40 to form a sub-pixel opening; the first connection line 551 It is spaced apart from the second connection line 552 and covers the sub-pixel opening.
  • the first connection line 551 covers the first electrode 41 of the light-emitting element 40 and extends from the periphery of the first electrode 41 to the first metal wall 511, so that the first connection line 551 forms a fan shape; similarly, the second connection The line 552 covers the second electrode 42 of the light-emitting element 40 and extends from the periphery of the second electrode 42 to the second metal wall 521, so that the first connection line 551 and the second connection line 552 cover the light-emitting element 40, so that the first connection line 551 and the second connection line 552 cover the light-emitting element 40.
  • connection line 551 and the second connection line 552 form a film layer similar to a light-shielding layer or a reflective film layer on the side of the light-emitting element 40 facing away from the substrate 10 , which can be used to reflect the light emitted by the light-emitting element 40 toward this position to the substrate 10 , to prevent the light emitted from the light-emitting element 40 from emitting from the side away from the substrate 10 or leaking to other places, thereby further improving the luminous efficiency of the light-emitting element 40 .
  • first connection line 551 and the second connection line 552 can be made of reflective materials or opaque materials to prevent the emitted light of the light-emitting element 40 from transmitting through the conductive layer 55; and the first connection line 551 and the second connection line 552 They still need to be spaced apart to avoid short circuit between the first electrode 41 and the second electrode 42 of the light emitting element 40 .
  • FIG. 5a is a schematic top structural view of a single sub-pixel of the display panel shown in FIG. 1 according to another embodiment.
  • the third An insulating reflective layer 61 is disposed in the gap between a connecting line 551 and a second connecting line 552, so that the first connecting line 551, the second connecting line 552 and the insulating reflective layer 61 form a continuous film layer that completely covers the sub-pixel opening.
  • the insulating reflective layer 61 is an insulating and reflective material to avoid short circuit between the first electrode 41 and the second electrode 42 .
  • FIG. 5b is a schematic top view of another embodiment of a single sub-pixel of the display panel shown in FIG. 1 ; the insulating reflective layer 61 can also be disposed on the light-emitting element 40 away from the substrate 10
  • One side can be provided in the same layer as the second covering layer 60 , or can be provided on the side of the second covering layer 60 close to the substrate, and completely covers the sub-pixel opening to seal the sub-pixel opening, thereby preventing the light-emitting element 40 from being damaged.
  • the emitted light is emitted from the side away from the substrate 10 or leaks to other places, and part of the emitted light of the light-emitting element 40 can also be reflected to the substrate 10 to further improve the luminous efficiency of the light-emitting element 40 .
  • the arrangement of the insulating reflective layer 61 in this embodiment is simpler, and the first connection line 551 and the second connection line 552 do not need to increase the area for reflecting light or blocking. The light is emitted, thereby making the distance between the first connection line 551 and the second connection line 552 larger, thereby effectively preventing the first electrode 41 and the second electrode 42 from being short-circuited.
  • the first metal wall 511 and the second metal wall 521 are in contact with the light-emitting element.
  • the portion of the first covering layer 50 between 40 can be set as a reflective or opaque film layer, thereby preventing the emitted light of the light-emitting element 40 from being emitted in a direction away from the substrate 10, and preventing the emitted light of the light-emitting element 40 from being emitted away from the substrate 10.
  • One side of the bottom 10 emit light, causing the problem of light leakage in the display panel 100 .
  • the first metal wall 511 and/or the second metal wall 521 is close to the surface of the light-emitting element 40 and the central axis of the light-emitting element 40 .
  • the radial distance between them gradually increases, so that part of the emitted light from the light-emitting element 40 is reflected to the substrate 10 through the first metal wall 511 and/or the second metal wall 521 and emitted from the substrate 10 .
  • the radial distance between the surface of the first metal wall 511 and/or the second metal wall 521 close to the light-emitting element 40 and the central axis of the light-emitting element 40 gradually increases, that is, the first metal wall 511 and/or the second metal wall 521.
  • the surface of a metal wall 511 and/or the second metal wall 521 close to the light-emitting element 40 is a slope, and the distance between the surface of the first metal wall 511 and/or the second metal wall 521 close to the light-emitting element 40 and the central axis of the light-emitting element 40
  • the opening gradually increases along the light emission direction of the display panel 100, thereby increasing the area of the reflective surface of the first metal wall 511 and the second metal wall 521 for reflecting the emitted light of the light-emitting element 40, so that more emitted light can pass through the third metal wall 511 and the second metal wall 521.
  • the hole configuration of the first through hole 51 and the second through hole 52 matches the shape and structure of the first metal wall 511 and the second metal wall 521 , so that the first through hole 51 and the second through hole 52
  • the middle filling metal forms the above-mentioned first metal wall 511 and second metal wall 521 .
  • the display panel 100 further includes a second covering layer 60 and a reflective layer 70 .
  • the second covering layer 60 is disposed on the side of the conductive layer 55 facing away from the substrate 10 and covers the conductive layer 55 to isolate the conductive layer 55 from the outside and avoid problems such as damage to the structure of the conductive layer 55 or short circuit of the connection lines due to external factors.
  • the reflective layer 70 is disposed on a side of the second covering layer 60 away from the substrate 10 and covers the second covering layer 60 to prevent light emitted from the light emitting element 40 from emitting from this side and causing light leakage.
  • the light emitted by the light-emitting element 40 in the direction away from the substrate 10 is basically reflected to the substrate 10 by the insulating reflective layer 61 (see FIG. 5b), or is formed by the conductive layer 55 and the insulating reflective layer 61.
  • the continuous film layer (see FIG. 5 a ) is reflected to the substrate 10 and then emitted through the substrate 10 , thereby effectively improving the luminous efficiency of the light-emitting element 40 and further reducing the power consumption of the display panel 100 .
  • the main function of the reflective layer 70 is to prevent light leakage caused by light emitting from the side away from the substrate 10 .
  • FIG. 6 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIGS. 7a-7k is a schematic process flow diagram of a method for manufacturing the display panel shown in FIG. 6.
  • a method of manufacturing the display panel 100 is provided.
  • the preparation method includes the following steps:
  • the driving circuit layer 20 includes the driving element 23, the common electrode 24 and the signal wiring;
  • the light-emitting element 40 includes a semiconductor layer 43, a first electrode 41 and a second electrode 42.
  • the first electrode 41 and the second electrode 42 are located on the side of the light-emitting element 40 away from the substrate 10. the surface of one side;
  • S5 Make the first covering layer 50 on the side of the light-emitting element 40 away from the substrate 10, and make the first covering layer 50 cover the light-emitting element 40;
  • S6 Make a first through hole 51 and a second through hole 52 on the first covering layer 50 to partially expose the driving element 23 and the common electrode 24 respectively; wherein the first through hole 51 and the second through hole 52 are spaced apart. , and is arranged around the side wall of the light-emitting element 40;
  • S7 Fill the first through hole 51 and the second through hole 52 with metal to form the first metal wall 511 and the second metal wall 521; wherein the first metal wall 511 and the second metal wall 521 are used to reflect the light emitting element. A portion of 40 emits light to the substrate 10;
  • S8 Make a conductive layer 55 on the first covering layer 50; the conductive layer 55 includes a first connection line 551 and a second connection line 552.
  • the first connection line 551 connects the first electrode 41 and the first metal wall 511.
  • the two connection lines 552 connect the second electrode 42 and the second metal wall 521 .
  • the substrate 10 provided in step S1 may be the substrate 10 involved in the above embodiment to provide support and protection to the driving circuit layer 20; specifically, in this embodiment , the substrate 10 can be made of a light-transmitting material, so that the light emitted by the light-emitting element 40 can be emitted through the substrate.
  • the driving element 23, the common electrode 24 and the signal wiring can be patterned and formed by photomask etching, thereby forming a complete array driving circuit, thereby realizing driving the light-emitting element. glow.
  • the driving circuit layer 20 produced in step S2 of this embodiment can be the driving circuit layer 20 involved in the above embodiment, and can achieve the same technical effect.
  • a groove 31 is formed on the surface of the flat layer 30 produced in step S3 facing away from the substrate 10 for accommodating the light emitting element 40 ; the flat layer 30 covers the driving circuit layer 20 to form a groove 31 on the surface facing away from the substrate 10
  • a relatively flat plane is formed on one side, which can not only be used as an insulating layer, but also can be used to set other components.
  • the material of the flat layer 30 may include an insulating transparent material, so that the flat layer 30 has insulation and light-transmitting properties; the thickness of the flat layer 30 may be set according to actual needs, and is not specifically limited.
  • step S4 the light-emitting element 40 is transferred to the groove 31 of the flat layer 30 through mass transfer.
  • the light-emitting element 40 can be accurately transferred into the groove 31. , effectively improving the transfer accuracy of the light-emitting element 40, thereby improving the product yield of the display panel 100.
  • the light-emitting element 40 can be the light-emitting element 40 involved in the above embodiment, and can achieve the same or similar technical effects, which will not be described again here.
  • a first covering layer 50 is formed to cover the light-emitting element 40.
  • the material of the first covering layer 50 includes an insulating material, thereby preventing a short circuit between the first electrode 41 and the second electrode 42 of the light-emitting element 40, resulting in abnormal image display.
  • a first through hole 51 and a second through hole 52 are formed on the first covering layer 50 so that the first through hole 51 extends toward the substrate 10 to the driving circuit layer 20 , so that the driving element 23 is partially exposed, and the second through hole 52 extends toward the substrate 10 direction to the driving circuit layer 20 so that the common electrode 24 is partially exposed.
  • the first through hole 51 extends toward the substrate 10 to the first driving element 21 so that the source/drain electrode 212 of the first driving element 21 is at least partially exposed
  • the second through hole 52 extends toward the substrate 10 Extend to the common electrode 24 (VSS common electrode 24), so that the common electrode 24 is partially exposed, so that the first electrode 41 and the second electrode 42 of the light-emitting element 40 can pass through the first through hole 51 and the second through hole 52 respectively.
  • first driving element 21 and the common electrode 24 It is electrically connected to the first driving element 21 and the common electrode 24, thereby realizing the electrical connection between the driving circuit layer 20 and the light-emitting element 40, so that the driving circuit layer 20 provides a driving signal to the light-emitting element 40, causing the light-emitting element 40 to emit light and display the corresponding image.
  • third and fourth through holes 53 and fourth through holes need to be made on the first covering layer 50 . Hole 54 to at least partially expose the first electrode 41 and the second electrode 42 .
  • the first through hole 51 and the second through hole 52 are filled with metal.
  • the metal can be a metal with good electrical conductivity such as gold, silver, copper, aluminum, zinc, or its alloy.
  • copper is preferably filled into the first through hole 51 and the second through hole 52 to form the first metal wall 511 and the second metal wall 521 .
  • the first electrode 41 and the second electrode 42 are electrically connected to the corresponding components or electrodes through the first connection line 551 and the second connection line 552 respectively. So that the light-emitting element 40 can be driven by the driving circuit layer 20 to emit light.
  • the first covering layer 50 is formed on the side of the light-emitting element 40 away from the substrate 10, and the first through hole 51 and the second through hole 52 are formed on the first covering layer 50, and the first through hole 51 is formed on the first covering layer 50.
  • the through hole 51 extends to the driving circuit layer 20 to partially expose the driving element 23, and the second through hole 52 extends to the driving circuit layer 20 to partially expose the common electrode 24, so that the first electrode 41 and the second electrode 42 of the light emitting element 40 can be respectively
  • the first through hole 51 and the second through hole 52 are electrically connected to the driving element 23 and the common electrode 24, so that the driving circuit layer 20 drives the light emitting element 40 to emit light; at the same time, through the first through hole 51 and the second through hole 52 Fill metal inside to form the first metal wall 511 and the second metal wall 521 in the first through hole 51 and the second through hole 52 respectively, thereby improving the conductive performance of the conductive structure in the through hole and avoiding the problem of poor conductivity;
  • the first through holes 51 and the second through holes 52 at intervals and surrounding the side walls of the light emitting element 40 , the first metal wall 511 and the second metal wall 511 formed in the first through holes 51 and the second through holes 52
  • the two metal walls 521 are spaced apart and surround the side walls
  • FIG. 8 is a schematic flowchart of an embodiment of step S2 of the preparation method shown in FIG. 6 .
  • the steps of fabricating the driving circuit layer 20 on one side of the substrate 10 may specifically include:
  • S21 Make the first driving element 21 on one side of the substrate 10; the first driving element 21 includes a low-temperature polysilicon transistor;
  • a low-temperature polysilicon transistor is made as the first driving element 21. Since its electron migration rate is higher than that of the traditional amorphous silicon semiconductor, its current passing capacity is higher, so that the display panel 100 The response speed is faster, which can better meet the needs of the large size of the display panel 100 and the larger current passing capacity of the LED display panel 100; at the same time, by using a low-temperature polysilicon transistor as the first driving element 21, the area occupied by the array driving circuit is reduced Smaller, thus making the light-transmitting area of the display panel 100 larger, improving the brightness and pixel resolution of image display, and also effectively reducing the power consumption of the driving circuit layer 20 .
  • the second driving element 22 By fabricating an oxide semiconductor transistor as the second driving element 22 and electrically connecting the second driving element 22 with the first driving element 21 for controlling the current magnitude of the first driving element 21, the second driving element 22 has lower requirements for current passing capability, but higher requirements for leakage current in the off state.
  • an oxide semiconductor transistor as the second driving element 22
  • not only the current flow to the first driving element 21 can be achieved
  • the size is controlled, and the leakage current of the second driving element 22 in the off state is reduced, thereby further reducing the power consumption of the array driving circuit.
  • the drain of the second driving element 22 is electrically connected to the gate 211 of the first driving element 21 , so that the second driving element 22 controls the current magnitude of the first driving element 21 .
  • the preparation method of the display panel may also include:
  • S10 Create a reflective layer 70 on the side of the second covering layer 60 facing away from the substrate 10, and make the reflective layer 70 cover the second covering layer 60.
  • the second covering layer 60 is formed on the side of the first covering layer 50 away from the substrate 10, and the second covering layer 60 covers the conductive layer 55, so that The conductive layer 55 is isolated from the outside to avoid problems such as damage to the structure of the conductive layer 55 or short circuit of the connecting lines due to external factors.
  • the reflective layer 70 By forming the reflective layer 70 on the side of the second covering layer 60 away from the substrate 10 and making the reflective layer 70 cover the second covering layer 60, the light emitted by the light-emitting element 40 can be prevented from being emitted from this side to cause light leakage, and the light can be diverted Reflected to the substrate 10 to improve the luminous efficiency of the light-emitting element 40 .

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Abstract

本申请提供一种显示面板及其制备方法。显示面板包括依次层叠的衬底、驱动电路层、平坦层、发光元件和第一覆盖层。发光元件的第一电极和第二电极分别与驱动电路层的驱动元件和公共电极电连接；第一覆盖层的第一通孔和第二通孔使驱动元件和公共电极部分暴露，并间隔设置且环绕发光元件的侧壁，两通孔内均填充有金属，形成第一金属壁和第二金属壁，使部分出射光经两金属壁反射后从衬底一侧出射；第一金属壁电连接第一电极与驱动元件，第二金属壁电连接第二电极与公共电极。该显示面板可提高透光率及降低功耗。

Description

显示面板及其制备方法
相关申请的交叉引用
本申请基于2022年8月2日提交的中国专利申请2022109239046主张其优先权，此处通过参照引入其全部的记载内容。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制备方法。
背景技术
无机微发光二极管(Micro Light Emitting Diode，Micro LED)显示面板是当今显示面板研究领域的热点之一，与OLED显示面板相比，Micro LED具有信赖性高、功耗低、亮度高及响应速度快等优点。特别是在AR/VR/XR以及穿戴领域中，由于其对显示尺寸的需求较小，再结合现在的Micro LED显示技术成熟程度，使得Micro LED得到了极大的关注和应用。
目前，显示面板中，需要在连接通孔中沉积导电层，以实现各元器件和/或信号线之间的电连接；同时，显示面板中需要设置黑矩阵或遮光层，以避免像素之间混光或漏光至驱动电路层导致驱动元件异常的现象发生。
然而，现有技术中的显示面板，连接通孔中的导电层极易出现因导电层沉积不均导致导电不良的问题；以及，黑矩阵或遮光层由于其吸光性，存在显示面板透光率较低的问题。
发明内容
本申请提供的显示面板及其制备方法，旨在解决现有显示面板中因连接通孔中导电层沉积不均导致导电不良的问题以及显示面板透光率较低的问题。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种显示面板。该显示面板包括：
衬底；
驱动电路层，设置于所述衬底的一侧，所述驱动电路层包括驱动元件、公共电极以及信号走线；
平坦层，设置于所述驱动电路层背离所述衬底的一侧，且覆盖所述驱动电路层；
发光元件，设置于所述平坦层背离所述衬底的一侧；所述发光元件包括半导体层、第一电极和第二电极；所述第一电极与所述驱动元件电连接，且所述第二电极与所述公共电极电连接；
第一覆盖层，设置于所述发光元件背离所述衬底的一侧，且覆盖所述发光元件；
其中，所述第一电极和所述第二电极位于所述半导体层背离所述衬底的一侧；所述第一覆盖层具有第一通孔和第二通孔，所述第一通孔延伸至所述驱动电路层，使所述驱动元件部分暴露；所述第二通孔延伸至所述驱动电路层，使所述公共电极部分暴露；
其中，所述第一通孔和所述第二通孔间隔设置且环绕所述发光元件的侧壁设置，在所述第一通孔和所述第二通孔内均填充有金属，以形成第一金属壁和第二金属壁， 使得所述发光元件的部分出射光经所述第一金属壁和所述第二金属壁反射从所述衬底一侧出射；且所述第一金属壁电连接所述第一电极与所驱动元件，所述第二金属壁电连接所述第二电极与所述公共电极。
其中，所述发光元件与所述驱动元件、所述公共电极以及所述信号走线错位设置，且所述驱动电路层的绝缘介质层与所述发光元件对应的部分采用透光材料，使得所述发光元件发射的光从所述衬底一侧出射。
其中，所述第一电极和所述第二电极在平行于所述显示面板的第一方向上间隔设置，所述发光元件具有沿着所述第一方向间隔设置的第一侧面和第二侧面，以及连接所述第一侧面和所述第二侧面的第三侧面和第四侧面；所述第一金属壁间隔设置于所述第一侧面一侧且延伸至所述第三侧面一侧和所述第四侧面一侧；所述第二金属壁间隔设置于所述第二侧面一侧且延伸至所述第三侧面一侧和所述第四侧面一侧；所述第一金属壁位于所述第三侧面一侧的部分在所述第三侧面的投影与所述第二金属壁位于所述第三侧面一侧的部分在所述第三侧面的投影至少部分重叠；所述第一金属壁位于所述第四侧面一侧的部分在所述第四侧面的投影与所述第二金属壁位于所述第四侧面一侧的部分在所述第四侧面的投影至少部分重叠。
其中，沿垂直于所述衬底的出光方向上，所述第一金属壁和/或所述第二金属壁靠近所述发光元件的表面与所述发光元件的中轴线之间的径向距离逐渐增大，以使所述发光元件的部分出射光经所述第一金属壁和/或所述第二金属壁反射至所述衬底。
所述平坦层背离所述衬底的一侧的表面形成有凹槽，所述发光元件设置于所述凹槽中。
所述第一覆盖层还具有第三通孔和第四通孔，所述第三通孔使所述第一电极至少部分暴露，所述第四通孔使所述第二电极至少部分暴露；
所述显示面板还包括导电层，所述导电层包括第一连接线路和第二连接线路；所述第一连接线路设置于所述第一覆盖层背离所述衬底的一侧且延伸至所述第三通孔，所述第二连接线路设置于所述第一覆盖层背离所述衬底的一侧且延伸至所述第四通孔；所述第一金属壁通过所述第一连接线路连接于所述第一电极，所述第二金属壁通过所述第二连接线路连接于所述第二电极。
其中，所述显示面板还包括：
第二覆盖层，设置于所述导电层背离所述衬底的一侧且覆盖所述导电层；
反射层，设置于所述第二覆盖层背离所述衬底的一侧且覆盖所述第二覆盖层。
其中，在所述第一覆盖层的平行方向上，所述第一金属壁和所述第二金属壁环绕所述发光元件的侧壁设置，形成子像素开口；所述第一连接线路和所述第二连接线路间隔设置，且覆盖于所述子像素开口。
其中，所述驱动电路层包括第一驱动元件和第二驱动元件；所述第一驱动元件位于所述第二驱动元件靠近所述衬底的一侧，且所述第二驱动元件电连接于所述第一驱动元件，所述第一电极与所述第一驱动元件电连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种显示面板的制备方法。该显示面板的制备方法包括：
提供衬底；
在所述衬底的一侧制作驱动电路层；所述驱动电路层包括驱动元件、公共电极以及信号走线；
在所述驱动电路层背离所述衬底的一侧制作平坦层，且使绝缘层覆盖所述驱动电路层；
将发光元件转移至所述平坦层；其中，所述发光元件包括半导体层、第一电极和第二电极，所述第一电极和所述第二电极位于所述发光元件背离所述衬底的一侧的表面；
在所述发光元件背离所述衬底的一侧制作第一覆盖层，且使第一覆盖层覆盖所述发光元件；
在第一覆盖层上制作第一通孔和第二通孔，以分别使所述驱动元件和所述公共电极部分暴露；其中，所述第一通孔和第二通孔间隔设置，且环绕所述发光元件的侧壁设置；
向所述第一通孔和所述第二通孔中填充金属，以形成第一金属壁和第二金属壁；其中，所述第一金属壁和所述第二金属壁用于反射所述发光元件的部分出射光至所述衬底；
在所述第一覆盖层上制作导电层；其中，所述导电层包括第一连接线路和第二连接线路，所述第一连接线路连接所述第一电极与所述第一金属壁，所述第二连接线路连接所述第二电极与所述第二金属壁。
本申请实施例的显示面板及其制备方法，该显示面板通过在发光元件背离衬底的一侧设置第一覆盖层，并在第一覆盖层上形成第一通孔和第二通孔，且第一通孔延伸至驱动电路层使驱动元件部分暴露，第二通孔延伸至驱动电路层使公共电极部分暴露，使得发光元件的第一电极和第二电极可分别通过第一通孔和第二通孔与驱动元件和公共电极电连接，从而使驱动电路层驱动发光元件发光；同时，通过在第一通孔和第二通孔内填充金属，以分别在第一通孔和第二通孔中形成第一金属壁和第二金属壁，从而提高通孔中导电结构的导电性能，避免导电不良的问题出现；此外，通过使第一通孔和第二通孔间隔设置且环绕发光元件的侧壁设置，使得形成于第一通孔和第二通孔中的第一金属壁和第二金属壁间隔设置且环绕发光元件的侧壁，从而使得第一金属壁和第二金属壁还可兼有黑矩阵的功能和作用，而且第一金属壁和第二金属壁由于其金属特性，使得发光元件的部分发射光发射至第一金属壁和/或第二金属壁时可被反射从衬底一侧出射，从而有效提高了发光元件的发光效率，提升了该显示面板的透光率，使得在显示时图像的亮度得到较大提升，且可进一步降低该显示面板的功耗。
附图说明
图1是本申请一实施例提供的显示面板的结构示意图；
图2是图1所示显示面板的单个子像素的第一实施例提供的俯视结构示意图；
图3是图1所示显示面板的单个子像素的其他实施例提供的俯视结构示意图；图3中的(a)是图1所示单个子像素的第二实施例提供的俯视结构示意图；图3中的(b)是图1所示单个子像素的第三实施例提供的的俯视结构示意图；图3中的(c)是图1所示单个子像素的第四实施例提供的的俯视结构示意图；图3中的(d)是图1所示单个子像素的第五实施例提供的的俯视结构示意图；图3中的(e)是图1所示单个子像素的第六实施例提供的的俯视结构示意图；图3中的(f)是图1所示单个子像素的第七实施例提供的的俯视结构示意图；
图4是图1所示显示面板的单个子像素的导电层与第一金属壁、第二金属壁和发光元件的另一实施例的俯视结构示意图；
图5a是图1所示显示面板的单个子像素的再一实施例的俯视结构示意图；
图5b是图1所示显示面板的单个子像素的又一实施例的俯视结构示意图；
图6是本申请一实施方式提供的显示面板的制备方法的流程示意图；
图7a-7k是图6所示显示面板的制备方法的工艺流程示意图；
图8是图6所示制备方法的步骤S2的一实施方式的流程示意图。
附图标记：
100-显示面板；10-衬底；20-驱动电路层；21-第一驱动元件；22-第二驱动元件；23-驱动元件；24-公共电极；211-栅极；212-源极/漏极电极；30-平坦层；31-凹槽；40-发光元件；401-第一侧面；402-第二侧面；403-第三侧面；404-第四侧面；41-第一电极；42-第二电极；43-半导体层；50-第一覆盖层；51-第一通孔；511-第一金属壁；52-第二通孔；521-第二金属壁；53-第三通孔；54-第四通孔；55-导电层；551-第一连接线路；552-第二连接线路；60-第二覆盖层；61-绝缘反光层；70-反射层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
下面结合附图和实施例对本申请进行详细的说明。
请参阅图1，图1是本申请一实施例提供的显示面板的结构示意图。在本实施例中，提供一种显示面板100，该显示面板100包括衬底10、驱动电路层20和多个发光元件40。其中，衬底10用于承载和保护驱动电路层20，避免驱动电路层20暴露而被破坏。驱动电路层20用于驱动发光元件40发光，从而显示图像。
其中，衬底10可为板状，其形状和大小可根据实际生产需求进行设置；例如，根据显示面板100的尺寸、形态等因素对衬底10的大小、形状、材质等进行设置。衬底10可为柔性基板或硬质基板。具体地，衬底10可为绝缘材质，例如玻璃、树脂、有机高分子材料等；衬底10也可为金属材质，在金属材质的基板上还需要设置绝缘层，以避免与显示面板100中其他金属层发生短路等问题。在本实施例中，该衬底10为透明材质的衬底10，以使发光元件40的出射光可经该衬底10出射。
其中，驱动电路层20设置于衬底10的一侧，用于向发光元件40提供驱动信号，以使发光元件40显示响应的图像。具体地，驱动电路层20包括驱动元件、公共电极24和信号走线。其中，各驱动元件及公共电极24分别通过相应的信号走线电连 接，以形成阵列驱动电路；具体地，信号走线可包括VDD信号走线、VSS信号走线，Data信号走线，Scan信号走线等。
具体地，驱动元件23包括第一驱动元件21和第二驱动元件22。其中，第一驱动元件21位于第二驱动元件22靠近衬底10的一侧，第一驱动元件21可采用低温多晶硅晶体管，以通过将低温多晶硅晶体管作为第一驱动元件21，由于其低温多晶硅的电子迁移速率相比传统的非晶硅半导体更高，其电流通过能力更高，使得该显示面板100的响应速度更快，能够更好地满足显示面板100大尺寸的需求以及LED显示面板100较大的电流通过能力；同时，通过使用低温多晶硅晶体管作为驱动元件23，使得阵列驱动电路占据的面积较小，从而使得显示面板100的透光区面积更大，提高了图像显示的亮度和像素解析度，同时还可有效降低驱动电路层20的功耗。
进一步地，第二驱动元件22设置于第一驱动元件21远离衬底10的一侧，第二驱动元件22与第一驱动元件21之间还设置有绝缘介质层，避免第一驱动元件21与第二驱动元件22之间发生短路问题；绝缘介质层具有导电连接孔，第二驱动元件22通过导电连接孔电连接于第一驱动元件21，以用于对第一驱动元件21的电流大小进行控制，因此，第二驱动元件22对电流通过能力的需求降低，但对关闭状态时的漏电流的要求较高，本实施例中通过采用氧化物半导体晶体管作为第二驱动元件22，不仅可实现对第一驱动元件21的电流大小进行控制，而且降低了第二驱动元件22在关闭状态时漏电流，从而进一步降低了阵列驱动电路的功耗。具体地，第二驱动元件22的漏极与第一驱动元件21的栅极211电连接，从而实现第二驱动元件22对第一驱动元件21的电流大小的控制。
在该实施例中，驱动电路层20通过采用具有较高电子迁移率的低温多晶硅晶体管和产生较小漏电流的氧化物半导体形成的阵列驱动电路，有效降低了该显示面板100的功耗，提高了图像显示的亮度和像素解析度。
进一步地，如图1所示，在驱动电路层20背离衬底10的一侧还设有平坦层30，平坦层30覆盖驱动电路层20，以在背离衬底10的一侧形成较为平坦的平面，不仅可用作绝缘层，还可用于设置其他元器件。具体地，平坦层30的材质可包括绝缘透明材质，以使得该平坦层30具有绝缘和透光特性；平坦层30的厚度具体可根据实际需要进行设置，对此不作具体限制。
在本实施例中，发光元件40设置于平坦层30背离衬底10的一侧，用于与驱动电路层20电连接，以接收阵列驱动电路的驱动信号，显示相应的图像信息。具体地，发光元件40包括半导体层43、第一电极41和第二电极42；其中，第一电极41和第二电极42位于半导体层43背离衬底10的一侧，从而使得该发光元件40的半导体层43位于靠近衬底10的一侧，第一电极41和第二电极42位于远离衬底10的一侧；也可以理解为，将发光元件40的半导体层43朝向衬底10设置，第一电极41和第二电极42朝向远离衬底10的方向设置，从而使得发光元件40的出射光的出射方向朝向衬底10，并经衬底10一侧向外出射；同时，发光元件40的该种设置方式，可先将发光元件40转移至驱动电路层20上后，再进行发光元件40和驱动电路层20的电连接，使得在转移发光元件40至驱动电路层20的过程中，无需通过键合方式将发光元件40的第一电极41和第二电极42对位贴合于驱动电路层20的相应焊盘上，避免了因转移精度较低导致对位不良造成的显示面板100的良率较低的问题。
其中，发光元件40的第一电极41可为阳极，第二电极42可为阴极；第一电极41与驱动电路层20的驱动元件23电连接，第二电极42与驱动电路层20的公共电极24电连接。具体地，第一电极41与第一驱动元件21的源极/漏极电极212电连接，第二电极42与驱动电路层20的公共电极24(VSS公共电极24)电连接，以使 驱动电路层20向发光元件40提供驱动信号，使发光元件40发光而显示相应的图像。具体地，发光元件40可为LED等电流驱动型发光元件40，例如Micro LED、Mini LED等；其中Mini LED的尺寸为50微米-200微米，Micro LED的尺寸小于50微米。在本实施例中，优选Micro LED作为发光元件40，以得到Micro LED显示面板100。
进一步地，为便于发光元件40的转移，平坦层30背离衬底10的一侧的表面形成有凹槽31，且发光元件40设置于凹槽31内，从而使得在将发光元件40巨量转移至驱动电路层20上时，发光元件40可准确转移至凹槽31内，有效提高了发光元件40的转移精度，从而提高该显示面板100的产品良率。
进一步地，在发光元件40背离衬底10的一侧，还设置有第一覆盖层50，第一覆盖层50用于覆盖发光元件40。具体地，第一覆盖层50的材质包括绝缘材质，从而避免发光元件40的第一电极41与第二电极42之间发生短路，导致图像显示异常。其中，第一覆盖层50具有第一通孔51和第二通孔52，且第一通孔51朝衬底10方向延伸至驱动电路层20，使驱动元件23部分暴露，第二通孔52朝衬底10方向延伸至驱动电路层20，使公共电极24部分暴露。具体地，第一通孔51朝衬底10方向延伸至第一驱动元件21处，使第一驱动元件21的源极/漏极电极212至少部分暴露，第二通孔52朝衬底10方向延伸至公共电极24(VSS公共电极24)处，以使公共电极24部分暴露，从而使发光元件40的第一电极41和第二电极42可分别通过第一通孔51和第二通孔52与第一驱动元件21和公共电极24电连接，从而实现驱动电路层20与发光元件40的电连接，以使驱动电路层20向发光元件40提供驱动信号，使发光元件40发光而显示相应的图像。
结合图2，图2是图1所示显示面板的单个子像素的第一实施例提供的俯视结构示意图。具体地，第一通孔51和第二通孔52间隔设置，且环绕发光元件40的侧壁设置，并在第一通孔51和第二通孔52内均填充有金属，以形成第一金属壁511和第二金属壁521，不仅提高了第一通孔51和第二通孔52中导电结构的导线性能，避免了通孔内导电不良的问题出现；而且，第一金属壁511和第二金属壁521环绕发光元件40的侧壁设置，还可兼有黑矩阵的功能作用，以避免像素之间混光或漏光至驱动电路层20导致驱动元件23异常的现象发生；同时，第一金属壁511和第二金属壁521由于其金属特性，使得发光元件40的部分出射光可经第一金属壁511和第二金属壁521反射后从衬底10一侧出射，从而效提高了发光元件40的发光效率，提升了该显示面板100的透光率，使得该显示面板100在显示时图像的亮度得到较大提升，且可进一步降低该显示面板100的功耗。具体的，在第一通孔51和第二通孔52内填充有金属，金属可为金、银、铜、铝、锌等导电性能较好的金属或其合金，在本实施例中，优选将铜填充于第一通孔51和第二通孔52内，以形成第一金属壁511和第二金属壁521。
进一步地，在本实施例中，第一覆盖层50还具有第三通孔53和第四通孔54。其中，第三通孔53使发光元件40的第一电极41至少部分暴露，第四通孔54使第二电极42至少部分暴露，从而使得第一电极41可通过第三通孔53与第一金属壁511电连接，第二电极42可通过第四通孔54与公共电极24电连接。
具体地，如图1所示，该显示面板100还包括导电层55，该导电层55设置于第一覆盖层50背离衬底10的一侧；导电层55包括第一连接线路551和第二连接线路552；第一连接线路551设置于第一覆盖层50背离衬底10的一侧且延伸至第三通孔53，第二连接线路552设置于第一覆盖层50背离衬底10的一侧且延伸至第四通孔54。其中，第一金属壁511通过第一连接线路551连接于第一电极41，第二金属壁521通过第二连接线路552连接于第二电极42，使得发光元件40的第一电极 41通过第一连接线路551和第一金属壁511电连接于第一驱动元件21，第二电极42通过第二连接线路552和第二金属壁521电连接于公共电极24。
在该显示面板100上，发光元件40与驱动元件23、公共电极24以及信号走线错位设置，且驱动电路层20的绝缘介质层与发光元件40对应的部分采用透光材料，使得发光元件40发射的光能够从衬底10一侧出射。可以理解为，在显示面板100的每个子像素中，驱动电路层20中的阵列驱动电路与发光元件40错开设置；或者也可以理解为，驱动电路层20中的阵列驱动电路在衬底10上的正投影与发光元件40在衬底10上的正投影不重叠；从而提高该显示面板100的像素开口率，避免阵列驱动电路遮挡发光元件40的出射光，降低该显示面板100的透光率，导致显示面板100的图像亮度较低的问题，从而实现该显示面板100以衬底10侧为发光面。
在本实施例中，如图2所示，发光元件40的第一电极41和第二电极42在平行于显示面板100的第一方向A上间隔设置；发光元件40具有沿着第一方向A间隔设置的第一侧面401和第二侧面402，以及连接第一侧面401和第二侧面402的第三侧面403和第四侧面404；第一金属壁511间隔设置于第一侧面401一侧且延伸至第三侧面403一侧和第四侧面404一侧；第二金属壁521间隔设置于第二侧面402一侧且延伸至第三侧面403一侧和第四侧面404一侧；第一金属壁511位于第三侧面403一侧的部分在第三侧面403的投影与第二金属壁521位于第三侧面403一侧的部分在第三侧面403的投影至少部分重叠；第一金属壁511位于第四侧面404一侧的部分在第四侧面404的投影与第二金属壁521位于第四侧面404一侧的部分在第四侧面404的投影至少部分重叠，从而保证第一金属壁511和第二金属壁521能够完全环绕发光元件40的侧壁，以避免发光元件40发射的光从第一金属壁511和第二金属壁521间隔的间隙中射出导致其漏光，造成像素间的混光，影响显示效果，以及漏光至驱动元件23造成驱动元件23的开关异常，从而影响驱动电路层20的驱动信号，使得图像显示异常。
请参见图3，图3是图1所示显示面板的单个子像素的其他实施例提供的俯视结构示意图；图3中的(a)是图1所示单个子像素的第二实施例提供的俯视结构示意图；图3中的(b)是图1所示单个子像素的第三实施例提供的的俯视结构示意图；图3中的(c)是图1所示单个子像素的第四实施例提供的的俯视结构示意图；图3中的(d)是图1所示单个子像素的第五实施例提供的的俯视结构示意图；图3中的(e)是图1所示单个子像素的第六实施例提供的的俯视结构示意图；图3中的(f)是图1所示单个子像素的第七实施例提供的的俯视结构示意图。在这些实施例中，在显示面板100的平行方向上，第一金属壁511和第二金属壁521的横截面可为弧形、不封闭的多边形、或其他不规则的图形，且为间隔设置，并环绕发光元件40的侧壁设置，以实现上述实施例中所涉及的第一金属壁511和第二金属壁521所能实现的技术效果。可以理解的是，第一金属壁511和第二金属壁521的具体形状和厚度还可以为其他形状和厚度，本申请实施例中仅是示例性地示出了一些，不代表其结构仅限于此。在具体实施例中，第一金属壁511和第二金属壁521的具体形状和厚度可根据实际需求进行设置即可，对此不作具体限制。
请参阅图4，图4是图1所示显示面板的单个子像素的导电层与第一金属壁、第二金属壁和发光元件的另一实施例的俯视结构示意图。进一步地，在本实施例中，在第一覆盖层50的平行方向上，第一金属壁511和第二金属壁521环绕发光元件40的侧壁设置，形成子像素开口；第一连接线路551和第二连接线路552间隔设置，且覆盖于子像素开口。具体地，第一连接线路551覆盖发光元件40的第一电极41，且从第一电极41的四周延伸至第一金属壁511，以使第一连接线路551形成扇形； 类似地，第二连接线路552覆盖发光元件40的第二电极42，且从第二电极42的四周延伸至第二金属壁521，从而使得第一连接线路551和第二连接线路552覆盖发光元件40，以使第一连接线路551和第二连接线路552在发光元件40背离衬底10的一侧形成类似遮光层或反光膜层的膜层，可用于将发光元件40射向该位置处的光线反射至衬底10，避免发光元件40的出射光从背离衬底10的一侧出射或漏光至他处，从而进一步提高发光元件40的发光效率。容易理解，第一连接线路551与第二连接线路552可采用反光材料或不透光材料，避免发光元件40的出射光从导电层55透过；且第一连接线路551和第二连接线路552仍需间隔设置，避免发光元件40的第一电极41与第二电极42之间短路。
请参阅图5a，图5a是图1所示显示面板的单个子像素的再一实施例的俯视结构示意图。在该实施例中，为进一步避免发光元件40的出射光从第一连接线路551与第二连接线路552之间的间隙中射出导致显示面板100漏光问题的发生，可在每个子像素中，第一连接线路551与第二连接线路552之间的间隙中设置绝缘反光层61，使得第一连接线路551、第二连接线路552和绝缘反光层61形成一连续膜层，完全覆盖于子像素开口，以用于将发光元件40发射至该处的光线反射至衬底10，从而避免发光元件40的出射光从背离衬底10的一侧射出导致显示面板100漏光的问题。可以理解，绝缘反光层61为绝缘且反光的材料，以避免第一电极41与第二电极42之间短路。
在其他实施例中，请参阅图5b，图5b是图1所示显示面板的单个子像素的又一实施例的俯视结构示意图；绝缘反光层61也可设置在发光元件40背离衬底10的一侧，可与第二覆盖层60同层设置，或者设置于第二覆盖层60靠近衬底的一侧，且完全覆盖子像素开口，以将子像素开口封住，从而避免发光元件40的出射光从背离衬底10的一侧出射或漏光至他处，且还可将发光元件40的部分出射光反射至衬底10，进一步提高发光元件40的发光效率。相较于图5a中的实施例，本实施例中的绝缘反光层61的设置方式更为简单，并且第一连接线路551和第二连接线路552可以不必增大面积以用于反射光线或阻挡光线射出，从而使得第一连接线路551与第二连接线路552之间的间隔较大，从而有效避免第一电极41与第二电极42短路。
在一些实施例中，请结合图1，为避免发光元件40的出射光从背离衬底10的一侧射出导致显示面板100漏光的问题，第一金属壁511和第二金属壁521与发光元件40之间的部分第一覆盖层50可设置成可反光或不透光的膜层，从而阻止发光元件40的出射光向背离衬底10的方向发射，避免发光元件40的出射光从背离衬底10的一侧射出导致显示面板100漏光的问题。
请再次参阅图1，在本实施例中，沿垂直于衬底10的出光方向上，第一金属壁511和/或第二金属壁521靠近发光元件40的表面与发光元件40的中轴线之间的径向距离逐渐增大，以使发光元件40的部分出射光经第一金属壁511和/或第二金属壁521反射至衬底10，从衬底10出射。可以理解，沿该显示面板100的出光方向，第一金属壁511和/或第二金属壁521靠近发光元件40的表面与发光元件40的中轴线之间的径向距离逐渐增大，即第一金属壁511和/或第二金属壁521靠近发光元件40的表面为斜面，且第一金属壁511和/或第二金属壁521靠近发光元件40的表面与发光元件40中轴线之间的开口沿显示面板100的出光方向逐渐增大，从而增大第一金属壁511和第二金属壁521用于反射发光元件40的出射光的反射面的面积，以使更多出射光能够经第一金属壁511和/或第二金属壁521反射后，从衬底10出射，进而提高发光元件40的发光效率，提高图像的亮度。容易理解，第一通孔51和第二通孔52的孔型设置与第一金属壁511和第二金属壁521的形状和结构相匹配，从 而在第一通孔51和第二通孔52中填充金属形成上述第一金属壁511和第二金属壁521。
进一步地，在本实施例中，显示面板100还包括第二覆盖层60和反射层70。第二覆盖层60设置于导电层55背离衬底10的一侧，且覆盖导电层55，从而使导电层55与外部隔离，避免因外界因素导致导电层55结构被破坏或连接线路短路等问题。反射层70设置于第二覆盖层60背离衬底10的一侧且覆盖第二覆盖层60，从而避免发光元件40射出的光从该侧出射造成漏光。可以理解的是，发光元件40朝向背离衬底10的方向射出的光基本上都被绝缘反光层61(见图5b)反射至衬底10，或者被导电层55和绝缘反光层61共同形成的连续膜层(见图5a)反射至衬底10，然后经衬底10出射，从而有效提高发光元件40的发光效率，可进一步降低显示面板100的功耗。因此发光元件40射向反射层70的光线极少，并且反射层70由于与发光元件40之间有一定的距离，且位于发光元件40背离衬底10一侧的像素开口被绝缘反光层61覆盖或被导电层55和绝缘反光层61共同形成的连续膜层覆盖，即使有光线发射至反射层70，反射层70也较难将发射至该处的光线再反射至反射层70；因而，在本实施例中，反射层70的主要作用是防止光线从背离衬底10的一侧射出造成的漏光。
请参见图6和图7a-7k，图6是本申请一实施方式提供的显示面板的制备方法的流程示意图，图7a-7k是图6所示显示面板的制备方法的工艺流程示意图。在该实施方式中，提供一种显示面板100的制备方法，该制备方法包括以下步骤：
S1：提供衬底10；
S2：在衬底10一侧制作驱动电路层20；驱动电路层20包括驱动元件23、公共电极24以及信号走线；
S3：在驱动电路层20背离衬底10的一侧制作平坦层30，且使绝缘层覆盖驱动电路层20；
S4：将发光元件40转移至平坦层30；其中，发光元件40包括半导体层43、第一电极41和第二电极42，第一电极41和第二电极42位于发光元件40背离衬底10的一侧的表面；
S5：在发光元件40背离衬底10的一侧制作第一覆盖层50，且使第一覆盖层50覆盖发光元件40；
S6：在第一覆盖层50上制作第一通孔51和第二通孔52，以分别使驱动元件23和公共电极24部分暴露；其中，第一通孔51和第二通孔52间隔设置，且环绕发光元件40的侧壁设置；
S7：向第一通孔51和第二通孔52中填充金属，以形成第一金属壁511和第二金属壁521；其中，第一金属壁511和第二金属壁521用于反射发光元件40的部分出射光至衬底10；
S8：在第一覆盖层50上制作导电层55；其中，导电层55包括第一连接线路551和第二连接线路552，第一连接线路551连接第一电极41与第一金属壁511，第二连接线路552连接第二电极42与第二金属壁521。
在该实施方式中，如图7a所示，步骤S1提供的衬底10可为上述实施例中所涉及的衬底10，以向驱动电路层20提供支撑和保护；具体地，在该实施方式中，衬底10可为透光材质，以使发光元件40射出的光可穿过衬底出射。
如图7b和图7c所示，具体地，驱动元件23、公共电极24以及信号走线均可通过光罩刻蚀方式进行图案化而形成，从而形成完整的阵列驱动电路，从而实现驱动发光元件发光。具体地，通过本实施方式步骤S2制作的驱动电路层20，可为上 述实施例中所涉及的驱动电路层20，且可实现相同的技术效果。
进一步地，如图7d所示，步骤S3制作的平坦层30背离衬底10的表面形成有凹槽31，用于容纳发光元件40；平坦层30覆盖驱动电路层20，以在背离衬底10的一侧形成较为平坦的平面，不仅可用作绝缘层，还可用于设置其他元器件。具体地，平坦层30的材质可包括绝缘透明材质，以使得该平坦层30具有绝缘和透光特性；平坦层30的厚度具体可根据实际需要进行设置，对此不作具体限制。
进一步地，如图7e所示，步骤S4中，将发光元件40通过巨量转移，转移至平坦层30的凹槽31中，通过制作凹槽31，发光元件40可准确转移至凹槽31内，有效提高了发光元件40的转移精度，从而提高该显示面板100的产品良率。具体地，发光元件40可为上述实施例中所涉及的发光元件40，且可实现相同或相似的技术效果，此处不再赘述。
如图7f所示，步骤S5中，通过制作第一覆盖层50，以用于覆盖发光元件40。具体地，第一覆盖层50的材质包括绝缘材质，从而避免发光元件40的第一电极41与第二电极42之间发生短路，导致图像显示异常。
进一步地，如图7g所示，步骤S6中，在第一覆盖层50上制作第一通孔51和第二通孔52，使第一通孔51朝衬底10方向延伸至驱动电路层20，使驱动元件23部分暴露，第二通孔52朝衬底10方向延伸至驱动电路层20，使公共电极24部分暴露。具体地，第一通孔51朝衬底10方向延伸至第一驱动元件21处，使第一驱动元件21的源极/漏极电极212至少部分暴露，第二通孔52朝衬底10方向延伸至公共电极24(VSS公共电极24)处，以使公共电极24部分暴露，从而使发光元件40的第一电极41和第二电极42可分别通过第一通孔51和第二通孔52与第一驱动元件21和公共电极24电连接，从而实现驱动电路层20与发光元件40的电连接，以使驱动电路层20向发光元件40提供驱动信号，使发光元件40发光而显示相应的图像。进一步地，为实现发光元件40的第一电极41和第二电极42与驱动电路层20的相应元件或电极电连接，在第一覆盖层50上还需制作第三通孔53和第四通孔54，以使第一电极41和第二电极42至少部分暴露。
如图7h所示，步骤S7中，在第一通孔51和第二通孔52中填充金属，金属可为金、银、铜、铝、锌等导电性能较好的金属或其合金，在本实施例中，优选将铜填充于第一通孔51和第二通孔52内，以形成第一金属壁511和第二金属壁521。
如图7i所示，在该实施方式中，通过制作导电层55，从而实现第一电极41和第二电极42分别通过第一连接线路551和第二连接线路552与相应元件或电极电连接，以使发光元件40可被驱动电路层20驱动而发光。
在本实施例中，通过在发光元件40背离衬底10的一侧制作第一覆盖层50，并在第一覆盖层50上制作第一通孔51和第二通孔52，且使第一通孔51延伸至驱动电路层20使驱动元件23部分暴露，第二通孔52延伸至驱动电路层20使公共电极24部分暴露，使得发光元件40的第一电极41和第二电极42可分别通过第一通孔51和第二通孔52与驱动元件23和公共电极24电连接，从而使驱动电路层20驱动发光元件40发光；同时，通过在第一通孔51和第二通孔52内填充金属，以分别在第一通孔51和第二通孔52中形成第一金属壁511和第二金属壁521，从而提高通孔中导电结构的导电性能，避免导电不良的问题出现；此外，通过使第一通孔51和第二通孔52间隔设置且环绕发光元件40的侧壁设置，使得形成于第一通孔51和第二通孔52中的第一金属壁511和第二金属壁521间隔设置且环绕发光元件40的侧壁，从而使得第一金属壁511和第二金属壁521还可兼有黑矩阵的功能和作用，而且第一金属壁511和第二金属壁521由于其金属特性，使得发光元件40的部分发 射光发射至第一金属壁511和/或第二金属壁521时可被反射从衬底10一侧出射，从而有效提高了发光元件40的发光效率，提升了该显示面板100的透光率，使得在显示时图像的亮度得到较大提升，且可进一步降低该显示面板100的功耗。
请参见图8，图8是图6所示制备方法的步骤S2的一实施方式的流程示意图。在本实施例中，在衬底10一侧制作驱动电路层20的步骤具体可包括：
S21：在衬底10的一侧制作第一驱动元件21；第一驱动元件21包括低温多晶硅晶体管；
S22：在第一驱动元件21一侧制作绝缘介质层，以覆盖第一驱动元件21；
S23：在绝缘介质层背离衬底10的一侧制作第二驱动元件22；第二驱动元件22包括氧化物半导体晶体管。
在该实施例中，通过制作低温多晶硅晶体管作为第一驱动元件21，由于其低温多晶硅的电子迁移速率相比传统的非晶硅半导体更高，其电流通过能力更高，使得该显示面板100的响应速度更快，能够更好地满足显示面板100大尺寸的需求以及LED显示面板100较大的电流通过能力；同时，通过使用低温多晶硅晶体管作为第一驱动元件21，使得阵列驱动电路占据的面积较小，从而使得显示面板100的透光区面积更大，提高了图像显示的亮度和像素解析度，同时还可有效降低驱动电路层20的功耗。通过制作氧化物半导体晶体管作为第二驱动元件22，并将第二驱动元件22与第一驱动元件21电连接，以用于对第一驱动元件21的电流大小进行控制，因此，第二驱动元件22对电流通过能力的需求降低，但对关闭状态时的漏电流的要求较高，本实施例中通过采用氧化物半导体晶体管作为第二驱动元件22，不仅可实现对第一驱动元件21的电流大小进行控制，而且降低了第二驱动元件22在关闭状态时漏电流，从而进一步降低了阵列驱动电路的功耗。具体地，第二驱动元件22的漏极与第一驱动元件21的栅极211电连接，从而实现第二驱动元件22对第一驱动元件21的电流大小的控制。
请继续参阅图6，进一步地，在本实施方式中，显示面板的制备方法还可包括：
S9：在第一覆盖层50背离衬底10的一侧制作第二覆盖层60，并使第二覆盖层60覆盖导电层55；
S10：在第二覆盖层60背离衬底10的一侧制作反射层70，并使反射层70覆盖第二覆盖层60。
在本实施方式中，如图7j和图7k所示，通过在第一覆盖层50背离衬底10的一侧制作第二覆盖层60，并使第二覆盖层60覆盖导电层55，从而使导电层55与外部隔离，避免因外界因素导致导电层55结构被破坏或连接线路短路等问题。通过在第二覆盖层60背离衬底10的一侧制作反射层70，并使反射层70覆盖第二覆盖层60，从而避免发光元件40射出的光从该侧出射造成漏光，且可将光线反射至衬底10，以提高发光元件40的发光效率。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，包括：
    衬底；
    驱动电路层，设置于所述衬底的一侧，所述驱动电路层包括驱动元件、公共电极以及信号走线；
    平坦层，设置于所述驱动电路层背离所述衬底的一侧，且覆盖所述驱动电路层；
    发光元件，设置于所述平坦层背离所述衬底的一侧；所述发光元件包括半导体层、第一电极和第二电极；所述第一电极与所述驱动元件电连接，且所述第二电极与所述公共电极电连接；
    第一覆盖层，设置于所述发光元件背离所述衬底的一侧，且覆盖所述发光元件；
    其中，所述第一电极和所述第二电极位于所述半导体层背离所述衬底的一侧；所述第一覆盖层具有第一通孔和第二通孔，所述第一通孔延伸至所述驱动电路层，使所述驱动元件部分暴露；所述第二通孔延伸至所述驱动电路层，使所述公共电极部分暴露；
    其中，所述第一通孔和所述第二通孔间隔设置且环绕所述发光元件的侧壁设置，在所述第一通孔和所述第二通孔内均填充有金属，以形成第一金属壁和第二金属壁，使得所述发光元件的部分出射光经所述第一金属壁和所述第二金属壁反射后从所述衬底一侧出射；且所述第一金属壁电连接所述第一电极与所驱动元件，所述第二金属壁电连接所述第二电极与所述公共电极。
  2. 根据权利要求1所述的显示面板，其中，所述发光元件与所述驱动元件、所述公共电极以及所述信号走线错位设置，且所述驱动电路层的绝缘介质层与所述发光元件对应的部分采用透光材料，使得所述发光元件发射的光从所述衬底一侧出射。
  3. 根据权利要求2所述的显示面板，其中，所述衬底的材质包括透明材质，所述平坦层的材质包括绝缘透明材质。
  4. 根据权利要求3所述的显示面板，其中，所述第一电极和所述第二电极在平行于所述显示面板的第一方向上间隔设置，所述发光元件具有沿着所述第一方向间隔设置的第一侧面和第二侧面，以及连接所述第一侧面和所述第二侧面的第三侧面和第四侧面；所述第一金属壁间隔设置于所述第一侧面一侧且延伸至所述第三侧面一侧和所述第四侧面一侧；所述第二金属壁间隔设置于所述第二侧面一侧且延伸至所述第三侧面一侧和所述第四侧面一侧；所述第一金属壁位于所述第三侧面一侧的部分在所述第三侧面的投影与所述第二金属壁位于所述第三侧面一侧的部分在所述第三侧面的投影至少部分重叠；所述第一金属壁位于所述第四侧面一侧的部分在所述第四侧面的投影与所述第二金属壁位于所述第四侧面一侧的部分在所述第四侧面的投影至少部分重叠。
  5. 根据权利要求1所述的显示面板，其中，沿垂直于所述衬底的出光方向上，所述第一金属壁和/或所述第二金属壁靠近所述发光元件的表面与所述发光元件的中轴线之间的径向距离逐渐增大，以使所述发光元件的部分出射光经所述第一金属壁和/或所述第二金属壁反射至所述衬底。
  6. 根据权利要求1所述的显示面板，其中，所述平坦层背离所述衬底的一 侧的表面形成有凹槽，所述发光元件设置于所述凹槽中。
  7. 根据权利要求1所述的显示面板，其中，所述第一覆盖层还具有第三通孔和第四通孔，所述第三通孔使所述第一电极至少部分暴露，所述第四通孔使所述第二电极至少部分暴露；
    所述显示面板还包括导电层，所述导电层包括第一连接线路和第二连接线路；所述第一连接线路设置于所述第一覆盖层背离所述衬底的一侧且延伸至所述第三通孔，所述第二连接线路设置于所述第一覆盖层背离所述衬底的一侧且延伸至所述第四通孔；所述第一金属壁通过所述第一连接线路连接于所述第一电极，所述第二金属壁通过所述第二连接线路连接于所述第二电极。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板还包括：
    第二覆盖层，设置于所述导电层背离所述衬底的一侧且覆盖所述导电层；
    反射层，设置于所述第二覆盖层背离所述衬底的一侧且覆盖所述第二覆盖层。
  9. 根据权利要求7所述的显示面板，其中，在所述第一覆盖层的平行方向上，所述第一金属壁和所述第二金属壁环绕所述发光元件的侧壁设置，形成子像素开口；所述第一连接线路和所述第二连接线路间隔设置，且覆盖于所述子像素开口。
  10. 根据权利要求9所述的显示面板，其中，所述第一连接线路覆盖所述发光元件的所述第一电极，且从所述第一电极的四周延伸至所述第一金属壁，以使所述第一连接线路形成扇形；所述第二连接线路覆盖所述发光元件的所述第二电极，且从所述第二电极的四周延伸至所述第二金属壁。
  11. 根据权利要求9所述的显示面板，其中，所述显示面板还包括绝缘反光层，所述绝缘反光层设置于所述第一连接线路与所述第二连接线路之间的间隙中，与所述第一连接线路和所述第二连接线路形成连续膜层，且完全覆盖于所述子像素开口。
  12. 根据权利要求9所述的显示面板，其中，所述显示面板还包括绝缘反光层；所述绝缘反光层设置于所述发光元件背离所述衬底的一侧，与所述第二覆盖层同层设置，且完全覆盖于所述子像素开口；或，
    所述绝缘反光层设置于所述第二覆盖层靠近所述衬底的一侧，且完全覆盖于所述子像素开口。
  13. 根据权利要求1所述的显示面板，其中，所述驱动电路层包括第一驱动元件和第二驱动元件；所述第一驱动元件位于所述第二驱动元件靠近所述衬底的一侧，且所述第二驱动元件电连接于所述第一驱动元件，所述第一电极与所述第一驱动元件电连接。
  14. 根据权利要求13所述的显示面板，其中，所述第一通孔朝所述衬底的方向延伸至所述第一驱动元件处，且使所述第一驱动元件的源极/漏极电极至少部分暴露；所述第二通孔朝所述衬底的方向延伸至所述公共电极处，且使所述公共电极部分暴露。
  15. 根据权利要求13所述的显示面板，其中，所述第一驱动元件采用低温多晶硅晶体管，所述第二驱动元件采用氧化物半导体晶体管，所述第二驱动元件用于控制所述第一驱动元件的电流。
  16. 根据权利要求1所述的显示面板，其中，所述发光元件为电流驱动型发光元件。
  17. 根据权利要求1所述的显示面板，其中，所述第一金属壁和所述第二金 属壁与所述发光元件之间的部分所述第一覆盖层为反光或不透光的膜层。
  18. 一种显示面板的制备方法，其中，包括：
    提供衬底；
    在所述衬底的一侧制作驱动电路层；所述驱动电路层包括驱动元件、公共电极以及信号走线；
    在所述驱动电路层背离所述衬底的一侧制作平坦层，且使绝缘层覆盖所述驱动电路层；
    将发光元件转移至所述平坦层；其中，所述发光元件包括半导体层、第一电极和第二电极，所述第一电极和所述第二电极位于所述发光元件背离所述衬底的一侧的表面；
    在所述发光元件背离所述衬底的一侧制作第一覆盖层，且使第一覆盖层覆盖所述发光元件；
    在第一覆盖层上制作第一通孔和第二通孔，以分别使所述驱动元件和所述公共电极部分暴露；其中，所述第一通孔和第二通孔间隔设置，且环绕所述发光元件的侧壁设置；
    向所述第一通孔和所述第二通孔中填充金属，以形成第一金属壁和第二金属壁；其中，所述第一金属壁和所述第一金属壁用于反射所述发光元件的部分出射光至所述衬底；
    在所述第一覆盖层上制作导电层；其中，所述导电层包括第一连接线路和第二连接线路，所述第一连接线路连接所述第一电极与所述第一金属壁，所述第二连接线路连接所述第二电极与所述第二金属壁。
  19. 根据权利要求18所述的显示面板的制备方法，其中，所述在所述衬底的一侧制作驱动电路层的步骤包括：
    在所述衬底的一侧制作第一驱动元件；所述第一驱动元件包括低温多晶硅晶体管；
    在所述第一驱动元件的一侧制作绝缘介质层，以覆盖所述第一驱动元件；
    在所述绝缘介质层背离所述衬底的一侧制作第二驱动元件；所述第二驱动元件包括氧化物半导体晶体管。
  20. 根据权利要求18所述的显示面板的制备方法，其中，所述制备方法还包括：
    在所述第一覆盖层背离所述衬底的一侧制作第二覆盖层，并使所述第二覆盖层覆盖所述导电层；
    在所述第二覆盖层背离所述衬底的一侧制作反射层，并使所述反射层覆盖所述第二覆盖层。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060060993A (ko) * 2004-12-01 2006-06-07 삼성에스디아이 주식회사 곡면형 플라즈마 디스플레이 패널, 그 제조 방법 및 이를구비한 곡면형 플라즈마 디스플레이 장치
CN111048568A (zh) * 2019-12-25 2020-04-21 上海天马微电子有限公司 显示面板及显示装置
CN114512436A (zh) * 2022-01-25 2022-05-17 合肥维信诺科技有限公司 显示面板的制造方法、显示面板及显示面板生产设备
CN114975740A (zh) * 2022-08-02 2022-08-30 惠科股份有限公司 显示面板及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265522B (zh) * 2019-06-28 2021-01-08 上海天马微电子有限公司 显示面板、显示装置和显示面板的制造方法
KR20210066205A (ko) * 2019-11-28 2021-06-07 엘지디스플레이 주식회사 표시 장치 및 표시 장치 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060060993A (ko) * 2004-12-01 2006-06-07 삼성에스디아이 주식회사 곡면형 플라즈마 디스플레이 패널, 그 제조 방법 및 이를구비한 곡면형 플라즈마 디스플레이 장치
CN111048568A (zh) * 2019-12-25 2020-04-21 上海天马微电子有限公司 显示面板及显示装置
CN114512436A (zh) * 2022-01-25 2022-05-17 合肥维信诺科技有限公司 显示面板的制造方法、显示面板及显示面板生产设备
CN114975740A (zh) * 2022-08-02 2022-08-30 惠科股份有限公司 显示面板及其制备方法

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