WO2022198575A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2022198575A1
WO2022198575A1 PCT/CN2021/083034 CN2021083034W WO2022198575A1 WO 2022198575 A1 WO2022198575 A1 WO 2022198575A1 CN 2021083034 W CN2021083034 W CN 2021083034W WO 2022198575 A1 WO2022198575 A1 WO 2022198575A1
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WIPO (PCT)
Prior art keywords
sub
pixel
electrode
line
driving circuit
Prior art date
Application number
PCT/CN2021/083034
Other languages
English (en)
French (fr)
Inventor
张星
高展
林奕呈
徐攀
韩影
张大成
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/642,786 priority Critical patent/US20240005869A1/en
Priority to CN202180000588.9A priority patent/CN115552614A/zh
Priority to GB2215692.1A priority patent/GB2610080A/en
Priority to PCT/CN2021/083034 priority patent/WO2022198575A1/zh
Publication of WO2022198575A1 publication Critical patent/WO2022198575A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a plurality of sensing signal lines.
  • the base substrate includes a display area, wherein the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along the first direction, the pixels
  • the region includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the base substrate, and the sub-pixel driving circuit
  • the circuit is configured to drive the light-emitting element to emit light; a plurality of sensing signal lines are arranged on the base substrate and extend along the second direction, wherein adjacent two of the plurality of sensing signal lines are arranged between two adjacent ones There are two rows of the repeating units, the two rows of repeating units extend along the second direction, each of the pluralit
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of power supply lines, wherein the plurality of power supply lines are disposed on the base substrate and extend along the second direction. Upward, the plurality of power supply lines and the plurality of sensing signal lines are alternately arranged, and between each of the plurality of sensing signal lines and the adjacent power supply lines, a line extending along the second direction is provided.
  • One row of the repeating units, two adjacent rows of the repeating units extending along the second direction are disposed between two adjacent ones of the plurality of power supply lines, each of the multiple power supply lines and the same
  • the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of the repeating units that are adjacent and respectively extend along the second direction are connected and configured to provide a first power supply voltage.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a peripheral region, a gate driving circuit, and a plurality of gate lines extending along the first direction, the peripheral region at least partially surrounds the display region, and the gate a pole driving circuit is located in the peripheral region, the plurality of gate lines are connected to the gate driving circuit and are respectively connected to the sub-pixel driving circuits of the pixel regions of each row of the repeating units extending along the first direction,
  • the gate driving circuit is configured to output one by one gate scanning signals for driving a plurality of sub-pixels in the pixel regions of each row of the repeating units extending along the first direction, and the repeating units are arranged to be respectively N rows extending along the first direction
  • the gate driving circuit includes N cascaded shift register units, and the nth stage shift register unit is connected to the sub-pixel driving circuit of the pixel area of the nth row of repeating units , where 1 ⁇ n ⁇ N, where N is an integer greater than or equal to 2.
  • a plurality of sub-pixel driving circuits in each of the pixel regions are arranged along the first direction, and each of the sub-pixel driving circuits includes a data writing circuit, a driving circuit, and a driving circuit.
  • a circuit, a charge storage circuit and a sensing circuit the drive circuit is connected to a first node, a second node and a third node, the third node is also connected to a first power supply voltage terminal, and the first power supply voltage terminal is connected to the power supply line is connected, and the driving circuit is configured to receive the first power supply voltage through the third node, and control the driving flow through the light-emitting element under the control of the level of the first node a current;
  • the data writing circuit is connected to the first node, and is configured to receive the gate scan signal as a scan drive signal, and write a data signal to the first node in response to the scan drive signal;
  • the The charge storage circuit is connected to the first node and the second node, and is configured to store the written data signal and the reference voltage signal;
  • the sensing circuit is connected to the second node and configured to receiving the gate scan signal as a sensing drive signal, the sensing circuit is further connected to the sensing signal line and configured to receive the reference voltage signal, and
  • the plurality of gate lines include a first gate line and a second gate line, and the first gate line is connected to the Mth row extending along the first direction.
  • the output end of the bit register unit is connected to output the gate scan signal output by the output end of the Mth shift register unit to the data writing circuit of the plurality of sub-pixel drive circuits in the pixel area of the Mth row of repeating units as the data writing circuit.
  • the scan drive signal and the sensing circuits output to a plurality of sub-pixel drive circuits in the pixel area of the M-1th row of repeating units are used as sensing drive signals.
  • the second gate line is connected to the M-th row of repeating units.
  • the output end of the register unit is connected to output the gate scan signal output by the output end of the M+1th shift register unit to the multiple sub-pixel driving circuits of the pixel area of the M+1th row of repeating units.
  • a data writing circuit is used as a scan driving signal, and a sensing circuit output to a plurality of sub-pixel driving circuits in the pixel region of the repeating unit of the M-th row is used as the sensing driving signal, wherein 1 ⁇ M ⁇ N, M is an integer.
  • the data writing circuit includes a data writing transistor
  • the driving circuit includes a driving transistor
  • the sensing circuit includes a sensing transistor
  • the data writing The active layer of the transistor, the active layer of the driving transistor, and the active layer of the sensing transistor extend along the second direction, and the base substrate is a flexible substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a semiconductor layer, a first conductive layer, a second conductive layer, a second insulating layer and a fourth insulating layer on the base substrate, the second conductive layer
  • the layer is located on the side of the semiconductor layer away from the base substrate, the fourth insulating layer is located between the second conductive layer and the semiconductor layer, and the first conductive layer is located on the second conductive layer the side of the layer away from the base substrate, the second insulating layer is located between the second conductive layer and the first conductive layer
  • the semiconductor layer includes the active layer of the data writing transistor,
  • the active layer of the driving transistor and the active layer of the sensing transistor, each of the plurality of power supply lines includes a first sub-line located in the second conductive layer and a sub-line located in the first conductive layer.
  • a second sub-line the first sub-line includes a plurality of first line segments extending along the second direction, the plurality of first line segments are respectively located in different repeating units, and the second sub-line passes through Through the display area, the second sub-line is stacked on a side of the first sub-line away from the base substrate, and is connected to the second sub-line through at least one first via penetrating the second insulating layer. The first sub-wire is connected.
  • each of the plurality of sensing signal lines includes a third sub-line located in the second conductive layer and a fourth sub-line located in the first conductive layer a sub-line
  • the third sub-line includes a plurality of second wiring segments extending along the second direction
  • the plurality of second wiring segments are distributed in different repeating units
  • the fourth sub-line passes through all the second wiring segments.
  • the display area, the fourth sub-line is stacked on a side of the third sub-line away from the base substrate, and is connected to the third sub-line through at least one second via hole penetrating the second insulating layer Subwire connection.
  • the display area includes a first repeating unit and a second repeating unit that are adjacently arranged along a first direction, and the pixel area of the first repeating unit is the same as the pixel area of the first repeating unit.
  • a sensing signal line is arranged between the transparent regions of the second repeating unit, the sensing signal line is connected to a plurality of sub-pixel driving circuits in the pixel regions of the first repeating unit and the second repeating unit, and the second repeating unit
  • a power supply line is provided on the side of the pixel area of the repeating unit away from the transparent area of the second repeating unit, and the power supply line is connected to a plurality of sub-pixel driving circuits in the pixel area of the second repeating unit.
  • the first repeating unit A side of the transparent area of the unit away from the pixel area of the first repeating unit is provided with another power supply line, and the other power supply line is connected to a plurality of sub-pixel driving circuits in the pixel area of the first repeating unit.
  • the plurality of sub-pixel driving circuits in the pixel area of the first repeating unit and the plurality of sub-pixel driving circuits in the pixel area of the second repeating unit respectively include a first sub-pixel driving circuit and a second sub-pixel arranged in the first direction.
  • a drive circuit and a third sub-pixel drive circuit, the first conductive layer includes a first transfer electrode extending along the first direction, a first electrode and a second electrode of the sensing transistor, the first transfer electrode The first end of the connecting electrode is connected with the first electrode of the sensing transistor of the third sub-pixel driving circuit of the first repeating unit, and the second end of the first transfer electrode is connected with the first electrode of the second repeating unit.
  • a first electrode of a sensing transistor of a sub-pixel driving circuit is connected, wherein the first transfer electrode is cross-connected with the second sub-line of the sensing signal line.
  • the second conductive layer includes a first connection trace extending along the first direction, and the first connection trace passes through at least one of the third via holes.
  • the part is connected to the first electrodes of the sensing transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit of the first repeating unit or the second repeating unit.
  • At least part of the orthographic projection of the first electrodes of the sensing transistors of the sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the board surface of the base substrate is the same as the first The orthographic projections of the connection traces on the board surface of the base substrate overlap.
  • the first electrode of the sensing transistor includes a first sub-section and a second sub-section connected along the second direction, and the third via hole A portion of the third via hole is configured to penetrate the second insulating layer and the fourth insulating layer to expose the active layer of the sensing transistor, and another portion of the third via hole is configured to penetrate the second insulating layer to expose the active layer of the sensing transistor.
  • the first connection trace, the first sub-section is in contact with the active layer of the sensing transistor, and the second sub-section is in contact with the first connection trace.
  • the charge storage circuit includes a storage capacitor
  • the semiconductor layer further includes a first electrode plate of the storage capacitor
  • the first conductive layer further includes a first electrode plate of the storage capacitor.
  • Diode plate, the second electrode of the sensing transistor is connected to one end of the second electrode plate close to the sensing transistor, and the second electrode of the sensing transistor is integrally arranged with the second electrode plate .
  • the data writing transistor and the driving transistor are located on a side of the storage capacitor away from the sensing transistor
  • the driving transistor is located between the data writing transistor and the storage capacitor
  • the first conductive layer further includes a first pole and a second pole of the data writing transistor, and a first pole of the driving transistor and the second pole, the second switching electrode and the third switching electrode, the second switching electrode and the third switching electrode respectively include the third node
  • the second pole of the driving transistor is located at the The side of the driving transistor away from the storage capacitor, one end of the second transfer electrode is connected to the second electrode of the driving transistor of the third sub-pixel driving circuit of the second repeating unit, and the second The other end of the transfer electrode is connected to the power line of the third sub-pixel driving circuit close to the second repeating unit, and one end of the third transferring electrode is connected to the driving transistor of the first sub-pixel driving circuit of the first repeating unit
  • the second pole of the first repeating unit is connected
  • the second conductive layer includes a second connection trace extending along the first direction, and the second connection trace passes through at least one of the fourth via holes. part, connected to the second poles of the driving transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit of the first repeating unit or the second repeating unit, the first sub-pixel driving circuit At least part of the orthographic projection of the second poles of the driving transistors of the sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the board surface of the base substrate is the same as that of the first sub-pixel driving circuit.
  • the orthographic projections of the two connection traces on the board surface of the base substrate overlap.
  • the first electrode of the driving transistor is connected to the end of the second electrode plate of the storage capacitor that is far away from the sensing transistor, and the driving transistor is The first electrode and the second electrode plate are integrally arranged, and the first electrode plate of the storage capacitor is connected to the active layer of the driving transistor and integrally arranged.
  • the first electrode plate and the second electrode plate of the storage capacitor include strips extending along the second direction
  • the display substrate further includes a filter layer
  • the filter layer is located on the side of the light-emitting element away from the base substrate
  • the filter layer includes a first sub-pixel filter area, a second sub-pixel filter area and a third sub-pixel filter area area, in each repeating unit, the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area are sequentially arranged along the second direction, so
  • the second sub-pixel filter area is located between the first sub-pixel filter area and the third sub-pixel filter area, and the first sub-pixel filter area and a plurality of sub-pixels in the pixel area are driven At least part of the sensing transistor of the circuit and the orthographic projection of the part of the storage capacitor close to the sensing transistor on the board surface of the base substrate overlap, the third sub-pixel filter area and the pixel area At least part of the data
  • the display substrate provided by at least one embodiment of the present disclosure further includes a third insulating layer and a pixel defining layer, the third insulating layer is located on a side of the first conductive layer away from the base substrate, and the light-emitting The element is located on a side of the third insulating layer away from the base substrate, and the light-emitting element of each of the plurality of sub-pixels includes a first electrode, a second electrode, and a light-emitting element located on the first electrode and the second electrode.
  • the pixel-defining layer is configured to define a light-emitting region of the light-emitting element
  • the plurality of light-emitting elements of each repeating unit includes a first light-emitting element, a second light-emitting element and a third light-emitting element
  • the first light-emitting element, the second light-emitting element and the third light-emitting element are respectively associated with the first sub-pixel filter region, the second sub-pixel filter region and the third sub-pixel filter region
  • the display substrate further includes a fifth via hole, a sixth via hole and a seventh via hole penetrating at least the third insulating layer, the fifth via hole, the sixth via hole and the The seventh via hole is configured to expose the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit, and the first electrode of the first light-emitting element passes through the fifth via
  • the hole is connected to the first sub-pixel driving circuit, the first electrode of the second light-
  • the orthographic projection of the fifth via hole on the board surface of the base substrate and the light-emitting region of the first light-emitting element on the base substrate The orthographic projection on the board surface does not overlap, and the orthographic projection of the sixth via hole on the board surface of the base substrate and the orthographic projection of the light-emitting area of the second light-emitting element on the board surface of the base substrate.
  • the orthographic projections do not overlap, and the orthographic projection of the seventh via hole on the board surface of the base substrate does not overlap with the orthographic projection of the light-emitting region of the third light-emitting element on the board surface of the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a black matrix, and in the pixel area of each repeating unit, the black matrix includes a plurality of light-shielding lines extending along the first direction, and a plurality of the At least part of the orthographic projection of the light-shielding line on the board surface of the base substrate, and the first sub-pixel filter region, the second sub-pixel filter region and the third sub-pixel filter region
  • the intervals in the second direction overlap, and the orthographic projections of the fifth via hole and the sixth via hole on the board surface of the base substrate are close to the first sub-pixel filter area and all the The orthographic projection of the light-shielding lines between the second sub-pixel filter regions on the board surface of the base substrate, and is located between the first sub-pixel filter region and the second sub-pixel filter region
  • the light-shielding lines are on both sides of the orthographic projection on the board surface of the base substrate, and the orthographic projection of the seventh via hole on the board surface of the base
  • the display substrate provided by at least one embodiment of the present disclosure further includes a black matrix, and in the pixel area of each repeating unit, the black matrix includes a plurality of light-shielding lines extending along the first direction, and a plurality of the At least part of the orthographic projection of the light-shielding line on the board surface of the base substrate, and the first sub-pixel filter region, the second sub-pixel filter region and the third sub-pixel filter region
  • the interval in the second direction overlaps, and the orthographic projection of the fifth via hole on the board surface of the base substrate is the same as that of the first plate of the storage capacitor of the first sub-pixel drive circuit.
  • the orthographic projection of the end connected to the second pole of the sensing transistor on the board surface of the base substrate overlaps, and the orthographic projection of the sixth via hole on the board surface of the base board is close to the an orthographic projection of the light-shielding line between the first sub-pixel filter region and the second sub-pixel filter region on the board surface of the base substrate, and overlaps with the second sub-pixel filter region
  • the orthographic projection of the seventh via hole on the board surface of the base substrate is close to the light-shielding line between the second sub-pixel filter area and the third sub-pixel filter area on the base substrate is an orthographic projection on the board surface, and overlaps with the third sub-pixel filter area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of data lines, the plurality of data lines extending along the second direction, the plurality of data lines including a first data line, a second data line located in each repeating unit Two data lines and a third data line, the first data line and the second data line are located between the first sub-pixel driving circuit and the second sub-pixel driving circuit, and the third data line is located between the first sub-pixel driving circuit and the second sub-pixel driving circuit.
  • the first conductive layer further includes a fourth transfer electrode, a fifth transfer electrode along the first direction a connecting electrode and a sixth connecting electrode, the fourth connecting electrode is connected to the first data line and the second electrode of the data writing transistor of the first sub-pixel driving circuit,
  • the first gate line and the second gate line are located in the second conductive layer, and the first gate line is close to the first repeating unit and the A sensing transistor of a second repeating unit, the second gate line is close to the first repeating unit and a data writing transistor of the second repeating unit, the first gate line includes a folded line portion, and the folded line portion includes a first fold line part along the first direction, a second fold line part and a third fold line part along the second direction connected to both ends of the first fold line part, respectively, the first fold line part, the The second folded line portion and the third folded line portion bypass the first connecting line, and the orthographic projection of the first folded line portion on the board surface of the base substrate is the same as the second folded line portion of the first repeating unit.
  • the orthographic projections of the active layers of the sensing transistors of the sensing transistors of the sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the board surface of the base substrate overlap, and the overlapping portion forms the gate of the sensing transistor.
  • a part of the first gate line and the first connection line that is parallel to the line is located on the first connection line the side of the transparent region close to the second repeating unit.
  • the second conductive layer further includes a third connection trace, a fourth connection trace, and a fifth connection trace, the third connection trace, all the The fourth connection line and the fifth connection line are "L"-shaped broken lines, the bending directions of the fourth connection line and the fifth connection line are the same, and the third connection line has the same bending direction.
  • the bending direction is opposite to the bending direction of the fourth connection line and the fifth connection line
  • the third connection line is connected to the data of the second gate line and the first sub-pixel driving circuit
  • the gate of the write transistor is connected
  • the fourth connection line is connected to the second gate line and the gate of the data write transistor of the second sub-pixel drive circuit
  • the fifth connection line is connected to the second gate line and the gate of the data write transistor of the second sub-pixel drive circuit
  • the second gate line is connected to the gate of the data writing transistor of the third sub-pixel driving circuit.
  • the first conductive layer includes a seventh transfer electrode, an eighth transfer electrode, and a ninth transfer electrode along the second direction, the first transfer electrode
  • the orthographic projection of the seventh transfer electrode, the eighth transfer electrode and the ninth transfer electrode on the board surface of the base substrate and the second connection trace on the board surface of the base substrate The orthographic projections on the above overlap, the first end of the seventh via electrode passes through at least part of the eighth via hole penetrating the second insulating layer, and the gate of the driving transistor of the first sub-pixel driving circuit connected, the second end of the seventh transfer electrode is connected to the first electrode of the data writing transistor of the first sub-pixel drive circuit, and the first end of the eighth transfer electrode passes through the second At least part of the ninth via hole of the insulating layer is connected to the gate of the driving transistor of the second sub-pixel driving circuit, and the second end of the eighth transfer electrode is connected to the data of the second sub-pixel driving circuit
  • the first electrode of the write transistor is connected, and the first end
  • At least one embodiment of the present disclosure further provides a display device including the display substrate described in any one of the above.
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a partial structure of the display substrate shown in FIG. 2;
  • FIG. 4 is a schematic plan view of the electrode overlap region in FIG. 3;
  • FIG. 5 is a schematic diagram of optical simulation of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic layout diagram of a sub-pixel driving circuit and a light-emitting element of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7 is a schematic layout diagram of a black matrix and a filter layer of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 8A is a circuit diagram of a sub-pixel driving circuit provided by at least one embodiment of the present disclosure.
  • 8B is a schematic diagram of the connection between a sub-pixel driving circuit and a register unit circuit of a sub-pixel unit circuit provided in at least one embodiment of the present disclosure
  • 9A is a plan view of a light shielding layer provided by at least one embodiment of the present disclosure.
  • 9B is a plan view of a first insulating layer provided by at least one embodiment of the present disclosure.
  • 9C is a plan view of a buffer layer provided by at least one embodiment of the present disclosure.
  • 9D is a plan view of a semiconductor layer provided by at least one embodiment of the present disclosure.
  • 9E is a layout diagram of a second conductive layer provided by at least one embodiment of the present disclosure.
  • 9F is a plan view of an interlayer insulating layer provided by at least one embodiment of the present disclosure.
  • 9G is a plan view of a first conductive layer provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a layout diagram of FIG. 9A to FIG. 9B after stacking
  • FIG. 11A is an enlarged view of the A1 area in FIG. 10;
  • 11B is a schematic cross-sectional view along the line B1-B2 in FIG. 11A;
  • Figure 11C is an enlarged view of the A2 area in Figure 10;
  • 12A is a plan view of a passivation layer provided by at least one embodiment of the present disclosure.
  • FIG. 12B is a plan view of a third insulating layer provided by at least one embodiment of the present disclosure.
  • 12C is a plan view of a first sublayer of a first electrode layer provided by at least one embodiment of the present disclosure
  • 12D is a plan view of a third sublayer of the first electrode layer provided by at least one embodiment of the present disclosure.
  • 12E is a plan view of a pixel defining layer provided by at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • FIGS. 14A-14F are schematic diagrams of a manufacturing process of a display device according to at least one embodiment of the present disclosure.
  • the common large-size transparent display resolution on the market is about 40PPI, and there are few products with high PPI.
  • a bottleneck of today's large-scale high-PPI transparent display devices is that, with the increase of PPI, the smaller the pixel size is, the higher the metal wiring density is, and the wiring density cannot be made too large.
  • the top-emitting white light OLED uses a transparent cathode with high resistance, an auxiliary cathode must be added to reduce the IR Drop, so the conventional auxiliary cathode also needs to occupy the transparent area of the transparent display device.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate and a light shielding layer.
  • the base substrate includes a display area, the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along a first direction, the pixel area includes a plurality of sub-pixels, and the Each includes a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the substrate, the sub-pixel driving circuit is configured to drive the light-emitting element to emit light, and the light-emitting element includes a first electrode, a second electrode and a light emitting layer located between the first electrode and the second electrode.
  • the light-shielding layer is arranged on the base substrate and is located on the side of the sub-pixel driving circuit close to the base substrate, and at least part of the orthographic projection of the light-shielding layer on the board surface of the base substrate is the same as that of the sub-pixel driving circuit on the board of the base substrate.
  • the orthographic projections on the surface overlap, and the light shielding layer is connected to the second electrode for multiplexing as an auxiliary electrode of the second electrode.
  • At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned display substrate.
  • the light shielding layer is used for shielding the sub-pixel driving circuit, and at the same time, it is also connected to the second electrode, so as to be multiplexed as an auxiliary electrode of the second electrode, so that the transparency of the display substrate can be improved.
  • This increases the light transmittance of the display substrate.
  • the resistance of the auxiliary electrode multiplexed by the light shielding layer is smaller, the effect of increasing the resistance of the second electrode is more obvious (that is, the effect of reducing the resistance drop is more obvious).
  • FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 2 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view of a partial structure of the display substrate shown in FIG. 2 .
  • the display substrate 1 includes a base substrate 10 .
  • the base substrate 10 includes a display area 101 .
  • the display area 101 includes a plurality of repeating cells C1 arranged in an array.
  • the plurality of repeating units C1 are arranged in a plurality of rows and rows along the first direction X and the second direction Y, for example, arranged in rows 1 to N extending along the first direction X, and extending along the second direction Y Row 1 and Row F.
  • Each of the plurality of repeating units C1 includes a transparent region TM10 and a pixel region P10 arranged along the first direction X.
  • the pixel region P10 includes a plurality of sub-pixels.
  • the pixel region P10 includes three sub-pixels as an example.
  • the base substrate 10 may be a flexible substrate or a rigid substrate.
  • the base substrate 10 may be made of, for example, glass, plastic, quartz or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the display substrate 1 includes a plurality of power supply lines VDD10 and a plurality of sensing lines SES10 .
  • a plurality of power supply lines VDD10 and a plurality of sensing lines SES10 are disposed on the base substrate 10 and extend along the second direction Y.
  • the plurality of power supply lines VDD10 and the plurality of sensing lines SES10 are respectively connected to the plurality of sub-pixels and extend to the bonding region 103 of the display substrate 1 .
  • the power line VDD10 is connected to a column of sub-pixels corresponding to extending in the second direction Y and provides a second power voltage signal.
  • the sensing line SES10 is connected to a column of sub-pixels corresponding to extending in the second direction Y and provides a reference voltage signal.
  • the display substrate further includes a gate driving circuit 13 located in the peripheral region 102 and a plurality of gate lines G10, and the plurality of gate lines G10 extend along the first direction X.
  • the gate driving circuit 13 is configured to output gate scanning signals for driving the plurality of sub-pixel unit circuits 16 to operate row by row.
  • the gate line G10 is connected to the gate driving circuit 13 and the gate scanning signal corresponding to a row of sub-pixels extending in the first direction X, and the sub-pixels operate.
  • each of the plurality of subpixels includes a subpixel driving circuit 1601 (eg, a first subpixel driving circuit P161 , a second subpixel driving circuit P162 , and a third subpixel driving circuit P163 ) and light-emitting element 160.
  • the light-emitting element 160 is located on the side of the sub-pixel driving circuit 1601 away from the base substrate 10 .
  • the sub-pixel drive circuit 1601 is configured to drive the light-emitting element 160 to emit light.
  • the light emitting element 160 includes a first electrode 161 , a second electrode 162 , and a light emitting layer 163 between the first electrode 161 and the second electrode 162 .
  • each sub-pixel driving circuit 1601 may include a pixel circuit having a circuit structure such as 7T1C, 8T2C, 4T1C, or 3T1C in the art, and the embodiments of the present disclosure take a pixel circuit including a 3T1C circuit structure as an example For introduction, the embodiments of the present disclosure do not limit this.
  • the light shielding layer 131 is disposed on the base substrate 10 and is located on the side of the sub-pixel driving circuit 1601 close to the base substrate 10 to block the irradiation of external light. At least a part of the orthographic projection of the light shielding layer 131 on the surface of the base substrate 10 (eg, the upper surface of the base substrate 10 ) overlaps with the orthographic projection of the sub-pixel driving circuit 1601 on the surface of the base substrate 10 .
  • the light shielding layer 131 is connected to the second electrode 162 to be multiplexed as an auxiliary electrode of the second electrode 162 .
  • the orthographic projection of the light shielding layer 131 on the board surface of the base substrate 10 overlaps with the pixel region P10 of the repeating unit C1, but does not overlap with the transparent region TM10 of the repeating unit C1. It is used as the auxiliary electrode of the second electrode 162, so that the space of the transparent area TM10 of the display substrate 1 can be increased, and the light transmittance of the display substrate 1 can be improved.
  • the effect of increasing the resistance of the second electrode 162 is more obvious (ie, the effect of reducing the resistance drop is more obvious).
  • the material of the light shielding layer 131 may be made of metal materials, for example, the metal materials include silver, aluminum, chromium, copper, molybdenum, titanium, aluminum-neodymium alloy, copper-molybdenum alloy, molybdenum-tantalum alloy, molybdenum-neodymium alloy or any of them. random combination.
  • the pixel region P10 includes an electrode bonding region 12 , and the electrode bonding region 12 is located on the side of the pixel region P10 close to the transparent region TM10 . That is, in one repeating unit C1, the electrode bonding area 12 is located between the pixel area P10 and the transparent area TM10.
  • the orthographic projection of the electrode bonding region 12 on the board surface of the base substrate 10 and the orthographic projection of the light shielding layer 131 on the board surface of the base substrate 10 at least partially overlap, eg, partially overlap.
  • the electrode overlap region 12 includes a first composite hole structure and a first composite overlap electrode.
  • the first composite hole structure is configured to expose the light shielding layer 131 , for example, the first composite hole structure includes a first overlapping hole F11 and a second overlapping hole F12 .
  • the first composite bonding electrode is configured to connect the second electrode 162 and the light shielding layer 131.
  • the first composite bonding electrode includes a first bonding electrode FD11 and a second bonding electrode FD12.
  • the light shielding layer 131 is connected to the second electrode 162 through the first composite lap electrode and the first composite hole structure, so as to be multiplexed as an auxiliary electrode of the second electrode 162 .
  • FIG. 4 is a schematic plan view of the electrode overlapping area in FIG. 3 .
  • the first composite bonding electrode includes a first bonding electrode FD11 and a second bonding electrode FD12 .
  • the first bonding electrode FD11 is located on the side of the second bonding electrode FD11 close to the base substrate 11 .
  • the first composite hole structure includes a first overlapping hole FK11 and a second overlapping hole FK12 .
  • the first overlapping hole FK11 is located on a side of the second overlapping hole FK12 close to the base substrate 10 .
  • the first bonding electrode FD11 is connected to the light shielding layer 131 through the first bonding hole FK11
  • the second bonding electrode FD12 is connected to the first bonding electrode FD11 through the second bonding hole FK12 .
  • the second bonding electrode FK12 is also connected to the second electrode 162 .
  • the second bonding electrode FK12 may also be indirectly connected to the second electrode 162 .
  • the light-emitting layer 163 is also spaced between the second bonding electrode FK12 and the second electrode 162 , that is, the second bonding electrode FK12 (eg, a part) is connected to the second electrode 162 through the light-emitting layer 163 .
  • the second bonding electrode FK12 may also be directly connected to the second electrode 162 .
  • 8A is a circuit diagram of a sub-pixel driving circuit provided by at least one embodiment of the present disclosure.
  • the sub-pixel driving circuit 1601 may adopt a pixel circuit with a 3T1C circuit structure in the art.
  • the sub-pixel driving circuit 1601 includes a data writing transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor CST.
  • the display substrate further includes a first insulating layer 132 (eg, a barrier layer), a second insulating layer 134 (eg, an interlayer insulating layer), a first conductive layer SD, a third The insulating layer 136 (eg, a planarization layer) and the first electrode layer AN.
  • the first insulating layer 132 is used to provide a flat surface for forming the sub-pixel driving circuit 1601, and can prevent impurities that may exist in the base substrate 10 from diffusing into the sub-pixel driving circuit or the gate driving circuit 13 and adversely affect the display substrate. performance, the thickness of the first insulating layer 132 can also avoid parasitic capacitance between the light shielding layer 131 and other film layers.
  • the material of the first insulating layer 132 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • the first insulating layer 132 is located on the side of the light shielding layer 131 away from the base substrate 10 .
  • the second insulating layer 134 is located on the side of the first insulating layer 132 away from the base substrate 10
  • the first conductive layer SD is located on the side of the second insulating layer 134 away from the base substrate 10
  • the third insulating layer 136 is located on the first conductive layer SD is located on the side away from the base substrate 10
  • the first electrode layer AN is located at the side of the third insulating layer 136 away from the base substrate 10 .
  • the first electrode layer AN is the film layer where the first electrode 162 of the light-emitting element 160 is located
  • the first conductive layer SD is the first electrode TSD22 (eg, the source electrode) and the second electrode TSD21 (eg, the drain electrode) of the driving transistor T2 the film layer.
  • the materials of the first insulating layer 132 and the second insulating layer 134 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • the material of the first conductive layer SD may include, for example, a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium, for example, the multi-layer structure is a multi-metal laminated layer (such as Titanium, aluminium and titanium three-layer metal stack (Ti/Al/Ti)).
  • a metal material or an alloy material such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium
  • the multi-layer structure is a multi-metal laminated layer (such as Titanium, aluminium and titanium three-layer metal stack (Ti/Al/Ti)).
  • Ti/Al/Ti titanium three-layer metal stack
  • the material of the third insulating layer 136 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzoin Organic insulating materials such as cyclobutene or phenolic resin, which are not limited in the embodiments of the present disclosure.
  • the first bonding hole FK11 includes a first bonding sub-hole FK111 passing through the first insulating layer 132 and a second bonding hole passing through the second insulating layer 134 Subhole FK112.
  • the second overlapping sub-hole FK112 is sleeved in the first overlapping sub-hole FK111, that is, the orthographic projection of the second overlapping sub-hole FK112 on the board surface of the base substrate 10 is located in the substrate of the first overlapping sub-hole FK111.
  • the front shot of the board surface of the substrate 10 is centered.
  • the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 are arranged to expose the light shielding layer 131 .
  • the first bonding electrode FD11 is located on the side of the second insulating layer 134 away from the base substrate 10 .
  • the second bonding hole FK12 penetrates through the third insulating layer 136 to expose the first bonding electrode FD11 .
  • the first conductive layer SD includes the first bonding electrode FD11.
  • the first electrode layer AN includes the second bonding electrode FD12 and the first electrode 161 of the light emitting element 160 .
  • the first electrode 161 and the second bonding electrode FD12 are provided in the same layer and with the same material, and the first electrode 161 and the second bonding electrode FD12 are spaced apart from each other.
  • first electrode 161 and the second bonding electrode FD12 are of the same layer and made of the same material, for example, prepared through the same process, the first electrode 161 and the second bonding electrode FD12 are disconnected Or not connected.
  • the second bonding electrode FD12 is configured to be connected to the second electrode 162 of the light emitting element and the first bonding electrode FD11.
  • the first electrode 161 and the second bonding electrode FD12 are prepared in the same film layer, which can reduce the patterning process and the thickness of the display substrate.
  • the display substrate further includes a buffer layer 133 .
  • the buffer layer 133 is located between the first insulating layer 132 and the second insulating layer 134
  • the first bonding hole FK11 further includes a third bonding sub-hole FK113 .
  • the third overlapping sub-hole FK113 is sleeved between the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 , and the third overlapping sub-hole FK113 penetrates through the buffer layer 133 and is disposed to expose the light shielding layer 131 .
  • the orthographic projection of the third overlapping sub-hole FK113 on the board surface of the base substrate 10 is located in the orthographic projection of the first overlapping sub-hole FK111 on the board surface of the base substrate 10 .
  • the first overlapping hole FK11 is a sleeve hole formed by the third overlapping sub-hole FK113 , the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 .
  • the material of the buffer layer may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • the second overlapping sub-hole FK112 may be formed by etching first, and then the third overlapping sub-hole FK113 may be formed by etching.
  • the dimensions of the contact sub-hole FK112 and the third overlapping sub-hole FK113 are basically the same.
  • the second insulating layer 134 will not be in contact with the third bridge sub-hole FK113.
  • the display substrate further includes a passivation layer 135 .
  • the passivation layer 135 is located between the third insulating layer 136 and the first conductive layer SD (first bonding electrode FD11).
  • the second bridging hole FK12 also penetrates the passivation layer 135 .
  • the passivation layer 135 can protect the first conductive layer SD from being corroded by water vapor.
  • the material of the passivation layer 135 may include organic insulating material or inorganic insulating material, for example, silicon nitride material, because of its high dielectric constant and good hydrophobic function, it can well protect the sub-pixel driving The circuit is not corroded by water vapor.
  • the widths of the first overlapping sub-holes FK111 and the second overlapping sub-holes FK112 in the first direction X may be about 3.5-4.5 microns, for example, about 4 microns .
  • the width of the third overlapping sub-hole FK113 in the first direction X may be about 7.5-8.5 micrometers, for example, about 8 micrometers.
  • the width of the second bonding hole FK12 in the first direction X may be about 6.5-7.5 micrometers, for example, about 7 micrometers.
  • the sizes of the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 may or may not be equal.
  • the sizes of the first overlapping sub-holes FK111, the second overlapping sub-holes FK112, the third overlapping sub-holes FK113 and the second overlapping sub-holes FK12 are selected by the manufacturing process of the display substrate, and the embodiments of the present disclosure are not limited thereto. .
  • the first electrode layer AN includes a first layer AN1 , a second layer AN2 and a third layer AN3 .
  • the first layer AN1 is located on the side of the third insulating layer 136 away from the base substrate 10
  • the third layer AN3 is located on the side of the first layer AN1 away from the base substrate 10
  • the second layer AN2 is located on the first layer AN1 and the third layer between AN3.
  • the first electrode 161 of the light emitting element 160 is a three-layer structure arranged in the same layer as the first layer AN1 , the second layer AN2 and the third layer AN3 respectively, and the cross section of the first electrode 161 is I-shaped.
  • the second electrode 162 may be disposed in part or the whole of the display area 101, so that it may be formed on the entire surface during the manufacturing process.
  • the first electrode 161 of the light emitting element may include a reflective layer
  • the second electrode 162 of the light emitting element may include a transparent layer or a semitransparent layer.
  • the first electrode 161 can reflect the light emitted from the light emitting layer 163, and the part of the light is emitted into the external environment through the second electrode 162, so that the light extraction rate can be improved.
  • the second electrode 162 includes a semi-transmissive layer, some light reflected by the first electrode 161 is reflected again by the second electrode 162, so the first electrode 161 and the second electrode 162 form a resonance structure, so that light extraction efficiency can be improved.
  • the materials of the first layer AN1 and the second layer AN2 may include at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the material of the third layer 163 may include an alloy material such as AlNd or the like.
  • the light-emitting layer 163 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, may emit red light, green light, blue light, or may emit white light; It may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light emitting layer may include quantum dot materials, eg, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead hydride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc., the particle size of the quantum dots is 2-20nm.
  • the light emitting layer 163 is taken as an example to emit white light.
  • the second electrode 162 may include various conductive materials.
  • the second electrode 162 may include metallic materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag).
  • the second electrode 162 may include a metal having high reflectivity, such as silver (Ag), as a reflective layer.
  • the second bonding electrode FD12 includes a first sub-electrode layer FD121 , a second sub-electrode layer FD122 and a third sub-electrode layer FD123 which are stacked on each other.
  • the first sub-electrode layer FD121 is located on the side of the third sub-electrode layer FD123 close to the base substrate 10
  • the second sub-electrode layer FD122 is located between the first sub-electrode layer FD121 and the third sub-electrode layer FD123.
  • the first sub-electrode layer FD121 and the first layer AN1 of the first electrode layer AN are provided in the same layer and with the same material.
  • the second sub-electrode layer FD122 and the second layer AN2 of the first electrode layer AN are provided in the same layer and with the same material.
  • the third sub-electrode layer FD123 and the third layer AN3 of the first electrode layer AN are provided in the same layer and with the same material.
  • At least one side in the circumferential direction of the first sub-electrode layer FD121 protrudes from the second sub-electrode layer FD122 in a direction parallel to the plate surface of the base substrate 10 .
  • the first sub-electrode layer FD121 protrudes from the second sub-electrode layer FD122 in the circumferential direction.
  • the orthographic projection of the second sub-electrode layer FD122 on the board surface of the base substrate 10 is located in the orthographic projection of the first sub-sub-electrode layer FD121 on the board surface of the base substrate 10 .
  • the orthographic projection of the third sub-electrode layer FD123 on the board surface of the base substrate 10 is located in the orthographic projection of the first sub-electrode layer FD121 on the board surface of the base substrate 10
  • the first sub-electrode layer FD121 is located on the base substrate 10
  • the projected area on the board surface is larger than the projected area of the third sub-electrode layer FD123 on the board surface of the base substrate 10 .
  • the projected area of the orthographic projection of the first sub-electrode layer FD121 on the board surface of the base substrate 10 is the largest, the projected area of the orthographic projection of the third sub-electrode layer FD123 on the board surface of the base substrate 10 is next, and the The projected area of the orthographic projection of the two sub-electrode layers FD122 on the board surface of the base substrate 10 is the smallest.
  • the portion of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122 can be used for connection with the second electrode 162 .
  • the projected area of the second sub-electrode layer FD122 on the board surface of the base substrate 10 is smaller than that of the first sub-electrode layer FD121 and the third sub-electrode layer FD123 respectively.
  • the projected area on the board surface of the base substrate 10 is I-shaped, and the first sub-electrode layer FD121 is connected to the first bonding electrode FD11 through the second bonding hole FK12 .
  • the width D3 of the first sub-electrode layer FD121 in the first direction X may be about 28-30 micrometers, for example, about 29 micrometers.
  • the length D4 of the first sub-electrode layer FD121 in the second direction Y may be about 30-31 microns, for example, about 31.5 microns.
  • the distance D1 between the third sub-electrode layer FD123 (or the second sub-electrode layer FD122 ) and the edge of the first sub-electrode layer FD121 in the first direction X may be, for example, about 5.5-6.5 microns, for example, about 6 microns.
  • the display substrate 10 further includes a pixel defining layer 138 .
  • the pixel defining layer 138 is located on the side of the first electrode 161 away from the base substrate 10 .
  • the pixel defining layer 138 includes a plurality of openings, and some of the plurality of openings define sub-pixels and correspond to the light-emitting regions of the light-emitting element 160 .
  • the light-emitting layer 163 is also provided on the entire surface of the second electrode 162 on the side close to the base substrate 10 .
  • the pixel defining layer 138 further has an opening, and the pixel defining layer 138 partially covers the region of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122.
  • the pixel defining layer 138 extends to a region of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122 and covers the edge of the first sub-electrode layer FD121. In this way, the pixel defining layer 138 can prevent the first sub-electrode layer FD121 from being discharged due to burrs in the corners of the first sub-electrode layer 163 , which may cause process defects.
  • the distance D2 between the edge of the pixel defining layer 138 and the edge of the first sub-electrode layer FD121 in the second direction Y may be, for example, about 2.5-3.5 ⁇ m, such as about 3 microns.
  • the light-emitting layer 163 of the light-emitting element 160 is stacked on a side of the pixel defining layer 138 away from the base substrate 10 .
  • the light emitting layer 163 includes a first portion 1631 and a second portion 1632 located in the electrode bonding region 12 .
  • the first portion 1631 covers at least a portion of a region of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122, and the first portion 1631 is in contact with the first sub-electrode layer FD121.
  • the second portion 1632 is located on the side of the third sub-electrode layer FD123 away from the base substrate 10 .
  • the second electrode 162 of the light emitting element 160 includes a first electrode portion 1621 and a second electrode portion 1622 located in the electrode overlap region 12 .
  • the first electrode part 1621 is located in a region of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122, and the first electrode part 1621 is in contact with the first and second sub-electrode layers FD121 and FD122.
  • the second electrode part FD122 is located on the side of the second part 1632 of the light emitting layer 163 away from the base substrate 10 .
  • the orthographic projection of the first portion 1631 of the light emitting layer 163 on the board surface of the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode portion 1621 on the board surface of the base substrate 10 . That is, in the region of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122, the first electrode portion 1621 and the first portion 1631 of the light-emitting layer 163 and the upper surface of the first sub-electrode layer FD121 (parallel to the lining The board surface of the base substrate 10 ) and the side surface (perpendicular to the board surface of the base substrate 10 ) of the second sub-electrode layer FD122 are in contact.
  • the display substrate 10 further includes a semiconductor layer ACT, a fourth insulating layer 137 (eg, a gate insulating layer), and a second conductive layer GATE.
  • the semiconductor layer ACT is located on the side of the buffer layer 133 away from the base substrate 10 .
  • the fourth insulating layer 137 is located on the side of the semiconductor layer ACT away from the base substrate 10 .
  • the second conductive layer GATE is located between the second insulating layer 134 and the fourth insulating layer 137 .
  • the semiconductor layer ACT includes the active layer TA2 of the driving transistor T2.
  • the second conductive layer GATE includes the gate electrode TG2 of the driving transistor T2, and the first conductive layer SD includes the first electrode TSD21 and the second electrode TSD22 of the driving transistor T2.
  • the second conductive layer active layer TA2 has a source region corresponding to the first electrode TSD21 and a drain region corresponding to the second electrode TSD22.
  • the semiconductor layer ACT further includes a first electrode plate CST1 of the storage capacitor CST, and the first conductive layer SD further includes a second electrode plate CST2 of the storage capacitor CST.
  • a second insulating layer 134 is spaced between the first electrode plate CST1 and the second electrode plate CST2. For example, the second electrode plate CST2 is connected to the first electrode TSD21 of the driving transistor T2.
  • the first electrode 161 of the light emitting element 160 is connected to the first conductive layer through a via hole passing through the passivation layer 135 and the third insulating layer 136 .
  • a portion of the first electrode 161 of the light-emitting element 160 in the same layer as the first sub-layer AN1 of the first electrode layer AN is connected to the first electrode of the driving transistor T2 through a via hole penetrating the passivation layer 135 and the third insulating layer 136 TSD21 connection.
  • a portion of the first electrode 161 of the light emitting element 160 on the same layer as the first sublayer AN1 of the first electrode layer AN is connected to the second electrode plate CST2 to be connected to the first electrode TSD21 of the driving transistor T2.
  • the portion of the first electrode 161 of the light emitting element 160 in the same layer as the first sub-layer AN1 of the first electrode layer AN is directly connected to the first electrode TSD21 of the driving transistor T2. That is, in a cross-sectional view perpendicular to the plate surface of the base substrate 10 , the first electrode TSD21 of the driving transistor T2 and the first electrode plate 1 of the storage capacitor CST are spaced apart from each other.
  • cross-sectional structures of other transistors of the sub-pixel driving circuit 160 such as the data writing transistor T1 and the driving transistor T2 and the cross-sectional structure of the sensing transistor T3 may be the same, which will not be repeated here.
  • the first electrode represents the source electrode of the transistor
  • the second electrode represents the drain electrode of the transistor
  • the material of the semiconductor layer ACT may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes metal oxide semiconductor (eg indium gallium zinc oxide (IGZO)), and the polysilicon includes low temperature polysilicon or high temperature polysilicon.
  • IGZO indium gallium zinc oxide
  • Polysilicon, etc. are not limited in the embodiments of the present disclosure.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which are not limited in the embodiments of the present disclosure.
  • the material of the fourth insulating layer 137 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • the material of the second conductive layer GATE may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum and titanium, for example, the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum, etc.) and titanium three-layer metal stack (Ti/Al/Ti)).
  • a metal material or an alloy material such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum and titanium
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum, etc.) and titanium three-layer metal stack (Ti/Al/Ti)).
  • the display substrate 10 further includes an encapsulation layer 139 .
  • the encapsulation layer 139 is provided on the side of the light emitting element 160 away from the base substrate 10 .
  • the encapsulation layer 139 seals the light emitting element 160 so that deterioration of the light emitting element 160 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 139 may have a single-layer structure or a composite-layer structure, and the composite-layer structure includes a structure in which an inorganic layer and an organic layer are stacked.
  • the encapsulation layer 139 includes at least one encapsulation sublayer.
  • the encapsulation layer 139 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.
  • the material of the encapsulation layer 139 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high compactness and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc. , such as polymer resin, etc.
  • the display substrate to planarize the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccants to absorb the water intruding inside, substances such as oxygen.
  • water-absorbing materials such as desiccants to absorb the water intruding inside, substances such as oxygen.
  • the display substrate 1 further includes a filter layer LG and a black matrix BM.
  • the filter layer LG and the black matrix BM are located on the side of the light emitting element 160 away from the base substrate 10 , that is, on the encapsulation layer 139 .
  • the filter layer LG and the black matrix BM may be partially stacked. In the stacked portion of the filter layer LG and the black matrix BM, the black matrix BM is located on the side of the filter layer LG close to the base substrate 10 .
  • FIG. 6 is a schematic layout diagram of a sub-pixel driving circuit and a light-emitting element of a display substrate according to at least one embodiment of the present disclosure.
  • 7 is a schematic layout diagram of a black matrix and a filter layer of a display substrate according to at least one embodiment of the present disclosure.
  • the black matrix BM in each pixel region P10 , includes a plurality of light-shielding lines extending along the first direction X (for example, BM1/BM2 shown in FIG. 7 ) .
  • the filter layer LG includes a first sub-pixel filter region LG1, a second sub-pixel rate filter region LG2 and a third sub-pixel filter region LG3.
  • the first sub-pixel filter area LG1 , the second sub-pixel rate filter area LG2 and the third sub-pixel filter area LG3 are arranged spaced apart from each other along the second direction Y.
  • At least part of the orthographic projection of the plurality of light-shielding lines on the board surface of the base substrate 10 is between the first sub-pixel filter region LG1, the second sub-pixel rate filter region LG2 and the third sub-pixel filter region LG3
  • the intervals in the second direction Y overlap.
  • at least part of the light-shielding line BM1 of the plurality of light-shielding lines and the orthographic projection on the board surface of the base substrate 10 is in the second direction Y with the first sub-pixel filter region LG1 and the second sub-pixel rate filter region LG2 The intervals above overlap.
  • At least part of the light-shielding line BM2 of the plurality of light-shielding lines and the orthographic projection on the board surface of the base substrate 10 is in the second direction Y with the second sub-pixel rate filter region LG2 and the third sub-pixel filter region LG3 The intervals above overlap.
  • the first sub-pixel filter region LG1, the second sub-pixel rate filter region LG2, and the third sub-pixel filter region LG3 correspond to the light-emitting elements of the sub-pixels of the pixel region P10, respectively.
  • the black matrix BM does not include other light-shielding lines that do not extend along the first direction X. That is to say, the black matrix BM does not include the light-shielding lines extending in other directions between the light-transmitting region TM10 and the pixel region P10, but only includes the filtering lines extending along the first direction and extending in the first sub-pixel shown in FIG. 7 .
  • the area of the light-transmitting region TM10 can be increased to increase the light transmittance of the display substrate.
  • the included angle between the first direction X and the second direction Y involved in the present disclosure is between 70° and 90°, inclusive.
  • the included angle between the first direction X and the second direction Y is 70°, 90°, or 80°, etc., which can be set according to actual conditions, which is not limited in the embodiments of the present disclosure.
  • the included angle between the first direction X and the second direction Y may also be 75°, 85°, or the like.
  • the material of the filter layer may include a resin material doped with a colorant, for example, a dye or a pigment may be used as the colorant, so that the resin material, such as a polymer resin material, has a color.
  • the material of the black matrix BM may include an opaque black resin material or the like.
  • the first sub-pixel filter region LG1 , the second sub-pixel rate filter region LG2 and the third sub-pixel filter region LG3 are respectively a red light region, a green light region and a blue light region, that is, respectively Transmits red, green and blue light.
  • the order of the colors of the light transmitted through the first sub-pixel filter region LG1 , the second sub-pixel rate filter region LG2 , and the third sub-pixel filter region LG3 may be interchanged, which is not limited to this embodiment of the present disclosure.
  • the first sub-pixel filter region LG1 in the first direction X, on the side of the pixel region P10 close to the light-transmitting region TM10 , the first sub-pixel filter region LG1 , the second sub-pixel filter region LG1
  • the orthographic projections of the light region LG2 and the third sub-pixel filter region LG3 on the board surface of the base substrate 10 partially overlap with the orthographic projection of the pixel defining layer 138 on the board surface of the base substrate 10 .
  • the first sub-pixel filter region LG1 the second sub-pixel rate filter region LG2 and the third sub-pixel filter region LG2
  • the edge of the pixel filter region LG3 beyond the pixel defining layer 138 extends above the pixel defining layer 138 .
  • the length of the overlapping portion of 138 on the board surface of the base substrate 10 is D5.
  • the light leakage of the light-emitting area of the light-emitting element can be reduced under different angles at the same time, so as to reduce the color attenuation of the display substrate.
  • FIG. 5 is a schematic diagram of optical simulation of a display substrate according to at least one embodiment of the present disclosure.
  • the first subpixel filter region LG1 , the second subpixel rate filter region LG2 , and the third subpixel filter region LG3 overlap the pixel defining layer 138 in a direction perpendicular to the base substrate 10
  • the size range of the portion along the first direction X is, for example, about 5 micrometers to 7 micrometers, for example, about 6 micrometers, so that a better display effect can be achieved.
  • an optical simulation in the second direction Y is performed to select a suitable distance where the filter area exceeds the pixel defining layer 138 .
  • value range the filter layer exceeds the size range of the length D5 (also shown in FIG. 3 ) of the pixel defining layer 138 in the first direction X, such as about 5 ⁇ m to 7 ⁇ m, such as about 6 ⁇ m, at this time , the effect of preventing light leakage is better, and it can meet the requirements of display effect.
  • the value of the length D5 is larger, the effect of preventing light leakage is better.
  • the pixel defining layer 138 in FIG. 5 shows an open area (that is, the pixel defining layer 138 is shown in reverse phase, and the marked area is a dug out area).
  • the display substrate further includes a light-transmitting layer 1310 and a protective layer 1311 .
  • the light-transmitting layer 1310 is disposed on the side of the filter layer LG away from the base substrate 10 .
  • the protective layer 1311 is disposed on a side of the light-transmitting layer 1310 away from the base substrate 10 .
  • the protective layer 1311 can be used as a cover plate, and the material of the protective layer 1311 can include flexible materials, such as transparent polyimide (CPI, Colorless Polyimide), polyethylene terephthalate (PET, Polyethylene Terephthalate) Or cycloolefin polymer (COP, Cyclo Olefin Polymer) and so on.
  • CPI transparent polyimide
  • PET Polyethylene terephthalate
  • COP Cyclo Olefin Polymer
  • the light-transmitting layer 1310 can be an optical adhesive layer, that is, it can play a role of light-transmitting or bonding.
  • the material of the light-transmitting layer 1310 can include a transparent insulating material, for example, the transparent insulating material is polyamide Transparent organic materials such as imines, resins, and a layer of optically transparent special substrate-free double-sided tape (OCA, Optically Clear Adhesive).
  • OCA optically transparent special substrate-free double-sided tape
  • the gate driving circuit 13 is configured to drive a plurality of sub-pixels in the pixel regions P10 of each row of repeating cells C1 extending along the first direction X through the gate line G10 one by one to operate. gate scan signal.
  • the plurality of repeating units C1 are arranged in N rows extending respectively along the first direction, the gate driving circuit 13 includes N cascaded shift register units 170 (as shown in FIG. 8B ), and the n-th shift register unit 170 It is connected to the sub-pixel driving circuit 1601 of the pixel region P10 of the nth row of repeating unit C1, wherein 1 ⁇ n ⁇ N, and N is an integer greater than or equal to 2.
  • the plurality of sub-pixel driving circuits in the pixel region P10 of each repeating unit C1 are arranged along the first direction X.
  • the plurality of sub-pixel drive circuits are respectively connected to different light-emitting elements.
  • the sub-pixel driving circuit 1601 of each of the plurality of sub-pixels includes a data writing circuit 1603, a driving circuit 1604, a charge storage circuit 1606, and a sensing circuit 1605.
  • the drive circuit 1604 is connected to the first node G, the second node S, and the third node D.
  • the third node D is also connected to the first power supply voltage terminal ELVDD.
  • the first power supply voltage terminal ELVDD is connected to the power supply line VDD10 which supplies the first power supply voltage.
  • the driving circuit 1604 is configured to control the driving current flowing through the light emitting element 160 under the control of the level of the first node G.
  • the data write circuit 1603 is connected to the first node G, and is configured to receive a gate scan signal (eg, provided by the gate drive circuit through the gate line G10 ) as the scan drive signal, and to write the data signal in response to the scan drive signal The first node G.
  • the charge storage circuit 1606 is connected to the first node G and the second node S, and is configured to store the written data signal and the reference voltage signal. Connected to the second node S, configured to connect the gate scan signal as a sensing driving signal, and write a reference voltage signal into the driving circuit 1604 or read the sensing voltage signal from the driving circuit 1604 in response to the sensing driving signal.
  • the light emitting element 160 (for example, the first electrode 161 of the light emitting element 160) is connected to the second node S and the second power supply voltage terminal ELVSS, and is configured to receive the second power supply voltage through the second power supply voltage terminal ELVSS, and drive current driven by the light.
  • the second power supply voltage terminal ELVSS is connected to a power supply line ELVSS (not shown in the figure), and the power supply line ELVSS is configured to provide the second power supply voltage.
  • the power line ELVSS is configured to run around the display area 101 , the second electrode 1602 of the light emitting element 160 is disposed on the entire surface, and is connected to the power line ELVSS to receive the second power supply voltage.
  • the data writing circuit 1603 is implemented as a data writing transistor T1
  • the driving circuit 1604 is implemented as a driving transistor T2
  • the charge storage circuit 1606 is implemented as a storage capacitor CST
  • the sensing circuit 1605 is implemented as a sensing transistor T3.
  • the plurality of gate lines G10 in FIG. 1 include a first gate line G1 and a second gate line G2.
  • the first pole of the data writing transistor T1 is connected to one of the plurality of data lines DATA so as to receive data signals, and the second pole of the data writing transistor T1 is connected to the first node G (that is, to the gate TG2 of the driving transistor T2). connect).
  • the gate TG1 of the data writing transistor T1 is connected to the first gate line G1 of the plurality of gate lines (ie, the gate line connected to the output end of the shift register unit) so as to receive a scan driving signal.
  • the first pole of the driving transistor T2 is connected to a second power supply voltage terminal ELVDD, configured to receive the first supply voltage, and the second pole of the driving transistor T2 is connected to the second node S (that is, to the first pole of the sensing transistor T3 ). pole connection).
  • the gate G221 of the sensing transistor T22 is configured to receive a sensing driving signal, for example, the gate G221 of the sensing transistor T22 and the second gate line G2 of the plurality of gate lines (ie, located in a different row from the sensing transistor T22)
  • the output end of the shift register unit is connected to the gate line) so as to receive the sensing driving signal.
  • the first pole of the sensing transistor T2 is connected to the second node S, and the second pole of the sensing transistor T2 is connected to a sensing signal line SENSE (which is one of the plurality of sensing signal lines SES10 in FIG. 1 ), which is It is configured to receive a reference voltage signal or output a sensed voltage signal.
  • the first electrode (eg, the first electrode 161 ) of the light-emitting element 160 is connected to the second node S, that is, the second electrode (eg, the second electrode 162 ) of the driving transistor T2 and the first electrode of the sensing transistor T3 are connected, Therefore, the driving current of the driving transistor T2 can be received;
  • the second pole of the light emitting element 160 is configured to be connected to the second power supply voltage terminal ELVSS to receive the second power supply voltage.
  • the second pole of the light-emitting element 160 is configured to be grounded, and the second driving voltage is 0V at this time.
  • the first power supply voltage is a high level voltage (eg, 5V, 10V or other suitable voltage)
  • the second power supply voltage is a low level voltage (eg, 0V, -5V, -10V or other suitable voltage).
  • the driving transistor T2 is turned on (or partially turned on)
  • the first power supply voltage and the second power supply voltage can be regarded as a power supply, and the power supply is used to generate a driving current for driving the light-emitting element 160 .
  • the light-emitting element 160 may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the above transistors are all described by taking N-type transistors as an example, that is, each transistor is turned on when the gate is connected to a high level (on level), and is turned off when it is connected to a low level (off level).
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also adopt P-type transistors.
  • the first electrode may be the source electrode
  • the second electrode may be the drain electrode.
  • the polarity of each pole of a transistor of a certain type may be connected according to the polarity of each pole of the corresponding transistor in the embodiment of the present disclosure.
  • FIG. 8B is a schematic diagram of the connection between the sub-pixel driving circuit and the register unit circuit of the sub-pixel unit circuit provided by at least one embodiment of the present disclosure.
  • the sensing circuits 1605 of the plurality of sub-pixel driving circuits 1601 in the pixel region P10 of the extended M-1 th row repeating unit C1 are connected to the output terminals of the M th row shift register unit 170 to connect the M th row shift register unit 170
  • the gate scan signal output from the output terminal of the M-th row is output to the data writing circuit 1603 of the plurality of sub-pixel drive circuits 1601 in the pixel region P10 of the M-th row of repeating units C1 as a scan drive signal, and output to the M-1th
  • the data writing circuits 1603 of the sub-pixel driving circuits 1601 are connected to the output terminals of the shift register unit 170 in the M+1 th row, so as to output the gate scan signal output from the output terminal of the shift register unit 170 in the M+1 th row to
  • the data writing circuits 1603 of the multiple sub-pixel driving circuits 1601 in the pixel region P10 of the repeating unit C1 in the M+1 row are used as scan driving signals and output to the multiple sub-pixel driving circuits in the pixel area P10 in the repeating unit C1 in the M+1 row.
  • the sensing circuit 1605 of 1601 serves as the sensing drive signal. 1 ⁇ M ⁇ N, where M is an odd number greater than
  • the Mth row extending along the first direction X represents the Mth row in the horizontal direction
  • the Mth row extending along the second direction Y represents the Mth row in the vertical direction
  • 9A is a plan view of a light shielding layer provided by at least one embodiment of the present disclosure.
  • the light-shielding layer 131 includes a light-shielding electrode 111 , and the light-shielding electrode 111 extends along the second direction Y (eg, the light-shielding electrode 111 in the second direction Y At least a part of the orthographic projection of the light-shielding electrode 111 on the board surface of the base substrate 10, for example, a part with the plurality of sub-pixel driving circuits 1601 of each pixel region P10 (for example, the first sub-pixel driving circuit 1601)
  • the orthographic projection of the circuit P161, the second sub-pixel driving circuit P162 or the third sub-pixel driving circuit P163) on the board surface of the base substrate 10 is overlapped, so that the external light can be blocked from irradiating the sub-pixel driving circuit, especially the transistor. active layer to avoid dark current generation.
  • the light-shielding electrode 131 includes a first end portion 1111 , a middle concave portion 1113 and a second end portion 1112 in the second direction Y, and the middle concave portion 1113 is located between the first end portion 1111 and the second end portion 1112 .
  • the width of the first end portion 1111 and the second end portion 1112 in the first direction X is greater than the width of the middle recessed portion 1113 in the first direction.
  • the orthographic projections of the first end portion 1111 and the second end portion 1112 on the board surface of the base substrate 10 are related to the data writing transistor T1 , the driving transistor T2 and the sensing transistor T3 of the sub-pixel driving circuit 1601 .
  • the orthographic projections of the active layer on the board surface of the base substrate 10 overlap.
  • the electrode bonding area 12 is located between the middle recess 1113 and the light-transmitting area TM10.
  • the light-shielding electrode 131 is arranged in the shape of narrow and two ends in the middle, which can reduce the space occupancy rate of the light-shielding electrode 131 and increase the area of the light-transmitting area.
  • the sensing transistor T3 is located above (eg, above the storage capacitor CST), and the driving transistor T2 and the data writing transistor T1 are located on the storage capacitor CST away from the sensing transistor T3 side.
  • the orthographic projection of the active layers of the data writing transistor T1 and the driving transistor T2 on the board surface of the base substrate 10 overlaps with the orthographic projection of the second end portion 1112 of the light shielding electrode 131 on the board surface of the base substrate 10 .
  • the orthographic projection of the active layer of the sensing transistor T3 on the board surface of the base substrate 10 overlaps with the orthographic projection of the first end portion 1111 of the light shielding electrode 131 on the board surface of the base substrate 10 . Therefore, the light shielding layer can block external light from irradiating the active layers of the data writing transistor T1 , the driving transistor T2 and the sensing transistor T3 of the transistors, so as to avoid the generation of dark current.
  • the sub-pixel driving circuit 1601 (eg, the first sub-pixel driving circuit P161 , the second sub-pixel driving circuit P162 , and the third sub-pixel driving circuit P162 in the pixel region P10 )
  • the first plate CST1 and the second plate CST2 of the storage capacitor CST of the circuit P163) include strips extending along the second direction Y.
  • the first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2 and the third sub-pixel filter area LG3 are arranged in sequence along the second direction Y, and the second sub-pixel filter area LG2
  • the region LG2 is located between the first subpixel filter region LG1 and the third subpixel filter region LG3.
  • At least part of the sensing transistor T3 of the sub-pixel driving circuit of the sub-pixels of the first sub-pixel filter region LG1 and the plurality of sub-pixels in the pixel region P10 (for example, the part close to the storage capacitor CST), and the part of the storage capacitor CST close to the sensing transistor T3
  • the orthographic projection of the part (for example, if the strip-shaped storage capacitor CST is divided into three parts in the first direction Y, this part is the upper part of the storage capacitor CST) on the board surface of the base substrate 10 overlaps.
  • At least parts of the data writing transistors and the driving transistors of the sub-pixel driving circuits of the sub-pixels in the third sub-pixel filter region LG3 and the sub-pixels in the pixel region P10 (for example, the part close to the storage capacitor CST), and the storage capacitor CST close to the driving transistor
  • the orthographic projection of the portion of T2 (eg, the portion where the storage capacitor CST is located below) on the board surface of the base substrate 10 overlaps.
  • the second sub-pixel filter region LG2 and the sub-pixel drive circuits of the sub-pixels in the pixel region P10 have a portion close to the middle of the storage capacitor CST in the first direction (for example, the middle portion of the storage capacitor CST) on the base substrate.
  • the orthographic projections on the board of 10 overlap.
  • the strip-shaped storage capacitor CST and the design of the square-like filter area can increase the area of the transparent area of the display substrate and improve the display effect.
  • the first sub-pixel filter area LG1 , the second sub-pixel rate filter area LG2 and the third sub-pixel filter area LG3 can also be designed as stripes extending along the second direction Y , the embodiments of the present disclosure are not limited thereto.
  • At least one embodiment of the present disclosure further provides a display substrate including a base substrate and a plurality of sensing lines.
  • a plurality of sensing signal lines are arranged on the base substrate and extend along a second direction different from the first direction, and two rows of the plurality of sensing signal lines along the second direction are respectively arranged between two adjacent ones of the plurality of sensing signal lines.
  • each of the plurality of sensing signal lines is simultaneously connected to the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of repeating units adjacent thereto and respectively along the second direction, and is configured to provide a reference voltage signal.
  • the space occupied by the signal wiring is reduced, the area of the transparent region is increased, and the light transmittance is improved.
  • a plurality of sensing signal lines SES10 are disposed on the base substrate 10 and extend along the second direction Y.
  • the plurality of sensing signal lines SES10 extend to the bonding area 13 , for example, are also connected to the contact pads (not shown in the figure) of the bonding area 13 to receive electrical signals provided by an external driving circuit (eg, a chip).
  • Two rows of repeating units C1 along the second direction Y are disposed between adjacent two of the plurality of sensing signal lines SES10, and each of the plurality of sensing signal lines SES10 is simultaneously and adjacent to it and respectively along the second direction Y.
  • the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of repeating units C10 in the two directions Y are connected and configured to provide reference voltage signals. That is, adjacent two of each of the plurality of sensing signal lines SES10 are separated by two repeating cells C1 in the same row. Each of the plurality of sensing signal lines SES10 is connected to the pixel regions P10 of the two repeating units C1 on both sides thereof along the first direction X. As a result, the sub-pixel driving circuits of multiple sub-pixels in the pixel region P10 of the two repeating units C1 share one sensing signal line SES10, thereby reducing the number of sensing signal lines and the occupied wiring space, thereby increasing the area of the transparent region .
  • a plurality of power supply lines VDD10 are disposed on the base substrate 10 and extend along the second direction Y, and in the first direction X, the plurality of power supply lines VDD10 and the plurality of sense The sensing signal lines SES10 are alternately arranged, and a row of repeating cells C1 extending along the second direction Y is disposed between each of the plurality of sensing signal lines SES10 and the power supply line VDD10 adjacent thereto. That is, the plurality of power supply lines VDD10 and the plurality of sensing signal lines SES10 define a space extending along the second direction Y where the repeating cells C1 are not lined up.
  • a row of repeating cells C1 extending along the second direction Y is disposed between each of the plurality of power supply lines VDD10 and the sensing signal line SES10 adjacent thereto.
  • Two rows of repeating cells C1 extending along the second direction Y are disposed between adjacent two of the plurality of power supply lines VDD10, and each of the plurality of power supply lines VDD10 is simultaneously and adjacent to it and extends along the second direction Y respectively.
  • the sub-pixel driving circuits of the plurality of sub-pixels of the two-row repeating unit C1 are connected and configured to provide a first power supply voltage. That is, adjacent two of each of the plurality of power supply lines VDD10 are separated by two repeating cells C1 in the same row.
  • Each of the plurality of power supply lines VDD10 is connected to the pixel regions P10 of the two repeating cells C1 on both sides thereof along the first direction X. Therefore, the sub-pixel driving circuits of multiple sub-pixels in the pixel region P10 of the two repeating units C1 share one power supply line VDD10, thereby reducing the number of power supply lines and the occupied wiring space, thereby increasing the area of the transparent region.
  • 9B is a plan view of a first insulating layer provided by at least one embodiment of the present disclosure.
  • 9C is a plan view of a buffer layer provided by at least one embodiment of the present disclosure.
  • 9D is a plan view of a semiconductor layer provided by at least one embodiment of the present disclosure.
  • FIG. 9E is a layout diagram of a second conductive layer provided by at least one embodiment of the present disclosure.
  • 9F is a plan view of an interlayer insulating layer provided by at least one embodiment of the present disclosure.
  • 9G is a plan view of the first conductive layer provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a layout diagram of FIG. 9A to FIG. 9B after stacking.
  • the structure of the sub-pixel unit driving circuit 1601 of a plurality of sub-pixels in the pixel area will be described in detail below with reference to FIGS. 9B-9G and FIG. 10 . It should be noted that the structure of one sub-pixel unit driving circuit 1601 in FIGS. 9B-9G and FIG. 10 will be used as an example for description, and the structures of other sub-pixel unit driving circuits are the same and will not be repeated.
  • the display area 101 includes a first repeating unit C11 and a second repeating unit C12 adjacently arranged along the first direction, and the pixel area of the first repeating unit C11 is the same as the A sensing signal line SES11 is provided between the transparent regions TM10 of the second repeating unit C12, and the sensing signal line SES11 is connected to a plurality of sub-pixel driving circuits in the pixel regions P10 of the first repeating unit C11 and the second repeating unit C12. That is, a plurality of sub-pixel driving circuits in the pixel region P10 of the first repeating unit C11 and the second repeating unit C12 share one sensing signal line.
  • a power supply line VDD11 is provided on the side of the pixel area P10 of the second repeating unit C12 away from the transparent area TM10 of the second repeating unit C12, and the power supply line VDD11 is connected to a plurality of sub-pixel driving circuits in the pixel area P10 of the second repeating unit C12.
  • a side of the transparent region TM10 of a repeating unit C11 away from the pixel area P10 of the first repeating unit C11 is provided with another power supply line VDD12, the other power supply line VDD12 and a plurality of sub-pixel driving circuits of the pixel area P10 of the first repeating unit C11 connect.
  • each power line is connected to the pixel area of two repeating units.
  • the structures shown in FIG. 2 and FIG. 6 are used for introduction, and other parts of the structures are similar and will not be illustrated and described in detail.
  • the plurality of sub-pixel driving circuits in the pixel region P10 of the first repeating unit C11 and the plurality of sub-pixel driving circuits in the pixel region P10 of the second repeating unit layer 2 are respectively It includes a first sub-pixel driving circuit P161, a second sub-pixel driving circuit P162 and a third sub-pixel driving circuit P163 arranged in the first direction X.
  • the second sub-pixel driving circuit P162 is located between the first sub-pixel driving circuit P161 and the third sub-pixel driving circuit P163.
  • the orthographic projections of the first sub-pixel driving circuit P161 , the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 on the board surface of the base substrate 10 all extend along the second direction Y.
  • the first sub-pixel driving circuit P161 is mirror-symmetrical with the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163.
  • the first sub-pixel driving circuit P161 , the second sub-pixel driving circuit P162 , and the third sub-pixel driving circuit P163 have the same structure as one sub-pixel driving circuit as an example. Introduced, other sub-pixel driving circuits will not be described in detail.
  • a first overlapping sub-hole FK111 located in the electrode overlapping region 12 is formed on the first insulating layer 132 to expose the light shielding layer 131 shown in FIG.
  • the buffer layer 133 has a third overlapping sub-hole FK113 located in the electrode overlapping area 12 to expose the light shielding layer 131 shown in FIG.
  • the third overlapping sub-hole FK113 is sleeved in the first overlapping sub-hole FK111.
  • the orthographic projections of the data writing transistor T1 , the driving transistor T2 and the sensing transistor T3 of the sub-pixel driving circuit on the base substrate 10 are all along the second direction Y extension.
  • the semiconductor layer ACT includes the active layer TA1 of the data writing transistor T1 of the sub-pixel driving circuit, the active layer TA2 of the driving transistor T2 and the active layer TA3 of the sensing transistor T3.
  • the active layer TA1 of the data writing transistor T1 of the sub-pixel driving circuit, the active layer TA2 of the driving transistor T2 and the active layer TA3 of the sensing transistor T3 all extend along the second direction Y.
  • the base substrate 10 may be a flexible substrate. Therefore, during the bending process of the display substrate, it can be ensured that the electrical performance of each transistor of the sub-pixel driving circuit is not affected, and the display stability of the display substrate is ensured.
  • the active layer TA1 of the data writing transistor T1, the active layer TA2 of the driving transistor T2 and the active layer TA3 of the sensing transistor T3 may not be parallel to the second direction Y, such as intersecting the second direction Y by a certain amount. angle.
  • the intersection angle is 20° or less.
  • the semiconductor layer ACT further includes the first electrode plate CST1 of the storage capacitor of the first sub-pixel driving circuit P161.
  • the active layer TA3 of the sensing transistor T3 is located on the upper side of the first plate CST1 of the storage capacitor, and the active layer TA2 of the driving transistor T2 and the active layer TA1 of the data writing transistor T1 are located on the first plate CST1 of the storage capacitor On the side away from the sensing transistor T3, the active layer TA2 of the driving transistor T2 is located between the sensing transistor T3 and the data writing transistor T1.
  • the first electrode plate CST1 of the storage capacitor CST is connected to the active layer TA2 of the driving transistor T2 and provided integrally.
  • the first plate CST1 of the storage capacitor is a strip extending along the second direction Y.
  • the position corresponding to the electrode overlap region 12 of the first plate CST1 of the storage capacitor is provided with a convex portion CST11 protruding like a side away from the transparent region TM10, and the convex portion has a notch CST12, the notch CST12
  • the electrode bonding area 12 is surrounded to leave a space for the electrode bonding area 12 . That is, the electrode overlap region 12 occupies part of the space of the first electrode plate CST1, thereby reducing the space occupied by the electrode overlap region 12 in the transparent region TM10 and increasing the area of the transparent region. For example, as shown in FIG.
  • the shape of the first electrode plate CST1 of the storage capacitor of the second sub-pixel driving circuit P162 is slightly different from that of the first electrode plate CST1 of the storage capacitor of the first sub-pixel driving circuit P161 .
  • the portion of the first plate CST1 of the storage capacitor of the second sub-pixel driving circuit P162 corresponding to the convex portion CST11 is bent to leave the wiring between the first sub-pixel driving circuit P161 and the second sub-pixel driving circuit P162 space.
  • the shape of the first electrode plate CST1 of the storage capacitor of the third subpixel driving circuit P163 is slightly different from that of the first electrode plate CST1 of the storage capacitor of the first subpixel driving circuit P161 and the second subpixel driving circuit P162.
  • the first plate CST1 of the storage capacitor of the third sub-pixel driving circuit P163 corresponds to the portion of the convex portion CST11, and the edge on the side close to the second sub-pixel driving circuit P162 is to the right (away from the second sub-pixel driving circuit P162 direction) is recessed to leave a wiring space between the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163. That is to say, a structure similar to the notch CST12 surrounding the electrode bonding area 12 can also be correspondingly provided in the first plate CST1 of the storage capacitors of the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163.
  • the active layer TA3 of the sensing transistor T3 includes a source region TS3 , a channel region TP3 and a drain region TD3 .
  • the active layer TA2 of the driving transistor T2 includes a source region TS2, a channel region TP2, and a drain region TD2.
  • the active layer TA1 of the data writing transistor T1 includes a source region TS1, a channel region TP1, and a drain region TD1.
  • the second conductive layer GATE includes the gate TG1 of the data writing transistor T1 , the gate TG2 of the driving transistor T2 and the gate TG3 of the sensing transistor T3 .
  • the orthographic projection of the channel region TP3 on the base substrate partially overlaps the orthographic projection of the gate TG3 on the base substrate.
  • the orthographic projection of the channel region TP1 on the base substrate partially overlaps the orthographic projection of the gate TG1 on the base substrate.
  • the orthographic projection of the channel region TP2 on the base substrate partially overlaps the orthographic projection of the gate TG2 on the base substrate.
  • the first conductive layer SD includes the first and second electrodes TSD11 and TSD12 of the data writing transistor T1, the first and second electrodes TSD21 and TSD22 of the driving transistor T2, and the gate of the sensing transistor T3
  • the poles are the first pole TSD31 and the second pole TSD32 and the second pole plate CST2 of the storage capacitor CST.
  • the first electrode TSD11 and the second electrode TSD12 of the data writing transistor T1 respectively overlap with the orthographic projections of the source region TS1 and the drain region TSD1 of the data writing transistor T1 on the base substrate 10 .
  • the first electrode TSD21 and the second electrode TSD22 of the driving transistor T2 respectively overlap with the orthographic projections of the source region TS2 and the drain region TD2 of the driving transistor T2 on the base substrate 10 .
  • the first electrode TSD31 and the second electrode TSD32 of the sensing transistor T3 respectively overlap with the orthographic projections of the source region TS3 and the drain region TD3 of the sensing transistor T3 on the base substrate 10 .
  • a second insulating layer 134 is spaced between the second electrode plate CST2 of the storage capacitor CST and the first electrode plate CST1 of the storage capacitor to form a capacitor function. As shown in FIG.
  • the first electrode TSD31 of the sensing transistor T3 is connected to the source region TS3 through the third via hole GK3, and the second electrode TSD32 of the sensing transistor T3 is connected to the source region TS3 through the first source-drain via hole SDG1 (for example, through the first source-drain via hole SDG1).
  • Two insulating layers 134) are connected to the drain region TD3.
  • the first electrode TSD21 of the driving transistor T2 is connected to the source region TS2 through the second source-drain via hole SDG2 (for example, passing through the second insulating layer 134 ), and the second electrode TSD22 of the driving transistor T2 is connected to the drain electrode through the fourth via hole GK3 Zone TD2 connection.
  • the first electrode TD11 of the data writing transistor T1 is connected to the source region TS1 through the third source-drain via hole SDG3 (for example, passing through the second insulating layer 134 ), and the second electrode TD12 of the data writing transistor T1 is connected to the source region TS1 through the fourth source drain hole.
  • the hole SDG4 (eg, through the second insulating layer 134 ) is connected to the drain region TD1 .
  • first source-drain via hole SDG1, the second source-drain via hole SDG2, the third source-drain via hole SDG3, and the fourth source-drain via hole SDG4 may be arranged to pass through the second insulating layer 134 and the fourth insulating layer Layer 137.
  • the size of the first source-drain via hole SDG1 , the second source-drain via hole SDG2 , the third source-drain via hole SDG3 , and the fourth source-drain via hole SDG4 may range from about 2 to 4 microns, for example, about 3 microns.
  • the sizes of the first source-drain via hole SDG1 , the second source-drain via hole SDG2 , the third source-drain via hole SDG3 , and the fourth source-drain via hole SDG4 are selected in a manufacturing process of the display substrate.
  • the second insulating layer 134 and the fourth insulating layer 137 may also be spaced between the second electrode plate CST2 and the first electrode plate CST1 of the storage capacitor CST, which is not limited to this embodiment of the present disclosure.
  • the second insulating layer 134 further includes a second bonding sub-hole FK112 located in the electrode bonding region 12 .
  • the first conductive layer SD further includes a first bonding electrode FD11 located in the electrode bonding region 12 .
  • one end of the second electrode plate CST2 of the storage capacitor CST close to the second electrode TSD32 of the sensing transistor T3 is connected to the second electrode TSD2 of the sensing transistor T3, and
  • the second electrode plate CST2 and the second electrode TSD32 of the sensing transistor T3 are integrally arranged.
  • the first electrode TSD21 of the driving transistor T2 is connected to the end of the second electrode plate CST2 of the storage capacitor CST far away from the sensing transistor T3, and the first electrode TSD21 of the driving transistor T2 and the second electrode plate CST2 are integrally arranged to reduce the occupied space. space.
  • each of the plurality of power supply lines includes the first sub-line VDD111 located in the second conductive layer GATE and the first sub-line VDD111 located in the first conductive layer.
  • the first sub-line VDD111 includes a plurality of first line segments VDD112 extending along the second direction Y, the plurality of first line segments VDD112 are respectively located in different repeating cells C1, and the second sub-line VDD121 passes through the display along the second direction Y District 101.
  • the power supply line is a double-layered line, respectively in the first conductive layer SD and the second conductive layer GATE, and each first line segment VDD112 of each first sub-line VDD111 in the second conductive layer GATE is located in a repeating cell C1 , and the second sub-line VDD121 of the first conductive layer SD extends along the second direction Y and passes through a row of repeating cells C1 in the second direction Y, that is, the second sub-line VDD121 extends along the second direction Y set up.
  • the second sub-line VDD121 is stacked on the side of the first sub-line VDD111 away from the base substrate 10 , and communicates with the first sub-line through at least one first via GK1 (as shown in FIG.
  • each of the plurality of sensing signal lines for example, the sensing line SES11 includes a third sub-line SES111 located in the second conductive layer GATE and a third sub-line SES111 located in the first conductive layer SD
  • the fourth sub-line SES121, the third sub-line SES111 includes a plurality of second wiring segments SES112 extending along the second direction Y, the plurality of second wiring segments SES112 are distributed in different repeating units, and the fourth sub-line SES121 is along the second The direction Y passes through the display area 101 .
  • the sensing line is a double-layered line, which is respectively in the first conductive layer SD and the second conductive layer GATE, and each second line segment SES112 of the third sub-line SES111 in the second conductive layer GATE is located in a repeating unit C1.
  • the fourth sub-line SES121 of the first conductive layer SD extends along the second direction Y, and passes through a row of repeating units C1 in the second direction Y, that is, the fourth sub-line SES121 extends in the second direction Y. set up.
  • the fourth sub-line SES121 is stacked on the side of the second sub-line SES111 away from the base substrate 10, and communicates with the third sub-line through at least one second via GK2 (as shown in FIG. 9F ) passing through the second insulating layer 124. SES111 connection.
  • a plurality of second via holes GK2 are arranged along the second direction Y for connecting the fourth sub-line SES121 and the third sub-line SES111 . Thereby, the wiring resistance of the power supply line can be reduced.
  • the first conductive layer SD includes a first transfer electrode ZL1 extending along the first direction X.
  • the first terminal ZL11 of the first transfer electrode ZL1 is connected to the first pole TSD31 of the sensing transistor T3 of the third sub-pixel driving circuit P163 of the first repeating unit C11.
  • the second end ZL12 of the first transfer electrode ZL1 is connected to the first pole TSD31 of the sensing transistor T3 of the first sub-pixel driving circuit P161 of the second repeating unit C12, and the first transfer electrode ZL1 is connected to the sensing signal line SES11.
  • the second sub-line SES121 is cross-connected. That is, the sensing signal line SES11 simultaneously provides the reference voltage signal to the first repeating unit C11 and the second repeating unit C12 through the first transition electrode ZL1.
  • FIG. 11A is an enlarged view of the area A1 in FIG. 10 .
  • the second conductive layer GATE includes a first connection trace LL1 extending along the first direction X, and the first connection trace LL1 passes through the third via GK3 At least a part (eg, part) of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12.
  • One pole TSD31 connection is not limited to be a part (eg, part) of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12.
  • a first connecting line LL1 is set in the pixel region of each repeating unit, so that the first electrodes TSD31 of the sensing transistors T3 of the plurality of sub-pixel driving circuits all receive the reference voltage signal provided by the sensing signal line SES11. At least part of the orthographic projection of the first pole TSD31 of the sensing transistor T3 of the first sub-pixel driving circuit P161 , the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 on the board surface of the base substrate 10 (for example, part) overlaps with the orthographic projection of the first connection wiring LL1 on the board surface of the base substrate 10 .
  • the first connection line LL1 may not be parallel to the first direction X, for example, intersect the first direction X at a certain angle.
  • the intersection angle is 20° or less.
  • FIG. 11B is a schematic cross-sectional view along the line B1-B2 in FIG. 11A .
  • the portion of the orthographic projection of the first pole TSD31 on the board surface of the base substrate 10 overlaps with the orthographic projection of the first connection line LL1 on the board surface of the base substrate 10 .
  • the first pole TSD31 of the sensing transistor T3 includes a first sub-section TSD311 and a second sub-section TSD312 connected along the second direction Y.
  • the projection of the third via hole GK3 on the base substrate 10 overlaps with the projections of the first sub-section TSD311 and the second sub-section TSD312 of the first pole TSD31 on the base substrate 10 .
  • a portion of the third via hole GK3 eg, a portion overlapping the projection of the first sub-portion TSD311 on the base substrate 10 , is configured to penetrate the second insulating layer 134 and the fourth insulating layer 137 to expose the active portion of the sensing transistor T3 Layer TA3 (eg source region TS3).
  • Another portion of the third via hole GK3 eg, a portion overlapping with the projection of the second sub-portion TSD312 on the base substrate 10 , is configured to penetrate through the second insulating layer 134 to expose the first connection trace LL1 .
  • the first sub-section TSD311 is in contact with and connected to the active layer TA3 of the sensing transistor T3, and the second sub-section TSD312 is in contact and connected with the first connection line LL1.
  • the cross-sectional structure of the third via hole GK3 can also be called a semi-buried hole, so that the wiring space can be reduced to leave the space for the transparent area.
  • the width of the third via hole GK3 in the first direction X is, for example, about 2-4 micrometers, for example, about 3 micrometers.
  • the length of the third via hole GK3 in the second direction Y is, for example, about 5-7 micrometers, for example, about 6 micrometers.
  • the first conductive layer SD further includes a second transfer electrode ZL2 and a third transfer electrode ZL3
  • the second transfer electrode ZL2 and the third transfer electrode ZL3 respectively includes the third nodes D (as shown in FIG. 8A ).
  • the second pole TSD22 of the driving transistor T2 is located on the side of the driving transistor T2 away from the storage capacitor CST.
  • One end of the second transfer electrode ZL2 is connected to the second electrode TSD22 of the driving transistor T2 of the third sub-pixel driving circuit P163 of the second repeating unit C12, and the other end of the second transfer electrode ZL2 is connected to the second repeating unit C12 close to the second electrode TSD22.
  • the power supply line VDD11 of the third sub-pixel driving circuit P163 is connected to provide the first power supply voltage.
  • the second transfer electrode ZL2 extends along the first direction X.
  • One end of the third transfer electrode ZL3 is connected to the second electrode TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161 of the first repeating unit C11, and the other end of the third transfer electrode ZL3 is connected to the first repeating unit C11 close to the second electrode TSD22.
  • the power supply line VDD12 of the transparent region TM10 is connected to provide a first power supply voltage.
  • the third transfer electrode ZL3 is routed on the lower side of the light-transmitting area TM10 (closer to the side of the data writing transistor T1), and is bent between the transparent area TM10 and the pixel area P10 to the side close to the driving transistor T2 line to reduce wiring space. That is to say, the power supply line VDD11 or the power supply line VDD12 is connected with a second transfer electrode ZL2 and a third transfer electrode ZL3 to connect the sub-pixel driving circuits on both sides thereof, and the power supply line VDD11 and the power supply line VDD12 on the other side are connected to each other. The structure will not be repeated here.
  • FIG. 11C is an enlarged view of the area A2 in FIG. 10 .
  • the second conductive layer includes a second connection trace LL2 extending along the first direction X, and the second connection trace LL2 passes through at least the fourth via GK4 part (eg, part) with the second pole of the driving transistor T2 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12 TSD22 connection. That is to say, the plurality of sub-pixel driving circuits in the pixel region are all connected to the power supply line through the second connection line LL2.
  • the part of the orthographic projection of the second electrode TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 on the board surface of the base substrate 10 is connected to the second The orthographic projections of the wiring LL2 on the board surface of the base substrate 10 overlap.
  • the cross-sectional structure of the fourth via hole GK4 is similar to that of the third via hole GK3 and will not be described in detail here.
  • the second connection line LL2 may not be parallel to the first direction X, for example, intersect the first direction X at a certain angle.
  • the intersection angle is 20° or less.
  • the display substrate 1 further includes a plurality of data lines, the plurality of data lines extend along the second direction Y, and the plurality of data lines include the first data line located in each repeating unit.
  • the first data line DR and the second data line DB are located between the first subpixel driving circuit P161 and the second subpixel driving circuit P162, and the third data line DB is located between the second subpixel driving circuit P162 and the third subpixel driving circuit Between P163.
  • the first data line DR, the second data line DG and the third data line DB are bent and routed at positions corresponding to the electrode bonding regions 12 .
  • the first data line DR, the second data line DG and the third data line DB are respectively electrically connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 to provide data signals respectively .
  • the first conductive layer further includes a fourth transfer electrode ZL4, a fifth transfer electrode ZL5 and a sixth transfer electrode ZL6 along the first direction X.
  • the fourth transfer electrode ZL4 is connected to the first data line DR and the second pole TSD12 of the data writing transistor T1 of the first sub-pixel driving circuit P161, and the fifth transfer electrode ZL5 is connected to the second data line DG and the second sub-pixel driving circuit
  • the sixth transfer electrode ZL6 is connected to the third data line DB and the second pole TSD12 of the data writing transistor T1 of the third sub-pixel driving circuit P163.
  • the fourth transfer electrode ZL4, the fifth transfer electrode ZL5 and the sixth transfer electrode ZL6 may not be parallel to the first direction X, for example, intersect the first direction X at a certain angle.
  • the intersection angle is 20° or less.
  • the second electrode TSD12 and the fourth transfer electrode ZL4 of the data writing transistor T1 of the first sub-pixel driving circuit P161 and the data writing transistor T1 of the second sub-pixel driving circuit P162 are mirror-symmetrical.
  • the first gate line G1 and the second gate line G2 are located in the second conductive layer GATE, and the first gate line G1 is close to the first repeating unit C11 and the second repeating unit
  • the sensing transistor T3 of the cell C12 and the second gate line G2 are close to the data writing transistor T1 of the first repeating cell C11 and the second repeating cell C12.
  • the first grid line G1 includes a broken line portion, and the broken line portion includes a first broken line portion G111 along the first direction X, a second broken line portion G112 and a third broken line along the second direction Y respectively connected to both ends of the first broken line portion G111. Section G113.
  • the first folding line part G111 , the second folding line part G111 and the third folding line part G113 bypass the first connecting line ZL1 .
  • the orthographic projection of the first folded line portion G111 on the board surface of the base substrate 10 corresponds to the sense of the first sub-pixel driving circuit P161 , the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 of the first repeating unit C10 .
  • the orthographic projections of the active layer TA3 of the sensing transistor T3 on the board surface of the base substrate 10 overlap, and the overlapping portion forms the gate TG3 of the sensing transistor T3.
  • the second conductive layer GATE further includes a third connection line LL3 , a fourth connection line LL4 and a fifth connection line LL5 .
  • the third connection line LL3, the fourth connection line LL4 and the fifth connection line LL5 are generally “L”-shaped fold lines, and the bending directions of the fourth connection line LL4 and the fifth connection line LL5 are the same (for example, toward the first A sub-pixel driving circuit P161), the bending direction of the third connecting line LL3 (eg toward the second sub-pixel driving circuit P162) is opposite to the bending direction of the fourth connecting line LL4 and the fifth connecting line LL5.
  • the third connecting line LL3 is connected to the second gate line G2 and the gate TG1 of the data writing transistor T1 of the first sub-pixel driving circuit P161.
  • the fourth connecting line LL4 is connected to the second gate line G2 and the second sub-pixel driving circuit The gate TG1 of the data writing transistor T1 of the circuit P162 is connected.
  • the fifth connecting line LL5 is connected to the second gate line G2 and the gate TG1 of the data writing transistor T1 of the third sub-pixel driving circuit P163.
  • the first conductive layer SD further includes a seventh transfer electrode ZL7 , an eighth transfer electrode ZL8 and a ninth transfer electrode ZL9 along the second direction Y .
  • the first end (the upper end) of the seventh transfer electrode ZL7 passes through at least part (eg, part) of the eighth via hole GK8 penetrating the second insulating layer 134 , and communicates with the driving transistor T2 of the first sub-pixel driving circuit P161 .
  • the gate TG2 is connected, and the second end (the lower end) of the seventh transfer electrode ZL7 is connected to the first electrode TSD11 of the data writing transistor T1 of the first sub-pixel driving circuit P161.
  • the first end (the upper end) of the eighth transfer electrode ZL8 passes through at least part (eg, part) of the ninth via hole GK9 penetrating the second insulating layer 134 to communicate with the driving transistor T2 of the second sub-pixel driving circuit P162.
  • the gate TG2 is connected, and the second end (the lower end) of the eighth transfer electrode ZL8 is connected to the first electrode TSD11 of the data writing transistor T1 of the second sub-pixel driving circuit P162.
  • the first end (the upper end) of the ninth transfer electrode ZL9 passes through at least a part (eg, part) of the tenth via hole GK10 penetrating the second insulating layer 134 to communicate with the driving transistor T3 of the third sub-pixel driving circuit P163.
  • the gate TG3 is connected, and the second end (the lower end) of the ninth transfer electrode ZL9 is connected to the first electrode TSD11 of the data writing transistor T1 of the third sub-pixel driving circuit P163.
  • the seventh transfer electrode ZL7 , the eighth transfer electrode ZL8 and the ninth transfer electrode ZL9 may not be parallel to the first direction X, for example, intersect the first direction X at a certain angle.
  • the intersection angle is 20° or less.
  • the structures of the eighth via hole GK8 , the ninth via hole GK9 and the tenth via hole GK10 may be similar to the structure of the third via hole GK3 , which will not be repeated here.
  • the part of the parallel wiring of the first gate line G1 and the first connection wiring ZL1 is located near the second repetition of the first connection wiring ZL1
  • the first connection trace ZL1 is spaced from the first folded portion G111 of the first gate line G1
  • the second connection trace ZL2 is spaced from the second gate line G2 to reduce the distance between trace signals interference.
  • 12A is a plan view of a passivation layer provided by at least one embodiment of the present disclosure.
  • 12B is a plan view of a third insulating layer provided by at least one embodiment of the present disclosure.
  • 12C is a plan view of a first sub-layer of a first electrode layer provided by at least one embodiment of the present disclosure.
  • 12D is a plan view of a third sublayer of the first electrode layer provided by at least one embodiment of the present disclosure.
  • 12E is a plan view of a pixel defining layer provided by at least one embodiment of the present disclosure.
  • the plurality of light emitting elements 160 of each repeating unit C1 includes a first light emitting element 164 , a second light emitting element 165 and a third light emitting element 166 .
  • the first light emitting element 164 , the second light emitting element 165 and the third light emitting element 166 are respectively disposed corresponding to the first sub-pixel filter region LG1 , the second sub-pixel filter region LG2 and the third sub-pixel filter region LG3 .
  • the display substrate 1 further includes a fifth via hole GK5 , a sixth via hole GK6 and a seventh via hole GK7 penetrating at least the third insulating layer 136 (and also the passivation layer 135 ).
  • the fifth via hole GK5 , the sixth via hole GK6 and the seventh via hole GK7 are respectively configured to expose the first sub-pixel driving circuit P161 , the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 .
  • the first electrode 161 of the first light emitting element 164 is connected to the first sub-pixel driving circuit P161 through the fifth via hole GK5.
  • the first electrode 161 of the second light emitting element 165 is connected to the second sub-pixel driving circuit P162 through the sixth via hole GK6.
  • the first electrode 161 of the third light-emitting element 166 is connected to the third sub-pixel driving circuit P163 through the seventh via hole GK7.
  • the fifth via hole GK5 , the sixth via hole GK6 and the seventh via hole GK7 penetrate the third insulating layer 136 and the passivation layer 135 respectively, so as to connect the first light emitting element 164 with the The first sub-pixel driving circuit P161 is connected, the second light-emitting element 165 is connected with the second sub-pixel driving circuit P162, and the third light-emitting element 166 is connected with the third sub-pixel driving circuit P163.
  • the third insulating layer 136 and the passivation layer 135 shown in FIG. 12A and FIG. 12B are in the reverse phase structure, that is, the filled part is the part that is dug out (absent).
  • the orthographic projection of the fifth via hole GK5 on the board surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting region of the first light-emitting element 164 on the board surface of the base substrate 10 , so that The flatness of the light-emitting region of the first light-emitting element 164 is improved.
  • the orthographic projection of the sixth via hole GK6 on the board surface of the base substrate 10 does not overlap with the orthographic projection of the light emitting region of the second light emitting element 165 on the board surface of the base substrate 10 , so as to improve the light emission of the second light emitting element 165 the flatness of the area.
  • the orthographic projection of the seventh via hole GK7 on the board surface of the base substrate 10 does not overlap with the orthographic projection of the light emitting region of the third light emitting element 166 on the board surface of the base substrate 10 , so as to improve the light emission of the third light emitting element 166 the flatness of the area.
  • the size range of the fifth via GK5, the sixth via GK6 and the seventh via GK7 may be about 9-12 microns.
  • the dimensions of the fifth via GK5, the sixth via GK6 and the seventh via GK7 are selected to be about 10 or 11 microns.
  • the sizes of the fifth via hole GK5 , the sixth via hole GK6 and the seventh via hole GK7 are selected by the display substrate in the manufacturing process.
  • the orthographic projections of the fifth via hole GK5 and the sixth via hole GK6 on the board surface of the base substrate 10 are close to the first sub-pixel filter
  • the light-shielding lines BM1 between are on both sides of the orthographic projection of the board surface of the base substrate 10 .
  • the fifth via hole GK5 is located below the light emitting area of the first light emitting element 164 and on the upper side of the light-shielding line BM1
  • the sixth via hole GK6 is located on the upper side of the light emitting area of the second light emitting element 165 .
  • the orthographic projection of the seventh via hole GK7 on the board surface of the base substrate 10 is close to the light-shielding line BM2 between the second sub-pixel filter region LG2 and the third sub-pixel filter region LG3 on the board surface of the base substrate 10 , and overlaps with the third sub-pixel filter region LG3.
  • the seventh via hole GK7 is located on the upper side of the light emitting region of the third light emitting element 166 to increase the area of the light emitting region of the third light emitting element 166 . It should be noted that, in this embodiment, the position of the fifth via hole GK5 is different from the position of the fifth via hole GK5 shown in FIG. 6 .
  • the orthographic projection of the fifth via GK5 on the board surface of the base substrate 10 corresponds to the storage capacitor of the first sub-pixel driving circuit P161
  • One end of the first electrode plate CST1 of the CST connected to the second electrode TSD31 of the sensing transistor T3 overlaps the orthographic projection of the first electrode plate CST1 on the plate surface of the base substrate 10 . That is, the fifth via hole GK5 is located on the upper side of the light emitting area of the first light emitting element 164 to reduce the influence on the light emitting area of the first light emitting element 164 .
  • the orthographic projection of the sixth via hole GK6 on the board surface of the base substrate 10 is close to the light-shielding line BM1 between the first sub-pixel filter region LG1 and the second sub-pixel filter region LG2 on the board surface of the base substrate 10 , and overlaps with the second sub-pixel filter region LG2. That is, the sixth via hole GK6 is located on the upper side of the light emitting region of the second light emitting element 165 to increase the area of the light emitting region of the first light emitting element 164 .
  • the orthographic projection of the seventh via hole GK7 on the board surface of the base substrate 10 is close to the light-shielding line BM2 between the second sub-pixel filter region LG2 and the third sub-pixel filter region LG3 on the board surface of the base substrate 10 , and overlaps with the third sub-pixel filter region LG3. That is to say, the seventh via hole GK7 is located on the upper side of the light emitting region of the third light emitting element 166 to increase the area of the light emitting region of the third light emitting element 166 .
  • the first layer AN1 of the first electrode layer AN includes the first sub-electrode layer FD121 and the linings adjacent to the first electrodes of the first light-emitting element 164 , the second light-emitting element 165 and the third light-emitting element 163
  • One layer of the base substrate 10 .
  • the layers of the first electrodes of the first light emitting element 164 , the second light emitting element 165 and the third light emitting element 163 close to the base substrate 10 pass through the fifth via GK5 , the sixth via GK6 and the seventh via GK7 respectively.
  • the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 are connected, and the third sub-pixel driving circuit P163 is connected.
  • the first sub-electrode layer FD121 is connected to the first bonding electrode FD11 through the second bonding hole FD12 penetrating the passivation layer 135 and the third insulating layer 136 in FIGS. 12A and 12B .
  • the third layer AN3 of the first electrode layer AN includes the second electrode layer FD122 and the first electrodes of the first light emitting element 164 , the second light emitting element 165 and the first electrode of the third light emitting element 163 remote from the substrate One layer of the substrate 10 .
  • the pixel defining layer 138 has a plurality of openings to define the light-transmitting region TM10 , the light-emitting regions of the first light-emitting element 164 , the second light-emitting element 165 and the third light-emitting element 163 , and the electrode bonding region 12 .
  • the pixel defining layer 138 is of an inverted structure in FIG. 12E , that is, the filled part in the figure represents the cut-out part.
  • the width of each trace of the first conductive layer SD (shown in FIG. 9G ) surrounding the via hole is 4-5 ⁇ m.
  • the width of each trace of the second conductive layer GATE (shown in FIG. 9E ) is 4-5 ⁇ m.
  • the first pole or the second pole of the data writing transistor T1 and the driving transistor T2 exceeds the via hole by 1 micrometer up and down, for example, 4.0-4.5 micrometers.
  • the thickness of the second conductive layer GATE is 2000-300 angstroms
  • the thickness of the first conductive layer SD is 5000-8000 angstroms, which is not limited by the embodiments of the present disclosure.
  • FIG. 13 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device 2 includes the display substrate 1 provided by any embodiment of the present disclosure, for example, the display substrate 1 shown in FIG. 2 .
  • the display device 2 may be a product or component with a transparent display function.
  • the display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.
  • FIGS. 14A-14F are schematic diagrams of a manufacturing process of a display device according to at least one embodiment of the present disclosure.
  • a base substrate 10 is provided, and a metal material is deposited on the base substrate to form a light shielding layer 131 through a patterning process.
  • metallic materials include silver, aluminum, chromium, copper, molybdenum, titanium, aluminum neodymium alloys, copper molybdenum alloys, molybdenum tantalum alloys, molybdenum neodymium alloys, or any combination thereof.
  • a first insulating layer 132 is formed by depositing an insulating material on the light shielding layer 131 through a patterning process. The first insulating layer 132 includes the first overlapping sub-holes FK111.
  • the material of the first insulating layer 132 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • a buffer layer 133 is formed by depositing an insulating material on the first insulating layer 132 through a patterning process.
  • the buffer layer 133 includes the third overlapping sub-holes FK113.
  • a semiconductor material is deposited on the buffer layer 133 to form the active layer TA2 of the driver circuit T2 of the sub-pixel driver circuit and the first plate CST1 of the storage capacitor CST through a patterning process, that is, the semiconductor layer ACT shown in FIG. 9D is formed.
  • a fourth insulating layer 137 is formed by depositing an insulating material on the semiconductor layer ACT through a patterning process.
  • a metal material is deposited on the four insulating layers 137 to form the gate TG2 of the driving circuit T2 of the sub-pixel driving circuit, that is, the second conductive layer GATE as shown in FIG. 9E is formed.
  • the material of the gate TG2 of the driving circuit T2 includes, for example, a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium, for example, the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum, etc.).
  • a second insulating layer 134 is formed by depositing an insulating material on the second conductive layer GATE through a patterning process.
  • the second insulating layer 134 includes the second bridge sub-hole FK112.
  • a metal material is deposited on the second insulating layer 134 to form the first electrode TSD21 and the second electrode TSD22 and the first bonding electrode FD11 of the driving circuit T2 through a patterning process, that is, the first conductive layer SD.
  • the materials of the first pole TSD21 and the second pole TSD22 and the first bonding electrode FD11 of the driving circuit T2 may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed of molybdenum, aluminum, and titanium, etc.
  • the multi-layer structure is a multi-metal stack (eg, titanium, aluminum, and titanium tri-metal stack (Ti/Al/Ti)).
  • a passivation layer 135 and a third insulating layer 136 are sequentially formed on the first conductive layer SD.
  • the passivation layer 135 and the third insulating layer 136 include a second tap hole FK12 and a via hole exposing the sub-pixel driving circuit.
  • a first layer AN1 of the first electrode layer AN is formed by depositing a metal material on the third insulating layer 136 through a patterning process.
  • the first layer AN1 of the first electrode layer AN includes two parts spaced apart from each other, namely the first sub-electrode layer FD121 of the second bonding electrode FD12 and a layer of the first electrode 161 of the light emitting element 160 close to the base substrate.
  • the first sub-electrode layer FD121 of the second bonding electrode FD12 is connected to the first bonding electrode through the second bonding hole FK12.
  • a layer of the first electrode 161 of the light-emitting element 160 close to the base substrate is connected to the sub-pixel driving circuit through the via holes in the chemical layer 135 and the third insulating layer 136 .
  • the material of the first layer AN1 of the first electrode layer AN includes at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • a material layer M2 is formed, for example, by means of evaporation, and the material layer M2 is used to form the second layer AN2 of the first electrode 161 .
  • the material layer M2 may include an alloy material such as AlNd or the like.
  • the material layer M3 is formed, and the material layer M3 is used to form the third layer AN3 of the first electrode 161 .
  • the material layer M3 may include at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • a patterning process is performed on the material layer M3 to form the third sub-electrode layer FD123 of the second bonding electrode FD12 and the layer of the first electrode 161 of the light-emitting element 160 away from the base substrate, that is, the first Layer 3 AN3.
  • a patterning process is performed on the material layer M2 to form an intermediate layer between the second sub-electrode layer FD122 of the second bonding electrode FD12 and the first electrode 161 of the light-emitting element 160 , that is, the second layer AN2 .
  • the cross-section of the first electrode 161 of the light-emitting element 160 is I-shaped and the first sub-electrode layers FD121, FD121, The cross sections of the second sub-electrode layer FD122 and the third sub-electrode layer FD123 are I-shaped.
  • the pixel defining layer 138, the light emitting layer 163 of the light emitting element 160, the second electrode 162 of the light emitting element 160, the encapsulation layer 139, the black matrix BM, and the filter layer are formed one by one on the first electrode layer AN. LG, light-transmitting layer 1310 and protective layer 1311 . The detailed preparation process of the above-mentioned film layer will not be repeated.
  • each film layer formed in the preparation process of the display substrate 2 can be referred to the introduction of FIG. 3 , and details are not repeated here.

Abstract

一种显示基板以及显示装置。该显示基板包括衬底基板和多条感测信号线。衬底基板包括显示区，显示区包括排布为阵列的多个重复单元，多个重复单元每个包括沿第一方向排列的透明区和像素区。多条感测信号线的相邻的两条之间设置有两排重复单元，两排重复单元沿第二方向延伸，多条感测信号线的每条和与其相邻且分别沿两排重复单元的多个子像素的子像素驱动电路连接，且配置为提供参考电压信号。该显示基板可以减小走线空间并提高显示的透光率。

Description

显示基板以及显示装置 技术领域
本公开的实施例涉及一种显示基板以及显示装置。
背景技术
在显示领域，目前市场对大尺寸高PPI(Pixels Per Inch)透明显示装置的需求日增，透明显示装置可用在车载、智能家居、商店橱窗等应用上，同时透明显示技术的开发可以有效的扩展OLED(Organic Light-Emitting Diode)的应用领域。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板和多条感测信号线。衬底基板包括显示区，其中，所述显示区包括排布为阵列的多个重复单元，所述多个重复单元每个包括沿所述第一方向排列的透明区和像素区，所述像素区包括多个子像素，所述多个子像素的每个包括子像素驱动电路和发光元件，所述发光元件位于所述子像素驱动电路的远离所述衬底基板的一侧，所述子像素驱动电路配置为驱动所述发光元件发光；多条感测信号线设置在所述衬底基板上并沿第二方向延伸，其中，所述多条感测信号线的相邻的两条之间设置有两排所述重复单元，所述两排重复单元沿所述第二方向延伸，所述多条感测信号线的每条和与其相邻且分别沿所述两排重复单元的多个子像素的子像素驱动电路连接，且配置为提供参考电压信号。
例如，本公开至少一实施例提供的显示基板还包括多条电源线，其中，所述多条电源线设置在所述衬底基板上并沿所述第二方向延伸，在所述第一方向上，所述多条电源线和所述多条感测信号线交替布置，所述多条感测信号线的每条和与其相邻的电源线之间设置有沿所述第二方向延伸的一排所述重复单元，所述多条电源线的相邻的两条之间设置有分别沿所述第二方向延伸的两排所述重复单元，所述多条电源线的每条和与其相邻且分别沿所述第二方向延伸的两排所述重复单元的多个子像素的子像素驱动电路连接，且配置为提供第一电源电压。
例如，本公开至少一实施例提供的显示基板还包括周边区、栅极驱动电路以及沿所述第一方向延伸的多条栅线，所述周边区至少部分围绕所述显示区，所述栅极驱动电路位于所述周边区，所述多条栅线与所述栅极驱动电路连接并与分别沿所述第一方向延伸的各排所述重复单元的像素区的子像素驱动电路连接，所述栅极驱动电路配置为逐一输出驱动分别沿所述第一方向延伸的各排所述重复单元的像素区的多个子像素工作的栅极扫描信号，所述多个重复单元排布为分别沿所述第一方向延伸的N排，所述栅极驱动电路包括N个级联的移位寄存器单元，第n级移位寄存器单元与第n排重复单元的像素区的子像素驱动电路连接，其中，1≤n≤N，N为大于等于2的整数。
例如，在本公开至少一实施例提供的显示基板中，每个所述像素区的多个子像素驱动电路沿所述第一方向排列，每个所述子像素驱动电路包括数据写入电路、驱动电路、电荷存储电路以及感测电路，所述驱动电路与第一节点、第二节点以及第三节点连接，所述第三节点还与第一电源电压端连接，所述第一电源电压端与所述电源线连接，所述驱动电路被配置为通过所述第三节点接收所述第一电源电压，并在所述第一节点的电平的控制下，控制流经所述发光元件的驱动电流；所述数据写入电路与所述第一节点连接，且被配置为接收所述栅极扫描信号作为扫描驱动信号，并且响应于所述扫描驱动信号将数据信号写入第一节点；所述电荷存储电路与所述第一节点以及所述第二节点连接，且被配置为存储写入的所述数据信号以及参考电压信号；所述感测电路与所述第二节点连接，配置为接收所述栅极扫描信号作为感测驱动信号，所述感测电路还与所述感测信号线连接且配置为接收所述参考电压信号，并且响应于所述感测驱动信号将所述参考电压信号写入所述驱动电路或从所述驱动电路读取感测电压信号；所述发光元件与所述第二节点以及第二电源电压端连接，且配置为通过所述第二电源电压端接收第二电源电压，并在所述驱动电流的驱动下发光。
例如，在本公开至少一实施例提供的显示基板中，所述多条栅线包括第一栅线和第二栅线，所述第一栅线与沿所述第一方向延伸的第M排重复单元的像素区的多个子像素驱动电路的数据写入电路、沿所述第一方向延伸的第M-1排重复单元的像素区的多个子像素驱动电路的感测电路以及第M个移位寄存器单元的输出端连接，以将第M个移位寄存器单元的输出端输出的栅极扫描信号输出至所述第M排重复单元的像素区的多个子像素驱动电路的数据写入电路作为扫描驱动信号、以及输出至所述第M-1排重复单元的像素区的多个子像素驱动电路的感测电路作为感测驱动信号，所述第二栅线与所述第M排重复单元的像素区的多个子像素驱动电路的感测电路、沿所述第一方向延伸的第M+1排重复单元的像素区的多个子像素驱动电路的数据写入电路以及第M+1个移位寄存器单元的输出端连接，以将所述第M+1个移位寄存器单元的输出端输出的栅极扫描信号输出至所述第M+1排重复单元的像素区的多个子像素驱动电路的数据写入电路作为扫描驱动信号、以及输出至所述第M排的重复单元的像素区的多个子像素驱动电路的感测电路作为所述感测驱动信号，其中，1＜M＜N，M为整数。
例如，在本公开至少一实施例提供的显示基板中，所述数据写入电路包括数据写入晶体管，所述驱动电路包括驱动晶体管，所述感测电路包括感测晶体管，所述数据写入晶体管的有源层、所述驱动晶体管的有源层以及所述感测晶体管的有源层沿所述第二方向延伸，以及所述衬底基板为柔性基板。
例如，本公开至少一实施例提供的显示基板还包括位于所述衬底基板上的半导体层、第一导电层、第二导电层、第二绝缘层以及第四绝缘层，所述第二导电层位于所述半导体层的远离所述衬底基板的一侧，所述第四绝缘层位于所述第二导电层与所述半导体层之间，所述第一导电层位于所述第二导电层远离所述衬底基板的一侧，所述第二绝缘层位于所述第二导电层和所述第一导电层之间，所述半导体层包括所述数据写入晶体管的 有源层、所述驱动晶体管的有源层以及所述感测晶体管的有源层，所述多条电源线的每条包括位于所述第二导电层的第一子线以及位于所述第一导电层的第二子线，所述第一子线包括多个沿所述第二方向延伸的第一走线段，多个所述第一走线段分别位于不同的重复单元中，所述第二子线穿过所述显示区，所述第二子线层叠在所述第一子线的远离所述衬底基板的一侧，且通过贯穿所述第二绝缘层的至少一个第一过孔与所述第一子线连接。
例如，在本公开至少一实施例提供的显示基板中，所述多条感测信号线的每条包括位于所述第二导电层的第三子线以及位于所述第一导电层的第四子线，所述第三子线包括多个沿所述第二方向延伸的第二走线段，多个所述第二走线段分布位于不同的重复单元中，所述第四子线穿过所述显示区，所述第四子线层叠在所述第三子线的远离所述衬底基板的一侧，且通过贯穿所述第二绝缘层的至少一个第二过孔与所述第三子线连接。
例如，在本公开至少一实施例提供的显示基板中，所述显示区包括沿第一方向相邻设置的第一重复单元和第二重复单元，所述第一重复单元的像素区与所述第二重复单元的透明区之间设置感测信号线，所述感测信号线与所述第一重复单元和所述第二重复单元的像素区的多个子像素驱动电路连接，所述第二重复单元的像素区的远离所述第二重复单元的透明区的一侧设置电源线，所述电源线与所述第二重复单元的像素区的多个子像素驱动电路连接，所述第一重复单元的透明区的远离所述第一重复单元的像素区的一侧设置另一电源线，所述另一电源线与所述第一重复单元的像素区的多个子像素驱动电路连接，所述第一重复单元的像素区的多个子像素驱动电路以及所述第二重复单元的像素区的多个子像素驱动电路分别包括在所述第一方向排列的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路，所述第一导电层包括沿所述第一方向延伸的第一转接电极、所述感测晶体管的第一极和第二极，所述第一转接电极的第一端与所述第一重复单元的第三子像素驱动电路的感测晶体管的第一极连接，所述第一转接电极的第二端与所述第二重复单元的第一子像素驱动电路的感测晶体管的第一极连接，其中，所述第一转接电极与所述感测信号线的第二子线交叉连接。
例如，在本公开至少一实施例提供的显示基板中，所述第二导电层包括沿所述第一方向延伸的第一连接走线，所述第一连接走线通过第三过孔的至少部分，与所述第一重复单元或所述第二重复单元的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路的感测晶体管的第一极连接，所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路的感测晶体管的第一极在所述衬底基板的板面上的正投影的至少部分与第一连接走线在所述衬底基板的板面上的正投影重叠。
例如，在本公开至少一实施例提供的显示基板中，所述感测晶体管的第一极包括沿所述第二方向连接的第一子部分以及第二子部分，所述第三过孔的部分配置为贯穿所述第二绝缘层和所述第四绝缘层以露出所述感测晶体管的有源层，所述第三过孔的另一部分配置为贯穿所述第二绝缘层以露出所述第一连接走线，所述第一子部分与所述感测晶体管的有源层接触，所述第二子部分与第一连接走线接触。
例如，在本公开至少一实施例提供的显示基板中，所述电荷存储电路包括存储电容，所述半导体层还包括存储电容的第一极板，所述第一导电层还包括存储电容的第二极板，所述感测晶体管的第二极与所述第二极板的靠近所述感测晶体管的一端连接，且所述感测晶体管的第二极与所述第二极板一体设置。
例如，在本公开至少一实施例提供的显示基板中，在所述第二方向上，所述数据写入晶体管和所述驱动晶体管位于所述存储电容的远离所述感测晶体管的一侧，所述驱动晶体管位于所述数据写入晶体管和所述存储电容之间，所述第一导电层还包括所述数据写入晶体管的第一极和第二极、所述驱动晶体管的第一极和第二极、第二转接电极以及第三转接电极，所述第二转接电极以及所述第三转接电极分别包括所述第三节点，所述驱动晶体管的第二极位于所述驱动晶体管的远离所述存储电容的一侧，所述第二转接电极的一端与所述第二重复单元的第三子像素驱动电路的驱动晶体管的第二电极连接，以及所述第二转接电极的另一端与靠近所述第二重复单元的第三子像素驱动电路的电源线连接，第三转接电极的一端与所述第一重复单元的第一子像素驱动电路的驱动晶体管的第二极连接，以及所述第三转接电极的另一端与靠近所述第一重复单元的透明区的电源线连接。
例如，在本公开至少一实施例提供的显示基板中，所述第二导电层包括沿所述第一方向延伸的第二连接走线，所述第二连接走线通过第四过孔的至少部分，与所述第一重复单元或所述第二重复单元的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路的驱动晶体管的第二极连接，所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路的驱动晶体管的第二极在所述衬底基板的板面上的正投影的至少部分，与所述第二连接走线在所述衬底基板的板面上的正投影重叠。
例如，在本公开至少一实施例提供的显示基板中，所述驱动晶体管的第一极与所述存储电容的第二极板的远离所述感测晶体管的一端连接，且所述驱动晶体管的第一极与所述第二极板一体设置，所述存储电容的第一极板与所述驱动晶体管的有源层连接且一体设置。
例如，在本公开至少一实施例提供的显示基板中，所述存储电容的第一极板和第二极板包括沿所述第二方向延伸的条状，所述显示基板还包括滤光层，所述滤光层位于所述发光元件的远离所述衬底基板的一侧，所述滤光层包括第一子像素滤光区、第二子像素滤光区以及第三子像素滤光区，在每个所述重复单元中，所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区沿所述第二方向依次排列，所述第二子像素滤光区位于所述第一子像素滤光区和所述第三子像素滤光区之间，所述第一子像素滤光区与所述像素区的多个子像素驱动电路的感测晶体管的至少部分，以及存储电容的靠近所述感测晶体管的部分在所述衬底基板的板面上的正投影重叠，所述第三子像素滤光区与所述像素区的多个子像素驱动电路的数据写入晶体管和驱动晶体管的至少部分，以及存储电容的靠近所述驱动晶体管的部分在所述衬底基板的板面上的正投影重叠，所述第二子像素滤光区与所述像素区的多个子像素驱动电路的存储电容的靠近其在第一方 向上中间的部分在所述衬底基板的板面上的正投影重叠，
例如，本公开至少一实施例提供的显示基板还包括第三绝缘层以及像素限定层，所述第三绝缘层位于所述第一导电层的远离所述衬底基板的一侧，所述发光元件位于所述第三绝缘层的远离所述衬底基板的一侧，所述多个子像素的每个的发光元件包括第一电极、第二电极以及位于所述第一电极和所述第二电极之间的发光层，所述像素限定层配置为限定所述发光元件的发光区，每个所述重复单元的多个发光元件包括第一发光元件、第二发光元件以及第三发光元件，所述第一发光元件、所述第二发光元件以及所述第三发光元件分别与所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区对应设置，所述显示基板还包括至少贯穿所述第三绝缘层的第五过孔、第六过孔以及第七过孔，所述第五过孔、所述第六过孔以及所述第七过孔配置为露出所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路，所述第一发光元件的第一电极通过所述第五过孔与所述第一子像素驱动电路连接，所述第二发光元件的第一电极通过所述第六过孔与所述第二子像素驱动电路连接，所述第三发光元件的第一电极通过所述第七过孔与所述第三子像素驱动电路连接。
例如，在本公开至少一实施例提供的显示基板中，所述第五过孔在所述衬底基板的板面上的正投影与所述第一发光元件的发光区在所述衬底基板的板面上的正投影不重叠，所述第六过孔在所述衬底基板的板面上的正投影与所述第二发光元件的发光区在所述衬底基板的板面上的正投影不重叠，所述第七过孔在所述衬底基板的板面上的正投影与所述第三发光元件的发光区在所述衬底基板的板面上的正投影不重叠。
例如，本公开至少一实施例提供的显示基板还包括黑矩阵，在每个所述重复单元的像素区，所述黑矩阵包括多条沿所述第一方向延展的遮光线条，多条所述遮光线条在所述衬底基板的板面上的正投影的至少部分，与所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区之间在所述第二方向上的间隔重叠，所述第五过孔以及所述第六过孔在所述衬底基板的板面上的正投影靠近所述第一子像素滤光区和所述第二子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且位于所述第一子像素滤光区和所述第二子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影的两侧，所述第七过孔在所述衬底基板的板面上的正投影靠近所述第二子像素滤光区和所述第三子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且与所述第三子像素滤光区重叠。
例如，本公开至少一实施例提供的显示基板还包括黑矩阵，在每个所述重复单元的像素区，所述黑矩阵包括多条沿所述第一方向延展的遮光线条，多条所述遮光线条在所述衬底基板的板面上的正投影的至少部分，与所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区之间在所述第二方向上的间隔重叠，所述第五过孔在所述衬底基板的板面上的正投影，与所述第一子像素驱动电路的存储电容的第一极板的与所述感测晶体管的第二极连接的一端，在所述衬底基板的板面上的正投影重叠，所述第六过孔在所述衬底基板的板面上的正投影靠近所述第一子像素滤光区和所述第二子像 素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且与所述第二子像素滤光区重叠，所述第七过孔在所述衬底基板的板面上的正投影靠近所述第二子像素滤光区和所述第三子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且与所述第三子像素滤光区重叠。
例如，本公开至少一实施例提供的显示基板还包括多条数据线，所述多条数据线沿第二方向延伸，所述多条数据线包括位于每个重复单元的第一数据线、第二数据线以及第三数据线，所述第一数据线和所述第二数据线位于所述第一子像素驱动电路与所述第二子像素驱动电路之间，所述第三数据线位于所述第二子像素驱动电路和所述第三子像素驱动电路之间，所述第一数据线、所述第二数据线以及所述第三数据线分别与所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路电连接，以提供数据信号，所述第一导电层还包括沿所述第一方向的第四转接电极、第五转接电极以及第六转接电极，所述第四转接电极连接所述第一数据线以及所述第一子像素驱动电路的数据写入晶体管的第二极，所述第五转接电极连接第二数据线以及所述第二子像素驱动电路的数据写入晶体管的第二极，所述第六转接电极连接所述第三数据线以及所述第三子像素驱动电路的数据写入晶体管的第二极。
例如，在本公开至少一实施例提供的显示基板中，所述第一栅线和所述第二栅线位于第二导电层，所述第一栅线靠近所述第一重复单元和所述第二重复单元的感测晶体管，所述第二栅线靠近所述第一重复单元和所述第二重复单元的数据写入晶体管，所述第一栅线包括折线部，所述折线部包括沿所述第一方向的第一折线部、分别与所述第一折线部两端连接的沿所述第二方向的第二折线部以及第三折线部，所述第一折线部、所述第二折线部以及所述第三折线部绕过所述第一连接走线，所述第一折线部在所述衬底基板的板面上的正投影，与所述第一重复单元的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路的感测晶体管的有源层在所述衬底基板的板面上的正投影交叠，所述交叠部分形成所述感测晶体管的栅极。
例如，在本公开至少一实施例提供的显示基板中，在所述第二方向上，所述第一栅线与所述第一连接走线并列走线的部分位于所述第一连接走线的靠近所述第二重复单元的透明区的一侧。
例如，在本公开至少一实施例提供的显示基板中，所述第二导电层还包括第三连接走线、第四连接走线以及第五连接走线，所述第三连接走线、所述第四连接走线以及所述第五连接走线呈“L”形折线，所述第四连接走线和所述第五连接走线的弯折方向相同，所述第三连接走线的弯折方向与所述第四连接走线和所述第五连接走线的弯折方向相对，所述第三连接走线与所述第二栅线以及所述第一子像素驱动电路的数据写入晶体管的栅极连接，所述第四连接走线与所述第二栅线以及所述第二子像素驱动电路的数据写入晶体管的栅极连接，所述第五连接走线与所述第二栅线以及所述第三子像素驱动电路的数据写入晶体管的栅极连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一导电层包括沿所述第二 方向的第七转接电极、第八转接电极以及第九转接电极，所述第七转接电极、所述第八转接电极以及所述第九转接电极在所述衬底基板的板面上的正投影与所述第二连接走线在所述衬底基板的板面上的正投影交叠，所述第七转接电极的第一端通过贯穿所述第二绝缘层的第八过孔的至少部分，与所述第一子像素驱动电路的驱动晶体管的栅极连接，所述第七转接电极的第二端与所述第一子像素驱动电路的数据写入晶体管的第一极连接，所述第八转接电极的第一端通过贯穿所述第二绝缘层的第九过孔的至少部分，与所述第二子像素驱动电路的驱动晶体管的栅极连接，所述第八转接电极的第二端与所述第二子像素驱动电路的数据写入晶体管的第一极连接，所述第九转接电极的第一端通过贯穿所述第二绝缘层的第十过孔的至少部分，与所述第三子像素驱动电路的驱动晶体管的栅极连接，所述第九转接电极的第二端与所述第三子像素驱动电路的数据写入晶体管的第一极连接。
本公开至少一实施例还提供一种显示装置，包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种显示基板的示意图；
图2为本公开至少一实施例提供的一种显示基板的平面布局示意图；
图3为图2所示显示基板的部分结构的截面示意图；
图4为图3中电极搭接区的平面布局示意图；
图5为本公开至少一实施例提供的一种显示基板的光学仿真模拟的示意图；
图6为本公开至少一实施例提供的一种显示基板的子像素驱动电路和发光元件的布局示意图；
图7为本公开至少一实施例提供的一种显示基板的黑矩阵和滤光层的布局示意图；
图8A为本公开至少一实施例提供的子像素驱动电路的电路图；
图8B为本公开至少一实施例提供的子像素单元电路的子像素驱动电路与寄存器单元电路连接的示意图；
图9A为本公开至少一实施例提供的遮光层的平面图；
图9B为本公开至少一实施例提供的第一绝缘层的平面图；
图9C为本公开至少一实施例提供的缓冲层的平面图；
图9D为本公开至少一实施例提供的半导体层的平面图；
图9E为本公开至少一实施例提供的第二导电层的布局图；
图9F为本公开至少一实施例提供的层间绝缘层的平面图；
图9G为本公开至少一实施例提供的第一导电层的平面图；
图10为图9A至图9B层叠后的布局图；
图11A为图10中A1区域的放大图；
图11B为图11A中沿线B1-B2的截面示意图；
图11C为图10中A2区域的放大图；
图12A为本公开至少一实施例提供的钝化层的平面图；
图12B为本公开至少一实施例提供的第三绝缘层的平面图；
图12C为本公开至少一实施例提供的第一电极层的第一子层的平面图；
图12D为本公开至少一实施例提供的第一电极层的第三子层的平面图；
图12E为本公开至少一实施例提供的像素限定层的平面图；
图13为本公开至少一实施例提供的一种显示装置的示意图；以及
图14A-图14F为本公开至少一实施例提供的一种显示装置的制备过程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本发明实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本发明实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
目前市面上常见的大尺寸透明显示分辨率约在40PPI左右，较少有高PPI产品的出现。现今大尺寸高PPI透明显示装置的一个瓶颈在于，随着PPI增大，像素尺寸越小，金属走线密度越大，而走线密度不能做的过大。并且，由于顶发射白光OLED使用电阻较大的透明阴极，必须增加辅助阴极以降低走线电阻降(IR Drop)，所以常规辅助阴极也需占用透明显示装置的透明区面积。以上原因均导致透明区面积越小，从而影响透过率的同时，更容易发生小孔衍射效应，反映在实际体验中即透过透明显示装置看到的物体有重影现象，严重影响了用户体验。如何在高PPI的前提下，尽可能的增大透明区面积，是目前透明显示装置设计的关键。
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板和遮光层。衬底基板包括显示区，显示区包括排布为阵列的多个重复单元，多个重复单元每个包括沿第一方向排列的透明区和像素区，像素区包括多个子像素，多个子像素的每个包括子像素驱动电路和发光元件，发光元件位于所述子像素驱动电路的远离衬底基板的一侧，子像素驱动电路配置为驱动发光元件发光，发光元件包括第一电极、第二电极以及位于第一电极和第二电极之间的发光层。遮光层设置在衬底基板上且位于子像素驱动电路的靠近衬底基板的一侧，遮光层在衬底基板的板面上的正投影的至少部分与子像素驱动电路在衬底基板的板面上的正投影重叠，遮光层与第二电极连接，以复用为第二电极的辅助电极。
本公开至少一实施例还提供一种对应于上述显示基板的显示装置。
本公开上述实施例提供的显示基板，通过将遮光层用于子像素驱动电路的遮光的同时，还与第二电极连接，以复用为第二电极的辅助电极，从而可以提高显示基板的透明区的空间，并提高显示基板的透光率，同时，由于遮光层复用的辅助电极的电阻更小，第二电极的电阻的增加的效果更加明显(即降低电阻降的效果更加明显)。
下面结合附图对本公开的实施例及其一些示例进行详细说明。
图1为本公开至少一实施例提供的一种显示基板的示意图。图2为本公开至少一实施例提供的一种显示基板的平面布局示意图。图3为图2所示显示基板的部分结构的截面示意图。
例如，如图1所示，显示基板1包括衬底基板10。衬底基板10包括显示区101。显示区101包括排布为阵列的多个重复单元C1。多个重复单元C1沿第一方向X和第二方向Y排布为多行多排，例如，排布为沿第一方向X延伸的第1行至第N行，以及沿第二方向Y延伸的第1排和第F排。多个重复单元C1每个包括沿第一方向X排列的透明区TM10和像素区P10。像素区P10包括多个子像素。例如，在本公开实施例中以像素区P10包括三个子像素为例。
例如，该衬底基板10可以为柔性基板或刚性基板。衬底基板10可以采用例如玻璃、塑料、石英或其他适合的材料，本公开的实施例对此不作限制。
例如，如图1所示，显示基板1包括多条电源线VDD10和多条感测线SES10。多条电源线VDD10和多条感测线SES10设置在衬底基板10上并沿第二方向Y延伸。多条电源线VDD10和多条感测线SES10分别与多个子像素连接并延伸至显示基板1的邦定区103。电源线VDD10与对应在第二方向Y上延伸的一列子像素连接并提供第二电源电压信号。感测线SES10与对应在第二方向Y上延伸的一列子像素连接并提供参考电压信号。显示基板还包括位于周边区102的栅极驱动电路13和多条栅线G10，多条栅线G10沿第一方向X延伸。栅极驱动电路13被配置为逐行输出驱动多个子像素单元电路16工作的栅极扫描信号。栅线G10与栅极驱动电路13和对应在第一方向X上延伸的一行子像素连接并子像素工作的栅极扫描信号。
例如，如图2和图3所示，多个子像素的每个包括子像素驱动电路1601(例如，第 一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163)和发光元件160。发光元件160位于子像素驱动电路1601的远离衬底基板10的一侧。子像素驱动电路1601配置为驱动发光元件160发光。发光元件160包括第一电极161、第二电极162以及位于第一电极161和第二电极162之间的发光层163。
例如，在一些实施例中，各个子像素驱动电路1601可以包括本领域内的具有7T1C、8T2C、4T1C或3T1C等电路结构的像素电路，本公开的实施例以包括3T1C电路结构的像素电路为例进行介绍，本公开的实施例对此不作限制。
例如，如图2和图3所示，遮光层131设置在衬底基板10上且位于子像素驱动电路1601的靠近衬底基板10的一侧，以阻挡外部光线的照射。遮光层131在衬底基板10的板面(例如为衬底基板10的上表面)上的正投影的至少部分与子像素驱动电路1601在衬底基板10的板面上的正投影重叠。遮光层131与第二电极162连接，以复用为第二电极162的辅助电极。遮光层131在衬底基板10的板面上的正投影与重复单元C1的像素区P10重叠，而不与重复单元C1的透明区TM10重叠，将遮光层131对像素区P10进行遮光的同时复用为第二电极162的辅助电极，从而可以提高显示基板1的透明区TM10的空间，并提高显示基板1的透光率，同时，由于遮光层131复用的辅助电极的电阻更小，第二电极162的电阻的增加的效果更加明显(即降低电阻降的效果更加明显)。
例如，遮光层131的材料可以由金属材料制成，例如，金属材料包括银、铝、铬、铜、钼、钛、铝钕合金、铜钼合金、钼钽合金、钼钕合金或任何它们的任意组合。
例如，如图2和图3所示，像素区P10包括电极搭接区12，电极搭接区12位于像素区P10的靠近透明区TM10的一侧。即，在一个重复单元C1中，电极搭接区12位于像素区P10和透明区TM10之间。电极搭接区12在衬底基板10的板面上的正投影与遮光层131在衬底基板10的板面上的正投影至少部分重合，例如，部分重合。电极搭接区12包括第一复合孔结构以及第一复合搭接电极。第一复合孔结构配置为露出遮光层131，例如，第一复合孔结构包括第一搭接孔F11和第二搭接孔F12。第一复合搭接电极配置为连接第二电极162和遮光层131，例如，第一复合搭接电极包括第一搭接电极FD11和第二搭接电极FD12。遮光层131通过第一复合搭接电极和第一复合孔结构与第二电极162连接，以复用为第二电极162的辅助电极。
图4为图3中电极搭接区的平面布局示意图。
例如，如图3和图4所示，第一复合搭接电极包括第一搭接电极FD11和第二搭接电极FD12。第一搭接电极FD11位于第二搭接电极FD11靠近衬底基板11的一侧。第一复合孔结构包括第一搭接孔FK11和第二搭接孔FK12，第一搭接孔FK11位于第二搭接孔FK12靠近衬底基板10的一侧。第一搭接电极FD11通过第一搭接孔FK11与遮光层131连接，第二搭接电极FD12通过第二搭接孔FK12与第一搭接电极FD11连接。第二搭接电极FK12还与第二电极162连接。例如，第二搭接电极FK12还与第二电极162可以间接连接。第二搭接电极FK12还与第二电极162之间间隔发光层163，也即第二搭接电极FK12(例如部分)通过发光层163与第二电极162连接。
例如，在其它实施例中，第二搭接电极FK12还与第二电极162可以直接连接。
图8A为本公开至少一实施例提供的子像素驱动电路的电路图。
例如，如图8A所示，子像素驱动电路1601可以采用本领域内的具有3T1C电路结构的像素电路。例如，子像素驱动电路1601包括数据写入晶体管T1、驱动晶体管T2、感测晶体管T3以及存储电容CST。
例如，在一些实施例中，如图3所示，显示基板还包括第一绝缘层132(例如阻挡层)、第二绝缘层134(例如层间绝缘层)、第一导电层SD、第三绝缘层136(例如平坦化层)以及第一电极层AN。第一绝缘层132以提供用于形成子像素驱动电路1601的平坦表面，并且可以避免衬底基板10中可能存在的杂质扩散到子像素驱动电路或栅极驱动电路13中而不利影响显示基板的性能，第一绝缘层132的厚度还可以避免遮光层131与其他膜层产生寄生电容。
例如，第一绝缘层132的材料可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它适合的材料。
例如，第一绝缘层132位于遮光层131的远离衬底基板10的一侧。第二绝缘层134位于第一绝缘层132远离衬底基板10的一侧，第一导电层SD位于第二绝缘层134远离衬底基板10的一侧，第三绝缘层136位于第一导电层SD远离衬底基板10的一侧，第一电极层AN位于第三绝缘层136远离衬底基板10的一侧。例如，第一电极层AN为发光元件160的第一电极162所在的膜层，第一导电层SD为驱动晶体管T2的第一极TSD22(例如源极)和第二极TSD21(例如漏极)所在的膜层。
例如，第一绝缘层132和第二绝缘层134的材料，例如可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它适合的材料。
例如，第一导电层SD的材料，例如可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。本公开的实施例对各功能层的材料不做具体限定。
例如，第三绝缘层136的材料，例如可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，也可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，本公开的实施例对此不做限定。
例如，在一些实施例中，如图3和图4所示，第一搭接孔FK11包括贯穿第一绝缘层132的第一搭接子孔FK111和贯穿第二绝缘层134的第二搭接子孔FK112。第二搭接子孔FK112套设在第一搭接子孔FK111中，即第二搭接子孔FK112在衬底基板10的板面上的正投影位于第一搭接子孔FK111在衬底基板10的板面上的正投中。第一搭接子孔FK111和第二搭接子孔FK112设置为露出遮光层131。第一搭接电极FD11位于第二绝缘层134的远离衬底基板10的一侧。第二搭接孔FK12贯第三绝缘层136，以露出第一搭接电极FD11。第一导电层SD包括所述第一搭接电极FD11。第一电极层AN包括第二搭接电极FD12以及发光元件160的第一电极161。第一电极161和第二搭接电极FD12同层且同材料设置，并且第一电极161和第二搭接电极FD12相互间隔。也就是说，虽然 第一电极161和第二搭接电极FD12是同层且同材料设置，例如经过相同的工艺过程制备，但是第一电极161和第二搭接电极FD12之间是断开的或者说是不连通的。第二搭接电极FD12配置为用于与发光元件的第二电极162和第一搭接电极FD11连接。第一电极161和第二搭接电极FD12在同一膜层制备，可以减少构图工艺以及显示基板的厚度。
例如，在一些实施例中，如图3和图4所示，显示基板还包括缓冲层133。缓冲层133位于第一绝缘层132和第二绝缘层134之间，第一搭接孔FK11还包括第三搭接子孔FK113。第三搭接子孔FK113套设在第一搭接子孔FK111和第二搭接子孔FK112之间，第三搭接子孔FK113贯穿缓冲层133且设置为露出遮光层131。第三搭接子孔FK113在衬底基板10的板面上的正投影位于第一搭接子孔FK111在衬底基板10的板面上的正投影中。第一搭接孔FK11为第三搭接子孔FK113、第一搭接子孔FK111和第二搭接子孔FK112形成的套孔。
例如，缓冲层的材料，例如可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它合适的材料。
例如，在其它实施例中，可以在显示基板上形成第二绝缘层134之后，先刻蚀形成第二搭接子孔FK112，再刻蚀形成第三搭接子孔FK113，此时，第二搭接子孔FK112和第三搭接子孔FK113的尺寸基本相同。第二绝缘层134将不与第三搭接子孔FK113接触。
例如，如图3和图4所示，显示基板还包括括钝化层135。钝化层135位于第三绝缘层136和第一导电层SD(第一搭接电极FD11)之间。第二搭接孔FK12还贯穿钝化层135。钝化层135可以保护第一导电层SD不被水汽腐蚀。
例如，钝化层135的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的保护子像素驱动电路不被水汽腐蚀。
例如，在一些实施例中，如图4所示，第一搭接子孔FK111和第二搭接子孔FK112在第一方向X上的宽度可以为约3.5-4.5微米，例如为约4微米。例如，第三搭接子孔FK113在第一方向X上的宽度可以为约7.5-8.5微米，例如为约8微米。例如，第二搭接孔FK12在第一方向X上的宽度可以为约6.5-7.5微米，例如为约7微米。例如，第一搭接子孔FK111和第二搭接子孔FK112的尺寸可以相等也可以不相等。第一搭接子孔FK111、第二搭接子孔FK112、第三搭接子孔FK113以及第二搭接孔FK12的尺寸由显示基板在制备工艺进行选择，本公开实施例不以此为限。
需要说明的是，在本公开实施例中，“约”表示可以在其所取数值的例如±15％或±5％范围内波动。
例如，在一些实施例中，如图3所示，第一电极层AN包括第一层AN1、第二层AN2以及第三层AN3。第一层AN1位于第三绝缘层136远离衬底基板10的一侧，第三层AN3位于第一层AN1远离衬底基板10的一侧，第二层AN2位于第一层AN1和第三层AN3之间。发光元件160的第一电极161为与第一层AN1、第二层AN2以及第三层AN3分别同层设置的三层结构且第一电极161的截面为工字形。第二电极162例如可以设置在 部分或整个显示区101中，从而在制备工艺中可以整面形成。
例如，发光元件的第一电极161可以包括反射层，发光元件的第二电极162可以包括透明层或半透明层。由此，第一电极161可以反射从发光层163发射的光，该部分光通过第二电极162发射到外界环境中，从而可以提供光出射率。当第二电极162包括半透射层时，由第一电极161反射的一些光通过第二电极162再次反射，因此第一电极161和第二电极162形成共振结构，从而可以改善光出射效率。
例如，第一层AN1和第二层AN2的材料可以包括至少一种透明导电氧化物材料，例如氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。例如，第三层163的材料可以包括合金材料，例如AlNd等。
例如，发光层163可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。在本公开实施例中，以发光层163发白光为例。
例如，第二电极162可以包括各种导电材料。例如，第二电极162可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。例如，第二电极162可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，在一些实施例中，如图3所示，第二搭接电极FD12包括彼此层叠的第一子电极层FD121、第二子电极层FD122以及第三子电极层FD123。第一子电极层FD121位于第三子电极层FD123的靠近衬底基板10的一侧，第二子电极层FD122位于第一子电极层FD121和第三子电极层FD123之间。第一子电极层FD121与第一电极层AN的第一层AN1同层且同材料设置。第二子电极层FD122与第一电极层AN的第二层AN2同层且同材料设置。第三子电极层FD123与第一电极层AN的第三层AN3同层且同材料设置。在平行于衬底基板10的板面的方向上，第一子电极层FD121周向的至少一侧突出于第二子电极层FD122。例如，如图中所示，第一子电极层FD121周向突出于第二子电极层FD122。第二子电极层FD122在衬底基板10的板面上的正投影位于第一子子电极层FD121在衬底基板10的板面上的正投影中。第三子电极层FD123在衬底基板10的板面上的正投影位于第一子电极层FD121在衬底基板10的板面上的正投影中，第一子电极层FD121在衬底基板10的板面上的投影面积大于第三子电极层FD123在衬底基板10的板面上的投影面积。即，第一子电极层FD121在衬底基板10的板面上的正投影的投影面积最大，第三子电极层FD123在衬底基板10的板面上的正投影的投影面积次之，第二子电极层FD122在衬底基板10的板面上的正投影的投影面积最小。由此，第一子电极层FD121突出于第二子电极层FD122的部分可以用于与第二电极162的连接。
例如，在一些实施例中，如图3所示，第二子电极层FD122在衬底基板10的板面 上的投影面积，分别小于第一子电极层FD121和第三子电极层FD123在衬底基板10的板面上的投影面积。第一子电极层FD121、第二子电极层FD122以及第三子电极层FD123的截面呈工字形，以及第一子电极层FD121通过第二搭接孔FK12与第一搭接电极FD11连接。
例如，在一些实施例中，如图4所示，第一子电极层FD121在第一方向X上的宽度D3可以为约28-30微米，例如为约29微米。第一子电极层FD121在第二方向Y上的长度D4可以为约30-31微米，例如为约31.5微米。第三子电极层FD123(或第二子电极层FD122)在第一方向X上与第一子电极层FD121的边缘的距离D1，例如可以约为5.5-6.5微米，例如为约6微米。
例如，在一些实施例中，显示基板10还包括像素限定层138。像素限定层138位于第一电极161的远离衬底基板10的一侧。像素限定层138包括多个开口，多个开口中的部分限定子像素，并对应发光元件160的发光区。例如发光层163也整面设置在第二电极162的靠近衬底基板10的一侧。在电极搭接区12，像素限定层138还具有开口，且像素限定层138部分覆盖第一子电极层FD121的突出于第二子电极层FD122的区域。例如，像素限定层138延伸到第一子电极层FD121的突出于第二子电极层FD122的区域并覆盖第一子电极层FD121的边缘。由此，像素限定层138可以避免第一子电极层FD121由于边角部分有毛刺导致发光层163放电造成工艺不良。
例如，在一些实施例中，如图4所示，像素限定层138的边缘在第二方向Y上与第一子电极层FD121的边缘的距离D2，例如可以约为2.5-3.5微米，例如为约3微米。
例如，在一些实施例中，如图3所示，发光元件160的发光层163层叠在像素限定层138远离衬底基板10的一侧。发光层163包括位于电极搭接区12的第一部分1631和第二部分1632。第一部分1631覆盖第一子电极层FD121的突出于第二子电极层FD122的区域的至少部分，第一部分1631与第一子电极层FD121接触。第二部分1632位于第三子电极层FD123的远离衬底基板10的一侧。
例如，在一些实施例中，如图3所示，发光元件160的第二电极162包括位于电极搭接区12的第一电极部分1621和第二电极部分1622。第一电极部分1621位于第一子电极层FD121的突出于第二子电极层FD122的区域，且第一电极部分1621与第一子电极层FD121和第二子电极层FD122接触。第二电极部分FD122位于发光层163的第二部分1632的远离衬底基板10的一侧。发光层163的第一部分1631在衬底基板10的板面上的正投影，与第一电极部分1621在衬底基板10的板面上的正投影的至少部分重叠。也就是说，在第一子电极层FD121的突出于第二子电极层FD122的区域，第一电极部分1621与发光层163的第一部分1631以及第一子电极层FD121的上表面(平行于衬底基板10的板面)以及第二子电极层FD122的侧表面(垂直于衬底基板10的板面)接触。
例如，在一些实施例中，显示基板10还包括半导体层ACT、第四绝缘层137(例如栅绝缘层)以及第二导电层GATE。半导体层ACT位于缓冲层133的远离衬底基板10的一侧。第四绝缘层137位于半导体层ACT远离衬底基板10的一侧。第二导电层GATE 位于第二绝缘层134与第四绝缘层137之间。半导体层ACT包括驱动晶体管T2的有源层TA2。第二导电层GATE包括驱动晶体管T2的栅极TG2，第一导电层SD包括驱动晶体管T2的第一极TSD21和第二极TSD22。第二导电层有源层TA2与第一极TSD21对应的源极区和与第二极TSD22对应的漏极区。半导体层ACT还包括存储电容CST的第一极板CST1，第一导电层SD还包括存储电容CST的第二极板CST2。第一极板CST1和第二极板CST2之间间隔第二绝缘层134。例如，第二极板CST2与驱动晶体管T2的第一极TSD21连接。例如，发光元件160的第一电极161通过贯穿钝化层135和第三绝缘层136的过孔与第一导电层连接。例如，发光元件160的第一电极161的与第一电极层AN的第一子层AN1同层的部分通过贯穿钝化层135和第三绝缘层136的过孔与驱动晶体管T2的第一极TSD21连接。例如，发光元件160的第一电极161的与第一电极层AN的第一子层AN1同层的部分与第二极板CST2连接，以与驱动晶体管T2的第一极TSD21连接。
例如，在其它实施例中，例如，发光元件160的第一电极161的与第一电极层AN的第一子层AN1同层的部分直接与驱动晶体管T2的第一极TSD21连接。也就是说，在垂直于衬底基板10的板面的截面图中，驱动晶体管T2的第一极TSD21与存储电容CST的第一极板1间隔设置。
需要说明的是，子像素驱动电路160的其它晶体管，例如数据写入晶体管T1、驱动晶体管T2的截面结构与感测晶体管T3的截面结构可以相同，这里不再赘述。
需要说明的是，在本公开实施例中，第一极表示晶体管的源极，第二极表示晶体管的漏极，也可以对以上进行互换，本公开实施例不以此为限。
例如，半导体层ACT的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。需要说明的是，上述的源极区以及漏极区可为掺杂有n型杂质或p型杂质的区域，本公开的实施例对此不作限制。
例如，第四绝缘层137的材料可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它适合的材料。
例如，第二导电层GATE的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。
例如，在一些实施例中，显示基板10还包括封装层139。封装层139设置在发光元件160的远离衬底基板10的一侧。封装层139将发光元件160密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件160的劣化。封装层139可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。封装层139包括至少一层封装子层。例如，封装层139可以包括依次设置的第一无机封装层、第一有机封装层、第二无机封装层。
例如，该封装层139的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，在一些实施例中，如图3所示，显示基板1还包括滤光层LG以及黑矩阵BM。滤光层LG以及黑矩阵BM位于发光元件160的远离衬底基板10的一侧，即位于封装层139上。滤光层LG以及黑矩阵BM可以部分层叠，在滤光层LG以及黑矩阵BM的层叠部分，黑矩阵BM位于滤光层LG的靠近衬底基板10的一侧。
图6为本公开至少一实施例提供的一种显示基板的子像素驱动电路和发光元件的布局示意图。图7为本公开至少一实施例提供的一种显示基板的黑矩阵和滤光层的布局示意图。
例如，在一些实施例中，结合图6和图7所示，在每个像素区P10，黑矩阵BM包括多条沿第一方向X延展的遮光线条(例如图7所示的BM1/BM2)。滤光层LG包括第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3。第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3沿与第二方向Y彼此间隔排列。多条遮光线条在衬底基板10的板面上的正投影的至少部分，与第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3之间在第二方向Y上的间隔重叠。例如，多条遮光线条的遮光线条BM1与在衬底基板10的板面上的正投影的至少部分与第一子像素滤光区LG1和第二子像素率滤光区LG2在第二方向Y上的间隔重叠。例如，多条遮光线条的遮光线条BM2与在衬底基板10的板面上的正投影的至少部分与第二子像素率滤光区LG2和第三子像素滤光区LG3在第二方向Y上的间隔重叠。例如，第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3分别与像素区P10的子像素的发光元件对应。除多条遮光线条之外，在滤光层LG的靠近透光区TM10的一侧，黑矩阵BM不包括沿不沿第一方向X延伸的其它遮光线条。也就是说，黑矩阵BM不包括设置在透光区TM10和像素区P10之间沿其它方向延伸的遮光线条，只包括图7中所示的沿第一方向延伸设置在第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3之间在第二方向Y上的间隔区域的遮光线条。由此，可以增加透光区TM10的面积以增加显示基板的透光率。
例如，在本公开中所涉及的第一方向X与所述第二方向Y的夹角在70°到90°之间，并包括70°和90°。例如，第一方向X与所述第二方向Y的夹角为70°、90°或80°等，可根据实际情况设定，本公开的实施例对此不作限制。例如，第一方向X与所述第二方向Y的夹角还可以为75°、85°等。
例如，滤光层的材料可以包括掺杂着色剂的树脂材料，例如着色剂可采用染料或颜料，使得树脂材料例如高分子树脂材料具有颜色。例如，黑矩阵BM的材料可以包括不透光的黑色树脂材料等。
例如，在一些实施例中，第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3分别为红光区、绿光区以及蓝光区，即分别透射红光、绿光和蓝光。第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3所透光光的颜色的顺序可以互换，本公开实施例不以此为限。
例如，在一些实施例中，如图2所示，在第一方向X上，在像素区P10的靠近透光区TM10的一侧，第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3在衬底基板10的板面上的正投影，与像素限定层138在衬底基板10的板面上的正投影部分重叠。也就是说，在垂直于衬底基板10的板面的方向上，在靠近透光区TM10的一侧，第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3的超出像素限定层138的边缘，延伸到像素限定层138的上方。如图3所示，第一子像素滤光区LG1、第二子像素率滤光区LG2或第三子像素滤光区LG3在衬底基板10的板面上的正投影，与像素限定层138在衬底基板10的板面上的重叠部分的长度为D5。由此，在不保证占用透明区的前提下，还同时保证不同角度下，可以减少发光元件的发光区的漏光，以减少显示基板的色衰减。
图5为本公开至少一实施例提供的一种显示基板的光学仿真模拟的示意图。
例如，在一些实施例中，第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3与像素限定层138在垂直衬底基板10的方向上重叠的部分，沿第一方向X的尺寸范围，例如约为5微米至7微米，例如约为6微米，由此，可以取得较好的显示效果。
例如，如图5所示，以滤光区在第一方向X上超出像素限定层138为例，做第二方向Y上的光学仿真，以选择滤光区超出像素限定层138的合适的取值范围。图5中滤光层超出像素限定层138的在第一方向X上的长度D5(还如图3所示)的尺寸范围，例如约为5微米至7微米，例如约为6微米，此时，防止漏光的效果较好，可以满足显示效果的要求。当长度D5的值取得越大，防止漏光的效果较好，在设计尺寸允许的情况下，还可以选择更大的长度D5。时，需要说明的是图5中的像素限定层138示出的是开口区(即，像素限定层138反相示出，标注的区域为被挖去的区域)。
例如，在一些实施例中，如图3所示，显示基板还包括透光层1310和保护层1311。透光层1310设置在滤光层LG的远离衬底基板10的一侧。保护层1311设置在透光层1310的远离衬底基板10的一侧。例如，保护层1311可以用作盖板，该保护层1311的材料可以包括柔性材料，例如透明聚酰亚胺(CPI，Colorless Polyimide)、聚对苯二甲酸乙二醇酯(PET，Polyethylene Terephthalate)或环烯烃聚合物(COP，Cyclo Olefin Polymer)等。例如，透光层1310可以为光学胶层，即可以起到透光的作用也可以起到粘结作用，例如，透光层1310的材料可以包括透明绝缘材料，例如该透明绝缘材料为聚酰亚胺、树脂、具有光学透明的一层特种无基材的双面胶(OCA，Optically Clear Adhesive)等透明有机材料。
例如，在一些实施例中，如图1所示，栅极驱动电路13配置为通过栅线G10逐一输 出驱动分别沿第一方向X延伸的各排重复单元C1的像素区P10的多个子像素工作的栅极扫描信号。多个重复单元C1排布为分别沿第一方向延伸的N排，栅极驱动电路13包括N个级联的移位寄存器单元170(如图8B所示)，第n级移位寄存器单元170与第n排重复单元C1的像素区P10的子像素驱动电路1601连接，其中，1≤n≤N，N为大于等于2的整数。
例如，如图2所示，每个重复单元C1的像素区P10的多个子像素驱动电路沿第一方向X排列。多个子像素驱动电路分别与不同的发光元件对应连接。
如8A所示，多个子像素的每个的子像素驱动电路1601包括数据写入电路1603、驱动电路1604、电荷存储电路1606以及感测电路1605。驱动电路1604与第一节点G、第二节点S以及第三节点D连接。第三节点D还与第一电源电压端ELVDD连接。例如，第一电源电压端ELVDD与提供第一电源电压的电源线VDD10连接。驱动电路1604被配置为在第一节点G的电平的控制下，控制流经发光元件160的驱动电流。数据写入电路1603与第一节点G连接，且被配置为接收栅极扫描信号(例如，栅极驱动电路通过栅线G10提供)作为扫描驱动信号，并且响应于扫描驱动信号将数据信号写入第一节点G。电荷存储电路1606与第一节点G以及所述第二节点S连接，且被配置为存储写入的数据信号以及参考电压信号。与第二节点S连接，配置为接栅极扫描信号作为感测驱动信号，并且响应于感测驱动信号将参考电压信号写入驱动电路1604或从驱动电路1604读取感测电压信号。发光元件160(例如，为发光元件160的第一电极161)和第二节点S以及第二电源电压端ELVSS连接，且配置为通过第二电源电压端ELVSS接收第二电源电压，并在驱动电流的驱动下发光。例如，第二电源电压端ELVSS和电源线ELVSS(图中未示出)连接，电源线ELVSS配置为提供第二电源电压。
例如，在本公开实施例中，电源线ELVSS配置为围绕显示区101走线，发光元件160的第二电极1602整面设置，并与电源线ELVSS连接以接收第二电源电压。
例如，如图8A所示，数据写入电路1603实现为数据写入晶体管T1，驱动电路1604实现为驱动晶体管T2，电荷存储电路1606实现为存储电容CST，以及感测电路1605实现为感测晶体管T3。图1中的多条栅线G10包括第一栅线G1和第二栅线G2。
数据写入晶体管T1的第一极与多条数据线DATA之一连接从而可以接收数据信号，数据写入晶体管T1的第二极与第一节点G连接(也就是与驱动晶体管T2的栅极TG2连接)。数据写入晶体管T1的栅极TG1与多条栅线中的第一栅线G1(即和移位寄存器单元的输出端连接的栅线)连接从而可以接收扫描驱动信号。
驱动晶体管T2的第一极与一条第二电源电压端ELVDD连接，被配置为接收第一电源电压，驱动晶体管T2的第二极和第二节点S连接(也就是与感测晶体管T3的第一极连接)。
感测晶体管T22的栅极G221被配置为接收感测驱动信号，例如，感测晶体管T22的栅极G221和多条栅线中的第二栅线G2(即和感测晶体管T22位于不同行的移位寄存器单元的输出端连接栅线)连接从而可以接收感测驱动信号。感测晶体管T2的第一极与 第二节点S连接，感测晶体管T2的第二极与一条感测信号线SENSE(为图1中的多条感测信号线SES10其中之一)连接，被配置为接收参考电压信号或者输出感测电压信号。
发光元件160的第一极(例如为第一电极161)和第二节点S连接，即与驱动晶体管T2的第二极(例如为第二电极162)以及感测晶体管T3的第一极连接，从而可以接收驱动晶体管T2的驱动电流；发光元件160的第二极被配置为与第二电源电压端ELVSS连接，以接收第二电源电压。例如，在一些实施例中，发光元件160的第二极被配置为接地，此时第二驱动电压为0V。例如，第一电源电压为高电平电压(例如，5V、10V或其他合适的电压)，第二电源电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。当驱动晶体管T2导通(或部分导通)时，第一电源电压和第二电源电压可以看作一个电源，该电源用于产生驱动发光元件160的驱动电流。
需要说明的是，该发光元件160例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。
例如上述晶体管均以N型晶体管为例进行说明，即各个晶体管在栅极接入高电平(导通电平)时导通，而在接入低电平(截止电平)时截止。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管，此时，第一极可以是源极，第二极可以是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管的各极的极性相应连接即可。
例如，图8B为本公开至少一实施例提供的子像素单元电路的子像素驱动电路与寄存器单元电路连接的示意图。如图8B所示，第一栅线G1与沿第一方向X延伸的第M排重复单元C1的像素区P10的多个子像素驱动电路1601的数据写入电路1603、沿所述第一方向X延伸的第M-1排重复单元C1的像素区P10的多个子像素驱动电路1601的感测电路1605以及第M行移位寄存器单元170的输出端连接，以将第M行移位寄存器单元170的输出端输出的栅极扫描信号输出至第M排重复单元C1的像素区P10的多个子像素驱动电路1601的数据写入电路1603作为扫描驱动信号、以及输出至第M-1排重复单元C1的像素区P10的多个子像素驱动电路1601的感测电路1605作为感测驱动信号。第二栅线G2与第M排重复单元C1的像素区P10的多个子像素驱动电路1601的感测电路1605、沿第一方向X延伸的第M+1排重复单元C1的像素区P10的多个子像素驱动电路1601的数据写入电路1603以及第M+1行移位寄存器单元170的输出端连接，以将第M+1行移位寄存器单元170的输出端输出的栅极扫描信号输出至第M+1行排重复单元C1的像素区P10的多个子像素驱动电路1601的数据写入电路1603作为扫描驱动信号、以及输出至第M排重复单元C1的像素区P10的多个子像素驱动电路1601的感测电路1605作为感测驱动信号。1＜M＜N，M为大于1的奇数。
需要说明的是，在本公开实施例中，沿第一方向X延伸的第M排表示横向的第M行，沿第二方向Y延伸的第M排表示纵向的第M列。
图9A为本公开至少一实施例提供的遮光层的平面图。
例如，在一些实施例中，结合图9A以及图6，在每个像素区P10，遮光层131包括 遮光电极111，遮光电极111沿第二方向Y(例如，第二方向Y上遮光电极111的长度较大)延伸，遮光电极111在衬底基板10的板面上的正投影的至少部分，例如部分与每个像素区P10的多个子像素驱动电路1601(例如，例如，第一子像素驱动电路P161、第二子像素驱动电路P162或第三子像素驱动电路P163)在衬底基板10的板面上的正投影重叠，从而可以阻挡外部光线的照射到子像素驱动电路上，尤其是晶体管的有源层，以避免暗电流的产生。
例如，如图9A所示，遮光电极131在第二方向Y包括第一端部1111、中间凹部1113和第二端部1112，中间凹部1113位于第一端部1111和第二端部1112之间。第一端部1111和第二端部1112在第一方向X上的宽度大于中间凹部1113在第一方向上的宽度。结合图6，第一端部1111和第二端部1112在衬底基板10的板面上的正投影，与子像素驱动电路1601的数据写入晶体管T1、驱动晶体管T2以及感测晶体管T3的有源层在衬底基板10的板面上的正投影重叠。电极搭接区12位于中间凹部1113与透光区TM10之间。遮光电极131设置为中间窄两头端的形状，可以减少遮光电极131对空间的占用率，增加透光区的面积。
例如，如图6所示，在第二方向Y上，感测晶体管T3位于上方(例如存储电容CST的上方)，驱动晶体管T2和数据写入晶体管T1位于存储电容CST的远离感测晶体管T3的一侧。数据写入晶体管T1和驱动晶体管T2的有源层在衬底基板10的板面上的正投影，与遮光电极131的第二端部1112在衬底基板10的板面上的正投影重叠。感测晶体管T3的有源层在衬底基板10的板面上的正投影，与遮光电极131的第一端部1111在衬底基板10的板面上的正投影重叠。由此，遮光层可以阻挡外部光线的照射到晶体管的数据写入晶体管T1、驱动晶体管T2以及感测晶体管T3的有源层，以避免暗电流的产生。
例如，在一些实施例中，如图6和图7所示，像素区P10的子像素驱动电路1601(例如，第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163)的存储电容CST的第一极板CST1和第二极板CST2包括沿第二方向Y延伸的条状。在每个重复单元C1中，第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3区沿第二方向Y依次排列，第二子像素滤光区LG2位于第一子像素滤光区LG1和第三子像素滤光区LG3之间。第一子像素滤光区LG1与像素区P10的多个子像素的子像素驱动电路的感测晶体管T3的至少部分(例如靠近存储电容CST的部分)，以及存储电容CST的靠近感测晶体管T3的部分(例如将条形存储电容CST在第一方向Y分为三份的话，该部分为存储电容CST位于上方的部分)在衬底基板10的板面上的正投影重叠。第三子像素滤光区LG3与像素区P10的多个子像素的子像素驱动电路的数据写入晶体管和驱动晶体管的至少部分(例如靠近存储电容CST的部分)，以及存储电容CST的靠近驱动晶体管T2的部分(例如存储电容CST位于下方的部分)在衬底基板10的板面上的正投影重叠。第二子像素滤光区LG2与像素区P10的多个子像素的子像素驱动电路的存储电容CST的靠近其在第一方向上中间的部分(例如存储电容CST位于中间的部分)在衬底基板10的板面上的正投影重叠。条状存储电容CST和类似方形的滤 光区的设计，可以增加显示基板的透明区的面积，提高显示效果。
例如，在其它实施例中，也可以将第一子像素滤光区LG1、第二子像素率滤光区LG2以及第三子像素滤光区LG3区设计为沿第二方向Y延伸的条形，本公开实施例不以此为限。
例如，本公开至少一实施例还提供一种显示基板，该显示基板包括衬底基板和多条感测线。多条感测信号线设置在衬底基板上并沿与第一方向不同的第二方向延伸，多条感测信号线的相邻的两条之间设置有分别沿第二方向的两排所述重复单元，多条感测信号线的每条同时和与其相邻且分别沿第二方向的两排重复单元的多个子像素的子像素驱动电路连接，且配置为提供参考电压信号。由此，减小信号走线占用的空间，增加透明区的面积，提高透光率。
例如，在一些实施例中，如图1所示，多条感测信号线SES10设置在衬底基板10上并沿第二方向Y延伸。多条感测信号线SES10延伸至邦定区13，例如还与邦定区13的接触垫(图中未示出)连接以接外部驱动电路(例如芯片)提供的电信号。多条感测信号线SES10的相邻的两条之间设置有分别沿所第二方向Y的两排重复单元C1，多条感测信号线SES10的每条同时和与其相邻且分别沿第二方向Y的两排重复单元C10的多个子像素的子像素驱动电路连接，且配置为提供参考电压信号。即，多条感测信号线SES10中的每条中相邻的两条之间在同一行中间隔两个重复单元C1。多条感测信号线SES10中的每条与其沿第一方向X的两侧的两个重复单元C1的像素区P10连接。由此，两个重复单元C1的像素区P10的多个子像素的子像素驱动电路共用一条感测信号线SES10，从而减少感测信号线的数量和占用的布线空间，进而增大透明区的面积。
例如，在一些实施例中，如图1所示，多条电源线VDD10设置在衬底基板10上并沿第二方向Y延伸，在第一方向X上，多条电源线VDD10和多条感测信号线SES10交替布置，多条感测信号线SES10的每条和与其相邻的电源线VDD10之间设置有沿第二方向Y延伸的一排重复单元C1。即多条电源线VDD10和多条感测信号线SES10限定出沿第二方向Y延伸的没排重复单元C1的空间。多条电源线VDD10的每条和与其相邻的感测信号线SES10之间设置有沿第二方向Y延伸的一排重复单元C1。多条电源线VDD10的相邻的两条之间设置有分别沿第二方向Y延伸的两排重复单元C1，多条电源线VDD10的每条同时和与其相邻且分别沿第二方向Y延伸的两排重复单元C1的多个子像素的子像素驱动电路连接，且配置为提供第一电源电压。即，多条电源线VDD10中的每条中相邻的两条之间在同一行中间隔两个重复单元C1。多条电源线VDD10中的每条与其沿第一方向X的两侧的两个重复单元C1的像素区P10连接。由此，两个重复单元C1的像素区P10的多个子像素的子像素驱动电路共用一条电源线VDD10，从而减少电源线的数量和占用的布线空间，进而增大透明区的面积。
图9B为本公开至少一实施例提供的第一绝缘层的平面图。图9C为本公开至少一实施例提供的缓冲层的平面图。图9D为本公开至少一实施例提供的半导体层的平面图。图9E为本公开至少一实施例提供的第二导电层的布局图。图9F为本公开至少一实施例提 供的层间绝缘层的平面图。图9G为本公开至少一实施例提供的第一导电层的平面图。图10为图9A至图9B层叠后的布局图。下面结合图9B-9G以及图10对像素区的多个子像素的子像素单元驱动电路1601的结构进行详细介绍。需要说明的是，将以图9B-9G以及图10中一个子像素单元驱动电路1601的结构为例进行介绍，而其它子像素单元驱动电路的结构与之相同将不再赘述。
例如，在一些实施例中，如图2和图6所示，显示区101包括沿第一方向相邻设置的第一重复单元C11和第二重复单元C12，第一重复单元C11的像素区与第二重复单元C12的透明区TM10之间设置感测信号线SES11，感测信号线SES11与第一重复单元C11和第二重复单元C12的像素区P10的多个子像素驱动电路连接。即第一重复单元C11和第二重复单元C12的像素区P10的多个子像素驱动电路共用一条感测信号线。第二重复单元C12的像素区P10的远离第二重复单元C12的透明区TM10的一侧设置电源线VDD11，电源线VDD11与第二重复单元C12的像素区P10的多个子像素驱动电路连接，第一重复单元C11的透明区TM10的远离第一重复单元C11的像素区P10的一侧设置另一电源线VDD12，另一电源线VDD12与第一重复单元C11的像素区P10的多个子像素驱动电路连接。在图2和图6所示的重复单元中，若在第一重复单元C11的左侧，即另一电源线VDD12远离第一重复单元C11的一侧，继续画出另一个重复单元，再该另一个重复单元的像素区的子像素还与另一电源线VDD12连接。同样的，在图2和图6所示的重复单元中，若在第二重复单元C12的右侧，即电源线VDD11远离第二重复单元C12的一侧，继续画出另一个重复单元，该另一个重复单元的像素区的子像素还与电源线VDD11连接。也就是说每一根电源线都是与两个重复单元的像素区连接。在本公开实施例中以图2和图6所示的结构进行介绍，其它部分结构相似将不再详细图示以及介绍。
例如，在一些实施例中，如图2和图6所示，第一重复单元C11的像素区P10的多个子像素驱动电路以及第二重复单元层2的像素区P10的多个子像素驱动电路分别包括在第一方向X排列的第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163。第二子像素驱动电路P162位于第一子像素驱动电路P161和第三子像素驱动电路P163之间。第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163在衬底基板10板面上的正投影都是沿第二方向Y延伸的。第一子像素驱动电路P161与第二子像素驱动电路P162和第三子像素驱动电路P163镜像对称。
需要说明的是，在本公开实施例中，第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163的结构相同的部分件以一个子像素驱动电路为例进行介绍，其它子像素驱动电路将不再详细赘述。
例如，如图9B所示，第一绝缘层132上开设位于电极搭接区12的第一搭接子孔FK111，以露出图9A所示的遮光层131，例如遮光层131的中间凹部1113。
例如，图9C所示，缓冲层133上开设位于电极搭接区12的第三搭接子孔FK113，以露出图9A所示的遮光层131，例如遮光层131的中间凹部1113。第三搭接子孔FK113 套设在第一搭接子孔FK111中。
例如，在一些实施例中，如图6和图9D所示，子像素驱动电路的数据写入晶体管T1、驱动晶体管T2以及感测晶体管T3在衬底基板10上的正投影都沿第二方向Y延伸。在图6中，半导体层ACT包括子像素驱动电路的数据写入晶体管T1的有源层TA1、驱动晶体管T2的有源层TA2以及感测晶体管T3的有源层TA3。子像素驱动电路的数据写入晶体管T1的有源层TA1、驱动晶体管T2的有源层TA2以及感测晶体管T3的有源层TA3都沿第二方向Y延伸。例如，衬底基板10可以为柔性基板。由此，当显示基板弯折的过程中，可以保证子像素驱动电路的各个晶体管的电学性能不受影响，保证显示基板显示的稳定性。
例如，数据写入晶体管T1的有源层TA1、驱动晶体管T2的有源层TA2以及感测晶体管T3的有源层TA3也可以不与第二方向Y平行，例如与第二方向Y相交一定的角度。例如，该交叉角度小于等于20°。
例如，如图9D所示，以第一子像素驱动电路P161为例，详细介绍子像素驱动电路的每个晶体管的有源层和存储电容的结构。例如，半导体层ACT还包括第一子像素驱动电路P161的存储电容的第一极板CST1。感测晶体管T3的有源层TA3位于存储电容的第一极板CST1的上侧，驱动晶体管T2的有源层TA2和数据写入晶体管T1的有源层TA1位于存储电容的第一极板CST1的远离感测晶体管T3的一侧，驱动晶体管T2的有源层TA2位于感测晶体管T3和数据写入晶体管T1之间。存储电容CST的第一极板CST1与驱动晶体管T2的有源层TA2连接且一体设置。存储电容的第一极板CST1为沿第二方向Y延伸的条状。且存储电容的第一极板CST1的与电极搭接区12对应的位置设置一个像远离透明区TM10的一侧凸出的凸部CST11，且该凸部有一个凹口CST12，该凹口CST12围绕电极搭接区12以留出电极搭接区12的空间。即，电极搭接区12占用了部分第一极板CST1的空间，从而减小电极搭接区12占用透明区TM10的空间，增加透明区的面积。例如，如图9D所示，第二子像素驱动电路P162的存储电容的第一极板CST1与第一子像素驱动电路P161的存储电容的第一极板CST1的形状略有不同。第二子像素驱动电路P162的存储电容的第一极板CST1对应于凸部CST11的部分发生弯折，以留出第一子像素驱动电路P161和第二子像素驱动电路P162之间的走线空间。第三子像素驱动电路P163的存储电容的第一极板CST1与第一子像素驱动电路P161和第二子像素驱动电路P162的存储电容的第一极板CST1的形状略有不同。第三子像素驱动电路P163的存储电容的第一极板CST1对应于凸部CST11的部分，在靠近第二子像素驱动电路P162的一侧的边缘向右侧(远离第二子像素驱动电路P162的方向)凹陷，以留出第二子像素驱动电路P162和第三子像素驱动电路P163之间的走线空间。也就是说，与围绕电极搭接区12的凹口CST12相似的结构也可以对应设置在第二子像素驱动电路P162和第三子像素驱动电路P163的存储电容的第一极板CST1中。
例如，如图9D所示，感测晶体管T3的有源层TA3包括源极区TS3、沟道区TP3以及漏极区TD3。例如，驱动晶体管T2的有源层TA2包括源极区TS2、沟道区TP2以 及漏极区TD2。例如，数据写入晶体管T1的有源层TA1包括源极区TS1、沟道区TP1以及漏极区TD1。
例如，如图9E所示，第二导电层GATE包括数据写入晶体管T1的栅极TG1、驱动晶体管T2的栅极TG2以及感测晶体管T3的栅极TG3。沟道区TP3在衬底基板上的正投影与栅极TG3在衬底基板上的正投影部分重叠。沟道区TP1在衬底基板上的正投影与栅极TG1在衬底基板上的正投影部分重叠。沟道区TP2在衬底基板上的正投影与栅极TG2在衬底基板上的正投影部分重叠。
例如，如图9G所示，第一导电层SD包括数据写入晶体管T1的第一极TSD11和第二极TSD12、驱动晶体管T2的第一极TSD21和第二极TSD22、感测晶体管T3的栅极第一极TSD31和第二极TSD32以及存储电容CST的第二极板CST2。结合图9D所示，数据写入晶体管T1的第一极TSD11和第二极TSD12分别与数据写入晶体管T1的源极区TS1和漏极区TSD1在衬底基板10上的正投影重叠。驱动晶体管T2的第一极TSD21和第二极TSD22分别与驱动晶体管T2的源极区TS2和漏极区TD2在衬底基板10上的正投影重叠。感测晶体管T3的第一极TSD31和第二极TSD32分别与感测晶体管T3的源极区TS3和漏极区TD3在衬底基板10上的正投影重叠。存储电容CST的第二极板CST2和存储电容的第一极板CST1之间间隔第二绝缘层134，以形成电容功能。结合图9F所示，感测晶体管T3的第一极TSD31通过第三过孔GK3与源极区TS3连接，感测晶体管T3的第二极TSD32通过第一源漏过孔SDG1(例如穿过第二绝缘层134)与漏极区TD3连接。驱动晶体管T2的第一极TSD21通过第二源漏过孔SDG2(例如穿过第二绝缘层134)与源极区TS2连接，驱动晶体管T2的第二极TSD22通过第四过孔GK3与漏极区TD2连接。数据写入晶体管T1的第一极TD11通过第三源漏过孔SDG3(例如穿过第二绝缘层134)与源极区TS1连接，数据写入晶体管T1的第二极TD12第四源漏过孔SDG4(例如穿过第二绝缘层134)与漏极区TD1连接。其中，第三过孔GK3和第四过孔GK3的结构将在后续详细介绍。
需要说明的是，第一源漏过孔SDG1、第二源漏过孔SDG2、第三源漏过孔SDG3以及第四源漏过孔SDG4可以设置为穿过第二绝缘层134和第四绝缘层137。
例如，第一源漏过孔SDG1、第二源漏过孔SDG2、第三源漏过孔SDG3以及第四源漏过孔SDG4的尺寸范围可以约为2-4微米，例如约为3微米。第一源漏过孔SDG1、第二源漏过孔SDG2、第三源漏过孔SDG3以及第四源漏过孔SDG4的尺寸由显示基板在制备工艺进行选择。
需要说明的是，存储电容CST的第二极板CST2和第一极板CST1之间还可以间隔二绝缘层134和第四绝缘层137，本公开实施例不以此为限。
例如，如图9F所示，第二绝缘层134还包括位于电极搭接区12的第二搭接子孔FK112。
例如，如图9G所示，第一导电层SD还包括位于电极搭接区12的第一搭接电极FD11。
例如，在一些实施例中，如图9G所示，存储电容CST的第二极板CST2的靠近感 测晶体管T3的第二极TSD32的一端和感测晶体管T3的第二极TSD2的连接，且第二极板CST2和感测晶体管T3的第二极TSD32一体设置。驱动晶体管T2的第一极TSD21与存储电容CST的第二极板CST2的远离感测晶体管T3的一端连接，且驱动晶体管T2的第一极TSD21与第二极板CST2一体设置，以减少占用的空间。
例如，如图9E、图9G和图10所示，多条电源线的每条，例如电源线VDD11或电源线VDD12，包括位于第二导电层GATE的第一子线VDD111以及位于第一导电层SD的第二子线VDD121。第一子线VDD111包括多个沿第二方向Y延伸的第一走线段VDD112，多个第一走线段VDD112分别位于不同的重复单元C1中，第二子线VDD121沿第二方向Y穿过显示区101。即电源线为双层走线，分别在第一导电层SD和第二导电层GATE，第二导电层GATE中的每个第一子线VDD111的每个第一走线段VDD112位于一个重复单元C1中，而第一导电层SD的第二子线VDD121沿第二方向Y延伸且穿过在第二方向Y上的一排重复单元C1，即第二子线VDD121在第二方向Y上整条设置。第二子线VDD121层叠在第一子线VDD111的远离衬底基板10的一侧，且通过贯穿第二绝缘层124的至少一个第一过孔GK1(如图9F所示)与第一子线VDD111连接。结合图9F所示，多个第一过孔GK1沿第二方向Y排布用于连接第二子线VDD121和第一子线VDD111。由此，可以减低电源线的走线电阻。
例如，如图9E、图9G和图10所示，多条感测信号线的每条，例如感测线SES11包括位于第二导电层GATE的第三子线SES111以及位于第一导电层SD的第四子线SES121，第三子线SES111包括多个沿第二方向Y延伸的第二走线段SES112，多个第二走线段SES112分布位于不同的重复单元中，第四子线SES121沿第二方向Y穿过显示区101。即感测线为双层走线，分别在第一导电层SD和第二导电层GATE，第二导电层GATE中的第三子线SES111的每个第二走线段SES112位于一个重复单元C1中，而第一导电层SD的第四子线SES121沿第二方向Y延伸，且穿过在第二方向Y上的一排重复单元C1，即第四子线SES121在第二方向Y上整条设置。第四子线SES121层叠在第二子线SES111的远离衬底基板10的一侧，且通过贯穿第二绝缘层124的至少一个第二过孔GK2(如图9F所示)与第三子线SES111连接。结合图9F所示，多个第二过孔GK2沿第二方向Y排布用于连接第四子线SES121和第三子线SES111。由此，可以减低电源线的走线电阻。
例如，在一些实施例中，如图9G和图10所示，第一导电层SD包括沿第一方向X延伸的第一转接电极ZL1。第一转接电极ZL1的第一端ZL11与第一重复单元C11的第三子像素驱动电路P163的感测晶体管T3的第一极TSD31连接。第一转接电极ZL1的第二端ZL12与第二重复单元C12的第一子像素驱动电路P161的感测晶体管T3的第一极TSD31连接，第一转接电极ZL1与感测信号线SES11的第二子线SES121交叉连接。也就是说，感测信号线SES11通过第一转接电极ZL1同时向第一重复单元C11和第二重复单元C12提供参考电压信号。
图11A为图10中A1区域的放大图。
例如，在一些实施例中，如图9E和图11A所示，第二导电层GATE包括沿第一方向X延伸的第一连接走线LL1，第一连接走线LL1通过第三过孔GK3的至少部分(例如部分)，与第一重复单元C11或第二重复单元C12的第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163的感测晶体管T3的第一极TSD31连接。即在每个重复单元的像素区都设置一条第一连接走线LL1，以使多个子像素驱动电路的感测晶体管T3的第一极TSD31都接收感测信号线SES11提供的参考电压信号。第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163的感测晶体管T3的第一极TSD31在衬底基板10的板面上的正投影的至少部分(例如部分)与第一连接走线LL1在衬底基板10的板面上的正投影重叠。
例如，第一连接走线LL1也可以不与第一方向X平行，例如与第一方向X相交一定的角度。例如，该交叉角度小于等于20°。
图11B为图11A中沿线B1-B2的截面示意图。
如图11B所示，第一极TSD31在衬底基板10的板面上的正投影的部分与第一连接走线LL1在衬底基板10的板面上的正投影重叠。感测晶体管T3的第一极TSD31包括沿第二方向Y连接的第一子部分TSD311以及第二子部分TSD312。第三过孔GK3在衬底基板10上的投影与第一极TSD31的第一子部分TSD311以及第二子部分TSD312在衬底基板10上的投影重叠。第三过孔GK3的部分，例如与第一子部分TSD311在衬底基板10上的投影重叠的部分，配置为贯穿第二绝缘层134和第四绝缘层137以露出感测晶体管T3的有源层TA3(例如源极区TS3)。第三过孔GK3的另一部分，例如与第二子部分TSD312在衬底基板10上的投影重叠的部分，配置为贯穿第二绝缘层134以露出第一连接走线LL1。第一子部分TSD311与感测晶体管T3的有源层TA3接触并连接，第二子部分TSD312与第一连接走线LL1接触并连接。第三过孔GK3的截面结构还可以称为半埋孔，从而可以减小布线空间以将空间留给透明区。
例如，如图11A所示，第三过孔GK3在第一方向X上的宽度例如约为2-4微米，例如约为3微米。第三过孔GK3在第二方向Y上的长度例如约为5-7微米，例如约为6微米。
例如，在一些实施例中，如图9G和图10所示，第一导电层SD还包括第二转接电极ZL2以及第三转接电极ZL3，第二转接电极ZL2以及第三转接电极ZL3分别包括所述第三节点D(如图8A所示)。驱动晶体管T2的第二极TSD22位于驱动晶体管T2的远离存储电容CST的一侧。第二转接电极ZL2的一端与第二重复单元C12的第三子像素驱动电路P163的驱动晶体管T2的第二电极TSD22连接，以及第二转接电极ZL2的另一端与靠近第二重复单元C12的第三子像素驱动电路P163的电源线VDD11连接，以提供第一电源电压。第二转接电极ZL2沿第一方向X延伸。第三转接电极ZL3的一端与第一重复单元C11的第一子像素驱动电路P161的驱动晶体管T2的第二极TSD22连接，以及第三转接电极ZL3的另一端与靠近第一重复单元C11的透明区TM10的电源线VDD12连接，以提供第一电源电压。第三转接电极ZL3在透光区TM10的下侧走线(靠近数据 写入晶体管T1的一侧)，并在透明区TM10和像素区P10之间向靠近驱动晶体管T2的一侧弯折走线，以减少布线空间。也就是说，电源线VDD11或电源线VDD12都与一个第二转接电极ZL2和第三转接电极ZL3连接以与其两侧的子像素驱动电路连接，电源线VDD11和电源线VDD12另一侧的结构这里将不再赘述。
图11C为图10中A2区域的放大图。
例如，在一些实施例中，如图9G和图11C所示，第二导电层包括沿第一方向X延伸的第二连接走线LL2，第二连接走线LL2通过第四过孔GK4的至少部分(例如部分)，与第一重复单元C11或第二重复单元C12的第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163的驱动晶体管T2的第二极TSD22连接。也就是说，通过第二连接走线LL2将像素区的多个子像素驱动电路都与电源线连接。第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163的驱动晶体管T2的第二极TSD22在衬底基板10的板面上的正投影的部分与第二连接走线LL2在衬底基板10的板面上的正投影重叠。第四过孔GK4的截面结构与第三过孔GK3相似这里不再详细赘述。
例如，第二连接走线LL2也可以不与第一方向X平行，例如与第一方向X相交一定的角度。例如，该交叉角度小于等于20°。
例如，在一些实施例中，如图9G和图10所示，显示基板1还包括多条数据线，多条数据线沿第二方向Y延伸，多条数据线包括位于每个重复单元的第一数据线DR、第二数据线DG以及第三数据线DB。第一数据线DR和第二数据线DB位于第一子像素驱动电路P161与第二子像素驱动电路P162之间，第三数据线DB位于第二子像素驱动电路P162和第三子像素驱动电路P163之间。第一数据线DR、第二数据线DG以及第三数据线DB在对应于电极搭接区12的位置弯折走线。第一数据线DR、第二数据线DG以及第三数据线DB分别与第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163电连接，以分别提供数据信号。第一导电层还包括沿第一方向X的第四转接电极ZL4、第五转接电极ZL5以及第六转接电极ZL6。第四转接电极ZL4连接第一数据线DR以及第一子像素驱动电路P161的数据写入晶体管T1的第二极TSD12，第五转接电极ZL5连接第二数据线DG以及第二子像素驱动电路P162的数据写入晶体管T1的第二极TSD12，第六转接电极ZL6连接第三数据线DB以及第三子像素驱动电路P163的数据写入晶体管T1的第二极TSD12。
例如，第四转接电极ZL4、第五转接电极ZL5以及第六转接电极ZL6也可以不与第一方向X平行，例如与第一方向X相交一定的角度。例如，该交叉角度小于等于20°。
例如，如图9G和图10所示，第一子像素驱动电路P161的数据写入晶体管T1的第二极TSD12和第四转接电极ZL4与第二子像素驱动电路P162的数据写入晶体管T1的第二极TSD12和第五转接电极ZL5为镜像对称。
例如，在一些实施例中，如图9E和图11A所示，第一栅线G1和第二栅线G2位于第二导电层GATE，第一栅线G1靠近第一重复单元C11和第二重复单元C12的感测晶 体管T3，第二栅线G2靠近第一重复单元C11和第二重复单元C12的数据写入晶体管T1。第一栅线G1包括折线部，折线部包括沿第一方向X的第一折线部G111、分别与第一折线部G111两端连接的沿第二方向Y的第二折线部G112以及第三折线部G113。第一折线部G111、第二折线部G111以及所述第三折线部G113绕过第一连接走线ZL1。第一折线部G111在衬底基板10的板面上的正投影，与第一重复单元C10的第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163的感测晶体管T3的有源层TA3在衬底基板10的板面上的正投影交叠，交叠部分形成感测晶体管T3的栅极TG3。
例如，如图9G和图10所示，第二导电层GATE还包括第三连接走线LL3、第四连接走线LL4以及第五连接走线LL5。第三连接走线LL3、第四连接走线LL4以及第五连接走线LL5大致呈“L”形折线，第四连接走线LL4以及第五连接走线LL5的弯折方向相同(例如朝向第一子像素驱动电路P161)，第三连接走线LL3的弯折方向((例如朝向第二子像素驱动电路P162)与第四连接走线LL4以及第五连接走线LL5的弯折方向相对。第三连接走线LL3与第二栅线G2以及第一子像素驱动电路P161的数据写入晶体管T1的栅极TG1连接。第四连接走线LL4与第二栅线G2以及第二子像素驱动电路P162的数据写入晶体管T1的栅极TG1连接。第五连接走线LL5与第二栅线G2以及第三子像素驱动电路P163的数据写入晶体管T1的栅极TG1连接。
例如，在一些实施例中，如图9G和图10所示，第一导电层SD还包括沿第二方向Y的第七转接电极ZL7、第八转接电极ZL8以及第九转接电极ZL9。第七转接电极ZL7、第八转接电极ZL8以及第九转接电极ZL9在衬底基板10的板面上的正投影与第二连接走线ZL2在衬底基板10的板面上的正投影交叠。第七转接电极ZL7的第一端(位于上方的一端)通过贯穿第二绝缘层134的第八过孔GK8的至少部分(例如部分)，与第一子像素驱动电路P161的驱动晶体管T2的栅极TG2连接，第七转接电极ZL7的第二端(位于下方的一端)与第一子像素驱动电路P161的数据写入晶体管T1的第一极TSD11连接。第八转接电极ZL8的第一端(位于上方的一端)通过贯穿第二绝缘层134的第九过孔GK9的至少部分(例如部分)，与第二子像素驱动电路P162的驱动晶体管T2的栅极TG2连接，第八转接电极ZL8的第二端(位于下方的一端)与第二子像素驱动电路P162的数据写入晶体管T1的第一极TSD11连接。第九转接电极ZL9的第一端(位于上方的一端)通过贯穿第二绝缘层134的第十过孔GK10的至少部分(例如部分)，与第三子像素驱动电路P163的驱动晶体管T3的栅极TG3连接，第九转接电极ZL9的第二端(位于下方的一端)与第三子像素驱动电路P163的数据写入晶体管T1的第一极TSD11连接。
例如，第七转接电极ZL7、第八转接电极ZL8以及第九转接电极ZL9也可以不与第一方向X平行，例如与第一方向X相交一定的角度。例如，该交叉角度小于等于20°。
例如，第八过孔GK8、第九过孔GK9以及第十过孔GK10的结构可以与第三过孔GK3的结构相似，这里不再赘述。
例如，在一些实施例中，如图10所示，在第二方向Y上，第一栅线G1与第一连接 走线ZL1并列走线的部分位于第一连接走线ZL1的靠近第二重复单元C12的透明区TM10的一侧。在第二方向Y上，第一连接走线ZL1与第一栅线G1的第一折线部G111间隔设置，第二连接走线ZL2与第二栅线G2间隔设置，以减少走线信号之间的干扰。
图12A为本公开至少一实施例提供的钝化层的平面图。图12B为本公开至少一实施例提供的第三绝缘层的平面图。图12C为本公开至少一实施例提供的第一电极层的第一子层的平面图。图12D为本公开至少一实施例提供的第一电极层的第三子层的平面图。图12E为本公开至少一实施例提供的像素限定层的平面图。进一步结合图12A至图12E对显示基板的结构进行详细介绍。
例如，在一些实施例中，如图6、图7以及图12C所示，每个重复单元C1的多个发光元件160包括第一发光元件164、第二发光元件165以及第三发光元件166。第一发光元件164、第二发光元件165以及第三发光元件166分别与第一子像素滤光区LG1、第二子像素滤光区LG2以及第三子像素滤光区LG3对应设置。显示基板1还包括至少贯穿第三绝缘层136(还可以贯穿钝化层135)的第五过孔GK5、第六过孔GK6以及第七过孔GK7。第五过孔GK5、第六过孔GK6以及第七过孔GK7分别配置为露出第一子像素驱动电路P161、第二子像素驱动电路P162以及第三子像素驱动电路P163。第一发光元件164的第一电极161通过第五过孔GK5与第一子像素驱动电路P161连接。第二发光元件165的第一电极161通过第六过孔GK6与第二子像素驱动电路连接P162。第三发光元件166的第一电极161通过第七过孔GK7与第三子像素驱动电路P163连接。
例如，如图12A和图12B所示，第五过孔GK5、第六过孔GK6以及第七过孔GK7分别贯穿第三绝缘层136和穿钝化层135，以将第一发光元件164与第一子像素驱动电路P161连接，第二发光元件165与第二子像素驱动电路P162连接，第三发光元件166与第三子像素驱动电路P163连接。
需要说明的是，图12A和图12B所示的第三绝缘层136和穿钝化层135为反相结构，即有填充的部分是被挖去(不存在)的部分。
例如，如图6所示，第五过孔GK5在衬底基板10的板面上的正投影与第一发光元件164的发光区在衬底基板10的板面上的正投影不重叠，以提高第一发光元件164的发光区的平整度。第六过孔GK6在衬底基板10的板面上的正投影与第二发光元件165的发光区在衬底基板10的板面上的正投影不重叠，以提高第二发光元件165的发光区的平整度。第七过孔GK7在衬底基板10的板面上的正投影与第三发光元件166的发光区在衬底基板10的板面上的正投影不重叠，以提高第三发光元件166的发光区的平整度。
例如，第五过孔GK5、第六过孔GK6以及第七过孔GK7的尺寸范围可以约为9-12微米。例如，第五过孔GK5、第六过孔GK6以及第七过孔GK7的尺寸选择为约10或11微米。第五过孔GK5、第六过孔GK6以及第七过孔GK7的尺寸由显示基板在制备工艺进行选择。
例如，在一些实施例中，如图2、图6以及图7所示，第五过孔GK5以及第六过孔GK6在衬底基板10的板面上的正投影靠近第一子像素滤光区LG1和第二子像素滤光区 LG2之间的遮光线条BM1在衬底基板10的板面上的正投影，且位于第一子像素滤光区LG1和第二子像素滤光区LG2之间的遮光线条BM1在衬底基板10的板面上的正投影的两侧。也就是说，第五过孔GK5在第一发光元件164的发光区的下方且位于遮光线条BM1的上侧，第六过孔GK6位于第二发光元件165的发光区的上侧。由此，可以增加第一发光元件164和第二发光元件165的发光区的面积。第七过孔GK7在衬底基板10的板面上的正投影靠近第二子像素滤光区LG2和第三子像素滤光区LG3之间的遮光线条BM2在衬底基板10的板面上的正投影，且与第三子像素滤光区LG3重叠。也就是说，第七过孔GK7位于第三发光元件166的发光区的上侧，以增加第三发光元件166的发光区的面积。需要说明的是，在该实施例中，第五过孔GK5的位置与图6中所示的第五过孔GK5的位置不同。
例如，在另外一些实施例中，如图2、图6以及图7所示，第五过孔GK5在衬底基板10的板面上的正投影，与第一子像素驱动电路P161的存储电容CST的第一极板CST1的与感测晶体管T3的第二极TSD31连接的一端，在衬底基板10的板面上的正投影重叠。即，第五过孔GK5位于第一发光元件164的发光区的上侧，以减少对第一发光元件164的发光区的影响。第六过孔GK6在衬底基板10的板面上的正投影靠近第一子像素滤光区LG1和第二子像素滤光区LG2之间的遮光线条BM1在衬底基板10的板面上的正投影，且与第二子像素滤光区LG2重叠。即，第六过孔GK6位于第二发光元件165的发光区的上侧，以增加第一发光元件164的发光区的面积。第七过孔GK7在衬底基板10的板面上的正投影靠近第二子像素滤光区LG2和第三子像素滤光区LG3之间的遮光线条BM2在衬底基板10的板面上的正投影，且与第三子像素滤光区LG3重叠。也就是说，第七过孔GK7位于第三发光元件166的发光区的上侧，以增加第三发光元件166的发光区的面积。
例如，如图12C所示，第一电极层AN的第一层AN1包括第一子电极层FD121和第一发光元件164、第二发光元件165以及第三发光元件163的第一电极的靠近衬底基板10的一层。第一发光元件164、第二发光元件165以及第三发光元件163的第一电极的靠近衬底基板10的一层分别通过第五过孔GK5、第六过孔GK6以及第七过孔GK7与第一子像素驱动电路P161、第二子像素驱动电路P162连接以及第三子像素驱动电路P163连接。第一子电极层FD121通过图12A和图12B中贯穿钝化层135和第三绝缘层136的第二搭接孔FD12与第一搭接电极FD11连接。
例如，如图12D所示，第一电极层AN的第三层AN3包括第二电极层FD122和第一发光元件164、第二发光元件165以及第三发光元件163的第一电极的远离衬底基板10的一层。
例如，如图12E所示，像素限定层138具有多个开口限定出透光区TM10、第一发光元件164、第二发光元件165以及第三发光元件163的发光区以及电极搭接区12。需要说明的是，像素限定层138在图12E中为反相结构，即图中填充的部分表示被挖去的部分。
例如，第一导电层SD(图9G所示)的包住过孔的各条走线的宽度为4～5微米。例如第二导电层GATE(图9E所示)的包各条走线的宽度为4～5微米。例如，数据写入晶体管T1和驱动晶体管T2的第一极或第二极为上下超过过孔1微米，例如为4.0～4.5微米。
例如，在一些示例中，第二导电层GATE的厚度为2000～300埃第一导电层SD的厚度为5000～8000埃，本公开的实施例对此不作限制。
本公开至少一实施例还提供一种显示装置。图13为本公开至少一实施例提供的一种显示装置的示意图。如图13所示，该显示装置2包括本公开任一实施例提供的显示基板1，例如，图2中所示的显示基板1。
需要说明的是，该显示装置2可以为具有透明显示功能的产品或部件。该显示装置2还可以包括其他部件，例如数据驱动电路、时序控制器等，本公开的实施例对此不作限定。
需要说明的是，为表示清楚、简洁，本公开的实施例并没有给出该显示装置的全部组成单元。为实现该显示装置的基板功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示装置2的技术效果可以参考本公开的实施例中提供的显示基板1的技术效果，这里不再赘述。
图14A-图14F为本公开至少一实施例提供的一种显示装置的制备过程示意图。
例如，如图14A所示，提供衬底基板10，在衬底基板上沉积金属材料通过构图工艺形成遮光层131。例如，金属材料包括银、铝、铬、铜、钼、钛、铝钕合金、铜钼合金、钼钽合金、钼钕合金或任何它们的任意组合。在遮光层131上沉积绝缘材料通过构图工艺形成第一绝缘层132。第一绝缘层132包括第一搭接子孔FK111。例如，第一绝缘层132的材料可以包括氧化硅、氮化硅、氧氮化硅等无机绝缘材料，或其它适合的材料。在第一绝缘层132上沉积绝缘材料通过构图工艺形成缓冲层133。缓冲层133包括第三搭接子孔FK113。在缓冲层133上沉积半导体材料通过构图工艺形成子像素驱动电路的驱动电路T2的有源层TA2和存储电容CST的第一极板CST1，也就是形成图9D中所示的半导体层ACT。
例如，如图14A所示，在半导体层ACT上沉积绝缘材料通过构图工艺形成第四绝缘层137。在四绝缘层137上沉积金属材料形成子像素驱动电路的驱动电路T2的栅极TG2，也就是形成如图9E所示的第二导电层GATE。驱动电路T2的栅极TG2的材料例如包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。在第二导电层GATE上沉积绝缘材料通过构图工艺形成第二绝缘层134。第二绝缘层134包括第二搭接子孔FK112。在第二绝缘层134上沉积金属材料通过构图工艺形成驱动电路T2的第一极TSD21和第二极TSD22以及第一搭接电极FD11，也就是第一导电层SD。例如，驱动电路T2的第一极TSD21和第二极TSD22以及第一搭接电极FD11的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构 为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。在第一导电层SD上依次形成钝化层135和第三绝缘层136。钝化层135和第三绝缘层136包括第二搭接孔FK12和露出子像素驱动电路的过孔。
例如，如图14A所示，在第三绝缘层136上沉积金属材料通过构图工艺形成第一电极层AN的第一层AN1。第一电极层AN的第一层AN1包括相互间隔的两部分，分别为第二搭接电极FD12的第一子电极层FD121和发光元件160的第一电极161的靠近衬底基板的一层。第二搭接电极FD12的第一子电极层FD121通过第二搭接孔FK12与第一搭接电极连接。发光元件160的第一电极161的靠近衬底基板的一层通过化层135和第三绝缘层136中的过孔与子像素驱动电路连接。例如，第一电极层AN的第一层AN1的材料包括至少一种透明导电氧化物材料，例如氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。
例如，如图14B所示，在第一电极层AN的第一层AN1上，例如通过蒸镀的方式，形成材料层M2，材料层M2用于形成第一电极161的第二层AN2。例如，材料层M2可以包括合金材料，例如AlNd等。
例如，如图14C所示，在材料层M2上，例如通过磁控溅射的方式，形成材料层M3，材料层M3用于形成第一电极161的第三层AN3。例如，材料层M3可以包括至少一种透明导电氧化物材料，例如氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。
例如，如图14D所示，对材料层M3进行构图工艺形成第二搭接电极FD12的第三子电极层FD123和发光元件160的第一电极161的远离衬底基板的一层，也就是第三层AN3。
例如，如图14E所示，对材料层M2进行构图工艺形成第二搭接电极FD12的第二子电极层FD122和发光元件160的第一电极161的中间层，也就是第二层AN2。
通过图14A至图14E所示的第一发光元件的第一电极161所在第一电极层AN的制备过程可以使得发光元件160的第一电极161的截面为工字形以及第一子电极层FD121、第二子电极层FD122以及第三子电极层FD123的截面呈工字形。
例如，如图14F所示，在第一电极层AN上逐一形成像素限定层138、发光元件160的发光层163、发光元件160的第二电极162、封装层139、黑矩阵BM、滤光层LG、透光层1310以及保护层1311。上述膜层的详细制备过程不再赘述。
需要说明的是显示基板2的制备过程中形成的各个膜层的结构可以参考对图3的介绍，这里不再详细赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开 的保护范围由所附的权利要求确定。

Claims (26)

  1. 一种显示基板，包括：
    衬底基板，包括显示区，其中，所述显示区包括排布为阵列的多个重复单元，所述多个重复单元每个包括沿所述第一方向排列的透明区和像素区，所述像素区包括多个子像素，所述多个子像素的每个包括子像素驱动电路和发光元件，所述发光元件位于所述子像素驱动电路的远离所述衬底基板的一侧，所述子像素驱动电路配置为驱动所述发光元件发光；以及
    多条感测信号线，设置在所述衬底基板上并沿第二方向延伸，其中，所述多条感测信号线的相邻的两条之间设置有两排所述重复单元，所述两排重复单元沿所述第二方向延伸，所述多条感测信号线的每条和与其相邻且分别沿所述两排重复单元的多个子像素的子像素驱动电路连接，且配置为提供参考电压信号。
  2. 根据权利要求1所述的显示基板，还包括多条电源线，
    其中，所述多条电源线设置在所述衬底基板上并沿所述第二方向延伸，在所述第一方向上，所述多条电源线和所述多条感测信号线交替布置，所述多条感测信号线的每条和与其相邻的电源线之间设置有沿所述第二方向延伸的一排所述重复单元，所述多条电源线的相邻的两条之间设置有分别沿所述第二方向延伸的两排所述重复单元，所述多条电源线的每条和与其相邻且分别沿所述第二方向延伸的两排所述重复单元的多个子像素的子像素驱动电路连接，且配置为提供第一电源电压。
  3. 根据权利要求2所述的显示基板，还包括周边区、栅极驱动电路以及沿所述第一方向延伸的多条栅线，所述周边区至少部分围绕所述显示区，所述栅极驱动电路位于所述周边区，所述多条栅线与所述栅极驱动电路连接并与分别沿所述第一方向延伸的各排所述重复单元的像素区的子像素驱动电路连接，
    所述栅极驱动电路配置为逐一输出驱动分别沿所述第一方向延伸的各排所述重复单元的像素区的多个子像素工作的栅极扫描信号，
    所述多个重复单元排布为分别沿所述第一方向延伸的N排，所述栅极驱动电路包括N个级联的移位寄存器单元，第n级移位寄存器单元与第n排重复单元的像素区的子像素驱动电路连接，其中，1≤n≤N，N为大于等于2的整数。
  4. 根据权利要求3所述的显示基板，其中，每个所述像素区的多个子像素驱动电路沿所述第一方向排列，每个所述子像素驱动电路包括数据写入电路、驱动电路、电荷存储电路以及感测电路，
    所述驱动电路与第一节点、第二节点以及第三节点连接，所述第三节点还与第一电源电压端连接，所述第一电源电压端与所述电源线连接，所述驱动电路被配置为通过所述第三节点接收所述第一电源电压，并在所述第一节点的电平的控制下，控制流经所述发光元件的驱动电流；
    所述数据写入电路与所述第一节点连接，且被配置为接收所述栅极扫描信号作为扫描驱动信号，并且响应于所述扫描驱动信号将数据信号写入第一节点；
    所述电荷存储电路与所述第一节点以及所述第二节点连接，且被配置为存储写入的所述数据信号以及参考电压信号；
    所述感测电路与所述第二节点连接，配置为接收所述栅极扫描信号作为感测驱动信号，所述感测电路还与所述感测信号线连接且配置为接收所述参考电压信号，并且响应于所述感测驱动信号将所述参考电压信号写入所述驱动电路或从所述驱动电路读取感测电压信号；
    所述发光元件与所述第二节点以及第二电源电压端连接，且配置为通过所述第二电源电压端接收第二电源电压，并在所述驱动电流的驱动下发光。
  5. 根据权利要求4所述的显示基板，其中，所述多条栅线包括第一栅线和第二栅线，
    所述第一栅线与沿所述第一方向延伸的第M排重复单元的像素区的多个子像素驱动电路的数据写入电路、沿所述第一方向延伸的第M-1排重复单元的像素区的多个子像素驱动电路的感测电路以及第M个移位寄存器单元的输出端连接，以将第M个移位寄存器单元的输出端输出的栅极扫描信号输出至所述第M排重复单元的像素区的多个子像素驱动电路的数据写入电路作为扫描驱动信号、以及输出至所述第M-1排重复单元的像素区的多个子像素驱动电路的感测电路作为感测驱动信号，
    所述第二栅线与所述第M排重复单元的像素区的多个子像素驱动电路的感测电路、沿所述第一方向延伸的第M+1排重复单元的像素区的多个子像素驱动电路的数据写入电路以及第M+1个移位寄存器单元的输出端连接，以将所述第M+1个移位寄存器单元的输出端输出的栅极扫描信号输出至所述第M+1排重复单元的像素区的多个子像素驱动电路的数据写入电路作为扫描驱动信号、以及输出至所述第M排的重复单元的像素区的多个子像素驱动电路的感测电路作为所述感测驱动信号，
    其中，1＜M＜N，M为整数。
  6. 根据权利要求5所述的显示基板，其中，所述数据写入电路包括数据写入晶体管，所述驱动电路包括驱动晶体管，所述感测电路包括感测晶体管，
    所述数据写入晶体管的有源层、所述驱动晶体管的有源层以及所述感测晶体管的有源层沿所述第二方向延伸，以及所述衬底基板为柔性基板。
  7. 根据权利要求6所述的显示基板，还包括位于所述衬底基板上的半导体层、第一导电层、第二导电层、第二绝缘层以及第四绝缘层，所述第二导电层位于所述半导体层的远离所述衬底基板的一侧，所述第四绝缘层位于所述第二导电层与所述半导体层之间，所述第一导电层位于所述第二导电层远离所述衬底基板的一侧，所述第二绝缘层位于所述第二导电层和所述第一导电层之间，
    所述半导体层包括所述数据写入晶体管的有源层、所述驱动晶体管的有源层以及所述感测晶体管的有源层，
    所述多条电源线的每条包括位于所述第二导电层的第一子线以及位于所述第一导电层的第二子线，所述第一子线包括多个沿所述第二方向延伸的第一走线段，多个所述第一走线段分别位于不同的重复单元中，所述第二子线穿过所述显示区，
    所述第二子线层叠在所述第一子线的远离所述衬底基板的一侧，且通过贯穿所述第二绝缘层的至少一个第一过孔与所述第一子线连接。
  8. 根据权利要求6或7所述的显示基板，其中，所述多条感测信号线的每条包括位于所述第二导电层的第三子线以及位于所述第一导电层的第四子线，所述第三子线包括多个沿所述第二方向延伸的第二走线段，多个所述第二走线段分布位于不同的重复单元中，所述第四子线穿过所述显示区，
    所述第四子线层叠在所述第三子线的远离所述衬底基板的一侧，且通过贯穿所述第二绝缘层的至少一个第二过孔与所述第三子线连接。
  9. 根据权利要求5-8任一所述的显示基板，其中，
    所述显示区包括沿第一方向相邻设置的第一重复单元和第二重复单元，所述第一重复单元的像素区与所述第二重复单元的透明区之间设置感测信号线，所述感测信号线与所述第一重复单元和所述第二重复单元的像素区的多个子像素驱动电路连接，
    所述第二重复单元的像素区的远离所述第二重复单元的透明区的一侧设置电源线，所述电源线与所述第二重复单元的像素区的多个子像素驱动电路连接，所述第一重复单元的透明区的远离所述第一重复单元的像素区的一侧设置另一电源线，所述另一电源线与所述第一重复单元的像素区的多个子像素驱动电路连接，
    所述第一重复单元的像素区的多个子像素驱动电路以及所述第二重复单元的像素区的多个子像素驱动电路分别包括在所述第一方向排列的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路，
    所述第一导电层包括沿所述第一方向延伸的第一转接电极、所述感测晶体管的第一极和第二极，所述第一转接电极的第一端与所述第一重复单元的第三子像素驱动电路的感测晶体管的第一极连接，所述第一转接电极的第二端与所述第二重复单元的第一子像素驱动电路的感测晶体管的第一极连接，
    其中，所述第一转接电极与所述感测信号线的第二子线交叉连接。
  10. 根据权利要求9所述的显示基板，其中，所述第二导电层包括沿所述第一方向延伸的第一连接走线，
    所述第一连接走线通过第三过孔的至少部分，与所述第一重复单元或所述第二重复单元的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路的感测晶体管的第一极连接，
    所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路的感测晶体管的第一极在所述衬底基板的板面上的正投影的至少部分与第一连接走线在所述衬底基板的板面上的正投影重叠。
  11. 根据权利要求10所述的显示基板，其中，所述感测晶体管的第一极包括沿所 述第二方向连接的第一子部分以及第二子部分，
    所述第三过孔的部分配置为贯穿所述第二绝缘层和所述第四绝缘层以露出所述感测晶体管的有源层，所述第三过孔的另一部分配置为贯穿所述第二绝缘层以露出所述第一连接走线，
    所述第一子部分与所述感测晶体管的有源层接触，所述第二子部分与第一连接走线接触。
  12. 根据权利要求10或11所述的显示基板，其中，所述电荷存储电路包括存储电容，所述半导体层还包括存储电容的第一极板，所述第一导电层还包括存储电容的第二极板，
    所述感测晶体管的第二极与所述第二极板的靠近所述感测晶体管的一端连接，且所述感测晶体管的第二极与所述第二极板一体设置。
  13. 根据权利要求12所述的显示基板，其中，在所述第二方向上，所述数据写入晶体管和所述驱动晶体管位于所述存储电容的远离所述感测晶体管的一侧，所述驱动晶体管位于所述数据写入晶体管和所述存储电容之间，
    所述第一导电层还包括所述数据写入晶体管的第一极和第二极、所述驱动晶体管的第一极和第二极、第二转接电极以及第三转接电极，所述第二转接电极以及所述第三转接电极分别包括所述第三节点，
    所述驱动晶体管的第二极位于所述驱动晶体管的远离所述存储电容的一侧，
    所述第二转接电极的一端与所述第二重复单元的第三子像素驱动电路的驱动晶体管的第二电极连接，以及所述第二转接电极的另一端与靠近所述第二重复单元的第三子像素驱动电路的电源线连接，
    第三转接电极的一端与所述第一重复单元的第一子像素驱动电路的驱动晶体管的第二极连接，以及所述第三转接电极的另一端与靠近所述第一重复单元的透明区的电源线连接。
  14. 根据权利要求13所述的显示基板，其中，所述第二导电层包括沿所述第一方向延伸的第二连接走线，
    所述第二连接走线通过第四过孔的至少部分，与所述第一重复单元或所述第二重复单元的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路的驱动晶体管的第二极连接，
    所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路的驱动晶体管的第二极在所述衬底基板的板面上的正投影的至少部分，与所述第二连接走线在所述衬底基板的板面上的正投影重叠。
  15. 根据权利要求13或14所述的显示基板，其中，所述驱动晶体管的第一极与所述存储电容的第二极板的远离所述感测晶体管的一端连接，且所述驱动晶体管的第一极与所述第二极板一体设置，
    所述存储电容的第一极板与所述驱动晶体管的有源层连接且一体设置。
  16. 根据权利要求13-15任一所述的显示基板，其中，所述存储电容的第一极板和第二极板包括沿所述第二方向延伸的条状，
    所述显示基板还包括滤光层，所述滤光层位于所述发光元件的远离所述衬底基板的一侧，
    所述滤光层包括第一子像素滤光区、第二子像素滤光区以及第三子像素滤光区，
    在每个所述重复单元中，所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区沿所述第二方向依次排列，所述第二子像素滤光区位于所述第一子像素滤光区和所述第三子像素滤光区之间，
    所述第一子像素滤光区与所述像素区的多个子像素驱动电路的感测晶体管的至少部分，以及存储电容的靠近所述感测晶体管的部分在所述衬底基板的板面上的正投影重叠，
    所述第三子像素滤光区与所述像素区的多个子像素驱动电路的数据写入晶体管和驱动晶体管的至少部分，以及存储电容的靠近所述驱动晶体管的部分在所述衬底基板的板面上的正投影重叠，
    所述第二子像素滤光区与所述像素区的多个子像素驱动电路的存储电容的靠近其在第一方向上中间的部分在所述衬底基板的板面上的正投影重叠。
  17. 根据权利要求16所述的显示基板，还包括第三绝缘层以及像素限定层，所述第三绝缘层位于所述第一导电层的远离所述衬底基板的一侧，所述发光元件位于所述第三绝缘层的远离所述衬底基板的一侧，所述多个子像素的每个的发光元件包括第一电极、第二电极以及位于所述第一电极和所述第二电极之间的发光层，所述像素限定层配置为限定所述发光元件的发光区，
    每个所述重复单元的多个发光元件包括第一发光元件、第二发光元件以及第三发光元件，
    所述第一发光元件、所述第二发光元件以及所述第三发光元件分别与所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区对应设置，
    所述显示基板还包括至少贯穿所述第三绝缘层的第五过孔、第六过孔以及第七过孔，所述第五过孔、所述第六过孔以及所述第七过孔配置为露出所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路，
    所述第一发光元件的第一电极通过所述第五过孔与所述第一子像素驱动电路连接，
    所述第二发光元件的第一电极通过所述第六过孔与所述第二子像素驱动电路连接，
    所述第三发光元件的第一电极通过所述第七过孔与所述第三子像素驱动电路连接。
  18. 根据权利要求17所述的显示基板，其中，
    所述第五过孔在所述衬底基板的板面上的正投影与所述第一发光元件的发光区在 所述衬底基板的板面上的正投影不重叠，
    所述第六过孔在所述衬底基板的板面上的正投影与所述第二发光元件的发光区在所述衬底基板的板面上的正投影不重叠，
    所述第七过孔在所述衬底基板的板面上的正投影与所述第三发光元件的发光区在所述衬底基板的板面上的正投影不重叠。
  19. 根据权利要求17或18所述的显示基板，还包括黑矩阵，
    在每个所述重复单元的像素区第七转接电极，所述黑矩阵包括多条沿所述第一方向延展的遮光线条，
    多条所述遮光线条在所述衬底基板的板面上的正投影的至少部分，与所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区之间在所述第二方向上的间隔重叠，
    所述第五过孔以及所述第六过孔在所述衬底基板的板面上的正投影靠近所述第一子像素滤光区和所述第二子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且位于所述第一子像素滤光区和所述第二子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影的两侧，
    所述第七过孔在所述衬底基板的板面上的正投影靠近所述第二子像素滤光区和所述第三子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且与所述第三子像素滤光区重叠。
  20. 根据权利要求17或18所述的显示基板，还包括黑矩阵，
    在每个所述重复单元的像素区，所述黑矩阵包括多条沿所述第一方向延展的遮光线条，
    多条所述遮光线条在所述衬底基板的板面上的正投影的至少部分，与所述第一子像素滤光区、所述第二子像素滤光区以及所述第三子像素滤光区之间在所述第二方向上的间隔重叠，
    所述第五过孔在所述衬底基板的板面上的正投影，与所述第一子像素驱动电路的存储电容的第一极板的与所述感测晶体管的第二极连接的一端，在所述衬底基板的板面上的正投影重叠，
    所述第六过孔在所述衬底基板的板面上的正投影靠近所述第一子像素滤光区和所述第二子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且与所述第二子像素滤光区重叠，
    所述第七过孔在所述衬底基板的板面上的正投影靠近所述第二子像素滤光区和所述第三子像素滤光区之间的遮光线条在所述衬底基板的板面上的正投影，且与所述第三子像素滤光区重叠。
  21. 根据权利要求9-20任一所述的显示基板，还包括多条数据线，所述多条数据线沿第二方向延伸，所述多条数据线包括位于每个重复单元的第一数据线、第二数据线以及第三数据线，
    所述第一数据线和所述第二数据线位于所述第一子像素驱动电路与所述第二子像素驱动电路之间，所述第三数据线位于所述第二子像素驱动电路和所述第三子像素驱动电路之间，
    所述第一数据线、所述第二数据线以及所述第三数据线分别与所述第一子像素驱动电路、所述第二子像素驱动电路以及所述第三子像素驱动电路电连接，以提供数据信号，
    所述第一导电层还包括沿所述第一方向的第四转接电极、第五转接电极以及第六转接电极，
    所述第四转接电极连接所述第一数据线以及所述第一子像素驱动电路的数据写入晶体管的第二极，
    所述第五转接电极连接第二数据线以及所述第二子像素驱动电路的数据写入晶体管的第二极，
    所述第六转接电极连接所述第三数据线以及所述第三子像素驱动电路的数据写入晶体管的第二极。
  22. 根据权利要求10-20任一所述的显示基板，其中，所述第一栅线和所述第二栅线位于第二导电层，所述第一栅线靠近所述第一重复单元和所述第二重复单元的感测晶体管，所述第二栅线靠近所述第一重复单元和所述第二重复单元的数据写入晶体管，
    所述第一栅线包括折线部，所述折线部包括沿所述第一方向的第一折线部、分别与所述第一折线部两端连接的沿所述第二方向的第二折线部以及第三折线部，所述第一折线部、所述第二折线部以及所述第三折线部绕过所述第一连接走线，
    所述第一折线部在所述衬底基板的板面上的正投影，与所述第一重复单元的第一子像素驱动电路、第二子像素驱动电路以及第三子像素驱动电路的感测晶体管的有源层在所述衬底基板的板面上的正投影交叠，所述交叠部分形成所述感测晶体管的栅极。
  23. 根据权利要求22所述的显示基板，其中，在所述第二方向上，所述第一栅线与所述第一连接走线并列走线的部分位于所述第一连接走线的靠近所述第二重复单元的透明区的一侧。
  24. 根据权利要求22或23所述的显示基板，其中，所述第二导电层还包括第三连接走线、第四连接走线以及第五连接走线，
    所述第三连接走线、所述第四连接走线以及所述第五连接走线呈“L”形折线，所述第四连接走线和所述第五连接走线的弯折方向相同，所述第三连接走线的弯折方向与所述第四连接走线和所述第五连接走线的弯折方向相对，
    所述第三连接走线与所述第二栅线以及所述第一子像素驱动电路的数据写入晶体管的栅极连接，
    所述第四连接走线与所述第二栅线以及所述第二子像素驱动电路的数据写入晶体管的栅极连接，
    所述第五连接走线与所述第二栅线以及所述第三子像素驱动电路的数据写入晶体 管的栅极连接。
  25. 根据权利要求14所述的显示基板，其中，所述第一导电层包括沿所述第二方向的第七转接电极、第八转接电极以及第九转接电极，
    所述第七转接电极、所述第八转接电极以及所述第九转接电极在所述衬底基板的板面上的正投影与所述第二连接走线在所述衬底基板的板面上的正投影交叠，
    所述第七转接电极的第一端通过贯穿所述第二绝缘层的第八过孔的至少部分，与所述第一子像素驱动电路的驱动晶体管的栅极连接，所述第七转接电极的第二端与所述第一子像素驱动电路的数据写入晶体管的第一极连接，
    所述第八转接电极的第一端通过贯穿所述第二绝缘层的第九过孔的至少部分，与所述第二子像素驱动电路的驱动晶体管的栅极连接，所述第八转接电极的第二端与所述第二子像素驱动电路的数据写入晶体管的第一极连接，
    所述第九转接电极的第一端通过贯穿所述第二绝缘层的第十过孔的至少部分，与所述第三子像素驱动电路的驱动晶体管的栅极连接，所述第九转接电极的第二端与所述第三子像素驱动电路的数据写入晶体管的第一极连接。
  26. 一种显示装置，包括权利要求1-25任一所述的显示基板。
PCT/CN2021/083034 2021-03-25 2021-03-25 显示基板以及显示装置 WO2022198575A1 (zh)

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