WO2024021709A9 - 电子设备、设备识别方法及充电系统 - Google Patents

电子设备、设备识别方法及充电系统 Download PDF

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Publication number
WO2024021709A9
WO2024021709A9 PCT/CN2023/090096 CN2023090096W WO2024021709A9 WO 2024021709 A9 WO2024021709 A9 WO 2024021709A9 CN 2023090096 W CN2023090096 W CN 2023090096W WO 2024021709 A9 WO2024021709 A9 WO 2024021709A9
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WO
WIPO (PCT)
Prior art keywords
data pin
unit
processor
external interface
switch
Prior art date
Application number
PCT/CN2023/090096
Other languages
English (en)
French (fr)
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WO2024021709A1 (zh
Inventor
张庭唯
王丰
Original Assignee
荣耀终端有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 荣耀终端有限公司 filed Critical 荣耀终端有限公司
Priority to EP23797620.4A priority Critical patent/EP4336309A1/en
Publication of WO2024021709A1 publication Critical patent/WO2024021709A1/zh
Publication of WO2024021709A9 publication Critical patent/WO2024021709A9/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00034—Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00036—Charger exchanging data with battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00045—Authentication, i.e. circuits for checking compatibility between one component, e.g. a battery or a battery charger, and another component, e.g. a power source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/30—Charge provided using DC bus or data bus of a computer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • the present application relates to the field of electronic technology, and in particular to an electronic device, a device identification method and a charging system.
  • USB universal serial bus
  • the present application provides an electronic device, a device identification method and a charging system.
  • a charging protocol chip is added to provide a fast charging function to the outside, and the external interface of the electronic device is only electrically connected to one of the processor and the charging protocol chip at the same time, so that the charging protocol chip and the processor will not interfere with each other when identifying the external device, so that the electronic device can realize fast charging to the outside without affecting the identification of USB2.0 devices.
  • the present application provides an electronic device, which includes: a processor, a controller, a charging protocol chip, an external interface and a switch circuit; the processor, the charging protocol chip and the external interface all include a data pin unit; the data pin unit of the processor, the data pin unit of the charging protocol chip, the data pin unit of the external interface and the controller are electrically connected to the switch circuit respectively; the controller is used to control the switch circuit so that the data pin unit of the external interface is connected to one of the data pin unit of the processor and the data pin unit of the charging protocol chip, and is disconnected from the other of the data pin unit of the processor and the data pin unit of the charging protocol chip.
  • the data pin unit may include one data pin or multiple data pins
  • a first protocol identification path may be formed between the data pin unit of the external interface and the data pin unit of the processor, and the first protocol identification path is, for example, a USB2.0 protocol identification path.
  • a second protocol identification path may be formed between the data pin unit of the external interface and the data pin unit of the charging protocol chip, and the second protocol identification path is, for example, an SCP/FCP protocol identification path.
  • a charging protocol chip is added so that a fast charging function can be provided to an external device, and when the external device is electrically connected to the external interface, since only one of the processor and the charging protocol chip is connected to the external device, The external interface is electrically connected, so when identifying or interacting with external devices, the charging protocol chip and the processor will not interfere with each other. Therefore, the electronic device can realize fast charging of external devices without affecting the recognition of USB2.0 devices.
  • the external interface is used to be electrically connected to an external device;
  • the processor is used to perform a first protocol identification on the external device when the external interface is electrically connected to the external device and the data pin unit of the processor is turned on the pin unit of the external interface;
  • the charging protocol chip is used to perform a second protocol identification on the external device when the external interface is electrically connected to the external device and the data pin unit of the charging protocol chip is turned on the pin unit of the external interface;
  • the processor and the charging protocol chip are respectively electrically connected to the controller, and are used to send an indication indicating success or failure of protocol identification to the controller;
  • the controller is used to continue to control the switch circuit to connect the data pin unit of the external interface to the data pin unit of the processor after receiving the indication indicating success of the first protocol identification sent by the processor.
  • the pin unit is turned on and disconnected from the data pin unit of the charging protocol chip, and after receiving the indication sent by the processor indicating that the first protocol recognition fails, the switch circuit is controlled to disconnect the data pin unit of the external interface from the data pin unit of the processor and turn on the data pin unit of the charging protocol chip; the controller is used to continue to control the switch circuit to connect the data pin unit of the external interface with the data pin unit of the charging protocol chip and disconnect it from the data pin unit of the processor after receiving the indication sent by the charging protocol chip indicating that the second protocol recognition is successful, and after receiving the indication sent by the charging protocol chip indicating that the second protocol recognition fails, the switch circuit is controlled to disconnect the data pin unit of the external interface from the data pin unit of the charging protocol chip and turn on it with the data pin unit of the processor.
  • the controller can control the switch circuit according to the indication of the success or failure of the recognition of the processor or the charging protocol chip, and when the processor or the charging protocol chip recognizes successfully, the switch circuit is controlled to continue to conduct the corresponding protocol recognition path, and when the recognition fails, the switch circuit is controlled to switch to another protocol recognition path, so that the electronic device can realize fast charging of the external device without affecting the recognition of the USB2.0 device.
  • the controller controls the switch circuit to connect the data pin unit of the external interface with the data pin unit of the charging protocol chip and disconnect it from the data pin unit of the processor; and after receiving an indication sent by the charging protocol chip indicating that the second protocol identification has failed, the controller controls the switch circuit to disconnect the data pin unit of the external interface from the data pin unit of the charging protocol chip and connect it to the data pin unit of the processor.
  • the controller controls the switch circuit to connect the external interface with the charging protocol chip by default, and first identify the second protocol (such as the charging protocol) of the external device, and then identify the first protocol of the external device after the second protocol identification fails. In this way, since the second protocol identification is first performed on the external device, in the case where the second protocol has a time requirement for the identification process, the situation of protocol identification failure or error caused by the identification time exceeding the time set for the second protocol identification can be avoided.
  • the electronic device further includes a voltage conversion circuit and a battery, and the external interface further includes a power pin; the battery is electrically connected to the power pin of the external interface through the voltage conversion circuit; the charging protocol chip is connected to the voltage conversion circuit, and is used to send an enable signal to the voltage conversion circuit after the charging protocol chip successfully recognizes the protocol, so that the voltage conversion circuit provides a set voltage to the power pin of the external interface.
  • the electronic device can provide the required charging voltage according to the needs of the device to be charged, and realize fast charging of the external device.
  • the controller is further used to obtain the battery power information after receiving the indication sent by the charging protocol chip indicating that the second protocol is successfully identified, and send an indication to the charging protocol chip to start fast charging or not to start fast charging according to the battery power information. In this way, it can be determined whether to fast charge the external device according to the battery power of the electronic device, so as to avoid the inability to fast charge or affect the use of the electronic device due to too low power.
  • the controller sends an instruction to start fast charging to the charging protocol chip when the battery power is greater than a set threshold, and sends an instruction to not start fast charging to the charging protocol chip when the battery power is less than or equal to the set threshold. In this way, it is possible to determine whether to fast charge the external device based on the battery power of the electronic device, thereby avoiding the inability to fast charge or affecting the use of the electronic device due to low power.
  • the processor when the external device is a device that supports the first protocol, and the external device is unplugged from the external interface, the processor is also used to send an indication of the unplugging of the external device to the controller after the external device is unplugged, and the controller controls the switch circuit to disconnect the data pin unit of the external interface from the data pin unit of the processor and connect with the data pin unit of the charging protocol chip according to the indication of the unplugging of the external device.
  • the controller controls the switch circuit to connect the external interface and the charging protocol chip by default, and first identify the second protocol (such as the charging protocol) of the external device, so that in the case where the second protocol has a time requirement for the identification process, it can avoid the situation where the identification time exceeds the time set for the second protocol identification, resulting in protocol identification failure or error.
  • the second protocol such as the charging protocol
  • the switch circuit includes a switch chip, and the data pin unit of the processor, the data pin unit of the charging protocol chip, the data pin unit of the external interface, and the controller are electrically connected to the switch chip respectively.
  • the electrical connection control between the external interface, the processor, and the data pin unit of the charging protocol chip can be realized through a switch chip, ensuring that the processor and the charging protocol chip will not interfere with each other during the external device identification process.
  • the switch circuit includes a first switch unit and a second switch unit; the data pin unit of the processor, the data pin unit of the external interface, and the controller are electrically connected to the first switch unit, respectively, and the controller is used to control the first switch unit to connect or disconnect the data pin unit of the external interface with the data pin unit of the processor; the data pin unit of the charging protocol chip, the data pin unit of the external interface, and the controller are electrically connected to the second switch unit, respectively, and the controller is used to control the second switch unit to connect or disconnect the data pin unit of the external interface with the data pin unit of the charging protocol chip.
  • the electrical connection between the processor and the charging protocol chip and the external interface is controlled by the first switch unit and the second switch unit, respectively, to ensure that the processor and the charging protocol chip do not interfere with each other during the external device identification process.
  • the first switch unit and the second switch unit both include a switch chip.
  • the first switch unit and the second switch unit can both implement a switch chip, which can be used as required. It is necessary to select a suitable chip to control the electrical connection between the processor and the charging protocol chip and the external interface.
  • the data pin unit includes a first data pin and a second data pin;
  • the switching circuit includes first to fourth switching units; the first data pin of the processor, the first data pin of the external interface, and the controller are respectively electrically connected to the first switching unit, and the controller is used to control the first switching unit to connect or disconnect the first data pin of the external interface with the first data pin of the processor; the second data pin of the processor, the second data pin of the external interface, and the controller are respectively electrically connected to the second switching unit, and the controller is used to control the second switching unit to connect or disconnect the second data pin of the external interface with the second data pin of the processor; the first data pin of the charging protocol chip, the first data pin of the external interface, and the controller are respectively electrically connected to the third switching unit, and the controller is used to control the third switching unit to connect or disconnect the first data pin of the external interface with the first data pin of the charging protocol chip; the second data pin of the charging protocol chip, the second data pin of the external interface, and
  • the first to fourth switch units all include switch chips or MOS transistors.
  • a suitable switch chip or MOS transistor can be selected as needed to control the electrical connection between the processor and the charging protocol chip and the external interface.
  • the first switch unit includes a PMOS transistor
  • the second switch unit includes a PMOS transistor
  • the third switch unit includes an NMOS transistor
  • the fourth switch unit includes an NMOS transistor.
  • control of the four switch units can be achieved through one switch signal or the same switch signal, for example, the third and fourth switch units can be turned on and the first and second switch units can be turned off through the same high-level signal, and the third and fourth switch units can be turned on and the first and second switch units can be turned on through the same low-level signal, so that the control process is simplified.
  • the first protocol includes the USB 2.0 protocol
  • the second protocol includes the SCP/FCP fast charging protocol. This allows the electronic device to implement SCP/FCP fast charging of external devices without affecting the identification of USB 2.0 devices.
  • the data pin unit includes a DP pin or a DM pin.
  • the electronic device can realize fast charging of the external device without affecting the recognition of the USB2.0 device.
  • the present application provides a device identification method, which is applied to the electronic device of the first aspect.
  • Other methods include:
  • the controller controls the switch circuit to connect the data pin unit of the external interface to one of the data pin unit of the processor and the data pin unit of the charging protocol chip, and disconnect the data pin unit of the processor and the data pin unit of the charging protocol chip;
  • One of the processor and the charging protocol chip identifies the type of the external device connected to the external interface, wherein the type of the external device includes, for example, an external device supporting the first protocol and an external device supporting the second protocol.
  • the external device includes a USB2.0 device and a terminal to be charged;
  • the controller controls the switch circuit to disconnect the data pin unit of the external interface from one of the data pin unit of the processor and the data pin unit of the charging protocol chip, and connect the data pin unit of the processor and the data pin unit of the charging protocol chip to the other one;
  • the other of the processor and the charging protocol chip identifies the type of the external device connected to the external interface.
  • the electronic device can achieve fast charging of the external device without affecting the identification of the USB2.0 device.
  • the controller controls the switch circuit to connect the data pin unit of the external interface with the data pin unit of the charging protocol chip and disconnect the data pin unit of the processor; the charging protocol chip identifies the type of the external device; after the charging protocol chip fails to identify, the controller controls the switch circuit to disconnect the data pin unit of the external interface from one of the data pin units of the charging protocol chip and connect the data pin unit of the data pin unit of the processor; the processor identifies the type of the external device.
  • the second protocol identification is first performed on the external device, in the case where the second protocol has a time requirement for the identification process, it can avoid the situation where the identification time exceeds the time set by the second protocol identification, resulting in protocol identification failure or error.
  • the device identification method further includes: the processor sends an indication of the external device being unplugged to the controller after the external device is unplugged; after receiving the indication of the external device being unplugged, the controller controls the switch circuit to connect the data pin unit of the external interface to the data pin unit of the charging protocol chip and disconnect the data pin unit of the processor.
  • the controller controls the switch circuit to connect the external interface to the charging protocol chip by default, and first identify the second protocol (such as the charging protocol) of the external device, so that in the case where the second protocol has a time requirement for the identification process, it can avoid the situation where the identification time exceeds the time set for the second protocol identification, resulting in protocol identification failure or error.
  • the second protocol such as the charging protocol
  • the present application provides a charging system, comprising the electronic device and the terminal of the first aspect; the terminal comprises a charging interface and a battery; the charging interface is electrically connected to the external interface; the electronic device charges the battery in the terminal through the external interface and the charging interface. In this way, the terminal can be quickly charged using the electronic device, which improves the convenience of charging.
  • the present application provides a chip, the chip comprising a processing circuit and a transceiver pin, wherein the transceiver pin and the processing circuit communicate with each other through an internal connection path, and the processing circuit executes the method in the second aspect or any possible implementation of the second aspect to control the receiving pin to receive a signal and control the sending pin to send a signal.
  • FIG1 is a schematic diagram of one of the exemplary application scenarios
  • FIG. 2 is a schematic diagram showing a structure of an electronic device applied to the application scenario shown in FIG. 1 ;
  • FIG3 is a schematic diagram showing an exemplary USB 2.0 device identification principle
  • 4 to 6 are schematic diagrams showing exemplary SCP protocol identification principles
  • FIG7 is a schematic diagram exemplarily showing the structure of an electronic device according to an embodiment of the present application.
  • FIG8 is a schematic diagram exemplarily showing a connection between an electronic device and a terminal to be charged according to an embodiment of the present application
  • FIG9 is a schematic diagram showing a connection between an electronic device and a USB 2.0 device according to an embodiment of the present application.
  • FIG10 is a schematic diagram of the structure of an external interface according to an embodiment of the present application.
  • FIG11 is a schematic diagram exemplarily showing a switch circuit of an electronic device according to an embodiment of the present application.
  • FIG12 is a schematic diagram exemplarily showing another switch circuit of an electronic device according to an embodiment of the present application.
  • FIG13 is a schematic diagram exemplarily showing another switch circuit of an electronic device according to an embodiment of the present application.
  • FIG14 is a schematic diagram exemplarily showing another switch circuit of an electronic device according to an embodiment of the present application.
  • FIG15 is a schematic diagram showing a flow chart of a device identification method according to an embodiment of the present application.
  • FIG. 16 is a schematic block diagram showing an exemplary embodiment of a device according to an embodiment of the present application.
  • a and/or B in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist.
  • a and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects.
  • a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.
  • words such as “exemplary” or “for example” are used to indicate examples, illustrations or descriptions. Any embodiment or design described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as “exemplary” or “for example” is intended to present related concepts in a specific way.
  • multiple refers to two or more than two.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • FIG. 1 is a schematic diagram showing an application scenario.
  • the electronic device 100 may be, for example, a device such as a laptop computer, which is provided with an external interface such as a Type-C universal serial bus (USB) interface. Through the external interface, the electronic device 100 may be connected to an external device 200.
  • the external device 200 may be a terminal to be charged such as a mobile phone, a tablet, etc.
  • the external device 200 may also be a USB2.0 device such as a U disk, a mobile hard disk, etc.
  • a USB2.0 device is a storage device or an electronic device that supports the USB2.0 protocol.
  • the electronic device 100 may quickly charge a terminal to be charged 201 such as a mobile phone or a tablet through an external interface, and may also communicate or exchange data with an electronic device such as a U disk or a mobile hard disk, a hard disk, or other types of USB2.0 devices 202 to achieve functions such as communication, data reading or storage.
  • a terminal to be charged 201 such as a mobile phone or a tablet
  • an electronic device such as a U disk or a mobile hard disk, a hard disk, or other types of USB2.0 devices 202 to achieve functions such as communication, data reading or storage.
  • the electronic device 100 can provide a fast charging function for a terminal 201 to be charged, such as a mobile phone or a tablet.
  • fast charging refers to charging with a charging power greater than 10W, for example, 18W, 22.5W, 40W, 60W, 100W, etc.
  • the electronic device 100 supports the Super Charge Protocol/Fast Charge Protocol (SCP)/Fast Charger Protocol, FCP). Through an external interface, the electronic device 100 can fast charge the terminal 201 to be charged that supports the SCP/FCP protocol.
  • SCP Super Charge Protocol/Fast Charge Protocol
  • FCP Full Charger Protocol
  • FIG. 2 is a schematic diagram of the structure of an electronic device 100 exemplarily applied to the application scenario shown in FIG. 1 .
  • the electronic device 100 includes a processor 110, a controller 120, a charging protocol chip 130, an external interface 140, a voltage conversion circuit 150, and a battery 160.
  • the external interface 140 may be exemplarily a type-C USB interface.
  • the processor 110 includes a first data pin 111 (e.g., DP or D+) and a second data pin (e.g., DM or D-).
  • the charging protocol chip 130 includes a first data pin 131 (e.g., DP or D+) and a second data pin 132 (e.g., DM or D-).
  • the external interface 140 includes a first data pin 141 (e.g., DP or D+) and a second data pin 142 (e.g., DM or D-).
  • the first data pin 141 and the second data pin 142 of the external interface 140 are respectively connected to the first data pin 111 and the second data pin 112 of the processor 110 to form a first protocol identification path.
  • the first protocol identification path is, for example, a USB2.0 device protocol identification path.
  • first data pin 141 and the second data pin 142 of the external interface 140 are respectively connected to the first data pin 131 and the second data pin 132 of the charging protocol chip 130 to form a second protocol identification path.
  • the second protocol identification path is, for example, a fast charging protocol identification path.
  • the first data pin 111 and the second data pin 112 of the processor 110 are grounded through, for example, a 15K ohm pull-down resistor R.
  • the first data pin 131 and the second data pin 132 of the charging protocol chip 130 are grounded through, for example, a 15K ohm pull-down resistor R.
  • the USB2.0 protocol and the SCP/FCP protocol of the electronic device 100 are both used to perform device identification through the pull-down resistor configuration level in the electronic device 100.
  • the processor 110 determines whether the device connected to the external interface 140 is a USB 2.0 device by detecting the levels of the first data pin 111 and the second data pin 112 of the processor 110.
  • the charging protocol chip 130 determines whether the device connected to the external interface 140 is a terminal device supporting the SCP/FCP protocol by detecting the levels of the first data pin 131 and the second data pin 132 of the charging protocol chip 130.
  • FIG3 is a schematic diagram of the USB2.0 device identification principle.
  • the data pins DP and DM of the processor 110 are grounded through pull-down resistors.
  • the USB high-speed/full-speed device includes a USB2.0 protocol chip and data pins DP and DM, and the DP pin is connected to the power supply Vcc through a pull-up resistor.
  • the USB low-speed device includes a USB2.0 protocol chip and data pins DP and DM, and the DM pin is connected to a power source Vcc via a pull-up resistor, wherein the resistance value of the pull-up resistor is, for example, 1.5K ⁇ .
  • the pull-down resistors connected to the DP pin and the DM pin make the voltages of the two data lines close to the ground (see (1) in FIG. 3).
  • the pull-down resistor connected to the data pin DP of the processor 110 and the pull-up resistor connected to the data pin DP of the external device 200 form a voltage divider. Since the resistance value of the pull-down resistor is 15K ⁇ and the resistance value of the pull-up resistor is 1.5K ⁇ , a DC high-level voltage of (Vcc*15/(15+1.5)) will appear on the data pin DP of the processor 110.
  • the processor 110 detects that the DP pin voltage is close to a high level and the DM pin remains grounded, it can be determined that a full-speed/high-speed USB2.0 device is connected.
  • the processor 110 detects that the DM pin voltage is close to a high level and the DP pin remains grounded, it can be determined that a low-speed USB2.0 device is connected.
  • USB 2.0 device identification process/method is only an example, and the embodiments of the present application may adopt other methods for identification based on the above principles or similar principles.
  • the SCP protocol detection process will first detect whether the charging interface is a dedicated charging interface (DCP interface) through BC1.2.
  • DCP interface dedicated charging interface
  • the detection principle of the SCP protocol is exemplarily described below in conjunction with Figures 4 to 6.
  • FIGS. 4 to 6 are schematic diagrams showing the SCP protocol identification principle.
  • the charging protocol BC1.2 Battery Charging Specification 1.2
  • the charging protocol BC1.2 defines three types of interfaces:
  • Standard Downstream Port is a USB port that supports the USB protocol.
  • the maximum current is 2.5mA when suspended and 100mA when connected and not suspended. Its DP and DM pins each have a 15k resistor connected to GND.
  • Dedicated Charging Port does not support any data transmission, but can provide more than 1.5A current. This type of interface supports wall chargers and car chargers with higher charging capabilities without enumeration.
  • CDP Charging Downstream Port
  • DP and DM pins have 15k ⁇ pull-down resistors necessary for communication, and also have internal circuits that switch during the charger detection phase. This internal circuit allows the device to distinguish CDP from other types of ports.
  • FIG. 4 it shows the working mode (dashed area in FIG. 4 ) when the USB interface of the terminal PD (portable device, such as the charging terminal 201) is connected to the external interface for data detection.
  • the DP pin of the terminal PD is maintained at a high level.
  • the minimum value requirement of the current source IDP_SRC (7uA) can ensure that the DP pin is maintained at the level VLGC_HI (for example, 4.0 ⁇ 3.6V) under the worst leakage current (RDAT_LKG and VDAT_LKG).
  • the DP pin is pulled down by the pull-down electronics RDP_DWN of the SDP interface.
  • the maximum value of the current source IDP_SRC (13uA) is required to ensure that under the worst leakage current (RDAT_LKG, VDAT_LKG and RDP_DWN), RDP_DWN keeps the DP pin at VLGC_LOW (Logic Low 0 ⁇ 0.8V). Therefore, after VBUS is valid, the current source IDP_SRC of the DP pin and the current source IDP_SRC of the DM pin are enabled.
  • the pull-down resistor can detect the level of the DP pin to determine whether the external interface connected to the terminal PD supports the data protocol.
  • FIG5 it shows the working mode when the USB interface of the terminal PD is connected to the DCP interface for the main detection (the dotted area in FIG5 ).
  • the main detection process is, for example: the terminal device PD turns on the voltage source VDP_SRC (for example, 0.5 to 0.7v) of the DP pin and the current source IDM_SINK (for example, 25 to 175 ⁇ A) of the DM pin.
  • VDP_SRC for example, 0.5 to 0.7v
  • IDM_SINK for example, 25 to 175 ⁇ A
  • the voltage comparator of the terminal PD at the DM pin compares the DM voltage with VDAT_REF (for example, 0.25 to 0.4v). If the DM pin voltage is greater than VDAT_REF, it can be determined that the terminal PD is connected to the charging interface, and then secondary detection is used to determine whether it is connected to the DCP interface or the CDP interface.
  • VDAT_REF for example 0.25 to 0.4v
  • FIG6 it shows the working mode when the USB interface of the terminal PD is connected to the DCP interface for secondary detection (the dotted area in FIG6 ).
  • the secondary detection process is, for example, as follows: the terminal PD enables the voltage source VDM_SRC on the DM pin, turns on the current source IDP_SINK, and then compares the voltage of the DP pin with the voltage of VDAT_REF. Because the DCP interface shorts the DP and DM pins through the shorting resistor RDCP_DAT inside, the voltage of the voltage source VDM_SRC makes VDAT_REF ⁇ DP ⁇ VDM_SRC. Therefore, when the terminal PD detects that VDAT_REF ⁇ DP pin voltage, it can be determined that the terminal is connected to the DCP interface.
  • the levels of the first data pin and the second data pin of the external interface 140 will change.
  • the first data pin 141 and the second data pin 142 of the external interface 140 are directly connected to the first data pin and the second data pin of the processor 110 and the charging protocol chip 130 (that is, the first and second protocol identification paths are both in the on state), and the same pull-down resistor is used, the pull-down resistors of each other will affect the protocol identification of the other party.
  • the processor 110 can also detect the level change of its first data pin and the second data pin, causing the external device to be identified as a USB2.0 device, or causing interference to the charging protocol identification of the external device, resulting in identification failure, which causes the electronic device 100 to neither correctly identify the USB2.0 device nor fast charge the charging terminal such as a mobile phone.
  • the embodiment of the present application provides an electronic device, a device identification method and a charging system, wherein the charging system includes the electronic device and a terminal, wherein the electronic device can charge the terminal.
  • the charging system includes the electronic device and a terminal, wherein the electronic device can charge the terminal.
  • the electronic device can be a device equipped with an external interface such as a laptop, an all-in-one computer, a desktop computer, etc.
  • the terminal can be a mobile phone, a laptop, a tablet computer, a personal digital assistant (PDA for short), a car computer, a television, a smart wearable device (such as a smart watch, etc.), a media player, a smart home device waiting for charging, and the embodiment of the present application does not specifically limit the specific form of the above-mentioned terminal.
  • PDA personal digital assistant
  • the embodiments of the present application are all explained by taking the electronic device as a laptop and the terminal as a mobile phone as an example.
  • the SCP/FCP protocol is used as an example in the above description.
  • the following also takes the SCP/FCP protocol as an example for explanation.
  • FIG7 is a schematic diagram showing the structure of an electronic device according to an embodiment of the present application.
  • the electronic device 100 includes a processor 110 , a controller 120 , a charging protocol chip 130 , an external interface 140 , a voltage conversion circuit 150 , a battery 160 , and a switch circuit 170 .
  • the electronic device 100 may also include one or more modules such as a power management module, an antenna, a wireless communication module, a mouse, an indicator, a keyboard, a camera, a display screen, an audio module, a speaker, a speaker interface, a microphone, etc., or may also include other modules, which are not specifically limited here.
  • modules such as a power management module, an antenna, a wireless communication module, a mouse, an indicator, a keyboard, a camera, a display screen, an audio module, a speaker, a speaker interface, a microphone, etc., or may also include other modules, which are not specifically limited here.
  • the processor 110 may include one or more processing units, for example, the processor 110 may include an application processor, a modem processor, a graphics processor GPU, an ISP, a memory, a video codec, a DSP, a baseband processor, and/or an NPU, etc. Different processing units may be independent devices or integrated into one or more processors.
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in the processor 110 is a cache memory.
  • the memory may store instructions or data that the processor 110 has just used or circulated. If the processor 10 needs to use the instruction or data again, it may be directly called from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thereby improving the efficiency of the system.
  • the processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit I2C interface, an integrated circuit built-in audio I2S interface, an eSPI interface, a PCM interface, a UART interface, a MIPI, a GPIO interface and/or a USB interface, etc.
  • the processor 110 includes a first data pin 111 and a second data pin 112.
  • the processor 110 is connected to the external interface 140 through the first data pin 111 and the second data pin 112, so as to perform data interaction or communication with the external device.
  • the first data pin 111 and the second data pin 112 of the processor 110 are grounded through a pull-down resistor R of, for example, 15K ohms.
  • the controller 120 is, for example, an embedded controller EC, which is used to implement functions such as keyboard control, touchpad, power management, fan control, etc.
  • the controller 120 may include independently running software stored in its own non-volatile medium.
  • the controller 120 may include one or more interfaces.
  • the interface may include a general input and output interface (GPIO), an eSPI (Enhanced Serial Peripheral) interface, an integrated circuit I2C interface, etc.
  • the controller 120 may be connected and communicated with the processor 110 through, for example, an eSPI interface and an eSPI bus.
  • the controller 120 may also be connected to the switch circuit 170 through, for example, a GPIO interface to output a control signal to the switch circuit 170 to control the switch circuit 170.
  • the controller 120 may also be connected to the charging protocol chip 130 through, for example, an integrated circuit I2C interface to communicate with the charging protocol chip 130.
  • the charging protocol chip 130 is, for example, a fast charging protocol chip supporting the SCP protocol, which is used for fast charging protocol identification and charging communication.
  • the charging protocol chip 130 includes a first data pin 131 and a second data pin 132.
  • the charging protocol chip 130 is connected to the external interface 140 through the first data pin 131 and the second data pin 132, so as to provide a fast charging protocol for external devices.
  • the first data pin 131 and the second data pin 132 of the charging protocol chip 130 are grounded through a pull-down resistor R of, for example, 15K ohms.
  • the charging protocol chip 130 may include one or more interfaces.
  • the interface may include an integrated circuit I2C interface, etc.
  • the charging protocol chip 130 is connected to the controller 120 through, for example, an I2C interface and an I2C bus.
  • the charging protocol chip 130 may send an indication or signal of success or failure of fast charging protocol recognition to the controller 120.
  • the charging protocol chip 130 is also connected to the voltage conversion circuit 150, and is used to send an enable signal to the voltage conversion circuit 150 after the fast charging protocol is successfully recognized, so that the voltage conversion circuit 150 outputs the charging voltage required by the terminal to the external port.
  • the external interface 140 can be exemplarily a type-C USB interface.
  • the external interface 140 includes a first data pin 141 and a second data pin 142.
  • the external interface 140 also includes a power pin VBUS and a communication pin.
  • the first data pin 141 and the second data pin 142 of the external interface 140 are respectively connected to the first data pin 111 and the second data pin 112 of the processor 110 on the one hand, forming a first protocol identification path (that is, a USB2.0 device protocol identification path); on the other hand, they are respectively connected to the first data pin 131 and the second data pin 132 of the charging protocol chip 130 to form a second protocol identification path (that is, a fast charging protocol identification path).
  • the battery 160 supplies power to the external interface 140 through the voltage conversion circuit 150, thereby supplying power or charging external devices.
  • the battery 160 also supplies power to the processor 110, the controller 120, the charging protocol chip 130, and the like.
  • the switch circuit 170 is arranged between the first data pin 141, the second data pin 142 of the external interface 140 and the processor 110 and the first data pin and the second data pin of the charging protocol chip 130, and is connected to the controller 120. Under the control of the controller 120, the switch circuit 170 enables only one of the first protocol identification path and the second protocol identification path to be turned on at the same time, thereby avoiding the interference of the two protocol identification paths to each other. In the embodiment of the present application, the switch circuit 170 defaults to the second protocol identification path being turned on under the control of the controller 120, and disconnects the second protocol identification path after the fast charging protocol identification fails, and turns on the first protocol identification path, and then identifies the USB2.0 device.
  • FIG8 is a schematic diagram of the connection between an electronic device and a terminal to be charged according to an embodiment of the present application.
  • the external interface 140 includes a first data pin 141 (e.g., DP), a second data pin 142 (e.g., DM), a first communication pin 143 (e.g., CC1), a second communication pin 144 (e.g., CC2), and a power pin 145 (e.g., VBUS pin).
  • a switch circuit for shorting the first data pin 141 and the second data pin 142 is provided inside the charging protocol chip 130.
  • the first communication pin 143 and the second communication pin 144 are connected to the power supply VCC (e.g., 5V) through a pull-up resistor.
  • VCC e.g., 5V
  • the terminal 201 to be charged includes a charging protocol chip 210, a battery 220, and a charging interface 230.
  • the charging interface 230 includes a first data pin 231 (e.g., DP), a second data pin 232 (e.g., DM), a first communication pin 233 (e.g., CC1), a second communication pin 234 (e.g., CC2), and a power pin 235 (e.g., VBUS pin).
  • the first communication pin 233 and the second communication pin 234 are grounded through a pull-down resistor.
  • the controller 120 controls the switch circuit 170 to open the charging protocol chip 130 and the first data pin 141 (eg DP) and the second protocol channel between the second data pin 142.
  • the terminal 201 to be charged is connected to the electronic device 100, that is, the charging interface 230 of the terminal 201 to be charged is connected to the external interface 140 of the electronic device 100
  • the power pin 145 of the electronic device 100 is connected to the power pin 235 of the terminal 201 to be charged, forming a power channel or a charging channel, through which the electronic device 100 can power the terminal 201 to be charged.
  • the first data pin 141 and the second data pin 142 of the electronic device 100 are respectively connected to the first data pin 231 and the second data pin 232 of the terminal 201 to be charged to form a protocol channel.
  • the electronic device 100 performs protocol communication with the terminal 201 to be charged through the protocol channel.
  • the first communication pin 143 and the second communication pin 144 of the electronic device 100 are respectively connected to the first communication pin 233 and the second communication pin 234 of the terminal 201 to be charged to form a handshake channel.
  • the electronic device 100 completes handshake with the terminal 201 to be charged through the handshake channel.
  • the charging protocol chip 130 and the charging protocol chip 210 adopt, for example, the SCP protocol.
  • the electronic device 100 completes a handshake with the terminal 201 to be charged through a handshake channel (that is, the charging protocol chip 130 completes a handshake with the charging protocol chip 210), and then provides a Vbus voltage of, for example, 5V to the power pin/power channel.
  • the handshake process between the electronic device 100 and the terminal 201 to be charged can be completed using various suitable handshake protocols.
  • a pull-up resistor is connected to the first communication pin 143 and the second communication pin 144 of the electronic device 100, and a pull-down resistor is connected to the first communication pin 233 and the second communication pin 234 of the terminal 201 to be charged.
  • the power pin 145 of the electronic device 100 Before the electronic device 100 is not connected to the terminal 201 to be charged, the power pin 145 of the electronic device 100 has no voltage output.
  • the first communication pin 143 and the second communication pin 144 of the electronic device 100 are respectively connected to the first communication pin 233 and the second communication pin 234 of the terminal 201 to be charged, forming a voltage divider.
  • the charging protocol chip 130 detects the pull-down resistance of the first communication pin 233 and the second communication pin 234 of the terminal 201 to be charged by detecting the level of the first communication pin 143 and the second communication pin 144, thereby determining whether the terminal 201 to be charged is connected to the external interface 140. Then the electronic device 100 closes the switch of the power pin 145 (not shown in FIG. 8), and outputs, for example, 5V Vbus power to the terminal 201 to be charged.
  • the charging protocol chip 130 closes the switch circuit that shorts the first data pin 141 and the second data pin 142, so that the first data pin 141 and the second data pin 142 are short-circuited.
  • the charging terminal 201 identifies whether the electronic device 100 is a DCP (Dedicated Charging Port) device based on the BC1.2 protocol (Battery Charging v1.2) (SCP fast charging protocol needs to first identify whether the electronic device 100 is a DCP device through the BC1.2 protocol).
  • the identification process is, for example, as follows: after the power pin 235 is powered on, the terminal 201 to be charged first performs a data connection detection.
  • the process of data connection detection is described in conjunction with FIG. 4 above and will not be described again here. If no data protocol support is detected within a set time (e.g., 300 to 900 ms), the terminal 201 to be charged will perform a DCP detection.
  • the DCP detection process can refer to the above description in combination with Figures 5 and 6.
  • the charging protocol chip 210 turns on the voltage source VDP_SRC of the first data pin 231 (for example, 0.5 ⁇ 0.7v, not shown in Figure 8, see Figures 5 and 6 for the setting method) and the current source IDM_SINK of the second data pin 232 (for example, 25 ⁇ 175 ⁇ A, not shown in Figure 8, see Figures 5 and 6 for the setting method).
  • the first data pin 231 and the second data pin 232 are shorted by the shorting resistor in the charging protocol chip 130, and the charging protocol chip 210 detects whether the voltage of the second data pin 232 reaches VDP_SRC.
  • the charging protocol chip 210 compares the voltage of the second data pin 232 with VDAT_REF (for example, 0.25 ⁇ 0.4v) at the voltage comparator of the second data pin 232 (not shown in Figure 8, see Figures 5 and 6 for the setting method). If the voltage of the second data pin 232 is greater than VDAT_REF, it can be determined that the terminal 201 to be charged is connected to the charging terminal. The secondary detection is then performed to determine whether the device is connected to a DCP interface or a CDP interface.
  • VDAT_REF for example, 0.25 ⁇ 0.4v
  • the charging protocol chip 210 enables the voltage source VDM_SRC on the second data pin 232 (not shown in FIG. 8 , see FIG. 5 and FIG. 6 for the setting method), turns on the current source IDP_SINK (not shown in FIG. 8 , see FIG. 5 and FIG. 6 for the setting method), and then compares the voltage of the first data pin 231 with the voltage of VDAT_REF. Because the first data pin 231 and the second data pin 232 are short-circuited by the short-circuit resistor in the charging protocol chip 130, the voltage of the voltage source VDM_SRC makes VDAT_REF ⁇ DP ⁇ VDM_SRC. Therefore, when the charging protocol chip 210 detects that VDAT_REF ⁇ DP pin voltage, it can be determined that the terminal 201 to be charged is connected to the DCP interface.
  • the charging protocol chip 130 continuously detects the relevant signal level, and disconnects the short circuit between the first data pin 141 and the second data pin 142 after a certain period of time, and determines whether to enter the fast charging mode (such as SCP fast charging) according to the set conditions. If it is determined to enter the fast charging mode, the charging protocol chip 130 communicates with the charging protocol chip 130 to adjust the voltage to determine the charging voltage and current required by the terminal 201 to be charged.
  • the fast charging mode such as SCP fast charging
  • handshake circuit, data detection circuit, and DCP detection circuit used in the above identification process are only exemplary, and the embodiments of the present application are not limited thereto, as long as the corresponding detection requirements of the BC1.2 and/or SCP protocols can be achieved.
  • FIG9 is a schematic diagram of the connection between an electronic device and a USB2.0 device according to an embodiment of the present application.
  • the external interface 140 includes a first data pin 141, a second data pin 142, and a power pin 145.
  • the USB2.0 device 202 includes a USB2.0 protocol chip 240, a storage unit 250, and a USB interface 260.
  • the USB interface 260 includes a first data pin 261, a second data pin 262, and a power pin 263. Based on the USB2.0 protocol, the USB2.0 device 202 will connect a pull-up resistor of, for example, 1.5K ohms to the first data pin 261P or the second data pin 262 according to different levels of the transmission rate.
  • the identification process of the USB2.0 device 202 is described in conjunction with FIG3 above, and will not be repeated here.
  • the charging protocol detection is first performed, as shown in the above content, which will not be repeated here. If the charging protocol detection fails, the controller 120 controls the switch circuit 170 to open the protocol path between the processor 110 and the first data pin 141 and the second data pin 142. As a host, the processor 110 can identify the USB2.0 device and its speed type through the level changes of the first data pin 141 and the second data pin 142 as long as it detects the pull-up resistor of the USB2.0 device. There is no insertion time limit for this identification process.
  • the electronic device 100 will first perform a fast charging protocol detection, so the identification of the USB 2.0 device is delayed. However, this delay is difficult for the user to perceive, so it does not reduce the user experience.
  • the embodiments of the present application do not limit the types of the external interface 140, the charging interface 230 and the USB interface 260, which may include, for example, a Type C USB interface, a Type A USB interface, etc.
  • the external interface 140 when the external interface 140 is a Type C USB interface, the external interface 140 includes an A side and a B side.
  • the A side includes a VBUS1 pin (pin A4) and a VBUS2 pin (pin A9)
  • the B side includes a VBUS2 pin (pin B9) and a VBUS1 pin (pin B4).
  • the VBUS1 pin (pin A4) of the A side is electrically connected to the VBUS1 pin (pin B4) of the B side
  • the VBUS2 pin (pin A9) of the A side is electrically connected to the VBUS2 pin (pin B9).
  • the VBUS1 pin (pin A4) of side A and the VBUS1 pin (pin B4) of side B are first power pins, which can be used as power pins 145, 235, 263.
  • the VBUS2 pin (pin A9) of side A and the VBUS1 pin (pin B4) of side B are second power pins, which can be used as power pins 145, 235, 263.
  • the DP pin pin A6 of side A and pin B6 of side B
  • the DM pin pin A7 of side A and pin B7 of side B
  • the CC1 pin pin A5 of side A
  • the CC2 pin pin B5 of side B
  • the external interface 140 shown in FIG. 10 can realize flexible forward and reverse insertion of the power cord, and can complete the connection of the external device 200 regardless of the insertion direction. There is no need to set up additional forward and reverse insertion software and hardware detection mechanisms to accurately match the power channel, protocol channel/data channel and handshake channel.
  • the external interface in Figure 10 is merely exemplary.
  • the external interface 140 may be other types of interfaces, such as a type A USB interface, or a Type C USB interface including fewer pins than those shown in Figure 10 , such as a Type C USB interface that does not include the TX1+, TX1-, RX2+, RX2-, etc. pins in Figure 10 .
  • FIG11 is a schematic diagram of a switch circuit of an electronic device according to an embodiment of the present application, which is exemplarily shown.
  • the switch circuit 170 includes four switch devices 10.
  • the switch device 10 includes a first switch transistor 11, a second switch transistor 12, a third switch transistor 13, and a fourth switch transistor 14.
  • the first switch transistor 11, the second switch transistor 12, the third switch transistor 13, and the fourth switch transistor 14 each include a first end, a second end, and a control end.
  • the controller 120 includes a general input and output interface (GPIO), and the general input and output interface (GPIO) of the controller 120 includes a first control pin, a second control pin, a third control pin, and a fourth control pin.
  • GPIO general input and output interface
  • the first end of the first switch transistor 11 is connected to the first data pin 141 of the external interface 140, the second end is connected to the first data pin 111 of the processor 110, and the control end is connected to the first control pin of the general input and output interface (GPIO) of the controller 120.
  • the first end of the first switch transistor 12 is connected to the second data pin 142 of the external interface 140, the second end is connected to the second data pin 112 of the processor 110, and the control end is connected to the second control pin of the general input and output interface (GPIO) of the controller 120.
  • the first end of the third switch transistor 13 is connected to the first data pin 111 of the external interface 140, the second end is connected to the first data pin 131 of the charging protocol chip 130, and the control end is connected to the third control pin of the general input and output interface (GPIO) of the controller 120.
  • the first end of the fourth switch transistor 14 is connected to the second data pin 142 of the USB interface 140, the second end is connected to the second data pin 132 of the charging protocol chip 130, and the control end is connected to the fourth control pin of the general input and output interface (GPIO) of the controller 120.
  • the controller 120 outputs a level signal or a control signal to the control ends of the first switch transistor 11, the second switch transistor 12, the third switch transistor 13 and the fourth switch transistor 14 through the first control pin, the second control pin, the third control pin and the fourth control pin of the GPIO interface to control the conduction or disconnection of the first switch transistor 11, the second switch transistor 12, the third switch transistor 13 and the fourth switch transistor 14.
  • the charging protocol chip 130 communicates with the external device through the second protocol identification path, thereby Charging protocol identification, determine whether the external device supports the corresponding charging protocol (such as SCP protocol), please refer to the above content for details.
  • the charging protocol chip 130 sends an indication of successful charging protocol identification to the controller 120, and the controller 120 determines whether to start fast charging to charge the external device based on the current state of the battery 160, such as the remaining power, the current output voltage, etc. For example, when the remaining battery power is greater than the set threshold (for example, 30%), it is determined to start fast charging.
  • the charging protocol chip 130 sends an enable signal to the voltage conversion circuit 150, and the voltage conversion circuit 150 fast charges the external device through the external interface 140 according to the charging voltage and current determined by the charging protocol chip 130.
  • the charging protocol chip 130 sends an indication of the charging protocol recognition failure to the controller 120.
  • the controller 120 changes the level signal or control signal output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface according to the indication, so that the third switch transistor 13 and the fourth switch transistor 14 are disconnected, the first switch transistor 11 and the second switch transistor 12 are turned on, so that the second protocol recognition path is disconnected and the first protocol recognition path is turned on.
  • the processor 110 communicates with the external device through the first protocol recognition path, thereby performing USB2.0 protocol recognition and determining whether the external device is a USB2.0 device (see the above description for the USB2.0 recognition process).
  • the external device When it is determined that the external device is a USB2.0 device, subsequent operations are performed based on the device type, such as data reading or storage, etc. For example, when the USB2.0 device is a high-speed storage device, high-speed data reading or storage is performed with the USB2.0 device. When the USB2.0 device is a low-speed storage device, low-speed data reading or storage is performed with the USB2.0 device.
  • the processor 110 sends an indication of the USB2.0 device being unplugged to the controller 120 through, for example, the eSPI bus.
  • the controller 120 changes the level signal or control signal output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, so that the third switch transistor 13 and the fourth switch transistor 14 are turned on, and the first switch transistor 11 and the second switch transistor 12 are turned off, so that the second protocol identification path is turned on, and the first protocol identification path is turned off, and the next external device connection is waited for again, and the above identification process is repeated.
  • the first switch transistor 11 and the second switch transistor 12 may be PMOS transistors
  • the third switch transistor 13 and the fourth switch transistor 14 may be NMOS transistors.
  • the controller 120 is configured to pull up the levels of the four pins of GIPO connected to the control end of the switch transistor by default (i.e., output a high level), so that the first switch transistor 11 and the second switch transistor 12 are disconnected, and the third switch transistor 13 and the fourth switch transistor 14 are turned on, so that the first protocol identification path is disconnected and the second protocol identification path is turned on.
  • the controller 120 pulls down the levels of the first control pin, the second control pin, the third control pin, and the fourth control pin of the GIPO interface (i.e., outputs a low level), so that the first switch transistor 11 and the second switch transistor 12 are turned on, and the third switch transistor 13 and the fourth switch transistor 14 are turned off, so that the first protocol identification path is turned on and the second protocol identification path is turned off.
  • the controller 120 again pulls up the levels of the first control pin, the second control pin, the third control pin, and the fourth control pin of the GIPO interface (i.e., outputs a high level), so that the second protocol identification path is turned on by default and the first protocol identification path is turned off by default.
  • the GPIO interface of the controller 120 uses four control pins to control the first to fourth switching transistors, in other embodiments, only one control pin may be used to control the first to fourth switching transistors, or two control pins may be used to control the first to fourth switching transistors.
  • the control terminals of the first to fourth switch transistors are all connected to the control pin, and the level output by the control pin turns on the first to second switch transistors, and turns off the third and fourth switch transistors. Or the third and fourth switch transistors are turned on, and the first to second switch transistors are turned off.
  • the first and second switch transistors are of the same type
  • the third and fourth switch transistors are of the same type
  • the first switch transistor and the third switch transistor are of opposite types.
  • the aforementioned exemplary first switch transistor 11 and the second switch transistor 12 can be PMOS transistors
  • the third switch transistor 13 and the fourth switch transistor 14 can be NMOS transistors.
  • the first switch transistor 11 and the second switch transistor 12 can be NMOS transistors
  • the third switch transistor 13 and the fourth switch transistor 14 can be PMOS transistors. In this way, only one control pin is needed to realize the control of the four switch transistors, which reduces the pin occupancy of the controller GPIO interface, and the control signal is relatively simple.
  • the control ends of the first to second switch transistors are connected to the first control pin, and the control ends of the third to fourth switch transistors are connected to the second control pin.
  • the first to second switch transistors are turned on and the third and fourth switch transistors are turned off by the levels output by the first and second control pins, or the third and fourth switch transistors are turned on and the first to second switch transistors are turned off.
  • the first and second switch transistors are of the same type, and the third and fourth switch transistors are of the same type, without the need for the first switch transistor and the third switch transistor to be of opposite types.
  • the first switch transistor 11 and the second switch transistor 12 can be PMOS transistors, and the third switch transistor 13 and the fourth switch transistor 14 can be PMOS transistors.
  • the first switch transistor 11 and the second switch transistor 12 can be NMOS transistors, and the third switch transistor 13 and the fourth switch transistor 14 can be NMOS transistors.
  • the first switch transistor 11 and the second switch transistor 12 can be PMOS transistors, and the third switch transistor 13 and the fourth switch transistor 14 can be NMOS transistors.
  • the first switch transistor 11 and the second switch transistor 12 can be PMOS transistors, and the third switch transistor 13 and the fourth switch transistor 14 can be NMOS transistors.
  • the first switch transistor 11 and the second switch transistor 12 can be NMOS transistors, and the third switch transistor 13 and the fourth switch transistor 14 can be PMOS transistors.
  • the first switch transistor 11 and the second switch transistor 12 can be NMOS transistors, and the third switch transistor 13 and the fourth switch transistor 14 can be PMOS transistors.
  • the above control effect can be achieved by simply adjusting the level of the controller control pin output according to the type of the switching transistor.
  • the types of the first to fourth switch transistors can all be P-type or N-type, and need not be the same.
  • FIG12 is a schematic diagram of another switch circuit of an electronic device according to an embodiment of the present application.
  • the switch circuit 170 includes four switch devices 20.
  • the switch device 20 includes a first switch chip 21, a second switch chip 22, a third switch chip 23, and a fourth switch chip 24.
  • the first switch chip 21, the second switch chip 22, the third switch chip 23, and the fourth switch chip 24 each include a first end, a second end, and a control end.
  • the first end of the first switch chip 21 is connected to the first data pin 141 of the external interface 140, the second end is connected to the first data pin 111 of the processor 110, and the control end is connected to the first control pin of the general input and output interface (GPIO) of the controller 120.
  • the first end of the second switch chip 22 is connected to the second data pin 142 of the external interface 140, the second end is connected to the second data pin 112 of the processor 110, and the control end is connected to the second control pin of the general input and output interface (GPIO) of the controller 120.
  • the first end of the third switch chip 23 is connected to the first data pin 111 of the external interface 140, the second end is connected to the first data pin 131 of the charging protocol chip 130, and the control end is connected to the third control pin of the general input and output interface (GPIO) of the controller 120.
  • the first end of the fourth switch chip 24 is connected to the second data pin 142 of the external interface 140, the second end is connected to the second data pin 142 of the charging protocol chip 130, and the control end is connected to the fourth control pin of the general input and output interface (GPIO) of the controller 120.
  • the controller 120 outputs a level signal or a control signal to the control ends of the first switch chip 21, the second switch chip 22, the third switch chip 23, and the fourth switch chip 24 through the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, thereby controlling the first switch chip 21,
  • the second switch chip 22 , the third switch chip 23 and the fourth switch chip 24 are turned on and off.
  • the working principle of the switch circuit of the electronic device shown in FIG. 12 is similar to the working principle of the switch circuit of the electronic device shown in FIG. 11 , and will not be described in detail here.
  • FIG13 is a schematic diagram of another switch circuit connected to an electronic device according to an embodiment of the present application.
  • the switch circuit 170 includes two switch devices 30.
  • the switch device 30 includes a first switch chip 31 and a second switch chip 32.
  • the first switch chip 31 and the second switch chip 32 each include two input terminals, two output terminals and a control terminal.
  • the two input terminals of the first switch chip 31 are respectively connected to the first data pin 141 and the second data pin 142 of the external interface 140, and the two output terminals are respectively connected to the first data pin 111 and the second data pin 112 of the processor 110, thereby forming a first protocol identification path.
  • the two input terminals of the second switch chip 32 are respectively connected to the first data pin 141 and the second data pin 142 of the external interface 140, and the two output terminals are respectively connected to the first data pin 111 and the second data pin 112 of the charging protocol chip 130, thereby forming a second protocol identification path.
  • the control terminals of the first switch chip 31 and the second switch chip 32 are respectively connected to the first control pin and the second control pin of the GPIO interface of the controller 120.
  • the controller 120 applies control signals to the control terminals of the first switch chip 31 and the second switch chip 32 to control the on and off of the first switch chip 31 and the second switch chip 32 , thereby controlling the on or off of the first and second protocol identification paths.
  • the working principle of the switch circuit of the electronic device shown in FIG13 is similar to the working principle of the switch circuit of the electronic device shown in FIG11 , and will not be described in detail here.
  • FIG14 is a schematic diagram of another switch circuit of an electronic device according to an embodiment of the present application.
  • the switch circuit 170 includes a switch chip 40.
  • the switch chip includes four input terminals, four output terminals, and two/four control terminals (two control terminals are shown in FIG14).
  • the two input terminals of the switch chip 40 are respectively connected to the first data pin 141 and the second data pin 142 of the external interface 140, and the two output terminals are respectively connected to the first data pin 111 and the second data pin 112 of the processor 110, thereby forming a first protocol identification path.
  • the other two input terminals of the switch chip 40 are respectively connected to the first data pin 141 and the second data pin 142 of the external interface 140, and the other two output terminals are respectively connected to the first data pin 111 and the second data pin 112 of the charging protocol chip 130, thereby forming a second protocol identification path.
  • the two/four control terminals of the switch chip 40 are respectively connected to 2/4 control pins of the GPIO interface of the controller 120.
  • the controller 120 applies a control signal to the control terminal of the switch chip 40 , thereby controlling the on or off of the first and second protocol identification paths.
  • the working principle of the switch circuit of the electronic device shown in FIG. 14 is similar to the working principle of the switch circuit of the electronic device shown in FIG. 11 , and will not be described in detail here.
  • the controller 120 and the switch circuit 170 are configured so that the default second protocol identification path (i.e., the charging protocol identification path) is turned on.
  • the charging protocol is first identified.
  • the second protocol identification path is disconnected by the controller 120 and the switch circuit 170, and the first protocol identification path is turned on to identify the USB2.0 device.
  • the USB2.0 device is unplugged from the USB interface 140, the second protocol identification path is turned on by default again through the controller 120 and the switch circuit 170, waiting for the next external device to be connected.
  • the electronic device provided in the embodiment of the present application not only can terminals that support protocols such as SCP be fast charged through the external interface, but also the identification of USB2.0 devices will not be affected.
  • the embodiment of the present application also provides a device identification method, which can be applied to the electronic device in the embodiment, and has the same beneficial effects. For details not described in detail in the embodiment, reference can be made to the embodiment of the electronic device.
  • the device identification method is introduced below in conjunction with the electronic devices shown in FIG8, FIG9 and FIG11.
  • the device identification method can be implemented through the following steps:
  • the controller controls the switch circuit so that the second protocol identification path is turned on by default and the first protocol identification path is turned off by default.
  • the controller 140 is configured to pull up the levels of the first control pin, the second control pin, the third control pin, and the fourth control pin of GIPO by default (i.e., output a high level), so that the first switch transistor 11 (PMOS) and the second switch transistor 12 (PMOS) are disconnected, and the third switch transistor 13 (NMOS) and the fourth switch transistor 14 (NMOS) are turned on, thereby disconnecting the first protocol identification path and turning on the second protocol identification path.
  • default i.e., output a high level
  • the charging protocol chip communicates with the external device, performs charging protocol detection, and feeds back the detection result to the controller.
  • the charging protocol chip 130 completes handshake with the terminal to be charged 201 through the handshake channel, and then provides a Vbus voltage of, for example, 5V, to the power pin/power channel. Then, after the terminal to be charged 201 identifies the electronic device 100 as a DCP (Dedicated Charging Port) device based on the BC1.2 protocol (Battery Charging v1.2), the charging protocol chip 130 performs charging protocol detection and feeds back the detection result to the controller 120. For example, the charging protocol chip 130 sends an indication of success or failure of the charging protocol detection to the controller 120 through the I2C bus.
  • DCP Dedicated Charging Port
  • BC1.2 Battery Charging v1.2
  • step S1503 After the charging protocol chip 130 detects the charging protocol successfully, the process proceeds to step S1503 , otherwise the process proceeds to step S1505 .
  • S1503 The controller determines whether to start fast charging based on the battery power.
  • the controller 120 determines whether to start fast charging according to the current power level of the battery 160. For example, when the current power level of the battery 160 is greater than a set threshold, the controller 120 determines to start fast charging.
  • step S1504 When the controller 120 determines that fast charging is started, it goes to step S1504, otherwise it goes to step S1505.
  • the charging protocol chip communicates charging information with the terminal, and after communicating the charging information, sends an enable signal to the voltage conversion circuit to start fast charging.
  • the charging protocol chip 210 of the terminal determines the required charging voltage and current according to the current circuit of the battery 220, and then sends it to the charging protocol chip 130.
  • the charging protocol chip 130 sends an enable signal to the voltage conversion circuit 150, and the voltage conversion circuit 150 fast charges the external device through the USB interface 140 according to the charging voltage and current determined by the charging protocol chip 130.
  • the controller controls the switch circuit to disconnect the second protocol path and connect the first protocol identification path.
  • the charging protocol chip 130 sends an indication to the controller 120 that the charging protocol identification has failed or that fast charging is not started.
  • the controller 120 changes the level signal or control signal output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface according to the indication, so that the third switch transistor 13 and the fourth switch transistor 14 are disconnected, and the first switch transistor 11 and the second switch transistor 12 are turned on, so that the second protocol identification path is disconnected and the first protocol identification path is turned on.
  • the processor 110 communicates with the external device through the first protocol identification path to perform USB2.0 protocol identification and determine whether the external device is a USB2.0 device. When it is determined that the external device is a USB2.0 device, subsequent operations are performed based on the device type, such as data reading or storage.
  • S1506 The processor notifies the controller that the USB 2.0 device is unplugged.
  • the processor 110 sends an indication of USB 2.0 device unplugging to the controller 120 via, for example, the eSPI bus.
  • the controller 120 changes the level signal or control signal output by the first control pin, the second control pin, the third control pin, and the fourth control pin of the GPIO interface, so that the third switch transistor 13 and the fourth switch transistor 14 are turned on, and the first switch transistor 11 and the second switch transistor 12 are turned off, thereby turning on the second protocol identification path and disconnecting the first protocol identification path.
  • the above example only shows a process of a device identification method, but does not constitute a limitation of the present application.
  • the device identification method may not include the above step S1503, or the above steps S1502 and S1504 may be combined into one step.
  • the electronic device includes hardware and/or software modules corresponding to the execution of each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to be beyond the scope of the present application.
  • FIG16 shows a schematic block diagram of a device 500 according to an embodiment of the present application.
  • the device 500 may include: a processor 501 and a transceiver/transceiver pin 502 , and optionally, a memory 503 .
  • bus 504 includes a power bus, a control bus, and a status signal bus in addition to a data bus.
  • bus 504 includes a power bus, a control bus, and a status signal bus in addition to a data bus.
  • all buses are referred to as bus 504 in the figure.
  • the memory 503 may be used for the instructions in the aforementioned method embodiment.
  • the processor 501 may be used to execute the instructions in the memory 503, and control the receiving pin to receive a signal, and control the sending pin to send a signal.
  • the apparatus 500 may be the electronic device or a chip of the electronic device in the above method embodiment.
  • the steps performed by the electronic device 100 in the device identification method provided in the above embodiment of the present application may also be performed by a chip system included in the electronic device 100, wherein the chip system may include a processor and a Bluetooth chip.
  • the chip system may be coupled to a memory so that when the chip system is running, the computer program stored in the memory is called to implement the steps performed by the above electronic device 100.
  • the processor in the chip system may be an application processor or a processor other than an application processor.

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Abstract

本申请提供了一种电子设备、设备识别方法和充电系统，涉及电子技术领域。该电子设备包括：处理器、控制器、充电协议芯片、外部接口和开关电路；该处理器、充电协议芯片和外部接口均包括数据引脚单元，处理器的数据引脚单元、充电协议芯片的数据引脚单元、外部接口的数据引脚单元、控制器分别电连接至开关电路；控制器用于控制开关电路，使外部接口的数据引脚单元与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中之一导通，与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中另一断开，这样外部接口仅与处理器和充电协议芯片其中之一进行电连接，使得充电协议芯片和处理器彼此不会对对方的外部设备的识别过程造成干扰。

Description

电子设备、设备识别方法及充电系统
本申请要求于2022年07月27日提交中国国家知识产权局、申请号为202210892907.8、申请名称为“电子设备、设备识别方法及充电系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种电子设备、设备识别方法及充电系统。
背景技术
目前诸如笔记本、手机、平板等设备已经成为人们日常生活工作中的常用设备，这些设备都需要在电池电量快耗尽时进行充电以补充电量。因此人们需要携带各种设备的充电线和充电器，这带来了诸多不便。
虽然可以通过笔记本的通用串行总线(universal serial bus，USB)接口为手机、平板等终端进行充电，但是目前笔记本并不支持手机、平板等设备所使用的快充协议，因此充电速度很慢，无法为手机、平板等快速补电。
发明内容
为了解决上述技术问题，本申请提供一种电子设备、设备识别方法及充电系统。在该电子设备中，增加充电协议芯片，以可以对外提供快充功能，并且电子设备的外部接口在同一时间仅与处理器和充电协议芯片其中之一电连接，使得在对外部设备进行识别时充电协议芯片和处理器不会对彼此造成干扰，从而使电子设备可以在对外实现快充的同时不影响对USB2.0设备的识别。
第一方面，本申请提供一种电子设备，该电子设备包括：处理器、控制器、充电协议芯片、外部接口和开关电路；处理器、充电协议芯片和外部接口均包括数据引脚单元；处理器的数据引脚单元、充电协议芯片的数据引脚单元、外部接口的数据引脚单元、控制器分别电连接至开关电路；控制器用于控制开关电路，使外部接口的数据引脚单元与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中之一导通，与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中另一断开。其中，数据引脚单元可以包括一个数据引脚，也可以包括多个数据引脚，外部接口的数据引脚单元与处理器的数据引脚单元之间可以形成第一协议识别通路，第一协议识别通路例如为USB2.0协议识别通路。外部接口的数据引脚单元与充电协议芯片的数据引脚单元之间可以形成第二协议识别通路，第二协议识别通路例如为SCP/FCP协议识别通路。通过控制器控制开关电路可以使得第一协议识别通路和第二协议识别通路其中之一导通时，其中另一关断。
根据第一方面的电子设备，增加了充电协议芯片，使得可以对外部设备提供快充功能，并且当外部设备电连接至外部接口时，由于处理器和充电协议芯片仅其中之一与外 部接口电连接，因此在对外部设备进行识别或与外部设备进行交互时，充电协议芯片和处理器彼此不会对对方造成干扰，因而电子设备既可以实现对外部设备的快充，又不影响对USB2.0设备的识别。
根据第一方面，或者以上第一方面的任意一种实现方式，外部接口用于与外部设备电连接；处理器用于在外部接口与外部设备电连接，且处理器的数据引脚单元与外部接口的引脚单元导通时，对外部设备进行第一协议识别；充电协议芯片用于在外部接口与外部设备电连接，且充电协议芯片的数据引脚单元与外部接口的引脚单元导通时，对外部设备进行第二协议识别；处理器和充电协议芯片分别与控制器电连接，用于向控制器发送表示协议识别成功或失败的指示；控制器用于在接收到处理器发送的表示第一协议识别成功的指示后，继续控制开关电路使外部接口的数据引脚单元与处理器的数据引脚单元导通，与充电协议芯片的数据引脚单元断开，以及在接收到处理器发送的表示第一协议识别失败的指示后，控制开关电路使外部接口的数据引脚单元与处理器的数据引脚单元断开，与充电协议芯片的数据引脚单元导通；控制器用于在接收到充电协议芯片发送的表示第二协议识别成功的指示后，继续控制开关电路使外部接口的数据引脚单元与充电协议芯片的数据引脚单元导通，与处理器的数据引脚单元断开，以及在接收到充电协议芯片发送的表示第二协议识别失败的指示后，控制开关电路使外部接口的数据引脚单元与充电协议芯片的数据引脚单元断开，与处理器的数据引脚单元导通。这样，控制器可以根据处理器或充电协议芯片的识别成功或失败的指示，对开关电路进行控制，在处理器或充电协议芯片识别成功时，控制开关电路继续导通相应的协议识别通路，在识别失败时，控制开关电路切换至另一协议识别通路，使得电子设备既可以实现对外部设备的快充，又不影响对USB2.0设备的识别。
根据第一方面，或者以上第一方面的任意一种实现方式，控制器控制开关电路使外部接口的数据引脚单元与充电协议芯片的数据引脚单元导通，与处理器的数据引脚单元断开；以及在接收到充电协议芯片发送的表示第二协议识别失败的指示后，控制开关电路使外部接口的数据引脚单元与充电协议芯片的数据引脚单元断开，与处理器的数据引脚单元导通。控制器控制开关电路默认先导通外部接口与充电协议芯片，先对外部设备进行第二协议(例如充电协议)识别，在第二协议识别失败之后，再对外部设备进行第一协议识别，这样由于先对外部设备进行第二协议识别，在第二协议对识别过程有时长要求的情形中，可以避免出现识别时长超过第二协议识别所设定的时长导致的协议识别失败或出错的情形。
根据第一方面，或者以上第一方面的任意一种实现方式，该电子设备还包括电压转换电路和电池，外部接口还包括电源引脚；电池通过电压转换电路与外部接口的电源引脚电连接；充电协议芯片与电压转换电路连接，用于在充电协议芯片议识别成功之后向电压转换电路发送使能信号，使电压转换电路向外部接口的电源引脚提供设定电压。这样，电子设备可以根据待充电设备的需求提供需要充电电压，实现对外部设备的快充。
根据第一方面，或者以上第一方面的任意一种实现方式，控制器还用于在接收到充电协议芯片发送的表示第二协议识别成功的指示后，获取电池的电量信息，并根据电池电量信息向充电协议芯片发送启动快充或不启动快充的指示。这样，可以根据电子设备的电池电量确定是否对外部设备进行快充，避免由于电量过低导致快充无法进行或者影响电子设备的使用。
根据第一方面，或者以上第一方面的任意一种实现方式，控制器在电池的电量大于设定阈值时向充电协议芯片发送启动快充的指示，在电池的电量小于等于设定阈值时向充电协议芯片发送不启动快充的指示。这样，可以根据电子设备的电池电量确定是否对外部设备进行快充，避免由于电量过低导致快充无法进行或者影响电子设备的使用。
根据第一方面，或者以上第一方面的任意一种实现方式，当外部设备为支持第一协议的设备，且外部设备从外部接口拔出后，处理器还用于在外部设备拔出后，向控制器发送外部设备拔出的指示，控制器根据外部设备拔出的指示，控制开关电路使外部接口的数据引脚单元与处理器的数据引脚单元断开，与充电协议芯片的数据引脚单元导通。这样，在外部设备拔出后，控制器控制开关电路默认先导通外部接口与充电协议芯片，先对外部设备进行第二协议(例如充电协议)识别，从而在第二协议对识别过程有时长要求的情形中，可以避免出现识别时长超过第二协议识别所设定的时长导致的协议识别失败或出错的情形。
根据第一方面，或者以上第一方面的任意一种实现方式，开关电路包括开关芯片，处理器的数据引脚单元、充电协议芯片的数据引脚单元、外部接口的数据引脚单元、控制器分别电连接至开关芯片。这样通过一个开关芯片即可实现对外部接口、处理器和充电协议芯片的数据引脚单元之间的电连接控制，保证在外部设备识别过程中处理器和充电协议芯片彼此不会造成干扰。
根据第一方面，或者以上第一方面的任意一种实现方式，开关电路包括第一开关单元和第二开关单元；处理器的数据引脚单元、外部接口的数据引脚单元、控制器分别电连接至第一开关单元，控制器用于控制第一开关单元以使外部接口的数据引脚单元与处理器的数据引脚单元导通或断开；充电协议芯片的数据引脚单元、外部接口的数据引脚单元、控制器分别电连接至第二开关单元，控制器用于控制第二开关单元以使外部接口的数据引脚单元与充电协议芯片的数据引脚单元导通或断开。这样通过第一开关单元和第二开关单元分别对处理器和充电协议芯片与外部接口的电连接进行控制，保证在外部设备识别过程中处理器和充电协议芯片彼此不会造成干扰。
根据第一方面，或者以上第一方面的任意一种实现方式，第一开关单元和第二开关单元均包括开关芯片。第一开关单元和第二开关单元均可以实现开关芯片，可以根据需 要选择合适的芯片来对处理器和充电协议芯片与外部接口的电连接进行控制。
根据第一方面，或者以上第一方面的任意一种实现方式，数据引脚单元包括第一数据引脚和第二数据引脚；开关电路包括第一至第四开关单元；处理器的第一数据引脚、外部接口的第一数据引脚、控制器分别电连接至第一开关单元，控制器用于控制第一开关单元以使外部接口的第一数据引脚与处理器的第一数据引脚导通或断开；处理器的第二数据引脚、外部接口的第二数据引脚、控制器分别电连接至第二开关单元，控制器用于控制第二开关单元以使外部接口的第二数据引脚与处理器的第二数据引脚导通或断开；充电协议芯片的第一数据引脚、外部接口的第一数据引脚、控制器分别电连接至第三开关单元，控制器用于控制第三开关单元以使外部接口的第一数据引脚与充电协议芯片的第一数据引脚导通或断开；充电协议芯片的第二数据引脚、外部接口的第二数据引脚、控制器分别电连接至第四开关单元，控制器用于控制第四开关单元以使外部接口的第二数据引脚与充电协议芯片的第二数据引脚导通或断开。这样，在数据引脚单元包括两个数据引脚的情形中，可以通过四个开关单元来分别对处理器和充电协议芯片与外部接口的电连接进行控制，保证在外部设备识别过程中处理器和充电协议芯片彼此不会造成干扰。
根据第一方面，或者以上第一方面的任意一种实现方式，第一至第四开关单元均包括开关芯片或MOS晶体管。这样可以根据需要选择合适的开关芯片或MOS晶体管来对处理器和充电协议芯片与外部接口的电连接进行控制。
根据第一方面，或者以上第一方面的任意一种实现方式，第一开关单元包括PMOS晶体管，第二开关单元包括PMOS晶体管，第三开关单元包括NMOS晶体管，第四开关单元包括NMOS晶体管。这样第一开关单元和第二开关单元晶体管类型相同，第三开关单元和第四开关单元晶体管类型相同，且与第一开关单元和第二开关单元相反，因此通过一个开关信号或相同的开关信号即可实现对四个开关单元的控制，例如通过同一个高电平信号即可导通第三和第四开关单元，并关断第一和第二开关单元，通过同一低电平信号即可关断第三和第四开关单元，并导通第一和第二开关单元，使得控制过程简单化。
根据第一方面，或者以上第一方面的任意一种实现方式，第一协议包括USB2.0协议，第二协议包括SCP/FCP快充协议。这样使得电子设备可以实现对外部设备的SCP/FCP快充，又不影响对USB2.0设备的识别。
根据第一方面，或者以上第一方面的任意一种实现方式，数据引脚单元包括DP引脚或DM引脚。这样，通过DP引脚和DM引脚进行协议通信时，电子设备均可以实现对外部设备的快充，又不影响对USB2.0设备的识别。
第二方面，本申请提供一种设备识别方法，应用于第一方面的电子设备，该设备识 别方法包括：
控制器控制开关电路，使外部接口的数据引脚单元与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中之一导通，与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中另一断开；
处理器和充电协议芯片其中之一对外部接口所连接的外部设备的类型进行识别，其中外部设备的类型例如包括支持第一协议的外部设备和支持第二协议外部设备，示例性地，外部设备包括USB2.0设备和待充电终端；
在处理器和充电协议芯片其中之一识别失败之后，控制器控制开关电路，使外部接口的数据引脚单元与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中之一断开，与处理器的数据引脚单元和充电协议芯片的数据引脚单元其中另一导通；
处理器和充电协议芯片其中另一对外部接口所连接的外部设备的类型进行识别。
根据第二方面的设备识别方法，当外部设备电连接至外部接口时，由于处理器和充电协议芯片仅其中之一与外部接口电连接，因此在对外部设备进行识别或与外部设备进行交互时，充电协议芯片和处理器彼此不会对对方造成干扰，因而电子设备既可以实现对外部设备的快充，又不影响对USB2.0设备的识别。
根据第二方面，或者以上第二方面的任意一种实现方式，控制器控制开关电路，使外部接口的数据引脚单元与充电协议芯片的数据引脚单元导通，与处理器的数据引脚单元断开；充电协议芯片对外部设备的类型进行识别；在充电协议芯片识别失败之后，控制器控制开关电路，使外部接口的数据引脚单元与充电协议芯片的数据引脚单元其中之一断开，与处理器的数据引脚单元的数据引脚单元导通；处理器对外部设备的类型进行识别。这样由于先对外部设备进行第二协议识别，在第二协议对识别过程有时长要求的情形中，可以避免出现识别时长超过第二协议识别所设定的时长导致的协议识别失败或出错的情形。
根据第二方面，或者以上第二方面的任意一种实现方式，在所述外部接口所连接的外部设备为所述处理器所对应的类型时，该设备识别方法还包括：处理器在外部设备拔出之后向控制器发送外部设备拔出的指示；控制器在接收到外部设备拔出的指示后，控制开关电路，使外部接口的数据引脚单元与充电协议芯片的数据引脚单元导通，与处理器的数据引脚单元断开。这样，在外部设备拔出后，控制器控制开关电路默认先导通外部接口与充电协议芯片，先对外部设备进行第二协议(例如充电协议)识别，从而在第二协议对识别过程有时长要求的情形中，可以避免出现识别时长超过第二协议识别所设定的时长导致的协议识别失败或出错的情形。
第三方面，本申请提供一种充电系统，包括第一方面的电子设备和终端；终端包括充电接口和电池；充电接口与外部接口电连接；电子设备通过外部接口和充电接口为终端内的电池充电。这样可以利用电子设备对终端进行快充，提高了充电的便利性。
第四方面，本申请提供了一种芯片，该芯片包括处理电路、收发管脚。其中，该收发管脚、和该处理电路通过内部连接通路互相通信，该处理电路执行第二方面或第二方面的任一种可能的实现方式中的方法，以控制接收管脚接收信号，以控制发送管脚发送信号。
附图说明
图1为示例性示出的应用场景示意图之一；
图2为示例性示出的应用于图1所示应用场景的电子设备的结构的示意图；
图3为示例性示出的USB2.0设备识别原理示意图；
图4-图6为示例性示出的SCP协议识别原理的示意图；
图7为示例性示出的根据本申请实施例的电子设备的结构的示意图；
图8为示例性示出的根据本申请实施例的电子设备与待充电终端的连接示意图；
图9为示例性示出的根据本申请实施例的电子设备与USB2.0设备的连接示意图；
图10为根据本申请实施例的一种外部接口的结构示意图；
图11为示例性示出的根据本申请实施例的电子设备的一开关电路的示意图；
图12为示例性示出的根据本申请实施例的电子设备的另一开关电路的示意图；
图13为示例性示出的根据本申请实施例的电子设备的又一开关电路的示意图；
图14为示例性示出的根据本申请实施例的电子设备的又一开关电路的示意图；
图15为示例性示出的根据本申请实施例的设备识别方法的流程示意图；
图16为示例性示出的根据本申请实施例的一种装置的示意性框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
图1为示例性示出一种应用场景示意图。参照图1，示例性的，电子设备100可以例如为笔记本电脑等设备，其配置有例如Type-C型通用串行总线(universal serial bus，USB)接口的外部接口。通过该外部接口，电子设备100可以与外部设备200连接。参考图1中(1)，示例性的，外部设备200可以为诸如手机、平板等的待充电终端。参考图1中(2)，示例性的，外部设备200还可以为诸如U盘、移动硬盘等USB2.0设备。其中，USB2.0设备即为支持USB2.0协议的存储设备或电子设备。在图1所示的应用场景中，电子设备100通过外部接口可以为诸如手机或平板的待充电终端201快速充电，也可以与诸如U盘或移动硬盘、作为硬盘使用的电子设备、或者其它类型的USB2.0设备202进行通信或数据交互，以实现通信、数据读取或存储等功能。
在图1所示的应用场景中，电子设备100可以为诸如手机或平板的待充电终端201提供快充功能。在本申请中快充指的是采用充电功率大于10W，例如可以为18W、22.5W、40W、60W、100W等的充电模式进行充电。在一种实现方式中，电子设备100支持超级充电协议/快速充电协议(Super Charge Protocol，SCP)/Fast Charger Protocol，FCP)。通过外部接口，电子设备100可以为支持SCP/FCP协议的待充电终端201进行快充。
图2为示例性示出的应用于图1所示应用场景的电子设备100的结构的示意图。参考图2，电子设备100包括处理器110、控制器120、充电协议芯片130、外部接口140、电压转换电路150和电池160。外部接口140示例性可以为type-C型USB接口。在图2所示电子设备100中，处理器110包括第一数据引脚111(例如DP或D+)和第二数据引脚例如(例如DM或D-)。充电协议芯片130包括第一数据引脚131(例如DP或D+)和第二数据引脚132(例如DM或D-)。外部接口140包括第一数据引脚141(例如DP或D+)和第二数据引脚142(例如DM或D-)。一方面外部接口140的第一数据引脚141和第二数据引脚142分别与处理器110的第一数据引脚111和第二数据引脚112连接，形成第一协议识别通路。第一协议识别通路例如为USB2.0设备协议识别通路。另一方面外部接口140的第一数据引脚141第二数据引脚142又分别与充电协议芯片130的第一数据引脚131和第二数据引脚132连接，形成第二协议识别通路。第二协议识别通路例如为快充协议识别通路。
基于USB2.0协议，处理器110的第一数据引脚111和第二数据引脚112分别通过例如15K欧姆的下拉电阻R接地。基于SCP/FCP协议，充电协议芯片130的第一数据引脚131和第二数据引脚132分别通过例如15K欧姆的下拉电阻R接地。在外部设备200接入外部接口140后，电子设备100的USB2.0协议和SCP/FCP协议都是通过电子设备100内的下拉电阻配置电平做来进行设备识别的。
具体地，例如处理器110通过检测处理器110的第一数据数据引脚111和第二数据引脚112的电平来判断接入外部接口140的设备是否为USB2.0设备。充电协议芯片130通过检测充电协议芯片130的第一数据引脚131和第二数据引脚132的电平来判断接入外部接口140的设备是否为支持SCP/FCP协议的终端设备。
图3为示例性示出的USB2.0设备识别原理示意图。参考图3中(1)，处理器110的数据引脚DP和DM分别通过下拉电阻接地。参考图3中(2)，USB高速/全速设备包括USB2.0协议芯片和数据引脚DP和DM，并且DP引脚通过上拉电阻连接电源Vcc。 参考图3中(3)，USB低速设备包括USB2.0协议芯片和数据引脚DP和DM，并且DM引脚通过上拉电阻连接电源Vcc。其中，上述上拉电阻的阻值例如为1.5KΩ。
当电子设备100没有连接外部设备200时，与DP引脚和DM引脚连接的下拉电阻使得这两条数据线的电压都是近地的(参见图3中(1))。当全速/高速设备与电子设备100连接以后，处理器110的数据引脚DP连接的下拉电阻和外部设备200的数据引脚DP连接的上拉电阻构成分压器。由于下拉电阻的阻值是15KΩ，上拉电阻的阻值是1.5KΩ，所以在处理器110的数据引脚DP上会出现大小为(Vcc*15/(15+1.5))的直流高电平电压。当处理器110探测到DP引脚电压已经接近高电平，而DM引脚保持接地时，就可确定接入了全速/高速USB2.0设备。相对应，当处理器110探测到DM引脚电压已经接近高电平，而DP引脚保持接地时，就可确定接入了低速USB2.0设备。
应当理解上述USB2.0设备的识别过程/方法仅是一个示例，本申请实施例可以基于上述原理或类似原理采用其它方式进行识别。
SCP协议检测过程会先通过BC1.2检测充电接口是否为专用充电接口(DCP接口)。下面结合图4-图6对SCP协议的检测原理进行示例性说明。
图4-图6为示例性示出的SCP协议识别原理示意图。充电协议BC1.2(BatteryChargingSpecification 1.2)定义3种接口类型：
标准下行接口(SDP,Standard Downstream Port)，这种接口支持USB协议，挂起时最大电流为2.5mA，连接且非挂起装置时为100mA。它的DP和DM引脚各有一只15k电阻连接到GND。
专用充电接口(DCP,Dedicated Charging Port)，这种端口不支持任何数据传输，但能够提供1.5A以上的电流。这种类型的接口支持较高充电能力的墙上充电器和车载充电器，无需枚举。
充电下行接口(CDP,Charging Downstream Port)，这种接口既支持大电流充电(最大为1.5A)，也支持完全兼容USB 2.0的数据传输。它的DP和DM引脚具有通信所必需的15kΩ下拉电阻，也具有充电器检测阶段切换的内部电路。该内部电路允许设备将CDP与其它类型端口区分开来。
参考图4，其示出了终端PD(portable device，例如待充电终端201)的USB接口与外部接口连接后进行数据检测时的工作模式(图4中虚线区域)。数据检测的过程例如为：终端PD在VBUS有效后，使能DP引脚的电流源IDP_SRC和DM引脚的下拉电阻，然后终端PD检测到DP引脚，检测时间持续TDCD_DBNC(Data contact detect debounce min＝10ms)，然后关闭DP引脚的电流源IDP_SRC和DM引脚的下拉电阻。在此过程中如果终端PD没有连接到外部接口上(例如电子设备100的外部接口140)时，终端PD的DP引脚保持在高电平。其中，电流源IDP_SRC(7uA)的最小值要求能保证在最坏漏电流(RDAT_LKG和VDAT_LKG)情况下，使DP引脚保持在电平VLGC_HI(例如为4.0～3.6V)。当终端连接到SDP接口时，DP引脚被SDP接口的下拉电子RDP_DWN拉低。其中，电流源IDP_SRC(13uA)的最大值要求能保证在最坏漏电流(RDAT_LKG,VDAT_LKG和RDP_DWN)情况下，RDP_DWN使DP引脚保持在VLGC_LOW(Logic Low 0～0.8V)。因此，在VBUS有效后，使能DP引脚的电流源IDP_SRC和DM引脚的 下拉电阻，通过检测DP引脚的电平即可判断终端PD所连接的外部接口是否支持数据协议。
参考图5，其示出了终端PD的USB接口与DCP接口连接后进行主检测时的工作模式(图5中虚线区域)。主检测的过程例如为：终端设备PD打开DP引脚的电压源VDP_SRC(例如为0.5～0.7v)和DM引脚的电流源IDM_SINK(例如为25～175μA)。DP和DM引脚通过DCP接口内的短接电阻RDCP_DAT(Dedicated Charging Port resistance across D+/-max＝200Ω)短接，终端PD检测DM的电压是否达到VDP_SRC。终端PD在DM引脚的电压比较器比较DM电压和VDAT_REF(例如为0.25～0.4v)，如果DM引脚电压大于VDAT_REF，就可以确定终端PD连接到了充电接口上，然后通过二次检测确定是连接到DCP接口还是CDP接口。
参考图6，其示出了终端PD的USB接口与DCP接口连接后进行二次检测时的工作模式(图6中虚线区域)。二次检测的过程例如为：终端PD在DM引脚上使能电压源VDM_SRC，打开电流源IDP_SINK，然后比较DP引脚的电压和VDAT_REF的电压，因为DCP接口内部通过短接电阻RDCP_DAT短接了DP和DM引脚，所以电压源VDM_SRC的电压使得VDAT_REF<DP<VDM_SRC。因此当终端PD检测到VDAT_REF<DP引脚电压时，就可判断终端连接到了DCP接口上。
综上可知，在USB2.0设备协议识别和SCP协议识别的过程中，外部接口140的第一数据引脚和第二数据引脚的电平均会发生变化。而在图2所示的电子设备中，由于外部接口140的第一数据引脚141和第二数据引脚142与处理器110和充电协议芯片130的第一数据引脚和第二数据引脚均为直接连接(即第一和第二协议识别通路均处于导通状态)，并且采用相同的下拉电阻，因此彼此的下拉电阻会对对方的协议识别产生影响。例如，假如接入外部接口140的外部设备是诸如手机的待充电终端201，处理器110也可检测到其第一数据引脚和第二数据引脚的电平变化，导致外部设备被识别为USB2.0设备，或者对外部设备的充电协议识别造成干扰导致识别失败，这样导致电子设备100既无法正确识别USB2.0设备，也无法为诸如手机等的待充电终端快充。
基于此，本申请实施例提供一种电子设备、设备识别方法和充电系统，充电系统包括该电子设备和终端，其中，该电子设备可以为终端进行充电。通过在电子设备中增加充电协议芯片来为终端提供快充功能，并增加开关电路来控制USB2.0设备协议识别通路和快充协议识别通路的通断，使得同一时间仅USB2.0设备协议识别通路和快充协议识别通路其中之一导通，从而避免两个协议识别通路对彼此的干扰，这样一来外部接口既可以做SCP快充功能，又不影响USB2.0设备的识别。其中，电子设备可以为诸如笔记本电脑、一体机、台式机等配有外部接口的设备。终端可以是手机、笔记本电脑、平板电脑、个人数字助理(personal digital assistant，简称PDA)、车载电脑、电视、智能穿戴式设备(例如智能手表等)、媒体播放机、智能家居设备等待充电的终端，本申请实施例对上述终端的具体形式不作特殊限定。为了方便说明，本申请实施例均以电子设备是笔记本电脑，终端是手机为例进行说明。
应当理解的是，在上述说明中以SCP/FCP协议为例进行说明，实际上对于采用第一数据引脚和第二数据引脚进行充电协议通信的芯片，在同一外部接口实现USB2.0支持和 快充支持时均存在上述提到的问题，而本申请实施例提出的电子设备、设备识别方法在此情形中同样适用。下文中同样以SCP/FCP协议为例进行说明。
还应当理解的是，上述示例均以外接接口为type-C型USB接口，type-C型USB接口的DP引脚以及DM引脚为例进行的说明，但并不构成对本申请的限定，只要通过该接口中的引脚实现数据通信功能以及协议识别功能的接口均在本申请实施例的保护范围内。下文中同样以type-C型USB接口为例进行的说明。
图7为示例性示出的根据本申请实施例的电子设备的结构的示意图。参考图7，电子设备100包括处理器110、控制器120、充电协议芯片130、外部接口140、电压转换电路150、电池160和开关电路170。
应当理解的是，电子设备100还可以包括电源管理模块、天线，无线通信模块、鼠标、指示器、键盘、摄像头，显示屏、音频模块、扬声器、音箱接口、麦克风等模块中的一种或多种，或者还可以包括其它模块，在此不做具体限定。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器，调制解调处理器，图形处理器GPU，ISP，存储器，视频编解码器，DSP，基带处理器，和/或NPU等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器10需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路I2C接口，集成电路内置音频I2S接口、eSPI接口、PCM接口、UART接、MIPI,GPIO接口和/或USB接口等。
在本申请实施例中，处理器110包括第一数据引脚111和第二数据引脚112。处理器110通过第一数据引脚111和第二数据引脚112与外部接口140连接，从而与外部设备进行数据交互或通信。示例性地，基于USB2.0协议，处理器110的第一数据引脚111和第二数据引脚112分别通过例如15K欧姆的下拉电阻R接地。
控制器120例如为嵌入式控制器EC，其用于实现键盘控制，触摸板，电源管理，风扇控制等等的功能。控制器120可以包含独立运行的软件，存放在自己的非易失性介质中。在一些实施例中，控制器120可以包括一个或多个接口。接口可以包括通用输入输出接口(GPIO)、eSPI(Enhanced Serial Peripheral，增强型串行外围)接口、集成电路I2C接口等。控制器120可以通过例如eSPI接口和eSPI总线与处理器110进行连接和通信。控制器120还可以通过例如GPIO接口与开关电路170连接，以向开关电路170输出控制信号，实现对开关电路170的控制。控制器120还可以通过例如集成电路I2C接口与充电协议芯片130连接，与充电协议芯片130进行通信。
充电协议芯片130例如为支持SCP协议的快充协议芯片，用于进行快充协议识别和充电沟通。充电协议芯片130包括第一数据引脚131和第二数据引脚132。充电协议芯片130通过第一数据引脚131和第二数据引脚132与外部接口140连接，从而为外部设备进 行快充。示例性地，基于SCP/FCP协议，充电协议芯片130的第一数据引脚131和第二数据引脚132分别通过例如15K欧姆的下拉电阻R接地。
充电协议芯片130可以包括一个或多个接口。接口可以包括集成电路I2C接口等。充电协议芯片130通过例如I2C接口和I2C总线与控制器120连接。充电协议芯片130可以向控制器120发送快充协议识别成功或失败的指示或信号。充电协议芯片130还与电压转换电路150连接，用于在快充协议识别成功后，向电压转换电路150发送使能信号，使电压转换电路150向外部端口输出终端所需要的充电电压。
外部接口140示例性可以为type-C型USB接口。外部接口140包括过第一数据引脚141和第二数据引脚142。示例性地，外接口140还包括电源引脚VBUS和通信引脚。外部接口140的第一数据引脚141和第二数据引脚142，一方面分别与处理器110的第一数据引脚111和第二数据引脚112连接，形成第一协议识别通路(也即USB2.0设备协议识别通路)；另一方面又分别与充电协议芯片130的第一数据引脚131和第二数据引脚132连接，形成第二协议识别通路(也即快充协议识别通路)。
电池160通过电压转换电路150为外部接口140供电，从而为外部设备供电或充电。电池160还为处理器110、控制器120、充电协议芯片130等供电。
开关电路170设置在外部接口140的第一数据引脚141、第二数据引脚142和处理器110以及充电协议芯片130的第一数据引脚和第二数据引脚之间，并且与控制器120连接。开关电路170在控制器120的控制下使得同一时间仅第一协议识别通路和第二协议识别通路其中之一导通，从而避免两个协议识别通路对彼此的干扰。在本申请实施例中，开关电路170在控制器120的控制下默认第二协议识别通路导通，并且在快充协议识别失败后断开第二协议识别通路，并导通第一协议识别通路，随后进行USB2.0设备的识别。这样在开关电路170和控制器120的作用下，当外部设备接入外部接口140后，电子设备100可以先进行充电协议识别，再进行USB2.0设备识别，不仅使得外部接口140同时支持USB2.0设备和快充功能，还能避免USB2.0设备的识别和待充电终端的识别之间的干扰，提高了外部设备识别的准确度和识别速度。换言之，采用上述电子设备100，通过外部接口不仅可以对支持诸如SCP协议等的终端进行快充，而且不会影响USB2.0设备的识别。
下面对上述电子设备100的外部设备的识别过程/方法进行详细说明。
图8为示例性示出的根据本申请实施例的电子设备与待充电终端的连接示意图。参考图8，外部接口140包括第一数据引脚141(例如DP)、第二数据引脚142(例如DM)、第一通信引脚143(例如CC1)、第二通信引脚144(例如CC2)和电源引脚145(例如VBUS引脚)。充电协议芯片130内部设置有短接第一数据引脚141和第二数据引脚142的开关电路。第一通信引脚143和第二通信引脚144通过上拉电阻与电源VCC(例如5V)连接。待充电终端201包括充电协议芯片210、电池220和充电接口230。充电接口230包括第一数据引脚231(例如DP)、第二数据引脚232(例如DM)、第一通信引脚233(例如CC1)、第二通信引脚234(例如CC2)和电源引脚235(例如VBUS引脚)。第一通信引脚233和第二通信引脚234通过下拉电阻接地。
控制器120控制开关电路170默认打开充电协议芯片130与第一数据引脚141(例如 DP)、第二数据引脚142之间的第二协议通路。当待充电终端201接入电子设备100后，即待充电终端201的充电接口230与电子设备100的外部接口140连接后，电子设备100的电源引脚145与待充电终端201的电源引脚235连接，构成电源通道或充电通道，电子设备100通过该通道可以为待充电终端201供电。电子设备100的第一数据引脚141、第二数据引脚142分别与待充电终端201的第一数据引脚231、第二数据引脚232连接，构成协议通道。电子设备100通过协议通道与待充电终端201进行协议通信。电子设备100的第一通信引脚143、第二通信引脚144分别与待充电终端201的第一通信引脚233、第二通信引脚234连接，构成握手通道。电子设备100通过握手议通道与待充电终端201完成握手。
示例性地，在本申请实施例中，充电协议芯片130与充电协议芯片210采用例如SCP协议。当待充电终端201接入电子设备100后，电子设备100通过握手通道与待充电终端201完成握手(也即，充电协议芯片130与充电协议芯片210完成握手)，随后为电源引脚/电源通道提供例如5V的Vbus电压。电子设备100与待充电终端201的握手过程可以采用各种合适的握手协议完成。示例性地，例如在电子设备100的第一通信引脚143、第二通信引脚144连接有上拉电阻，待充电终端201的第一通信引脚233和第二通信引脚234连接有下拉电阻。在电子设备100与待充电终端201未连接之前，电子设备100的电源引脚145没有电压输出。当电子设备100与待充电终端201连接后，电子设备100的第一通信引脚143、第二通信引脚144分别与待充电终端201的第一通信引脚233、第二通信引脚234连接，构成分压器。充电协议芯片130通过检测第一通信引脚143、第二通信引脚144的电平来检测待充电终端201的第一通信引脚233和第二通信引脚234的下拉电阻，从而确定待充电终端201是否连接到外部接口140。随后电子设备100闭合电源引脚145的开关(图8中未示出)，输出例如5V的Vbus电源给待充电终端201。
当电子设备100通过握手通道与待充电终端201完成握手后，充电协议芯片130闭合短接第一数据引脚141和第二数据引脚142的开关电路，使第一数据引脚141和第二数据引脚142短接。待充电终端201基于BC1.2协议(Battery Charging v1.2)识别电子设备100是否为DCP(Dedicated Charging Port，专用充电接口)设备(SCP快充协议需要先通过BC1.2协议识别电子设备100是否为DCP设备)。
识别过程例如为：待充电终端201在电源引脚235上电后，先进行数据连接检测。数据连接检测的过程参见前述结合图4的描述，在此不再赘述。如果在设定时长内(例如300～900ms)没有检测数据协议支持，则待充电终端201会进行DCP检测。
DCP检测过程可以参考前述结合图5和图6的描述。例如可以为：首先，充电协议芯片210打开第一数据引脚231的电压源VDP_SRC(例如为0.5～0.7v，图8未示出，设置方式参见图5和图6)和第二数据引脚232引脚的电流源IDM_SINK(例如为25～175μA，图8未示出，设置方式参见图5和图6)。第一数据引脚231和第二数据引脚232通过充电协议芯片130内的短接电阻短接，充电协议芯片210检测第二数据引脚232的电压是否达到VDP_SRC。充电协议芯片210在第二数据引脚232的电压比较器(图8未示出，设置方式参见图5和图6)比较第二数据引脚232电压和VDAT_REF(例如为0.25～0.4v)，如果第二数据引脚232电压大于VDAT_REF，就可以确定待充电终端201连接到了充电 接口上，然后通过二次检测确定是连接到DCP接口还是CDP接口。
然后，充电协议芯片210在第二数据引脚232上使能电压源VDM_SRC(图8未示出，设置方式参见图5和图6)，打开电流源IDP_SINK(图8未示出，设置方式参见图5和图)，然后比较第一数据引脚231的电压和VDAT_REF的电压，因为第一数据引脚231和第二数据引脚232通过充电协议芯片130内的短接电阻短接，所以电压源VDM_SRC的电压使得VDAT_REF<DP<VDM_SRC。因此当充电协议芯片210检测到VDAT_REF<DP引脚电压时，就可判断待充电终端201连接到了DCP接口上。
与此同时，充电协议芯片130持续检测相关信号电平，并在一定时间后断开第一数据引脚141和第二数据引脚142之间的短接，并根据设定条件确定是否进入快充模式(例如SCP快充)。如果确定进入快充模式，充电协议芯片130与充电协议芯片130进行通讯调压，以确定待充电终端201所需要的充电电压和电流。
应当理解的是，上述识别过程所使用的握手电路、数据检测电路、DCP检测电路仅是示例性的，本本申请实施例不限于此，只要可以实现BC1.2和/或SCP协议的相应检测要求即可。
图9为示例性示出的根据本申请实施例的电子设备与USB2.0设备的连接示意图。参考图9，外部接口140包第一数据引脚141、第二数据引脚142和电源引脚145。USB2.0设备202包括USB2.0协议芯片240、存储单元250和USB接口260。USB接口260包括第一数据引脚261、第二数据引脚262和电源引脚263。基于USB2.0协议，USB2.0设备202则会根据传输速率的不同等级会在第一数据引脚261P或第二数据引脚262上连接例如1.5K欧姆的上拉电阻。USB2.0设备202的识别过程参见前述结合图3的描述，在此不再赘述。
当USB2.0设备202接入电子设备100后，即USB2.0设备202的USB接口260与电子设备100的外部接口140连接后，先进行充电协议检测，如前述内容所示，此处不再赘述。充电协议检测失败，控制器120控制开关电路170打开处理器110与第一数据引脚141、第二数据引脚142之间的协议通路。处理器110作为Host(主机设备)只要检测到USB2.0设备的上拉电阻，就可以通过第一数据引脚141、第二数据引脚142的电平变化识别到USB2.0设备及其速度类型，这一识别过程没有插入时间限制。
需要说明的是，当外部设备为USB2.0设备时，由于电子设备100会先进行快充协议检测，因此使得USB2.0设备的识别由一定延迟。然而该延迟对用户而言很难感知到，因此不会降低用户体验。
应当理解的是，本申请实施例不对外部接口140、充电接口230和USB接口260的类型进行限定，它们例如可包括Type C USB接口、TypeA USB接口等。
下面对当外部接口140、充电接口230和USB接口260为Type C USB接口时，各引脚的位置进行说明。下述示例不构成对本申请的限定。
参见图10，当外部接口140为Type C USB接口时，外部接口140包括A面和B面。A面包括VBUS1引脚(引脚A4)和VBUS2引脚(引脚A9)，B面包括VBUS2引脚(引脚B9)和VBUS1引脚(引脚B4)。A面的VBUS1引脚(引脚A4)与B面的VBUS1引脚(引脚B4)电连接，A面的VBUS2引脚(引脚A9)与B面的VBUS2引脚(引脚 B9)电连接。A面的VBUS1引脚(引脚A4)与B面的VBUS1引脚(引脚B4)为第一电源引脚，可用作电源引脚145、235、263。A面的VBUS2引脚(引脚A9)与B面的VBUS1引脚(引脚B4)为第二电源电引脚，可用作电源引脚145、235、263。在本申请实施例中，对于USB2.0协议或SCP协议，DP引脚(A面的引脚A6和B面的引脚B6)为第一数据引脚111、131、141、231、261，DM引脚(A面的引脚A7和B面的引脚B7)为第二数据引脚112、132、142、232、262；CC1引脚(A面的引脚A5)为第一通信引脚143、263，CC2引脚(B面的引脚B5)为第二通信引脚144、264。图10所示的外部接口140可实现电源线的灵活正反插，无论何种插入方向均可完成外部设备200的连接，无需额外设置正反插软硬件检测机制辅助，即可准确匹配电源通道、协议通道/数据通道和握手通道。
应当理解的是图10中的外部接口仅仅是示例性的，在本申请其它实施例中，外部接口140可以为其它类型的接口，例如type A USB接口，或者包括少于图10所示引脚的Type C USB接口，例如不包括图10中的TX1+、TX1-、RX2+、RX2-等引脚的Type C USB接口。
下面对上述电子设备100的开关电路的结构和工作原理进行详细说明。
图11为示例性示出的根据本申请实施例的电子设备的一开关电路的示意图。参考图11，开关电路170包括4个开关器件10。示例性地，开关器件10包括第一开关晶体管11、第二开关晶体管12、第三开关晶体管13和第四开关晶体管14。第一开关晶体管11、第二开关晶体管12、第三开关晶体管13和第四开关晶体管14均包括第一端、第二端和控制端。控制器120包括通用输入输出接口(GPIO)，控制器120的通用输入输出接口(GPIO)包括第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚。第一开关晶体管11的第一端与外部接口140的第一数据引脚141连接，第二端与处理器110的第一数据引脚111连接，控制端与控制器120的通用输入输出接口(GPIO)的第一控制引脚连接。第一开关晶体管12的第一端与外部接口140的第二数据引脚142连接，第二端与处理器110的第二数据引脚112连接，控制端与控制器120的通用输入输出接口(GPIO)的第二控制引脚连接连接。第三开关晶体管13的第一端与外部接口140的第一数据引脚111连接，第二端与充电协议芯片130的第一数据引脚131连接，控制端与控制器120的通用输入输出接口(GPIO)的第三控制引脚连接。第四开关晶体管14的第一端与USB接口140的第二数据引脚142连接，第二端与充电协议芯片130的第二数据引脚132连接，控制端与控制器120的通用输入输出接口(GPIO)的第四控制引脚连接。控制器120通过GPIO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚向第一开关晶体管11、第二开关晶体管12、第三开关晶体管13和第四开关晶体管14的控制端输出电平信号或控制信号，来控制第一开关晶体管11、第二开关晶体管12、第三开关晶体管13和第四开关晶体管14的导通或断开。
当外部设备没有接入外部接口140时，在控制器120输出的电平信号或控制信号作用下，第三开关晶体管13和第四开关晶体管14导通，第一开关晶体管11和第二开关晶体管12断开，使得第二协议识别通路导通，第一协议识别通路断开。当外部设备接入外部接口140后，充电协议芯片130通过第二协议识别通路与对外部设备通信，从而进行 充电协议识别，确定外部设备是否支持对应的充电协议(例如SCP协议)，具体参见上文内容，如果充电协议识别成功，则充电协议芯片130向控制器120发送充电协议识别成功的指示，控制器120根据电池160的当前状态，例如剩余电量、当前输出电压等确定是否启动快充为外部设备充电。例如，当电池剩余电量大于设定阈值(例如30％)时，确定启动快充。在控制器120确定启动快充为外部设备充电后，充电协议芯片130向电压转换电路150发送使能信号，电压转换电路150根据充电协议芯片130确定的充电电压和电流通过外部接口140对外部设备进行快充。
如果充电协议识别失败，则充电协议芯片130向控制器120发送充电协议识别失败的指示，控制器120根据该指示改变GPIO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚输出的电平信号或控制信号，使得第三开关晶体管13和第四开关晶体管14断开，第一开关晶体管11和第二开关晶体管12导通，使得第二协议识别通路断开，第一协议识别通路导通。然后处理器110通过第一协议识别通路与对外部设备通信，从而进行USB2.0协议识别，确定外部设备是否为USB2.0设备(USB2.0的识别过程参见前述描述)。当确定外部设备为USB2.0设备后则基于设备类型进行后续操作，例如数据读取或存储等，例如当USB2.0设备为高速存储设备时，则与USB2.0设备进行高速数据读取或存储。当USB2.0设备为低速存储设备时，则与USB2.0设备进行低速数据读取或存储。当外部设备从外部接口140拔出后，处理器110通过例如eSPI总线将USB2.0设备拔出的指示发送至控制器120。随后，控制器120改变GPIO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚输出的电平信号或控制信号，使得第三开关晶体管13和第四开关晶体管14导通，第一开关晶体管11和第二开关晶体管12断开，从而使得第二协议识别通路导通，第一协议识别通路断开，重新等待下一次外部设备的接入，并重复上述识别过程。
示例性地，第一开关晶体管11和第二开关晶体管12可以为PMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为NMOS晶体管。控制器120配置为默认拉高GIPO的4个与开关晶体管控制端连接的引脚的电平(即输出高电平)，使得第一开关晶体管11和第二开关晶体管12断开，第三开关晶体管13和第四开关晶体管14导通，从而使得第一协议识别通路断开，第二协议识别通路导通。当充电协议识别失败后，控制器120拉低GIPO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚的电平(即输出低电平)，使得第一开关晶体管11和第二开关晶体管12导通，第三开关晶体管13和第四开关晶体管14断开，从而使得第一协议识别通路导通，第二协议识别通路断开。当外部设备拔出后，控制器120再次拉高GIPO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚的电平(即输出高电平)，使得第二协议识别通路默认导通，第一协议识别通路默认断开。
应当理解的是，虽然在图11所示实施例中，控制器120的GPIO接口使用四个控制引脚来控制第一至第四开关晶体管，但是在其它实施例中，也可以仅使用一个控制引脚来控制第一至第四开关晶体管，或者使用两个控制引脚来控制第一至第四开关晶体管。
使用一个控制引脚时，第一至第四开关晶体管的控制端均与该控制引脚连接，通过该控制引脚输出的电平使第一至第二开关晶体管导通，第三和第四开关晶体管关关断， 或者第三和第四开关晶体管关导通，第一至第二开关晶体管关断。此时第一和第二开关晶体管类型相同，第三和第四开关晶体管类型相同，且第一开关晶体管和第三开关晶体管类型相反。例如前述示例性的第一开关晶体管11和第二开关晶体管12可以为PMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为NMOS晶体管。或者还可以是：第一开关晶体管11和第二开关晶体管12可以为NMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为PMOS晶体管。这样仅需要使用一个控制引脚即可实现对四个开关晶体管的控制，减少了控制器GPIO接口的引脚占用，并且控制信号相对简单。
使用两个控制引脚时，第一至第二开关晶体管的控制端均与第一控制引脚连接，第三至第四开关晶体管的控制端均与第二控制引脚连接，通过第一和第二控制引脚输出的电平使第一至第二开关晶体管导通，第三和第四开关晶体管关关断，或者第三和第四开关晶体管关导通，第一至第二开关晶体管关断。此时第一和第二开关晶体管类型相同，第三和第四开关晶体管类型相同即可，无需第一开关晶体管和第三开关晶体管类型相反。示例性的，第一开关晶体管11和第二开关晶体管12可以为PMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为PMOS晶体管。或者还可以是：第一开关晶体管11和第二开关晶体管12可以为NMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为NMOS晶体管。还可以是第一开关晶体管11和第二开关晶体管12可以为PMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为NMOS晶体管。或者还可以是：第一开关晶体管11和第二开关晶体管12可以为NMOS晶体管，第三开关晶体管13和第四开关晶体管14可以为PMOS晶体管。这种情形中，仅需根据开关晶体管的类型调节控制器控制引脚输出的电平即可实现上述控制效果。
还应当理解的是，当如图11所示使用四个控制引脚时，第一至第四开关晶体管的类型均可以为P型或N型，且无需相同。
图12为示例性示出的根据本申请实施例的电子设备的另一开关电路的示意图。参考图12，与图11不同的是，在图12所示电子设备中，开关电路170包括4个开关器件20。示例性地，开关器件20包括第一开关芯片21、第二开关芯片22、第三开关芯片23和第四开关芯片24。第一开关芯片21、第二开关芯片22、第三开关芯片23和第四开关芯片24均包括第一端、第二端和控制端。第一开关芯片21的第一端与外部接口140的第一数据引脚141连接，第二端与处理器110的第一数据引脚111连接，控制端与控制器120的通用输入输出接口(GPIO)的第一控制引脚连接连接。第二开关芯片22的第一端与外部接口140的第二数据引脚142连接，第二端与处理器110的第二数据引脚112连接，控制端与控制器120的通用输入输出接口(GPIO)的第二控制引脚连接。第三开关芯片23的第一端与外部接口140的第一数据引脚111连接，第二端与充电协议芯片130的第一数据引脚131连接，控制端与控制器120的通用输入输出接口(GPIO)的第三控制引脚连接。第四开关芯片24的第一端与外部接口140的第二数据引脚142连接，第二端与充电协议芯片130的第二数据引脚142连接，控制端与控制器120的通用输入输出接口(GPIO)的第四控制引脚连接。控制器120通过GPIO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚向第一开关芯片21、第二开关芯片22、第三开关芯片23和第四开关芯片24的控制端输出电平信号或控制信号，从而控制第一开关芯片21、 第二开关芯片22、第三开关芯片23和第四开关芯片24的导通和关断。
图12所示的电子设备的开关电路的工作原理与图11所示的电子设备的开关电路的工作原理类似，在此不再赘述。
图13为示例性示出的根据本申请实施例的接电子设备的又一开关电路的示意图。参考图13，与图11不同的是，在图13所示电子设备中，开关电路170包括2个开关器件30。示例性地，开关器件30包括第一开关芯片31和第二开关芯片32。第一开关芯片31和第二开关芯片32均包括两个输入端、两个输出端和一个控制端。第一开关芯片31的两个输入端分别与外部接口140的第一数据引脚141和第二数据引脚142连接，两个输出端分别与处理器110的第一数据引脚111和第二数据引脚112连接，从而构成第一协议识别通路。第二开关芯片32的两个输入端分别与外部接口140的第一数据引脚141和第二数据引脚142连接，两个输出端分别与充电协议芯片130的第一数据引脚111和第二数据引脚112连接，从而构成第二协议识别通路。第一开关芯片31和第二开关芯片32的控制端分别与控制器120的GPIO接口的第一控制引脚和第二控制引脚连接。控制器120向第一开关芯片31和第二开关芯片32的控制端施加控制信号，从而控制第一开关芯片31和第二开关芯片32的导通和关断，进而控制第一和第二协议识别通路的导通或关断。
图13所示的电子设备的开关电路的工作原理与图11所示的电子设备的开关电路的工作原理类似，在此不再赘述。
图14为示例性示出的根据本申请实施例的电子设备的又一开关电路的示意图。参考图14，与图11不同的是，在图14所示电子设备中，开关电路170包括1个开关芯片40。开关芯片包括四个输入端、四个输出端，二/四个控制端(图14中示例为两个控制端)。开关芯片40的两个输入端分别与外部接口140的第一数据引脚141和第二数据引脚142连接，两个输出端分别与处理器110的第一数据引脚111和第二数据引脚112连接，从而构成第一协议识别通路。开关芯片40的另外两个输入端分别与外部接口140的第一数据引脚141和第二数据引脚142连接，另外两个输出端分别与充电协议芯片130的第一数据引脚111和第二数据引脚112连接，从而构成第二协议识别通路。开关芯片40的二/四个控制端分别与控制器120的GPIO接口的2/4个控制引脚连接。控制器120向开关芯片40的控制端施加控制信号，从而控制控制第一和第二协议识别通路的导通或关断。
图14所示的电子设备的开关电路的工作原理与图11所示的电子设备的开关电路的工作原理类似，在此不再赘述。
综上可知，在本申请实施例提供的电子设备中，通过配置控制器120和开关电路170，使得默认第二协议识别通路(即充电协议识别通路)导通。当外部设备接入外部接口140后，先进行充电协议的识别，在充电协议识别失败后，再通过控制器120和开关电路170断开第二协议识别通路，并使第一协议识别通路导通，进行USB2.0设备的识别。且当USB2.0设备从USB接口140拔出后，通过控制器120和开关电路170再次使第二协议识别通路默认导通，等待下次外部设备的接入。采用本申请实施例提供的电子设备，通过外部接口不仅可以对支持诸如SCP协议等的终端进行快充，而且不会影响USB2.0设备的识别。
本申请实施例还提供一种设备识别方法，该设备识别方法例如可以应用于本实施例中的电子设备，具有相同的有益效果，在该实施例中未详尽描述的细节内容，可以参考上述电子设备的实施例。下面结合图8、图9和图11所示的电子设备对设备识别方法进行介绍。
如图15所示，设备识别方法可通过如下步骤实现：
S1501，控制器控制开关电路，使第二协议识别通路默认导通，第一协议识别通路默认断开。
例如，控制器140配置为默认拉高GIPO的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚的电平(即输出高电平)，使得第一开关晶体管11(PMOS)和第二开关晶体管12(PMOS)断开，第三开关晶体管13(NMOS)和第四开关晶体管14(NMOS)导通，从而使得第一协议识别通路断开，第二协议识别通路导通。
S1502，充电协议芯片与外部设备进行通信，进行充电协议检测，并将检测结果反馈至控制器。
例如，充电协议芯片130通过握手通道与待充电终端201完成握手，随后为电源引脚/电源通道提供例如5V的Vbus电压。然后，在待充电终端201基于BC1.2协议(Battery Charging v1.2)识别电子设备100为DCP(Dedicated Charging Port，专用充电接口)设备后，充电协议芯片130进行充电协议检测，并将检测结果反馈至控制器120。例如充电协议芯片130通过I2C总线向控制器120发送充电协议检测成功或失败的指示。
在充电协议芯片130充电协议检测成功后，进入步骤S1503，反之则进入步骤S1505。
S1503，控制器根据电池电量判断是否启动快充。
例如控制器120根据电池160的当前电量判断是否启动快充。例如，在电池160的当前电量大于设定阈值时，控制器120确定启动快充。
当控制器120确定启动快充后，进入步骤S1504，反之则进入步骤S1505。
S1504，充电协议芯片与终端沟通充电信息，并在沟通充电信息后给电压转换电路发送使能信号，启动快充。
例如，终端的充电协议芯片210根据电池220的当前电路确定所需要的充电电压和电流，然后将其发送至充电协议芯片130。充电协议芯片130向电压转换电路150发送使能信号，电压转换电路150根据充电协议芯片130确定的充电电压和电流通过USB接口140对外部设备进行快充。
S1505，控制器控制开关电路断开第二协议通路，导通第一协议识别通路。
例如，充电协议芯片130向控制器120发送充电协议识别失败或不启动快充的指示，控制器120根据该指示改变GPIO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚输出的电平信号或控制信号，使得第三开关晶体管13和第四开关晶体管14断开，第一开关晶体管11和第二开关晶体管12导通，使得第二协议识别通路断开，第一协议识别通路导通。随后，处理器110通过第一协议识别通路与外部设备通信，从而进行USB2.0协议识别，确定外部设备是否为USB2.0设备。当确定外部设备为USB2.0设备后则基于设备类型进行后续操作，例如数据读取或存储等。
S1506，处理器告知控制器USB2.0设备拔出。
例如，当外部设备从外部接口140拔出后，处理器110通过例如eSPI总线向控制器120发送USB2.0设备拔出的指示。
随后返回至步骤S1501，控制器120改变GPIO接口的第一控制引脚、第二控制引脚、第三控制引脚、第四控制引脚输出的电平信号或控制信号，使得第三开关晶体管13和第四开关晶体管14导通，第一开关晶体管11和第二开关晶体管12断开，从而使得第二协议识别通路导通，第一协议识别通路断开。
需要说明的是，上述示例仅示出一种设备识别方法的流程，但不构成对本申请的限定。例如，设备识别方法可以不包括上述步骤S1503，又或者上述步骤S1502和S1504可以合并为一个步骤。
可以理解的是，电子设备为了实现上述功能，其包含了执行各个功能相应的硬件和/或软件模块。结合本文中所公开的实施例描述的各示例的算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以结合实施例对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
一个示例中，图16示出了本申请实施例的一种装置500的示意性框图。装置500可包括：处理器501和收发器/收发管脚502，可选地，还包括存储器503。
装置500的各个组件通过总线504耦合在一起，其中总线504除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都称为总线504。
可选地，存储器503可以用于前述方法实施例中的指令。该处理器501可用于执行存储器503中的指令，并控制接收管脚接收信号，以及控制发送管脚发送信号。
装置500可以是上述方法实施例中的电子设备或电子设备的芯片。
其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
上述本申请实施例提供的一种设备识别方法中电子设备100所执行的步骤，也可以由电子设备100中包括的一种芯片系统来执行，其中，该芯片系统可以包括处理器和蓝牙芯片。该芯片系统可以与存储器耦合，使得该芯片系统运行时调用该存储器中存储的计算机程序，实现上述电子设备100执行的步骤。其中，该芯片系统中的处理器可以是应用处理器也可以是非应用处理器的处理器。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (33)

  1. 一种电子设备，其特征在于，包括：处理器、控制器、充电协议芯片、外部接口和开关电路；
    所述处理器、所述充电协议芯片和所述外部接口均包括数据引脚单元；
    所述处理器的数据引脚单元、所述充电协议芯片的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述开关电路；
    所述控制器用于控制所述开关电路，使所述外部接口的数据引脚单元与所述处理器的数据引脚单元和所述充电协议芯片的数据引脚单元其中之一导通，与所述处理器的数据引脚单元和所述充电协议芯片的数据引脚单元其中另一断开。
  2. 根据权利要求1所述的电子设备，其特征在于，
    所述外部接口用于与外部设备电连接；
    所述处理器用于在所述外部接口与所述外部设备连接，且所述处理器的数据引脚单元与所述外部接口的引脚单元导通时，对所述外部设备进行第一协议识别；
    所述充电协议芯片用于在所述外部接口与所述外部设备连接，且所述充电协议芯片的数据引脚单元与所述外部接口的引脚单元导通时，对所述外部设备进行第二协议识别；
    所述处理器和所述充电协议芯片分别与所述控制器电连接，用于向所述控制器发送表示协议识别成功或失败的指示；
    所述控制器用于在接收到所述处理器发送的表示第一协议识别成功的指示后，继续控制所述开关电路使所述外部接口的数据引脚单元与所述处理器的数据引脚单元导通，与所述充电协议芯片的数据引脚单元断开，以及在接收到所述处理器发送的表示第一协议识别失败的指示后，控制所述开关电路使所述外部接口的数据引脚单元与所述处理器的数据引脚单元断开，与所述充电协议芯片的数据引脚单元导通；
    所述控制器用于在接收到所述充电协议芯片发送的表示第二协议识别成功的指示后，继续控制所述开关电路使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通，与所述处理器的数据引脚单元断开，以及在接收到所述充电协议芯片发送的表示第二协议识别失败的指示后，控制所述开关电路使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元断开，与所述处理器的数据引脚单元导通。
  3. 根据权利要求2所述的电子设备，其特征在于，所述控制器控制所述开关电路使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通，与所述处理器的数据引脚单元断开；以及
    在接收到所述充电协议芯片发送的表示第二协议识别失败的指示后，控制所述开关电路使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元断开，与所述处理器的数据引脚单元导通。
  4. 根据权利要求2所述的电子设备，其特征在于，还包括电压转换电路和电池，
    所述外部接口还包括电源引脚；
    所述电池通过所述电压转换电路与所述外部接口的电源引脚电连接；
    所述充电协议芯片与所述电压转换电路连接，用于在所述充电协议芯片议识别成功之后向所述电压转换电路发送使能信号，使所述电压转换电路向所述外部接口的电源引脚提供设定电压。
  5. 根据权利要求4所述的电子设备，其特征在于，所述控制器还用于在接收到所述充电协议芯片发送的表示第二协议识别成功的指示后，获取所述电池的电量信息，并根据所述电池电量信息向所述充电协议芯片发送启动快充或不启动快充的指示。
  6. 根据权利要求5所述的电子设备，其特征在于，所述控制器在所述电池的电量大于设定阈值时向所述充电协议芯片发送启动快充的指示，在所述电池的电量小于等于设定阈值时向所述充电协议芯片发送不启动快充的指示。
  7. 根据权利要求2所述的电子设备，其特征在于，当所述外部设备为支持第一协议的设备，且所述外部设备从所述外部接口拔出后，所述处理器还用于在所述外部设备拔出后，向所述控制器发送所述外部设备拔出的指示，所述控制器根据所述外部设备拔出的指示，控制所述开关电路使所述外部接口的数据引脚单元与所述处理器的数据引脚单元断开，与所述充电协议芯片的数据引脚单元导通。
  8. 根据权利要求1-7中的任意一项所述的电子设备，其特征在于，所述开关电路包括开关芯片，所述处理器的数据引脚单元、所述充电协议芯片的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述开关芯片。
  9. 根据权利要求1-7中的任意一项所述的电子设备，其特征在于，所述开关电路包括第一开关单元和第二开关单元；
    所述处理器的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述第一开关单元，所述控制器用于控制所述第一开关单元以使所述外部接口的数据引脚单元与所述处理器的数据引脚单元导通或断开；
    所述充电协议芯片的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述第二开关单元，所述控制器用于控制所述第二开关单元以使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通或断开。
  10. 根据权利要求9所述的电子设备，其特征在于，所述第一开关单元和所述第二开关单元均包括开关芯片。
  11. 根据权利要求1-7中的任意一项所述的电子设备，其特征在于，所述数据引脚单元包括第一数据引脚和第二数据引脚；
    所述开关电路包括第一至第四开关单元；
    所述处理器的第一数据引脚、所述外部接口的第一数据引脚、所述控制器分别电连接至所述第一开关单元，所述控制器用于控制所述第一开关单元以使所述外部接口的第一数据引脚与所述处理器的第一数据引脚导通或断开；
    所述处理器的第二数据引脚、所述外部接口的第二数据引脚、所述控制器分别电连接至所述第二开关单元，所述控制器用于控制所述第二开关单元以使所述外部接口的第二数据引脚与所述处理器的第二数据引脚导通或断开；
    所述充电协议芯片的第一数据引脚、所述外部接口的第一数据引脚、所述控制器分别电连接至所述第三开关单元，所述控制器用于控制所述第三开关单元以使所述外部接口的第一数据引脚与所述充电协议芯片的第一数据引脚导通或断开；
    所述充电协议芯片的第二数据引脚、所述外部接口的第二数据引脚、所述控制器分别电连接至所述第四开关单元，所述控制器用于控制所述第四开关单元以使所述外部接口的第二数据引脚与所述充电协议芯片的第二数据引脚导通或断开。
  12. 根据权利要求11所述的电子设备，其特征在于，所述第一至第四开关单元均包括开关芯片或MOS晶体管。
  13. 根据权利要求12所述的电子设备，其特征在于，所述第一开关单元包括PMOS晶体管，所述第二开关单元包括PMOS晶体管，所述第三开关单元包括NMOS晶体管，所述第四开关单元包括NMOS晶体管。
  14. 根据权利要求2-7中的任一项所述的电子设备，其特征在于，所述第一协议包括USB2.0协议，所述第二协议包括SCP/FCP快充协议。
  15. 根据权利要求1-7中的任一项所述的电子设备，其特征在于，所述数据引脚单元包括DP引脚或DM引脚。
  16. 一种设备识别方法，应用于权利要求1-15中的任意一项所述的电子设备，其特征在于，所述方法包括：
    控制器控制所述开关电路，使所述外部接口的数据引脚单元与所述处理器的数据引脚单元和所述充电协议芯片的数据引脚单元其中之一导通，与所述处理器的数据引脚单元和所述充电协议芯片的数据引脚单元其中另一断开；
    所述处理器和所述充电协议芯片其中之一对所述外部接口所连接的外部设备的类型进行识别；
    在所述处理器和所述充电协议芯片其中之一识别失败之后，控制器控制所述开关电路，使所述外部接口的数据引脚单元与所述处理器的数据引脚单元和所述充电协议芯片的数据引脚单元其中之一断开，与所述处理器的数据引脚单元和所述充电协议芯片的数据引脚单元其中另一导通；
    所述处理器和所述充电协议芯片其中另一对所述外部接口所连接的外部设备的类型进行识别。
  17. 根据权利要求16所述的设备识别方法，其特征在于，
    所述控制器控制所述开关电路，使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通，与所述处理器的数据引脚单元断开；
    所述充电协议芯片对所述外部设备的类型进行识别；
    在所述充电协议芯片识别失败之后，控制器控制所述开关电路，使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元其中之一断开，与所述处理器的数据引脚单元的数据引脚单元导通；
    所述处理器对所述外部设备的类型进行识别。
  18. 根据权利要求17所述的设备识别方法，其特征在于，在所述外部接口所连接的外部设备为所述处理器所对应的类型时，该方法还包括：
    所述处理器在所述外部设备拔出之后向所述控制器发送所述外部设备拔出的指示；
    所述控制器在接收到所述外部设备拔出的指示后，控制所述开关电路，使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通，与所述处理器的数据引脚单元断开。
  19. 一种充电系统，其特征在于，包括权利要求1-15任一项所述的电子设备和终端；
    所述终端包括充电接口和电池；
    所述充电接口与所述外部接口电连接；
    所述电子设备通过所述外部接口和所述充电接口为所述终端内的所述电池充电。
  20. 一种电子设备，其特征在于，包括：处理器、控制器、充电协议芯片、外部接口和开关电路；
    所述处理器、所述充电协议芯片和所述外部接口均包括数据引脚单元；
    所述处理器的数据引脚单元、所述充电协议芯片的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述开关电路；
    所述控制器用于控制所述开关电路，使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通，与所述处理器的数据引脚单元断开；
    所述充电协议芯片用于在所述外部接口与外部设备连接时，对所述外部设备进行第二协议识别；
    所述控制器用于在接收到所述充电协议芯片发送的表示第二协议识别失败的指示后，控制所述开关电路使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元断开，与所述处理器的数据引脚单元导通；
    所述处理器用于在所述外部接口与所述外部设备连接，且所述处理器的数据引脚单元与所述外部接口的引脚单元导通时，对所述外部设备进行第一协议识别，
    所述第一协议包括数据传输协议，所述第二协议包括快充协议。
  21. 根据权利要求20所述的电子设备，其特征在于，
    所述控制器用于在接收到所述处理器发送的表示第一协议识别成功的指示后，继续控制所述开关电路使所述外部接口的数据引脚单元与所述处理器的数据引脚单元导通，与所述充电协议芯片的数据引脚单元断开，以及在接收到所述处理器发送的表示第一协议识别失败的指示后，控制所述开关电路使所述外部接口的数据引脚单元与所述处理器的数据引脚单元断开，与所述充电协议芯片的数据引脚单元导通；
    所述控制器用于在接收到所述充电协议芯片发送的表示第二协议识别成功的指示后，继续控制所述开关电路使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通，与所述处理器的数据引脚单元断开。
  22. 根据权利要求20所述的电子设备，其特征在于，还包括电压转换电路和电池，
    所述外部接口还包括电源引脚；
    所述电池通过所述电压转换电路与所述外部接口的电源引脚电连接；
    所述充电协议芯片与所述电压转换电路连接，用于在所述充电协议芯片议识别成功之后向所述电压转换电路发送使能信号，使所述电压转换电路向所述外部接口的电源引脚提供设定电压。
  23. 根据权利要求22所述的电子设备，其特征在于，所述控制器还用于在接收到所述充电协议芯片发送的表示第二协议识别成功的指示后，获取所述电池的电量信息，并根据所述电池电量信息向所述充电协议芯片发送启动快充或不启动快充的指示。
  24. 根据权利要求23所述的电子设备，其特征在于，所述控制器在所述电池的电量大于设定阈值时向所述充电协议芯片发送启动快充的指示，在所述电池的电量小于等于设定阈值时向所述充电协议芯片发送不启动快充的指示。
  25. 根据权利要求20所述的电子设备，其特征在于，当所述外部设备为支持第一协议的设备，且所述外部设备从所述外部接口拔出后，所述处理器还用于在所述外部设备拔出后，向所述控制器发送所述外部设备拔出的指示，所述控制器根据所述外部设备拔出的指示，控制所述开关电路使所述外部接口的数据引脚单元与所述处理器的数据引脚单元断开，与所述充电协议芯片的数据引脚单元导通。
  26. 根据权利要求20-25中的任意一项所述的电子设备，其特征在于，所述开关电路包括开关芯片，所述处理器的数据引脚单元、所述充电协议芯片的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述开关芯片。
  27. 根据权利要求20-25中的任意一项所述的电子设备，其特征在于，所述开关电 路包括第一开关单元和第二开关单元；
    所述处理器的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述第一开关单元，所述控制器用于控制所述第一开关单元以使所述外部接口的数据引脚单元与所述处理器的数据引脚单元导通或断开；
    所述充电协议芯片的数据引脚单元、所述外部接口的数据引脚单元、所述控制器分别电连接至所述第二开关单元，所述控制器用于控制所述第二开关单元以使所述外部接口的数据引脚单元与所述充电协议芯片的数据引脚单元导通或断开。
  28. 根据权利要求27所述的电子设备，其特征在于，所述第一开关单元和所述第二开关单元均包括开关芯片。
  29. 根据权利要求20-25中的任意一项所述的电子设备，其特征在于，所述数据引脚单元包括第一数据引脚和第二数据引脚；
    所述开关电路包括第一至第四开关单元；
    所述处理器的第一数据引脚、所述外部接口的第一数据引脚、所述控制器分别电连接至所述第一开关单元，所述控制器用于控制所述第一开关单元以使所述外部接口的第一数据引脚与所述处理器的第一数据引脚导通或断开；
    所述处理器的第二数据引脚、所述外部接口的第二数据引脚、所述控制器分别电连接至所述第二开关单元，所述控制器用于控制所述第二开关单元以使所述外部接口的第二数据引脚与所述处理器的第二数据引脚导通或断开；
    所述充电协议芯片的第一数据引脚、所述外部接口的第一数据引脚、所述控制器分别电连接至所述第三开关单元，所述控制器用于控制所述第三开关单元以使所述外部接口的第一数据引脚与所述充电协议芯片的第一数据引脚导通或断开；
    所述充电协议芯片的第二数据引脚、所述外部接口的第二数据引脚、所述控制器分别电连接至所述第四开关单元，所述控制器用于控制所述第四开关单元以使所述外部接口的第二数据引脚与所述充电协议芯片的第二数据引脚导通或断开。
  30. 根据权利要求29所述的电子设备，其特征在于，所述第一至第四开关单元均包括开关芯片或MOS晶体管。
  31. 根据权利要求30所述的电子设备，其特征在于，所述第一开关单元包括PMOS晶体管，所述第二开关单元包括PMOS晶体管，所述第三开关单元包括NMOS晶体管，所述第四开关单元包括NMOS晶体管。
  32. 根据权利要求20-25中的任一项所述的电子设备，其特征在于，所述第一协议包括USB2.0协议，所述第二协议包括SCP/FCP快充协议。
  33. 根据权利要求20-25中的任一项所述的电子设备，其特征在于，所述数据引脚 单元包括DP引脚或DM引脚。
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