WO2024021154A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2024021154A1
WO2024021154A1 PCT/CN2022/110982 CN2022110982W WO2024021154A1 WO 2024021154 A1 WO2024021154 A1 WO 2024021154A1 CN 2022110982 W CN2022110982 W CN 2022110982W WO 2024021154 A1 WO2024021154 A1 WO 2024021154A1
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region
inversion
doping
doped region
semiconductor structure
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PCT/CN2022/110982
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English (en)
French (fr)
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唐怡
肖剑锋
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长鑫存储技术有限公司
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Priority to EP22782647.6A priority Critical patent/EP4336567A4/en
Priority to US17/933,139 priority patent/US20240038846A1/en
Publication of WO2024021154A1 publication Critical patent/WO2024021154A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • Leakage currents that cause static power consumption in transistor devices mainly include: sub-threshold leakage current from source to drain, gate leakage current, or gate-induced drain leakage (Gate-Induce) that occurs in the overlap area of gate and drain.
  • Drain Leakage, GIDL Drain Leakage
  • GIDL gate-induced drain leakage
  • embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate includes an active area having a contact area; a stacked semiconductor layer and a conductive layer, the semiconductor layer is located in the contact area, wherein, The bandgap width of the material of the semiconductor layer is smaller than the bandgap width of the material of the active area; the contact plug is located on the surface of the conductive layer.
  • embodiments of the present disclosure provide a semiconductor structure, including: an active pillar, the active pillar includes: a channel region, and a first doped region and a second doped region located on both sides of the channel region.
  • Doping region wherein the channel region, the first doping region and the second doping region have the same doping type; an inversion doping region is provided in the channel region, and the inversion doping region is close to the first doping region , where the doping type in the inversion doped region is different from the doping type in the channel region; the gate, the gate surrounds part of the channel region, and on the plane where the axis of the active pillar is located, the projection of the gate It partially coincides with the projection of the inversion doped region.
  • the doping concentration of the channel region ranges from 1E 14 cm -3 to 1E 19 cm -3
  • the doping concentration of the first doped region and the second doped region ranges from 1E 19 cm -3 to 1E 22 cm -3
  • the doping concentration of the inversion doped region is 1E 17 cm -3 ⁇ 1E 19 cm -3 .
  • the active pillar is a cylinder, an elliptical cylinder or a prism, and the cross-sectional shape of the inversion doped region is the same as the cross-sectional shape of the active pillar.
  • the cross-sectional width of the channel region is greater than or equal to 30 nm.
  • the difference between the cross-sectional width of the channel region and the cross-sectional width of the inversion doped region is 10 nm to 20 nm.
  • the axis of the channel region coincides with the axis of the inversion doped region.
  • the axis of the channel region is offset from the axis of the inversion doped region, and the offset distance between the two axes is less than or equal to 5 nm.
  • the inversion doped region includes a connected first inversion region and a second inversion region, and on the plane where the axis of the active pillar is located, the projection of the first inversion region is located within the gate projection, The projection of the second inversion region is connected to the projection of the gate electrode.
  • the gate length is 60% to 80% of the length of the channel region, and the length of the first inversion region is 20% to 60% of the gate length.
  • the length of the second inversion region is 20% to 60% of the distance between the gate electrode and the first doped region.
  • the embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate includes an active pillar, the active pillar has a first doping type; forming an inversion doping area, the inversion doped area is located in the active pillar and close to one end of the active pillar.
  • the doping type of the inversion doped area is different from the doping type in the active pillar; a gate is formed, and the gate surrounds the active pillar.
  • the projection of the gate partially coincides with the projection of the inversion doped region; perform ion recombination of the first doping type on both ends of the active pillar Doping to form first doped regions and second doped regions respectively.
  • the first doped region is located on a side of the inversion doped region away from the gate, and the remaining active pillar between the first doped region and the second doped region serves as the channel region.
  • forming the inversion doping region includes: doping a region near one end of the active pillar to form an initial inversion doping region; doping the surface of the initial inversion doping region, To form a surface region with a first doping type, the remaining initial inversion doping region serves as an inversion doping region.
  • the doping concentration of the surface region is equal to the doping concentration of the channel region.
  • forming the inversion doped region includes: performing ion implantation into an internal region near one end of the active column to directly form the inversion doped region inside the active column.
  • Figure 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional structural diagram along the BB1 direction of Figure 1;
  • Figure 3 is a schematic diagram of another cross-sectional structure along the BB1 direction of Figure 1;
  • 4 to 9 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • the gate and drain regions need to be strictly aligned in theory, but in fact, when the drain is doped, an overlapping region of the drain and gate will inevitably occur.
  • an NMOS transistor when the negative voltage is turned off and the gate is at negative voltage, a large electric field will be generated in the area where the gate and drain overlap, and a thin depletion region will appear near the gate dielectric layer.
  • the avalanche multiplication effect and band tunneling effect will occur (electrons tunnel directly from the valence band of the P region to the conduction band of the N region), so that the drain electrode under the gate Minority carriers are generated in the device and pushed into the substrate by the negative gate voltage, thereby increasing the gate-induced drain leakage current.
  • An embodiment of the present disclosure provides a semiconductor structure to improve the problem of gate-induced drain leakage current in the semiconductor structure, thereby improving the reliability of the semiconductor structure.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional structural diagram of FIG. 1 along the BB1 direction.
  • FIG. 3 is a schematic cross-sectional structural diagram of FIG. 1 along the BB1 direction.
  • the semiconductor structure includes: an active pillar AA.
  • the active pillar AA includes: a channel region 100, and a first doping region 101 and a second doping region 102 located on both sides of the channel region 100, wherein the channel The channel region 100, the first doping region 101 and the second doping region 102 have the same doping type; an inversion doping region 200 is provided in the channel region 100, and the inversion doping region 200 is close to the first doping region 101 , where the doping type in the inversion doped region 200 is different from the doping type in the channel region 100; the gate 103, the gate 103 surrounds part of the channel region 100, and is located where the axis S of the active column AA is located. On the plane, the projection of the gate 103 partially coincides with the projection of the inversion doped region 200 .
  • the active column AA formed by the channel region 100 and the first doped region 101 and the second doped region 102 located on both sides of the channel region 100 can be used to form a structure of a junctionless transistor.
  • the first doped region 101 As one of the source electrode or the drain electrode of the junctionless transistor, the second doped region 102 serves as the other one of the source electrode or the drain electrode of the junctionless transistor.
  • the junctionless transistor can Reduce the steep concentration gradient distribution between the channel region and the source or drain, thereby reducing the thermal budget;
  • the gate 103 is arranged around part of the channel region 100, which can form a transistor with a fully surrounding gate structure and increase the area of the channel region
  • the full surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure; an inversion type is provided in the channel region 100
  • the doped region 200 can form a PN junction in the channel region 100.
  • the inversion doped region 200 extends toward the end close to the first doped region 101, and can open the gap between the gate 103 and the first doped region 101. distance, so that there is no overlapping area between the first doped region 101 and the gate electrode 103, thereby reducing the electric field intensity between the first doped region 101 and the gate electrode 103, and the effective current width of the first doped region 101 is also Therefore, the band-to-band tunneling current is reduced, thereby reducing the gate-induced drain leakage current between the first doped region 101 and the gate electrode 103 .
  • band tunneling (BTBT) current formula when the effective width W decreases, that is, when the width of the channel region 100 remaining after the cross-sectional width of the channel region 100 minus the cross-sectional width of the inversion doped region 200 decreases, The corresponding band-to-band tunneling current is reduced, thereby reducing the generation of gate-induced drain leakage current.
  • m*DOS represents the effective mass of the density of states
  • D represents the factor determined by the concentration of electrons and holes
  • W represents the effective width
  • Tpro represents the tunneling probability
  • E represents the electron kinetic energy
  • h represents Planck's constant
  • q represents the charge amount.
  • K is Boltzmann’s constant
  • T represents temperature.
  • the first doped region 101 serves as the drain of the transistor
  • the second doped region 102 serves as the source of the transistor.
  • the specific connection method of "source” and “drain” defined above does not constitute a limitation on the embodiments of the present application. In other embodiments, “drain” can be used to replace “source” and “source” can be used. “Drain” connection.
  • the active pillar AA includes: a channel region 100, a first doped region 101 and a second doped region 102, and the channel region 100, the first doped region 101 and the second doped region 102
  • the doping types are the same.
  • the doping types of the channel region 100, the first doping region 101 and the second doping region 102 may be P-type or N-type, and the N-type doping ions include phosphorus ions. , arsenic ions or antimony ions; P-type doping ions include boron ions, indium ions or boron fluoride ions.
  • the doping type of the inversion doping region 200 is different from the doping type of the channel region 100. If the doping ion type of the channel region 100 is N type, then the inversion doping region 200 The doping ion type of the channel region 100 is P type; if the doping ion type of the channel region 100 is P type, the doping ion type of the inversion doping region 200 is N type.
  • the doping concentration of the channel region 100 is 1E 14 cm -3 ⁇ 1E 19 cm -3 .
  • the doping concentration of the channel region 100 may be 1E 14 cm -3 or 1E 15 cm -3 , 1E 18 cm -3 or 1E 19 cm -3 ;
  • the doping concentration of the first doped region 101 and the second doped region 102 is 1E 19 cm -3 ⁇ 1E 22 cm -3 , for example, the first doped region
  • the doping concentration of 101 and the second doped region 102 can be 1E 19 cm -3 , 1E 20 cm -3 , 1E 21 cm -3 or 1E 22 cm -3 ;
  • the doping concentration of the inversion doped region 200 is 1E 17 cm -3 ⁇ 1E 19 cm -3 .
  • the doping concentration of the inversion doped region 200 may be 1E 17 cm -3 , 1E 18 cm -3 or 1E 19 cm -3 .
  • the relationship between the channel region 100 and the first doped region 101 and the second doped region 102 can be reduced.
  • the steep concentration gradient distribution between the two regions reduces the thermal budget; a moderate degree of doping in the inversion doped region can form a PN junction in the channel region 100, which can make the gate between the gate electrode 103 and the first doped region 101
  • the gate-induced drain leakage current cannot pass through the inversion doped region 200, thereby reducing the gate-induced drain leakage current when the transistor is in the off state and improving the reliability of the semiconductor structure.
  • the gate electrode 103 is arranged around the surface of part of the channel region 100, and on the plane where the axis S of the active pillar AA is located, the projection of the gate electrode 103 partially coincides with the projection of the inversion doped region 200. That is to say, the channel region 100 wrapped by the gate electrode 103 contains part of the inversion doping region 200, thereby forming the inversion doping region 200 as an obstacle on the path between the gate electrode 103 and the first doping region 101. To reduce the induced drain leakage current between the gate 103 and the first doped region 101 .
  • the gate 103 includes a gate dielectric layer 123 and a gate conductive layer 113 .
  • the gate dielectric layer 123 covers the surface disposed surrounding part of the channel region 100
  • the gate conductive layer 113 covers the surface of the gate dielectric layer 123 . , which can prevent the gate conductive layer 113 from reacting with the active pillar AA during subsequent processes, causing damage to the semiconductor structure.
  • the material of the gate dielectric layer 123 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the material of the gate conductive layer 113 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper or tungsten.
  • the inversion doping region 200 includes a connected first inversion region 201 and a second inversion region 202 .
  • the first inversion region 200 includes a connected first inversion region 201 and a second inversion region 202 .
  • the projection of the mold region 201 is located within the projection of the gate electrode 103, and the projection of the second inversion region 202 is connected to the projection of the gate electrode 103.
  • a part of the length of the inversion doped region 200 is within the range where the gate electrode 103 wraps the channel region 100 , and the other part of the length is between the gate electrode 103 and the first doped region 101 within the channel region 100 between.
  • the gate-induced drain leakage current is the leakage current between the gate and the drain, that is, the leakage current between the gate 103 and the first doped region 101.
  • the inversion doped region 200 When the inversion doped region 200 is located at the gate When the channel region 100 between the electrode 103 and the first doped region 101 is formed, the inversion doped region 200 can act as an obstacle on the path of the gate-induced drain leakage current to avoid the gate-induced drain leakage current from the inversion-type doped region 100 .
  • the doped region 200 passes through, thereby reducing the gate-induced drain leakage current between the gate 103 and the first doped region 101 and improving the reliability of the semiconductor structure.
  • the length of the gate 103 is 60% to 80% of the length of the channel region 100
  • the length of the first inversion region 201 is the length of the gate 103 20% to 60%. It can be understood that since a large electric field will be generated if the gate electrode 103 overlaps with the first doped region 101 or the second doped region 102, a thin depletion region will appear near the gate dielectric layer 123.
  • the length of the gate 103 is The length of the channel region 100 is 60% to 80%, which can prevent the first doped region 101 or the second doped region 102 from overlapping the gate electrode 103, thereby improving the reliability of the semiconductor structure.
  • the projection of the first inversion area 201 is located within the projection of the gate 103.
  • the shorter the length in the S direction the smaller the impact on the area where carriers pass through in actual use, and the corresponding blocking effect on the gate-induced drain leakage current is also reduced, which may not be able to reduce the gate-induced leakage.
  • the effect of extreme leakage current Therefore, the length of the first inversion region 201 needs to be adjusted within a certain range according to the actual situation, so as to block the gate-induced drain leakage current without affecting the performance of the semiconductor structure.
  • the length of the second inversion region 202 is 20% to 60% of the distance between the gate electrode 103 and the first doping region 101 . It can be understood that, on the plane where the axis S of the active pillar AA is located, the projection of the second inversion region 202 is connected to the projection of the gate electrode 103, that is, the second inversion region 202 is located between the gate electrode 103 and the first doped electrode. between the doped regions 101 to reduce the gate-induced drain leakage current between the first doped regions 101 and the gate 103 and improve the reliability of the semiconductor structure.
  • the length of the second inversion region 202 may come into contact with the first doped region 101, causing the transistor structure to be damaged, thereby affecting the performance of the semiconductor structure; if the length of the second inversion region 202 is too long, If it is too short, it may not be able to hinder the gate-induced drain leakage current, which will lead to a decrease in the reliability of the semiconductor structure. Therefore, the length of the second inversion region 202 needs to be adjusted within a certain range according to the actual situation, so as to block the gate-induced drain leakage current without affecting the performance of the semiconductor structure.
  • the active pillar AA is a cylinder, and the cross-sectional shape of the inversion doped region 200 is the same as the cross-sectional shape of the active pillar AA; in other embodiments, the active pillar AA can also be It is a prism or an elliptical cylinder, and the cross-sectional shape of the inversion doped region 200 is the same as the cross-sectional shape of the active pillar AA. It can be understood that, with reference to Figure 2, the active pillar AA is a cylinder or an elliptical cylinder, which can make the surface of the active pillar AA smoothly transition to avoid tip discharge or leakage in the transistor structure formed by the active pillar AA during operation.
  • the active pillar AA is a prism, for example, referring to Figure 3, when the cross-sectional shape of the active pillar AA is a square, the edges and corners of the active pillar AA can be chamfered, so that the edges and corners of the active pillar AA transition smoothly. , it can also avoid the formation of tips that lead to leakage or discharge.
  • the axis of the channel region coincides with the axis of the inversion doping region; in other embodiments, the axis of the channel region and the axis of the inversion doping region may be offset, and The axis offset distance between the two is less than or equal to 5nm. It can be understood that the inversion doping region is located inside the channel region to act as an obstacle to the gate-induced drain leakage current between the first doping region and the gate electrode. The axis of the channel region is related to the inversion doping region.
  • Coincidence of the axes of the regions can make the width of the remaining channel regions similar, so that the channel widths of carriers passing through the channel regions outside the inversion doped region are the same to keep carriers passing through the channel region along the periphery of the inversion doped region density is the same.
  • the axis of the channel region and the axis of the inversion doping region may shift.
  • the offset distance between the two axes is less than or equal to 5 nm, the distance between the axis of the inversion doping region and the axis of the inversion doping region can be reduced as much as possible.
  • the influence of the axis offset of the channel region avoids the excessive density gap of carriers passing along the channel region around the inversion doped region due to the transition of the inversion doped region close to the boundary of the channel region, so as to improve the stability of the semiconductor structure Use performance.
  • the cross-sectional width of the channel region 100 is greater than or equal to 30 nm.
  • the interface width of the channel region 100 may be 30 nm, 40 nm, or 60 nm. Since the inversion doping region 200 needs to be provided in the channel region 100, if the cross-sectional width of the channel region 100 is too small, that is, the diameter of the channel region 100 is too small, the inversion doping region 200 may not be located in the channel region 100. inside, thereby affecting the performance of the transistor structure.
  • the cross-sectional width of the channel region 100 is greater than or equal to 30 nm, which can facilitate the formation of the inversion doped region 200 in the channel region 100; however, the larger the cross-sectional width of the channel region 100, the corresponding volume of the formed transistor structure increases, and thus This results in a decrease in the integration density of semiconductor structures per unit space. Therefore, the cross-sectional width of the channel region 100 needs to be selected and adjusted according to actual conditions. This embodiment does not excessively limit the cross-sectional width of the channel region 100 .
  • the difference between the cross-sectional width of the channel region and the cross-sectional width of the inversion doped region is 10 nm to 20 nm. That is to say, after subtracting the cross-sectional width of the inversion doped region from the cross-sectional width of the channel region, the width of the remaining channel region is 10nm to 20nm.
  • the inversion doped region serves as the gate in the off state Obstruction of induced drain leakage current.
  • the remaining channel region serves as a channel for carriers. If the cross-sectional width of the inversion doped region is too large, the corresponding cross-sectional width of the remaining channel region will become larger.
  • the cross-sectional width of the inversion doped region is too small, the corresponding inversion doped region will induce leakage to the gate.
  • the blocking effect of extreme leakage current is reduced, resulting in a decrease in the reliability of the semiconductor structure. Therefore, the difference between the cross-sectional width of the channel region and the cross-sectional width of the inversion doped region needs to be set within a certain range to prevent the gate-induced drain leakage current while maintaining the performance of the semiconductor structure.
  • the semiconductor structure provided by the embodiment of the present disclosure can be used to form a structure of a junctionless transistor through the channel region and the active pillars formed by the first and second doping regions located on both sides of the channel region.
  • the doped region serves as one of the source or drain of the junctionless transistor, and the second doped region serves as the other of the source or drain of the junctionless transistor.
  • the junctionless transistor has The transistor can reduce the steep concentration gradient distribution between the channel area and the source or drain, thereby reducing the thermal budget; the gate is set around part of the channel area, which can form a transistor with a fully surrounding gate structure, increasing the area of the channel area In order to improve the transistor's ability to control the current, thereby improving the performance of the semiconductor structure, at the same time, the fully surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure; setting up an inversion doping in the channel region doped region, a PN junction can be formed in the channel region, in which the inversion doped region extends toward the end of the first doped region, which can widen the distance between the gate and the first doped region, so that the first doped region There is no overlapping area between the impurity region and the gate electrode, thereby reducing the electric field intensity between the first doping region and the gate electrode, and the effective current width of the first doping region also decreases, thereby reducing the band
  • Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure to improve the problem of gate-induced drain leakage current in the semiconductor structure and improve the reliability of the semiconductor structure.
  • FIG. 4 to 9 are schematic structural diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. The details are as follows:
  • a substrate (not shown in the figure) is provided, including active pillars AA having a first doping type.
  • the material of the substrate may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.
  • the material of the active pillar AA may be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.
  • the material of the active pillar AA is the same as the material of the substrate; in other embodiments, the material of the active pillar AA may be different from the material of the substrate.
  • the first doping type may be P-type or N-type.
  • N-type doping ions include phosphorus ions, arsenic ions or antimony ions;
  • P-type doping ions include boron ions, indium ions or boron fluoride ions. .
  • an inversion doping region 200 is formed.
  • the inversion doping region 200 is close to one end of the active column AA.
  • the doping type of the inversion doping region 200 is different from the doping type in the active column AA.
  • the doping type of the inversion doping region 200 is different from the doping type of the active pillar AA. If the doping ion type of the active pillar AA is N type, then the inversion doping region 200 The doping ion type of the active pillar AA is P type; if the doping ion type of the active pillar AA is P type, the doping ion type of the inversion doped region 200 is N type.
  • forming the inversion doping region includes: referring to Figure 6, doping a region near one end of the active pillar AA to form an initial inversion doping region 210; referring to Figure 7, doping the initial inversion doping region The surface of the doped region 210 is doped to form a surface region 220 with a first doping type, and the remaining initial inverted doped region 210 serves as the inverted doped region 200 .
  • the doping type forming the initial inversion doping region 210 is different from the doping type of the active pillar. If the doping ion type of the active pillar AA is N type, then the initial inversion doping type The doping ion type of the doping region 210 is P type; if the doping ion type of the active pillar AA is P type, the doping ion type of the initial inversion doping region 210 is N type.
  • the surface of the initial inversion doping region 210 is doped to form a surface region 220 with a first doping type. That is, if the doping ion type of the active pillar AA is P type, the initial inversion doping is The type of doping ions used for doping the surface of the region 210 is P type; if the type of doping ions used for the active pillar AA is N type, the type of doping ions used for doping the surface of the initial inversion doped region 210 The type is N type.
  • the doping concentration of surface region 220 is equal to the doping concentration in active pillar AA. Making the doping concentration of the active pillar AA around the inversion doping region the same can avoid the use of semiconductor structures due to different doping concentrations in the channel region other than the inversion doping region after forming the transistor structure. Performance suffers as a result.
  • forming the inversion doping region includes: performing ion implantation on an internal region near one end of the active column, and directly forming the inversion doping region inside the active column to form the semiconductor shown in Figure 4 structure.
  • a PN junction can be formed in the active pillar, so that in the subsequent formation of the transistor structure, the source or drain formed close to one end of the inversion doped region can be connected with the active column.
  • the distance between the gates in the middle of the source pillars is so that there is no overlapping area between the source or drain of the transistor and the gate, thereby reducing the electric field intensity of the source or drain and the gate, and the source or drain.
  • the effective current width is also reduced, thereby reducing the band tunneling current, thereby reducing the gate-induced drain leakage current between the source or drain and the gate.
  • a gate electrode 103 is formed.
  • the gate electrode 103 surrounds part of the surface of the active pillar AA, and on the plane where the axis S of the active pillar AA is located, the projection of the gate electrode 103 and the projection part of the inversion doped region 200 coincide.
  • a transistor with a fully surrounding gate structure can be formed, increasing the area of the channel region to improve the transistor's ability to control current, thereby improving the performance of the semiconductor structure.
  • the entire The surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure.
  • the step of forming the gate 103 includes: forming a gate dielectric layer 123 surrounding part of the surface of the active pillar AA; forming a gate conductive layer 113 covering the gate.
  • the gate dielectric layer 123 covers the surface surrounding part of the channel region 100, and the gate conductive layer 113 covers the surface of the gate dielectric layer 123, which can prevent the gate conductive layer 113 from reacting with the active pillar AA during subsequent processes, causing damage to the semiconductor structure.
  • the material forming the gate dielectric layer 123 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the material forming the gate conductive layer 113 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper or tungsten.
  • two ends of the active pillar AA are heavily doped with ions of the first doping type to form a first doped region 101 and a second doped region 102 respectively.
  • the first doped region 101 is located on the side of the inversion doped region 200 away from the gate 103.
  • the first doped region 101 can be used as one of the source or drain of the transistor, and the second doped region 102 can be used as the transistor.
  • the other one of the source or drain, the remaining active column AA between the first doped region 101 and the second doped region 102 serves as the channel region 100, thereby forming a junctionless transistor structure.
  • junctionless transistors can reduce the steep concentration gradient distribution between the channel region 100 and the source or drain, thereby reducing the thermal budget.
  • the first doping region 101 is located on the side of the inversion doping region 200 away from the gate 103 , that is, the inversion doping region 200 is close to the first doping region in the active pillar AA. 101; in other embodiments, the inversion doped region 200 may be located close to one end of the second doped region 102 in the active column AA.
  • the first doped region 101 serves as the drain of the transistor, and the second doped region 102 serves as the source of the transistor.
  • the specific connection method of "source” and “drain” defined above does not constitute a limitation on the embodiments of the present application. In other embodiments, “drain” can be used to replace “source” and “source” can be used. “Drain” connection.
  • the doping concentration of the channel region 100 is 1E 14 cm -3 ⁇ 1E 19 cm -3 .
  • the doping concentration of the channel region 100 may be 1E 14 cm -3 or 1E 15 cm -3 , 1E 18 cm -3 or 1E 19 cm -3 ;
  • the doping concentration of the first doped region 101 and the second doped region 102 is 1E 19 cm -3 ⁇ 1E 22 cm -3 , for example, the first doped region
  • the doping concentration of 101 and the second doped region 102 can be 1E 19 cm -3 , 1E 20 cm -3 , 1E 21 cm -3 or 1E 22 cm -3 ;
  • the doping concentration of the inversion doped region 200 is 1E 17 cm -3 ⁇ 1E 19 cm -3 .
  • the doping concentration of the inversion doped region 200 may be 1E 17 cm -3 , 1E 18 cm -3 or 1E 19 cm -3 .
  • the first doped region 101 and the second doped region 102 heavily doped and the channel region 100 lightly doped, the relationship between the channel region 100 and the first doped region 101 and the second doped region 102 can be reduced.
  • the steep concentration gradient distribution between the two regions reduces the thermal budget; a moderate degree of doping in the inversion doped region can form a PN junction in the channel region 100, which can make the gate between the gate electrode 103 and the first doped region 101
  • the gate-induced drain leakage current cannot pass through the inversion doped region 200, thereby reducing the gate-induced drain leakage current when the transistor is in the off state and improving the reliability of the semiconductor structure.
  • the semiconductor structure manufacturing method provided by the embodiments of the present disclosure can be used to form a junctionless transistor structure through the active pillars formed by the channel region and the first and second doped regions located on both sides of the channel region.
  • the first doped region serves as one of the source or drain of the junctionless transistor
  • the second doped region serves as the other of the source or drain of the junctionless transistor.
  • the junctionless transistor can reduce the steep concentration gradient distribution between the channel area and the source or drain, thereby reducing the thermal budget; the gate is set around part of the channel area, which can form a transistor with a fully surrounding gate structure and increase the channel area. area to improve the transistor's ability to control current, thereby improving the performance of the semiconductor structure.
  • the full surround gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure; setting up an inverter in the channel area Type doped region can form a PN junction in the channel region, wherein the inverted doped region extends toward the end of the first doped region, which can widen the distance between the gate and the first doped region, so that the third There is no overlapping area between a doped region and the gate, thereby reducing the electric field intensity between the first doped region and the gate, and the effective current width of the first doped region is also reduced, thereby reducing the band-to-band tunneling current. , thereby reducing the gate-induced drain leakage current between the first doped region and the gate electrode.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及其制作方法，半导体结构包括：有源柱，有源柱包括：沟道区，以及位于沟道区两侧的第一掺杂区和第二掺杂区，其中，沟道区、第一掺杂区和第二掺杂区的掺杂类型相同；沟道区中设置有反型掺杂区，反型掺杂区靠近第一掺杂区，其中，反型掺杂区中的掺杂类型与沟道区中掺杂类型不同；栅极，栅极环绕部分沟道区，且于有源柱的轴线所在的平面上，栅极的投影与反型掺杂区的投影部分重合。

Description

半导体结构及其制作方法
交叉引用
本公开要求于2022年07月28日递交的名称为“半导体结构及其制作方法”、申请号为202210899449.0的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
晶体管器件中引发静态功耗的泄露电流主要包括：源极到漏极的亚阈泄露电流、栅极泄露电流或者发生在栅极和漏极交叠区的栅极诱导漏极泄漏(Gate-Induce Drain Leakage，GIDL)电流。而在这些泄露电流中，当晶体管器件处于关态或者处于等待状态时，GIDL电流在泄露电流中处主导地位，由此可见，GIDL电流已经成为影响小尺寸晶体管器件可靠性和功耗等方面的主要原因之一。
如何降低接触结构与导电结构之间的接触电阻，晶体管器件的漏极在掺杂过程中不可避免的会存在与栅极交叠的区域，该栅漏交叠区域容易产生较高的GIDL电流，从而使漏电流增加。当栅漏交叠区域的栅漏电压很大时，栅漏交叠区域界面附近衬底中电子在价带和导带之间发生带间隧穿(BTBT)形成电流，这种电流称之为GIDL隧穿电流，随着栅介质层越来越薄，GIDL隧穿电流急剧增加，GIDL隧穿电流对晶体管器件的可靠性产生较大影响。
当工艺进入超深亚微米时代后，由于晶体管器件尺寸日益缩小，GIDL电流引发的众多可靠性问题变得愈加严重；因此，需要一种减小GIDL电流的方法，能够有效地减小GIDL电流的同时有效控制漏极的横向扩散及对器件特性的影响。
发明内容
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底，基底包括具有接触区的有源区；层叠设置的半导体层以及导电层，半导体层位于接触区，其中，半导体层的材料的禁带宽度小于有源区的材料的 禁带宽度；接触插塞，接触插塞位于导电层的表面。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：有源柱，有源柱包括：沟道区，以及位于沟道区两侧的第一掺杂区和第二掺杂区，其中，沟道区、第一掺杂区和第二掺杂区的掺杂类型相同；沟道区中设置有反型掺杂区，反型掺杂区靠近第一掺杂区，其中，反型掺杂区中的掺杂类型与沟道区中掺杂类型不同；栅极，栅极环绕部分沟道区，且于有源柱的轴线所在的平面上，栅极的投影与反型掺杂区的投影部分重合。
在一些实施例中，沟道区的掺杂浓度为1E 14cm -3～1E 19cm -3，第一掺杂区和第二掺杂区的掺杂浓度为1E 19cm -3～1E 22cm -3，反型掺杂区的掺杂浓度为1E 17cm -3～1E 19cm -3。
在一些实施例中，有源柱为圆柱体、椭圆柱体或棱柱体，反型掺杂区的截面形状与有源柱的截面形状相同。
在一些实施例中，沟道区的截面宽度大于等于30nm。
在一些实施例中，沟道区的截面宽度与反型掺杂区的截面宽度之差为10nm～20nm。
在一些实施例中，沟道区的轴线与反型掺杂区的轴线重合。
在一些实施例中，沟道区的轴线与反型掺杂区的轴线偏移，且两者的轴线偏移距离小于等于5nm。
在一些实施例中，反型掺杂区包括相连的第一反型区和第二反型区，在有源柱的轴线所在的平面上，第一反型区的投影位于栅极投影内，第二反型区的投影与栅极的投影相接。
在一些实施例中，在所述有源柱的轴线方向上，栅极长度为沟道区长度的60％～80％，第一反型区的长度为栅极长度的20％～60％。
在一些实施例中，在所述有源柱的轴线方向上，第二反型区的长度为栅极与第一掺杂区之间距离的20％～60％。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制作方法，包括：提供基底，基底包括有源柱，有源柱具有第一掺杂类型；形成反型掺杂区，反型掺杂区位于有源柱内，且靠近有源柱的一端，反型掺杂区的掺杂类型与有源柱中的掺杂类型不同；形成栅极，栅极环绕有源柱的部分 表面，且于有源柱的轴线所在的平面上，栅极的投影与反型掺杂区的投影部分重合；对有源柱的两个端部进行第一掺杂类型的离子重掺杂，以分别形成第一掺杂区和第二掺杂区。
在一些实施例中，第一掺杂区位于反型掺杂区远离栅极的一侧，第一掺杂区与第二掺杂区之间剩余的有源柱作为沟道区。
在一些实施例中，形成反型掺杂区，包括：对靠近有源柱一端的区域进行掺杂处理，形成初始反型掺杂区；对初始反型掺杂区的表面进行掺杂处理，以形成具有第一掺杂类型的表面区域，剩余的初始反型掺杂区作为反型掺杂区。
在一些实施例中，表面区域的掺杂浓度等于沟道区的掺杂浓度。
在一些实施例中，形成反型掺杂区，包括：对靠近有源柱一端的内部区域进行离子注入，直接在有源柱内部形成反型掺杂区。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动新的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的半导体结构示意图；
图2为图1沿BB1方向的剖面结构示意图；
图3为图1沿BB1方向的另一种剖面结构示意图；
图4至图9为本公开另一实施例提供的半导结构的制作方法各个步骤对应的结构示意图。
具体实施方式
由背景技术可知，半导体结构中存在栅极诱导漏极泄漏电流的问题。
分析发现，在晶体管结构中，栅极与漏极区域在理论上是需要严格对齐的，但是实际上在对漏极进行掺杂时，不可避免的会产生漏极与栅极的交叠区域。例如，对于NMOS管而言，当负压关断，栅极为负压时，栅极与漏极交叠 的区域会产生较大的电场，靠近栅介质层的位置会出现一个薄的耗尽区，由于薄的耗尽区和较高的电场会发生雪崩倍增效应和带带隧穿效应(电子直接从P区的价带隧穿到N区的导带)，从而在栅极下方的漏极中产生少数载流子，并被负栅极电压推入衬底，进而增加了栅极诱导漏极泄漏电流。
本公开一实施例提供一种半导体结构，以改善半导体结构中栅极诱导漏极泄漏电流的问题，从而提高半导体结构的可靠性。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1为本公开一实施例提供的半导体结构示意图，图2为图1沿BB1方向的剖面结构示意图，图3为图1沿BB1方向的另一种剖面结构示意图，以下将结合附图对本实施例提供的半导体结构进行详细说明，具体如下：
参考图1，半导体结构包括：有源柱AA，有源柱AA包括：沟道区100，以及位于沟道区100两侧的第一掺杂区101和第二掺杂区102，其中，沟道区100、第一掺杂区101和第二掺杂区102的掺杂类型相同；沟道区100中设置有反型掺杂区200，反型掺杂区200靠近第一掺杂区101，其中，反型掺杂区200中的掺杂类型与沟道区100中掺杂类型不同；栅极103，栅极103环绕部分沟道区100，且于有源柱AA的轴线S所在的平面上，栅极103的投影与反型掺杂区200的投影部分重合。
通过沟道区100以及位于沟道区100两侧的第一掺杂区101和第二掺杂区102形成的有源柱AA，可以用于构成无结晶体管的结构，第一掺杂区101作为无结晶体管的源极或者漏极中的一者，第二掺杂区102作为无结晶体管的源极或者漏极中的另一者，相对于有结型晶体管来说，无结晶体管可以降低沟道区与源极或者漏极之间陡峭的浓度梯度分布，从而降低热预算；栅极103环绕部分沟道区100设置，可以形成全环绕栅极结构的晶体管，增加沟道区的面积以提高晶体管对电流的控制能力，进而提高半导体结构的使用性能，同时，全环绕栅极结构可以提高半导体结构的空间利用率，从而进一步半导体结构的集成密度；在沟道区100中设置反型掺杂区200，可以在沟道区100中形成PN结，其中，反型掺杂区200向靠近第一掺杂区101端延伸，可以拉开栅极103与第一掺杂区101之间的距离，使第一掺杂区101与栅极103之间没有重叠区 域，从而降低第一掺杂区101与栅极103之间电场强度，并且，第一掺杂区101的有效电流宽度也降低，从而带带隧穿电流降低，进而降低第一掺杂区101与栅极103之间的栅极诱导漏极泄漏电流。
根据下述带带隧穿(BTBT)电流公式可知，当有效宽度W降低时，即沟道区100的截面宽度减去反型掺杂区200截面宽度后剩余的沟道区100宽度降低时，相应带带隧穿电流随之降低，进而减少栅极诱导漏极泄漏电流的产生。
Figure PCTCN2022110982-appb-000001
其中，m*DOS表示态密度有效质量；D表示由电子和空穴浓度决定的因子；W表示有效宽度；Tpro表示隧穿机率；E表示电子动能；h表示普朗克常数；q表示电荷量；K为波尔兹曼常数；T表示温度。
需要说明的是，在本实施例中，第一掺杂区101作为晶体管的漏极，第二掺杂区102作为晶体管的源极。上述定义的具体“源极”和“漏极”的连接方式，并不构成对本申请实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
对于有源柱AA，有源柱AA包括：沟道区100、第一掺杂区101和第二掺杂区102，且沟道区100、第一掺杂区101和第二掺杂区102的掺杂类型相同，在一些实施例中，沟道区100、第一掺杂区101和第二掺杂区102的掺杂类型可以是P型或者N型，N型掺杂离子包括磷离子、砷离子或者锑离子；P型掺杂离子包括硼离子、铟离子或者氟化硼离子。
对于反型掺杂区200，反型掺杂区200的掺杂类型与沟道区100的掺杂类型不同，若沟道区100的掺杂离子类型为N型，则反型掺杂区200的掺杂离子类型为P型；若沟道区100的掺杂离子类型为P型，则反型掺杂区200的掺杂离子类型为N型。
在一些实施例中，沟道区100的掺杂浓度为1E 14cm -3～1E 19cm -3，例如，沟道区100的掺杂浓度可以是1E 14cm -3、1E 15cm -3、1E 18cm -3或者1E 19cm -3；第一掺杂区101和第二掺杂区102的掺杂浓度为1E 19cm -3～1E 22cm -3，例如，第一掺杂区101和第二掺杂区102的掺杂浓度可以是1E 19cm -3、1E 20cm -3、1E 21cm -3或者1E 22cm -3；反型掺杂区200的掺杂浓度为1E 17cm -3～1E 19cm -3，例如，反型掺杂区200的掺杂浓度可以是1E 17cm -3、1E 18cm -3或者1E 19cm -3。
通过使第一掺杂区101和第二掺杂区102形成重掺杂，沟道区100形成 轻掺杂，可以降低沟道区100与第一掺杂区101和第二掺杂区102之间的陡峭的浓度梯度分布，从而降低热预算；反型掺杂区形成中等程度的掺杂可以在沟道区100中形成PN结，可以使栅极103与第一掺杂区101之间栅极诱导漏极泄漏电流无法从反型掺杂区200通过，从而降低晶体管在关态时栅极诱导漏极泄漏电流，提高半导体结构的可靠性。
对于栅极103，栅极103环绕部分沟道区100的表面设置，且于有源柱AA的轴线S所在的平面上，栅极103的投影与反型掺杂区200的投影部分重合。也就是说，栅极103包裹的沟道区100中含有部分反型掺杂区200，从而在栅极103至第一掺杂区101之间的路径上形成反型掺杂区200作为阻碍，以降低栅极103至第一掺杂区101之间的诱导漏极泄漏电流。
继续参考图1，在一些实施例中，栅极103包括栅介质层123和栅导电层113，栅介质层123覆盖环绕部分沟道区100的表面设置，栅导电层113覆盖栅介质层123表面，可以防止后续工艺过程中栅导电层113与有源柱AA发生反应，导致半导体结构的损坏。
对于栅介质层123，栅介质层123的材料包括氧化硅、氮化硅或者氮氧化硅中的至少一种。
对于栅导电层113，栅导电层113的材料包括多晶硅、氮化钛、铝化钛、氮化钽、钽、铜、铝、镧、铜或者钨中的至少一种。
继续参考图1，在本实施例中，反型掺杂区200包括相连的第一反型区201和第二反型区202，在有源柱AA的轴线S所在的平面上，第一反型区201的投影位于栅极103投影内，第二反型区202的投影与栅极103的投影相接。也就是说，反型掺杂区200沿有源柱AA的轴线S方向上，一部分长度处于栅极103包裹沟道区100的范围内，另一部分长度处于栅极103与第一掺杂区101之间的沟道区100内。可以理解的是，栅极诱导漏极泄漏电流是栅极与漏极之间的泄漏电流，即栅极103与第一掺杂区101之间的泄露电流，当反型掺杂区200位于栅极103与第一掺杂区101之间的沟道区100时，反型掺杂区200可以相当于栅极诱导漏极泄漏电流路径上的阻碍，避免栅极诱导漏极泄漏电流从反型掺杂区200通过，从而可以降低栅极103与第一掺杂区101之间的栅极诱导漏极泄漏电流，提高半导体结构的可靠性。
进一步地，在一些实施例中，沿有源柱AA的轴线S方向上，栅极103长度为沟道区100长度的60％～80％，第一反型区201的长度为栅极103长度的 20％～60％。可以理解的是，由于栅极103与第一掺杂区101或者第二掺杂区102若有重叠区域会产生较大的电场，靠近栅介质层123的位置会出现一个薄的耗尽区，而薄的耗尽区和较高的电场，会发生雪崩倍增效应和带带隧穿效应，从而影响半导体结构的性能；因此，在有源柱AA的轴线S方向上，栅极103的长度为沟道区100长度的60％～80％，可以避免第一掺杂区101或者第二掺杂区102与栅极103产生重叠区域，从而提高半导结构的可靠性。在有源柱AA的轴线S所在的平面上，第一反型区201的投影位于栅极103投影内，第一反型区201沿有源柱AA的轴线S方向上的长度越长，与栅极103的投影重合面积越大，则对于晶体管来说，实际使用时的载流子通过的区域变小，进而可能造成半导体结构受到影响；第一反型区201沿有源柱AA的轴线S方向上的长度越短，则对于实际使用时的载流子通过的区域的影响变小，相应的栅极诱导漏极泄漏电流的阻碍作用也减小，可能无法起到降低栅极诱导漏极泄漏电流的作用。因此，第一反型区201的长度需要根据实际情况，在一定范围内进行调整，以达到阻碍栅极诱导漏极泄漏电流的同时，不影响半导体结构的使用性能。
在一些实施例中，沿有源柱AA的轴线S方向上，第二反型区202的长度为栅极103与第一掺杂区101之间距离的20％～60％。可以理解的是，在有源柱AA的轴线S所在的平面上，第二反型区202的投影与栅极103的投影相接，即第二反型区202位于栅极103与第一掺杂区101之间，以降低第一掺杂区101与栅极103之间的栅极诱导漏极泄漏电流，提高半导体结构的可靠性。若第二反型区202的长度过长，则可能与第一掺杂区101接触，从而导致晶体管结构被破坏，进而导致半导体结构的性能受到影响；若第二反型掺杂区202的长度过短，则对于栅极诱导漏极泄漏电流可能无法产生阻碍作用，进而导致半导体结构的可靠性下降。因此，第二反型区202的长度需要根据实际情况，在一定范围内进行调整，以达到阻碍栅极诱导漏极泄漏电流的同时，不影响半导体结构的使用性能。
参考图2，在本实施例中，有源柱AA为圆柱体，且反型掺杂区200的截面形状与有源柱AA的截面形状相同；在其他实施例中，有源柱AA还可以是棱柱体或者椭圆柱，反型掺杂区200的截面形状与有源柱AA的截面形状相同。可以理解的是，参考图2，有源柱AA为圆柱体或者椭圆柱体可以使有源柱AA的表面圆滑过渡，以避免有源柱AA形成的晶体管结构在工作过程中发生尖端放电或者漏电现象。当有源柱AA为棱柱体时，例如，参考图3，有源柱AA的截面形状为正方形时，可以对有源柱AA的棱角进行倒角处理，从而 使有源柱AA的棱角平缓过渡，也可以避免形成尖端导致漏电或者放电现象。
需要注意的是，在本实施例中，沟道区的轴线与反型掺杂区的轴线重合；在其他实施例中，沟道区的轴线与反型掺杂区的轴线可以偏移，且两者的轴线偏移距离小于等于5nm。可以理解的是，反型掺杂区位于沟道区的内部，以作为第一掺杂区与栅极之间的栅极诱导漏极泄露电流的阻碍，沟道区的轴线与反型掺杂区的轴线重合可以使剩余的沟道区宽度相近，从而载流子通过反型掺杂区以外的沟道区的通道宽度相同，以保持载流子沿反型掺杂区周围通过沟道区时的密度相同。然而实际半导体结构的制作过程中，沟道区的轴线与反型掺杂区的轴线可能发生偏移，当两者的轴线偏移距离小于等于5nm，可以尽可能降低反型掺杂区轴线与沟道区轴线偏移的影响，避免由于反型掺杂区过渡靠近沟道区边界，导致载流子沿反型掺杂区周围的沟道区通过的密度差距过大，以提高半导体结构的使用性能。
继续参考图2，在一些实施例中，沟道区100的截面宽度大于等于30nm，例如，沟道区100的界面宽度可以是30nm、40nm或者60nm。由于沟道区100中需要设置反型掺杂区200，若沟道区100的截面宽度过小，即沟道区100的直径过小，则反型掺杂区200可能无法位于沟道区100的内部，进而导致晶体管结构的使用性能受到影响。沟道区100的截面宽度大于等于30nm，可以便于在沟道区100中形成反型掺杂区200；但沟道区100的截面宽度越大，相应的所形成晶体管结构的体积增大，进而导致半导体结构在单位空间内的集成密度下降，因此，沟道区100的截面宽度需要根据实际情况进行选择和调整，本实施例不对沟道区100的截面宽度做过度的限定。
进一步地，在一些实施例中，沟道区的截面宽度与反型掺杂区的截面宽度之差为10nm～20nm。也就是说，沟道区的截面宽度减去反型掺杂区的截面宽度后，剩余沟道区的宽度为10nm～20nm，可以理解的是，反型掺杂区在关态下作为栅极诱导漏极泄漏电流的阻碍，在晶体管结构的使用过程中，剩余的沟道区作为载流子的通道，若反型掺杂区的截面宽度过大，相应的剩余沟道区的截面宽度越小，晶体管使用过程中的载流子通道宽度也越小，从而导致晶体管的使用性能可能受到影响；若反型掺杂区的截面宽度过小，相应的反型掺杂区对栅极诱导漏极泄漏电流的阻碍作用降低，从而导致半导体结构的可靠性下降。因此，沟道区的截面宽度与反型掺杂区的截面宽度之差需要设置在一定范围内，以保持半导体结构的性能不受影响的同时达到阻碍栅极诱导漏极泄漏电流的作用。
本公开实施例提供的半导体结构，通过沟道区以及位于沟道区两侧的第一掺杂区和第二掺杂区形成的有源柱，可以用于构成无结晶体管的结构，第一掺杂区作为无结晶体管的源极或者漏极中的一者，第二掺杂区作为无结晶体管的源极或者漏极中的另一者，相对于有结型晶体管来说，无结晶体管可以降低沟道区与源极或者漏极之间陡峭的浓度梯度分布，从而降低热预算；栅极环绕部分沟道区设置，可以形成全环绕栅极结构的晶体管，增加沟道区的面积以提高晶体管对电流的控制能力，进而提高半导体结构的使用性能，同时，全环绕栅极结构可以提高半导体结构的空间利用率，从而进一步半导体结构的集成密度；在沟道区中设置反型掺杂区，可以在沟道区中形成PN结，其中，反型掺杂区向靠近第一掺杂区端延伸，可以拉开栅极与第一掺杂区之间的距离，使第一掺杂区与栅极之间没有重叠区域，从而降低第一掺杂区与栅极之间电场强度，并且，第一掺杂区的有效电流宽度也降低，从而使带带隧穿电流降低，进而降低第一掺杂区与栅极之间栅极诱导漏极泄漏电流。
本发明另一实施例提供一种半导体结构的制作方法，可用于形成上述半导体结构，以改善半导体结构中栅极诱导漏极泄漏电流的问题，提高半导体结构的可靠性。需要说明的是，与上述实施例相同或者相应的部分，可参考前述实施例的相应说明，以下将不做详细赘述。
图4至图9为本公开另一实施例提供的半导结构的制作方法各个步骤对应的结构示意图，具体如下：
参考图4，提供基底(图中未示出)，基底包括有源柱AA，有源柱AA具有第一掺杂类型。
对于基底，基底的材料可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
对于有源柱AA，有源柱AA的材料可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。在本实施例中，有源柱AA的材料与基底的材料相同；在其他实施例中，有源柱AA的材料可以与基底的材料不同。
在一些实施例中，第一掺杂类型可以是P型或者N型，N型掺杂离子包括磷离子、砷离子或者锑离子；P型掺杂离子包括硼离子、铟离子或者氟化硼 离子。
参考图5，形成反型掺杂区200，反型掺杂区200靠近有源柱AA的一端，反型掺杂区200的掺杂类型与有源柱AA中的掺杂类型不同。
对于反型掺杂区200，反型掺杂区200的掺杂类型与有源柱AA的掺杂类型不同，若有源柱AA的掺杂离子类型为N型，则反型掺杂区200的掺杂离子类型为P型；若有源柱AA的掺杂离子类型为P型，则反型掺杂区200的掺杂离子类型为N型。
在一些实施例中，形成反型掺杂区，包括：参考图6，对靠近有源柱AA一端的区域进行掺杂处理，形成初始反型掺杂区210；参考图7，对初始反型掺杂区210的表面进行掺杂处理，以形成具有第一掺杂类型的表面区域220，剩余的初始反型掺杂区210作为反型掺杂区200。
对于初始反型掺杂区210，形成初始反型掺杂区210的掺杂类型与有源柱的掺杂类型不同，若有源柱AA的掺杂离子类型为N型，则初始反型掺杂区210的掺杂离子类型为P型；若有源柱AA的掺杂离子类型为P型，则初始反型掺杂区210的掺杂离子类型为N型。
对初始反型掺杂区210的表面进行掺杂处理，以形成具有第一掺杂类型的表面区域220，即若有源柱AA的掺杂离子类型为P型，则对初始反型掺杂区210的表面进行掺杂处理的掺杂离子类型为P型；若有源柱AA的掺杂离子类型为N型，则对初始反型掺杂区210的表面进行掺杂处理的掺杂离子类型为N型。
进一步地，在一些实施例中，表面区域220的掺杂浓度等于有源柱AA中的掺杂浓度。使反型掺杂区周围的有源柱AA掺杂浓度相同，可以避免形成晶体管结构后由于沟道区中反型掺杂区以外的沟道区中掺杂浓度不同，从而避免半导体结构的使用性能因此受到影响。
在另一些实施例中，形成反型掺杂区，包括：对靠近有源柱一端的内部区域进行离子注入，直接在有源柱内部形成反型掺杂区，以形成图4所示的半导体结构。通过调节离子注入的能量以使掺杂离子直接到达有源柱中相应的深度，以直接在有源柱中形成反型掺杂区，减少半导体结构的制作工艺，提高半导体结构的制作效率。
通过上述两种反型掺杂区的形成方法，可以在有源柱内形成PN结，以 便于后续形成晶体管结构中，使靠近反型掺杂区的一端形成的源极或者漏极，与有源柱中间的栅极之间拉开距离，使晶体管的源极或者漏极与栅极之间没有重叠区域，从而降低源极或者漏极与栅极电场强度，并且，源极或者漏极的有效电流宽度也降低，从而带带隧穿电流降低，进而达到降低源极或者漏极与栅极之间的栅极诱导漏极泄露电流。
参考图8，形成栅极103，栅极103环绕有源柱AA的部分表面，且于有源柱AA的轴线S所在的平面上，栅极103的投影与反型掺杂区200的投影部分重合。
通过形成栅极103环绕部分沟道区100的结构，可以形成全环绕栅极结构的晶体管，增加沟道区的面积以提高晶体管对电流的控制能力，进而提高半导体结构的使用性能，同时，全环绕栅极结构可以提高半导体结构的空间利用率，从而进一步半导体结构的集成密度。
继续参考图8，在一些实施例中，形成栅极103的步骤包括：形成栅介质层123，栅介质层123环绕有源柱AA的部分表面；形成栅导电层113，栅导电层113覆盖栅介质层123的表面。栅介质层123覆盖环绕部分沟道区100的表面设置，栅导电层113覆盖栅介质层123表面，可以防止后续工艺过程中栅导电层113与有源柱AA发生反应，导致半导体结构的损坏。
对于栅介质层123，形成栅介质层123的材料包括氧化硅、氮化硅或者氮氧化硅中的至少一种。
对于栅导电层113，形成栅导电层113的材料包括多晶硅、氮化钛、铝化钛、氮化钽、钽、铜、铝、镧、铜或者钨中的至少一种。
参考图9，对有源柱AA的两个端部进行第一掺杂类型的离子重掺杂，以分别形成第一掺杂区101和第二掺杂区102。第一掺杂区101位于反型掺杂区200远离栅极103的一侧，第一掺杂区101可以作为晶体管的源极或者漏极中的一者，第二掺杂区102可以作为晶体管的源极或者漏极中的另一者，第一掺杂区101和第二掺杂区102之间剩余的有源柱AA作为沟道区100，从而构成无结晶体管的结构，相对于有结型晶体管来说，无结晶体管可以降低沟道区100与源极或者漏极之间陡峭的浓度梯度分布，从而降低热预算。
需要说明的是，在本实施例中，第一掺杂区101位于反型掺杂区200远离栅极103的一侧，即反型掺杂区200靠近有源柱AA中第一掺杂区101的一 端；在其他实施例中，反型掺杂区200可以位于靠近有源柱AA中第二掺杂区102的一端。
在本实施例中，第一掺杂区101作为晶体管的漏极，第二掺杂区102作为晶体管的源极。上述定义的具体“源极”和“漏极”的连接方式，并不构成对本申请实施例的限定，在其他实施例中，可以采用“漏极”替换“源极”，“源极”替换“漏极”的连接方式。
在一些实施例中，沟道区100的掺杂浓度为1E 14cm -3～1E 19cm -3，例如，沟道区100的掺杂浓度可以是1E 14cm -3、1E 15cm -3、1E 18cm -3或者1E 19cm -3；第一掺杂区101和第二掺杂区102的掺杂浓度为1E 19cm -3～1E 22cm -3，例如，第一掺杂区101和第二掺杂区102的掺杂浓度可以是1E 19cm -3、1E 20cm -3、1E 21cm -3或者1E 22cm -3；反型掺杂区200的掺杂浓度为1E 17cm -3～1E 19cm -3，例如，反型掺杂区200的掺杂浓度可以是1E 17cm -3、1E 18cm -3或者1E 19cm -3。通过使第一掺杂区101和第二掺杂区102形成重掺杂，沟道区100形成轻掺杂，可以降低沟道区100与第一掺杂区101和第二掺杂区102之间的陡峭的浓度梯度分布，从而降低热预算；反型掺杂区形成中等程度的掺杂可以在沟道区100中形成PN结，可以使栅极103与第一掺杂区101之间栅极诱导漏极泄漏电流无法从反型掺杂区200通过，从而降低晶体管在关态时栅极诱导漏极泄漏电流，提高半导体结构的可靠性。
本公开实施例提供的半导体结构制作方法，通过沟道区以及位于沟道区两侧的第一掺杂区和第二掺杂区形成的有源柱，可以用于构成无结晶体管的结构，第一掺杂区作为无结晶体管的源极或者漏极中的一者，第二掺杂区作为无结晶体管的源极或者漏极中的另一者，相对于有结型晶体管来说，无结晶体管可以降低沟道区与源极或者漏极之间陡峭的浓度梯度分布，从而降低热预算；栅极环绕部分沟道区设置，可以形成全环绕栅极结构的晶体管，增加沟道区的面积以提高晶体管对电流的控制能力，进而提高半导体结构的使用性能，同时，全环绕栅极结构可以提高半导体结构的空间利用率，从而进一步半导体结构的集成密度；在沟道区中设置反型掺杂区，可以在沟道区中形成PN结，其中，反型掺杂区向靠近第一掺杂区端延伸，可以拉开栅极与第一掺杂区之间的距离，使第一掺杂区与栅极之间没有重叠区域，从而降低第一掺杂区与栅极之间电场强度，并且，第一掺杂区的有效电流宽度也降低，从而使带带隧穿电流降低，进而降低第一掺杂区与栅极之间栅极诱导漏极泄漏电流。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体 实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (15)

  1. 一种半导体结构，包括：
    有源柱，所述有源柱包括：沟道区，以及位于所述沟道区两侧的第一掺杂区和第二掺杂区，其中，所述沟道区、所述第一掺杂区和所述第二掺杂区的掺杂类型相同；
    所述沟道区中设置有反型掺杂区，所述反型掺杂区靠近所述第一掺杂区，其中，所述反型掺杂区中的掺杂类型与所述沟道区中掺杂类型不同；
    栅极，所述栅极环绕部分所述沟道区，且于所述有源柱的轴线所在的平面上，所述栅极的投影与所述反型掺杂区的投影部分重合。
  2. 如权利要求1所述的半导体结构，其中，所述沟道区的掺杂浓度为1E 14cm -3～1E 19cm -3，所述第一掺杂区和所述第二掺杂区的掺杂浓度为1E 19cm -3～1E 22cm -3，所述反型掺杂区的掺杂浓度为1E 17cm -3～1E 19cm -3。
  3. 如权利要求1所述的半导体结构，其中，所述有源柱为圆柱体、椭圆柱体或棱柱体，所述反型掺杂区的截面形状与所述有源柱的截面形状相同。
  4. 如权利要求1所述的半导体结构，其中，所述沟道区的截面宽度大于等于30nm。
  5. 如权利要求4所述的半导体结构，其中，所述沟道区的截面宽度与所述反型掺杂区的截面宽度之差为10nm～20nm。
  6. 如权利要求1～5中任意一项所述的半导体结构，其中，所述沟道区的轴线与所述反型掺杂区的轴线重合。
  7. 如权利要求1～5中任意一项所述的半导体结构，其中，所述沟道区的轴线与所述反型掺杂区的轴线偏移，且两者的轴线偏移距离小于等于5nm。
  8. 如权利要求1所述的半导体结构，其中，所述反型掺杂区包括相连的第一反型区和第二反型区，在所述有源柱的轴线所在的平面上，所述第一反型区的投影位于所述栅极投影内，所述第二反型区的投影与所述栅极的投影相接。
  9. 如权利要求8所述的半导体结构，其中，在所述有源柱的轴线方向上，所述栅极长度为所述沟道区长度的60％-80％，所述第一反型区的长度为所述栅极长度的20％～60％。
  10. 如权利要求9所述的半导体结构，其中，在所述有源柱的轴线方向上，所述第二反型区的长度为所述栅极与所述第一掺杂区之间距离的20％～60％。
  11. 一种半导体结构的制作方法，包括：
    提供基底，所述基底包括有源柱，所述有源柱具有第一掺杂类型；
    形成反型掺杂区，所述反型掺杂区位于所述有源柱内，且靠近所述有源柱的一端，所述反型掺杂区的掺杂类型与所述有源柱中的掺杂类型不同；
    形成栅极，所述栅极环绕所述有源柱的部分表面，且于所述有源柱的轴线所在的平面上，所述栅极的投影与所述反型掺杂区的投影部分重合；
    对所述有源柱的两个端部进行第一掺杂类型的离子重掺杂，以分别形成第一掺杂区和第二掺杂区。
  12. 如权利要求11所述的半导体结构的制作方法，其中，所述第一掺杂区位于所述反型掺杂区远离所述栅极的一侧，所述第一掺杂区与所述第二掺杂区之间剩余的所述有源柱作为沟道区。
  13. 如权利要求12所述的半导体结构的制作方法，其中，形成所述反型掺杂区，包括：对靠近所述有源柱一端的区域进行掺杂处理，形成初始反型掺杂区；对所述初始反型掺杂区的表面进行掺杂处理，以形成具有所述第一掺杂类型的表面区域，剩余的所述初始反型掺杂区作为所述反型掺杂区。
  14. 如权利要求13所述的半导体结构的制作方法，其中，所述表面区域的掺杂浓度等于所述沟道区的掺杂浓度。
  15. 如权利要求11所述的半导体结构的制作方法，其中，形成所述反型掺杂区，包括：对靠近所述有源柱一端的内部区域进行离子注入，直接在所述有源柱内部形成所述反型掺杂区。
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