WO2024018927A1 - リニア電源装置、および電源システム - Google Patents

リニア電源装置、および電源システム Download PDF

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Publication number
WO2024018927A1
WO2024018927A1 PCT/JP2023/025292 JP2023025292W WO2024018927A1 WO 2024018927 A1 WO2024018927 A1 WO 2024018927A1 JP 2023025292 W JP2023025292 W JP 2023025292W WO 2024018927 A1 WO2024018927 A1 WO 2024018927A1
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Prior art keywords
power supply
linear power
voltage information
output
voltage
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English (en)
French (fr)
Japanese (ja)
Inventor
勇武 岩橋
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Rohm Co Ltd
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Rohm Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Definitions

  • the present disclosure relates to a linear power supply device and a power supply system.
  • linear power supplies linear regulators
  • linear regulators linear regulators
  • Some linear power supply devices use two linear power supply devices and commonly connect the output terminals of the respective linear power supply devices to a common load (for example, Patent Document 1). That is, such linear power supplies are connected in parallel to a common load.
  • the purpose of such a linear power supply is to disperse heat by distributing the load current into the output current output from the output terminals, or to increase the load current based on the output current output from each output terminal. The purpose is to do something.
  • an object of the present disclosure is to provide a linear power supply device that can effectively perform parallel operation in parallel connection applications, regardless of variations in the linear power supply devices.
  • the linear power supply device is an output transistor having a first main electrode configured to be connectable to an input voltage application end and a second main electrode; an output terminal connected to the second main electrode; an error amplifier configured to receive a feedback voltage based on the output voltage generated at the output terminal and a reference voltage, and to be able to drive a control end of the output transistor; a mirror transistor configured to be able to generate a mirror current of the current flowing through the output transistor; a current/voltage converter that converts the mirror current into first voltage information; a voltage information output terminal configured to be able to output the first voltage information to the outside; a voltage information input terminal configured to allow input of second voltage information from the outside; a comparison unit configured to compare the second voltage information and the first voltage information;
  • the control transistor is configured to include a control transistor that is driven based on the comparison result of the comparison section and controls so that the difference between the second voltage information and the first voltage information becomes small.
  • linear power supply device in parallel connection applications, it is possible to effectively perform parallel operation regardless of variations in the linear power supply devices.
  • FIG. 1 is a diagram showing the configuration of a power supply system according to a comparative example.
  • FIG. 2 is a diagram showing the configuration of the power supply system according to the first embodiment.
  • FIG. 3 is a diagram showing an OR circuit.
  • FIG. 4 is a diagram showing another configuration example of the power supply system according to the first embodiment.
  • FIG. 5 is a diagram showing an example of a current waveform in the configuration shown in FIG. 4.
  • FIG. 6 is a diagram showing the configuration of a power supply system according to the second embodiment.
  • FIG. 7 is a diagram showing another configuration example of the power supply system according to the second embodiment.
  • FIG. 1 is a diagram showing the configuration of a power supply system 50 according to a comparative example.
  • the power supply system 50 includes a linear power supply device 10A, a linear power supply device 10B, and resistors Ra and Rb.
  • Power supply system 50 supplies load current Iout to load RL using two linear power supplies 10A and 10B.
  • the linear power supplies 10A and 10B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 10A and the linear power supply device 10B are ICs (Integrated Circuits) with the same configuration, and corresponding components are designated with “A” or "B” for the same reference numerals. It is illustrated. Below, the configuration of the linear power supply device 10A will be representatively explained.
  • the linear power supply device 10A is an IC that includes an output transistor M10A, resistors R11A and 12A, and an error amplifier AP10A, and integrates these into one chip.
  • the source of the output transistor M10A configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) is connected to the input terminal of the input voltage Vin.
  • the drain of the output transistor M10A and the first end of the resistor R11A are commonly connected to an output terminal ToA for outputting the output voltage VoA.
  • a second end of resistor R11A is connected to a first end of resistor R12A.
  • a second end of the resistor R12A is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP10A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP10A is connected to the gate of the output transistor M
  • the on-resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB matches its target value.
  • the output terminal ToA is connected to the first end of a resistor Ra provided outside the linear power supply devices 10A and 10B.
  • the output terminal ToB is connected to a first end of a resistor Rb provided outside the linear power supply devices 10A and 10B.
  • the second ends of each of the resistors Ra and Rb are commonly connected to the load RL. Therefore, linear power supplies 10A and 10B are connected in parallel to a common load RL.
  • the standard values (Typ values) of the output voltages VoA and VoB of the linear power supplies 10A and 10B are set to be the same, but due to variations in the linear power supplies, the output voltage may vary from the standard value. be. For example, it varies by ⁇ 2% with respect to the standard value of 5V. Such variations are caused by, for example, variations in the reference voltage, feedback voltage, or threshold voltage of the output transistor, as well as variations in the input offset voltage of the error amplifier.
  • the output transistor M10B on the linear power supply 10B side is kept off, and the output is output from the output terminal ToB.
  • the current IoutB is not output, and the load current Iout is supplied only by the output current IoutA output from the output terminal ToA of the linear power supply device 10A. Therefore, the output current is concentrated on one linear power supply device.
  • the output voltage VoA when the output voltage VoA is higher than VoB, as the load current Iout gradually increases from 0 A, the output voltage VoA is dropped by the resistor Ra.
  • the output voltage Vo generated at the node to which the second ends of the resistors Ra and Rb are connected gradually decreases.
  • the output transistor M10B on the linear power supply device 10B side starts operating, and the output of the output current IoutB is started from the output terminal ToB. That is, a parallel operation is started in which the load current Iout is supplied by both the output currents IoutA and IoutB.
  • the resistors Ra and Rb may be set to such resistance values that the voltage drop across the resistors is greater than or equal to the voltage difference between the maximum and minimum values due to variations in the output voltage.
  • this comparative example has problems in that loss and heat generation occur due to the resistors Ra and Rb, and that the output currents IoutA and IoutB are not equal. Further, when the load current Iout changes, the output voltage Vo changes due to the voltage drop caused by the resistors Ra and Rb, causing a problem in the function as a regulator.
  • FIG. 2 is a diagram showing the configuration of the power supply system 5 according to the first embodiment.
  • the power supply system 5 includes a linear power supply device 1A and a linear power supply device 1B.
  • the power supply system 5 supplies a load current Iout to the load RL using two linear power supplies 1A and 1B.
  • the linear power supplies 1A and 1B are linear regulators that step down the input voltage Vin to generate desired output voltages VoA and VoB, respectively.
  • the linear power supply device 1A and the linear power supply device 1B are ICs with the same configuration, and corresponding components are shown with "A” or "B" attached to the same reference numerals. There is. Below, the configuration of the linear power supply device 1A will be representatively explained.
  • the linear power supply device 1A includes an output transistor M1A, a mirror transistor M2A, an error amplifier AP1A, feedback resistors R1A, R2A, R3A, R4A, a bypass switch BPA, a sense resistor RsA, and a comparator.
  • This IC includes a CPA, an NMOS transistor (N-channel MOSFET) NMA, a resistor RA, NMOS switches NS1A, NS2A, and a PMOS switch PMA, and these are integrated into one chip.
  • the linear power supply device 1A has external terminals such as an output terminal ToA and a voltage information transmission/reception terminal TvA in order to establish electrical connection with the outside.
  • the source of the output transistor M1A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of output transistor M1A is connected to the first end of feedback resistor R1A.
  • the drain of the output transistor M1A is connected to an output terminal ToA for outputting an output voltage VoA.
  • a second end of feedback resistor R1A is connected to a first end of feedback resistor R2A.
  • a second end of feedback resistor R2A is connected to a first end of feedback resistor R3A.
  • a second end of feedback resistor R3A is connected to a first end of feedback resistor R4A.
  • a second end of the feedback resistor R4A is connected to a ground terminal.
  • the inverting input terminal (-) of the error amplifier AP1A is connected to the application terminal of the reference voltage VrefA.
  • the output terminal of the error amplifier AP1A is connected to the gate of the output transistor M1A.
  • bypass switch BPA constituted by an NMOS transistor
  • the source of bypass switch BPA is connected to the second end of feedback resistor R4A.
  • a gate of bypass switch BPA is connected to an application terminal of control signal ScA. Thereby, the on state/off state of the bypass switch BPA is switched according to the control signal ScA.
  • the bypass switch BPA is in the on state, both ends of the feedback resistor R4A are short-circuited, and the feedback resistor R4A is bypassed.
  • the bypass switch BPA is in the off state, the feedback resistor R4A is enabled.
  • the source of the mirror transistor M2A configured as a PMOS transistor is connected to the application terminal of the input voltage Vin.
  • the drain of mirror transistor M2A is connected to the first end of sense resistor RsA.
  • the gate of mirror transistor M2A is connected to the output terminal of error amplifier AP1A.
  • a second end of the sense resistor RsA is connected to a ground terminal.
  • a first end of the sense resistor RsA is connected to the drain of an NMOS switch NS1A configured as an NMOS transistor.
  • the source of the NMOS switch NS1A is connected to the voltage information transmission/reception terminal TvA.
  • the gate of the NMOS switch NS1A is connected to the application terminal of the control signal ScA. The on/off state of the NMOS switch NS1A is switched by the control signal ScA.
  • a mirror current Im2A of the current flowing through the output transistor M1A flows through the mirror transistor M2A.
  • the mirror current Im2A is, for example, several hundredths or several thousandths of the current flowing through the output transistor M1A.
  • voltage information Vmon obtained by converting the mirror current Im2A into a current/voltage by the sense resistor RsA can be outputted to the outside from the voltage transmitting/receiving terminal TvA via the NMOS switch NS1A.
  • the comparator CPA includes PMOS transistors P1 and P2 and NMOS transistors N1 and N2.
  • the sources of PMOS transistors P1 and P2 are connected to the drain of PMOS switch PMA.
  • the gate of PMOS transistor P1 is connected to voltage information transmission/reception terminal TvA.
  • the gate of PMOS transistor P2 is connected to the first end of sense resistor RsA.
  • the drain of PMOS transistor P1 is connected to the drain of NMOS transistor N1.
  • the drain and gate of NMOS transistor N1 are shorted.
  • the gates of NMOS transistors N1 and N2 are connected to each other.
  • the sources of NMOS transistors N1 and N2 are connected to a ground terminal.
  • the drain of the NMOS transistor N2 and the drain of the PMOS transistor P2 are connected at a node Nd. Note that a phase compensation capacitor C1 is connected between the gate and drain of the NMOS transistor N2.
  • NMOS transistor NMA The gate of NMOS transistor NMA is connected to node Nd.
  • the source of the NMOS transistor NMA is connected to a ground terminal via a resistor RA.
  • the drain of the NMOS transistor NMA is connected to a node NDA to which feedback resistors R1A and R2A are connected. Note that a phase compensation capacitor C2 is connected between the gate and drain of the NMOS transistor NMA.
  • the drain of the NMOS switch NS2A is connected to the gate of the NMOS transistor NMA.
  • the source of NMOS switch NS2A is connected to the ground terminal.
  • the gate of the PMOS switch PMA and the gate of the NMOS switch NS2A are connected to the application terminal of the control signal ScA.
  • the control signal ScA switches the on state/off state of the PMOS switch PMA and the NMOS switch NS2A.
  • the NMOS switch NS1A When the control signal ScA is at a low level, the NMOS switch NS1A is in the off state, the PMOS switch PMA is in the on state, and the NMOS switch NS2A is in the off state.
  • voltage information Vmon input from the outside to the voltage information transmitting/receiving terminal TvA is applied to the gate of the PMOS transistor P1
  • voltage information Vs obtained by converting the mirror current Im2A into a voltage by the sense resistor RsA is applied to the gate of the PMOS transistor P2. Applied to the gate.
  • the voltage information Vs and Vmon are compared by the comparator CPA, and the gate of the NMOS transistor NMA is driven based on the comparison result. Since the drain of the NMOS transistor NMA is connected to the node NDA, the output voltage VoA is controlled so that the voltage information Vs and Vmon match.
  • FIG. 3 is a diagram showing an OR circuit Or provided in the linear power supply device 1A.
  • the protection signals P1 to Pn, the enable signal En, and the master/slave selection signal MS are input to the OR circuit Or.
  • a control signal ScA is output from the OR circuit Or.
  • the control signal ScA is at a high level. Note that the configuration is not limited to the OR circuit, but may be configured using other logic circuits such as a NAND circuit.
  • the output terminal ToA of the linear power supply device 1A and the output terminal ToB of the linear power supply device 1B are commonly connected to the load RL. That is, two linear power supplies are connected in parallel to the load RL. Further, the voltage information transmitting/receiving terminal TvA of the linear power supply device 1A and the voltage information transmitting/receiving terminal TvB of the linear power supply device 1B are connected.
  • One of the linear power supply devices 1A and 1B is set as a master, and the other is set as a slave.
  • the linear power supply device 1A is set as the master and the linear power supply device 1B is set as the slave.
  • the linear power supply device 1A is set as the master (FIG. 2).
  • the control signal ScA becomes high level
  • the NMOS switch NS1A is turned on
  • the PMOS switch PMA is turned off
  • the NMOS switch NS2A is turned on.
  • the voltage information Vmon to be output from the voltage information transmission/reception terminal TvA.
  • no current is supplied to the comparator CPA, making the comparator CPA ineffective, and the gate of the NMOS transistor NMA becomes a low level.
  • the bypass switch BPA is turned on, and the feedback resistor R4A is bypassed.
  • the linear power supply device 1B is set as a slave (FIG. 2).
  • the control signal ScB becomes a low level
  • the NMOS switch NS1B is turned off
  • the PMOS switch PMB is turned on
  • the NMOS switch NS2B is turned off.
  • a current is supplied to the comparator CPB, and the comparator CPB becomes valid, making it possible to compare the voltage information Vs and Vmon.
  • NMOS transistor NMB becomes valid.
  • the bypass switch BPB is turned off, and the feedback resistor R4B is enabled.
  • the feedback resistors R4A and R4B may be set to a resistance value that is greater than or equal to the voltage difference between the maximum value and the minimum value due to variations in the output voltage. Thereby, even if there are variations in the output voltages VoA and VoB, the output voltage VoB can be set lower than VoA.
  • the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply device 1B. That is, parallel operation of the linear power supplies 1A and 1B is started.
  • the mirror current Im2B also starts flowing, and by driving the NMOS transistor NMB by comparing the voltage information Vs and Vmon, the voltage information Vs and Vmon match, that is, the output currents IoutB and IoutA match. controlled as follows.
  • linear power supply devices may be connected in parallel to the load RL.
  • Output terminals ToA, ToB, and ToC of linear power supplies 1A, 1B, and 1C shown in FIG. 4 are commonly connected to a load RL.
  • voltage information transmitting/receiving terminals TvA, TvB, and TvC of the linear power supplies 1A, 1B, and 1C are connected.
  • the linear power supply device 1A is set as a master, and the linear power supply devices 1B and 1C are set as slaves.
  • the output currents IoutA, IoutB, and IoutC of the linear power supplies 1A, 1B, and 1C are controlled to match (that is, the output currents IoutA, IoutB, and IoutC are each controlled to 1 ⁇ 3 of the load current Iout).
  • FIG. 5 shows a schematic current waveform at startup in the configuration shown in FIG. 4. As shown in FIG. 5, first, the output current IoutA of the master linear power supply device 1A rises, and then the output currents IoutB and IoutC rise. Then, the output currents IoutA, IoutB, and IoutC are controlled to match.
  • three or more linear power supply devices may be provided as slaves. That is, it is possible to provide two or more linear power supply devices that are set as slaves for a linear power supply device that is set as a master. Since the voltage information Vmon output from the master linear power supply is a voltage signal rather than a current signal, the signal is not divided by two or more slave linear power supply devices, and the output current of each linear power supply can be made equal.
  • FIG. 6 is a diagram showing the configuration of a power supply system 5 according to the second embodiment.
  • FIG. 6 shows the configuration of a power supply system 5 according to the second embodiment.
  • FIG. 2 shows the configuration of this embodiment and the first embodiment (FIG. 2).
  • the configuration of the linear power supply device 1A among the linear power supply devices 1A and 1B will be representatively explained.
  • the NMOS switch NS1A is not provided, and the first end of the sense resistor RsA is connected to the voltage source terminal TsrA, which is an external terminal.
  • the voltage source terminal TsrA is a terminal for outputting to the outside voltage information VmonA obtained by converting the mirror current Im2A into a current voltage using the sense resistor RsA.
  • the gate of the PMOS transistor P1 is connected to the voltage sink terminal TskA.
  • the voltage sink terminal TskA is a terminal for inputting voltage information Vmon from the outside.
  • Voltage source terminal TsrA and voltage sink terminal TskA are separate terminals.
  • the feedback resistor R4A and the bypass switch BPA are not provided.
  • the voltage source terminal TsrA of the linear power supply device 1A is connected to the voltage sink terminal TskB of the linear power supply device 1B. Thereby, the voltage information VmonA output from the voltage source terminal TsrA is input to the voltage sink terminal TskB.
  • a comparator CPB compares voltage information VsB obtained by converting the mirror current Im2B into a current voltage using a sense resistor RsB and VmonA.
  • the voltage source terminal TsrB of the linear power supply device 1B is connected to the voltage sink terminal TskA of the linear power supply device 1A. Thereby, the voltage information VmonB output from the voltage source terminal TsrB is input to the voltage sink terminal TskA.
  • a comparator CPA compares voltage information VsA obtained by converting a mirror current Im2A into a current voltage using a sense resistor RsA and VmonB.
  • the output voltage VoA of the linear power supply device 1A is higher than the output voltage VoB of the linear power supply device 1B due to variations in the linear power supply device.
  • the output current IoutB is not initially output from the output terminal ToB of the linear power supply 1B, and the load is caused only by the output current IoutA output from the output terminal ToA of the linear power supply 1A.
  • a current Iout is supplied.
  • mirror current Im2A flows, and voltage information VmonA based on mirror current Im2A is output from voltage source terminal TsrA and input to voltage sink terminal TskB.
  • mirror current Im2B does not flow, voltage information VsB and VmonA are compared by comparator CPB, NMOS transistor NMB is driven, and output voltage VoB of linear power supply device 1B is increased.
  • the output voltage VoB increases. Then, when the output voltage VoB reaches VoA, the output current IoutB starts to be output from the output terminal ToB in the linear power supply device 1B. That is, parallel operation of the linear power supplies 1A and 1B is started.
  • the mirror current Im2B also starts to flow, and the NMOS transistor NMB is driven by comparing the voltage information VsB and VmonA, and is controlled so that the voltage information VsB and VmonA match.
  • the NMOS transistor NMA is driven by comparing the voltage information VsA and VmonB, and is controlled so that the voltage information VsA and VmonB match. Thereby, the output currents IoutA and IoutB are controlled to match.
  • FIG. 7 is a diagram showing a case where three linear power supply devices according to the second embodiment are connected in parallel to a load RL to configure a power supply system 5.
  • the voltage source terminal TsrA of the linear power supply 1A is connected to the voltage sink terminal TskB of the linear power supply 1B
  • the voltage source terminal TsrB of the linear power supply 1B is connected to the voltage sink terminal TskC of the linear power supply 1C
  • the linear A voltage source terminal TsrC of the power supply device 1C is connected to a voltage sink terminal TskA of the linear power supply device 1A.
  • the output currents IoutA, IoutB, and IoutC of the linear power supply devices 1A, 1B, and 1C can be equally controlled. Note that even if four or more linear power supply devices 1 are connected in parallel to the load RL, each output current can be controlled equally.
  • the linear power supply device (1A) having a first main electrode configured to be connectable to an application end of the input voltage (Vin) and a second main electrode; an output terminal (ToA) connected to the second main electrode; an error amplifier (AP1A) configured to receive a feedback voltage (VfbA) based on the output voltage (VoA) generated at the output terminal and a reference voltage (VrefA) and to be able to drive a control end of the output transistor; a mirror transistor (M2A) configured to be able to generate a mirror current (Im2A) of the current flowing through the output transistor; a current/voltage converter (RsA) that converts the mirror current into first voltage information (Vmon, Vs); a voltage information output terminal (TvA) configured to be able to output the first voltage information (Vmon) to the outside; a voltage information input terminal (TvA) configured to be able to input
  • the first main electrode of the control transistor (NMA) is connected to the feedback resistor section (R1A, R2A, R3A, R4A) connected to the second main electrode of the output transistor (M1A).
  • a configuration in which they are connected may also be used (second configuration).
  • the voltage information output terminal and the voltage information input terminal are the same terminal (TvA), further comprising a first switch (NS1A) for switching whether or not to output the first voltage information from the voltage information output terminal;
  • a first switch for switching whether or not to output the first voltage information from the voltage information output terminal;
  • a second switch switches whether or not to bypass a part of the feedback resistor (R4A) of the feedback resistor section connected to the second main electrode of the output transistor (M1A).
  • the second switch may be configured to operate in conjunction with the first switch (fourth configuration).
  • the third switch (PMA) is further provided for switching whether or not to supply current to the comparing section (CPA), and the third switch is interlocked with the first switch. (fifth configuration).
  • any one of the third to fifth configurations further comprising a fourth switch (NS2A) connected between the control terminal and the ground terminal of the control transistor (NMA),
  • the fourth switch may be configured to work in conjunction with the first switch (sixth configuration).
  • the voltage information output terminal (TsrA) and the voltage information input terminal (TskA) may be separate terminals (seventh configuration).
  • a power supply system (5) includes a master linear power supply device (1A) that is a linear power supply device having the third configuration, in which the first switch (NS1A) is set to an on state; one or more slave linear power supply devices (1B), which are linear power supply devices of the third configuration, in which the first switch is set to an off state;
  • the output terminal (ToA) of the master linear power supply device and the output terminal (ToB) of the slave linear power supply device can be commonly connected to a load,
  • the voltage information output terminal (TvA) of the master linear power supply device and the voltage information input terminal (TvB) of the slave linear power supply device are connectable (eighth configuration).
  • the number of slave linear power supply devices may be two or more (ninth configuration).
  • a power supply system (5) includes a plurality of linear power supply devices according to the seventh configuration,
  • the respective output terminals (ToA, ToB) in the plurality of linear power supply devices (1A, 1B) can be commonly connected to a load,
  • the voltage information output terminals (TsrA, TsrB) and the voltage information input terminals (TskB, TskA) are sequentially connected between different linear power supply devices. (10th configuration).
  • the present disclosure can be used in power supply systems installed in various devices.

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  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
PCT/JP2023/025292 2022-07-21 2023-07-07 リニア電源装置、および電源システム Ceased WO2024018927A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02171811A (ja) * 1988-10-31 1990-07-03 Nixdorf Comput Ag 電力分配式電源系
JPH1020947A (ja) * 1996-06-28 1998-01-23 Sony Corp リダンダント型安定化電源装置
JP2021061655A (ja) * 2019-10-03 2021-04-15 株式会社豊田自動織機 電源装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02171811A (ja) * 1988-10-31 1990-07-03 Nixdorf Comput Ag 電力分配式電源系
JPH1020947A (ja) * 1996-06-28 1998-01-23 Sony Corp リダンダント型安定化電源装置
JP2021061655A (ja) * 2019-10-03 2021-04-15 株式会社豊田自動織機 電源装置

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