WO2024018798A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024018798A1
WO2024018798A1 PCT/JP2023/022613 JP2023022613W WO2024018798A1 WO 2024018798 A1 WO2024018798 A1 WO 2024018798A1 JP 2023022613 W JP2023022613 W JP 2023022613W WO 2024018798 A1 WO2024018798 A1 WO 2024018798A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor device
insulating layer
exposed
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/022613
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English (en)
French (fr)
Japanese (ja)
Inventor
寛之 新開
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Rohm Co Ltd
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Rohm Co Ltd
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Publication date
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Priority to JP2024534973A priority Critical patent/JPWO2024018798A1/ja
Publication of WO2024018798A1 publication Critical patent/WO2024018798A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor device including a horizontally structured semiconductor element (HEMT).
  • the semiconductor element has a first electrode and a second electrode.
  • a semiconductor element is bonded to a die pad.
  • the first electrode and the second electrode are electrically connected to a plurality of terminal leads located around the die pad via wires.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones.
  • an object of the present disclosure is to provide a semiconductor device that can reduce noise while reducing the size of the device.
  • a semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element having a wiring layer and a plurality of electrodes facing the wiring layer, and the plurality of electrodes being conductively bonded to the wiring layer; an insulating layer that covers a wiring layer; a sealing resin that is located on the opposite side of the wiring layer with respect to the insulating layer in a first direction and surrounds at least the semiconductor element when viewed in the first direction; A metal film that covers the semiconductor element and includes a portion located between the insulating layer and the sealing resin. A portion of the insulating layer is located between the wiring layer and the semiconductor element.
  • the sealing resin has a first side surface facing in a direction perpendicular to the first direction. The insulating layer is exposed to the outside from the first side surface.
  • FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure, through which a sealing resin is seen.
  • FIG. 2 is a plan view corresponding to FIG. 1, further showing the semiconductor element, the insulating layer, and the metal film.
  • FIG. 3 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2.
  • FIG. 5 is a sectional view taken along line VV in FIG. 2.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a partially enlarged view of FIG. 4.
  • FIG. 8 is a partially enlarged view of FIG. 5.
  • FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 10 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 11 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 12 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 13 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 14 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 15 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 16 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG. 1.
  • FIG. 10 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 11 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 12 is a cross-sectional view illustrating the manufacturing process of the semiconductor
  • FIG. 17 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 18 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG. 1.
  • FIG. 19 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG. 1.
  • FIG. 20 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 21 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG.
  • FIG. 22 is a cross-sectional view illustrating the manufacturing process of the semiconductor device shown in FIG. 1.
  • FIG. 23 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present disclosure.
  • FIG. 24 is a plan view of a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 24.
  • FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24.
  • FIG. 27 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, through which the sealing resin is seen.
  • FIG. 28 is a plan view corresponding to FIG. 27, in which the semiconductor element, the insulating layer, and the metal film are further penetrated.
  • FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28.
  • FIG. 30 is a cross-sectional view taken along the line XXX-XXX in FIG. 28.
  • FIG. 31 is a cross-sectional view taken along line XXXI-XXI in FIG. 28.
  • the semiconductor device A10 includes a base material 10, a plurality of wiring layers 21, a plurality of terminals 22, a heat dissipation layer 23, a plurality of dummy terminals 24, a semiconductor element 30, a plurality of bonding layers 39, an insulating layer 41, a metal film 42, and a sealing layer. It includes a resin 50 and a plurality of coating layers 60.
  • the semiconductor device A10 is in the form of a resin package that is surface mounted on a wiring board.
  • the resin package format is a QFN (quad flat non-leaded package) in which a plurality of leads do not protrude from the sealing resin 50.
  • FIG. 1 for convenience of understanding, the sealing resin 50 is shown.
  • FIG. 2 further shows the semiconductor element 30, the insulating layer 41, and the metal film 42 compared to FIG.
  • the transparent sealing resin 50 is shown by an imaginary line (two-dot chain line).
  • the semiconductor element 30 and the sealing resin 50 that are transmitted through the light are shown by imaginary lines.
  • the IV-IV line and the VV line are each shown by a dashed-dotted line.
  • the semiconductor device A10 for convenience, the normal direction of the main surface 11 of the base material 10, which will be described later, will be referred to as a "first direction z.”
  • One direction perpendicular to the first direction z is called a "second direction x.”
  • a direction perpendicular to the first direction z and the second direction x is referred to as a "third direction y.”
  • the semiconductor device A10 has a rectangular shape when viewed in the first direction z (in plan view).
  • the base material 10 supports a plurality of wiring layers 21, as shown in FIGS. 4 to 6.
  • the base material 10 has electrical insulation properties.
  • the base material 10 is made of a material containing black epoxy resin.
  • the base material 10 has a main surface 11, a back surface 12, and a plurality of second side surfaces 13.
  • the main surface 11 and the back surface 12 face opposite to each other in the first direction z.
  • the main surface 11 faces the plurality of wiring layers 21 .
  • the back surface 12 is exposed to the outside.
  • the plurality of second side surfaces 13 face in a direction perpendicular to the first direction z.
  • the plurality of second side surfaces 13 are connected to the main surface 11 and the back surface 12.
  • the plurality of second side surfaces 13 include two second side surfaces 13 facing in the second direction x and two second side surfaces 13 facing in the third direction y.
  • the plurality of wiring layers 21 are supported on the main surface 11 of the base material 10, as shown in FIGS. 4 to 6.
  • the plurality of wiring layers 21, together with the plurality of terminals 22, constitute a conductive path between the semiconductor element 30 and the wiring board on which the semiconductor device A10 is mounted.
  • the composition of the plurality of wiring layers 21 includes titanium (Ti) and copper (Cu).
  • each of the plurality of wiring layers 21 has an end surface 211.
  • the end surface 211 faces in a direction perpendicular to the first direction z. End surface 211 is exposed from insulating layer 41.
  • the plurality of wiring layers 21 include ground wiring 21A.
  • the ground wiring 21A functions as a ground (GND) for the semiconductor device A10.
  • the ground wiring 21A has an exposed surface 212 facing the same side as the main surface 11 of the base material 10 in the first direction z. Exposed surface 212 is exposed from insulating layer 41 .
  • the plurality of terminals 22 are housed in the base material 10, as shown in FIGS. 4 to 6. Each of the plurality of terminals 22 is connected to one of the plurality of wiring layers 21.
  • the composition of the plurality of terminals 22 includes copper.
  • each of the plurality of terminals 22 has a first exposed surface 221 and a second exposed surface 222.
  • the first exposed surface 221 faces the same side as the back surface 12 of the base material 10 in the first direction z.
  • the first exposed surface 221 is exposed from the back surface 12.
  • the second exposed surface 222 faces in a direction perpendicular to the first direction z.
  • the second exposed surface 222 is exposed from any one of the plurality of second side surfaces 13 of the base material 10.
  • the second exposed surface 222 is flush with any end surface 211 of the plurality of wiring layers 21 .
  • the heat dissipation layer 23 overlaps the semiconductor element 30 when viewed in the first direction z. As shown in FIGS. 4 and 5, the heat dissipation layer 23 is accommodated in the base material 10. The heat dissipation layer 23 is connected to any one of the plurality of wiring layers 21. The composition of the heat dissipation layer 23 is the same as that of the plurality of terminals 22.
  • the heat dissipation layer 23 has a third exposed surface 231.
  • the third exposed surface 231 faces the same side as the back surface 12 of the base material 10 in the first direction z.
  • the third exposed surface 231 is exposed from the back surface 12.
  • the plurality of dummy terminals 24 are located at the four corners of the base material 10 when viewed in the first direction z. As shown in FIG. 6, the plurality of dummy terminals 24 are housed in the base material 10. The plurality of dummy terminals 24 are located apart from the plurality of wiring layers 21, the plurality of terminals 22, and the plurality of heat dissipation layers 23. The composition of the plurality of dummy terminals 24 is the same as the composition of the plurality of terminals 22.
  • each of the plurality of dummy terminals 24 has a fourth exposed surface 241 and a fifth exposed surface 242.
  • the fourth exposed surface 241 faces the same side as the back surface 12 of the base material 10 in the first direction z.
  • the fourth exposed surface 241 is exposed from the back surface 12.
  • the fifth exposed surface 242 faces in a direction perpendicular to the first direction z.
  • the fifth exposed surface 242 is exposed from any one of the plurality of second side surfaces 13 of the base material 10.
  • each of the plurality of bonding layers 39 is disposed on one of the plurality of wiring layers 21 and is connected to one of the plurality of wiring layers 21.
  • the plurality of bonding layers 39 are conductors.
  • each of the plurality of bonding layers 39 has a seat portion 391 and a bonding portion 392.
  • the seat portion 391 is connected to any one of the plurality of wiring layers 21.
  • the composition of the seat portion 391 includes nickel (Ni).
  • Joint portion 392 is located above seat portion 391 .
  • the composition of the joint portion 392 includes tin (Sn) and silver (Ag).
  • the composition of the joint portion 392 may include tin and antimony (Sb).
  • the semiconductor element 30 is conductively bonded to the plurality of wiring layers 21 via the plurality of bonding layers 39.
  • the semiconductor element 30 has a peripheral surface 301, a main body 31, a plurality of electrodes 32, and a passivation film 33.
  • the peripheral surface 301 faces in a direction perpendicular to the first direction z.
  • the main body portion 31 and the passivation film 33 include a peripheral surface 301 .
  • the main body portion 31 is located on the opposite side of the plurality of wiring layers 21 with respect to the plurality of electrodes 32 in the first direction z.
  • the main body portion 31 includes a semiconductor substrate, a semiconductor layer stacked on the semiconductor substrate, and a rewiring layer electrically connected to the semiconductor layer. Various circuits are configured in the semiconductor layer.
  • the main body portion 31 has an upper surface 311. The upper surface 311 faces the same side as the main surface 11 of the base material 10 in the first direction z.
  • each of the plurality of electrodes 32 face the plurality of wiring layers 21.
  • each of the plurality of electrodes 32 has a base portion 321 and a columnar portion 322.
  • the base portion 321 is connected to the main body portion 31.
  • the columnar portion 322 protrudes from the base portion 321 toward the plurality of wiring layers 21 .
  • the composition of the columnar portion 322 includes copper.
  • the columnar portions 322 of each of the plurality of electrodes 32 are individually conductively bonded to the bonding portions 392 of the plurality of bonding layers 39 . Thereby, the plurality of electrodes 32 are electrically connected to the plurality of wiring layers 21.
  • the passivation film 33 covers the surface of the main body portion 31 facing opposite to the upper surface 311 in the first direction z.
  • the passivation film 33 has electrical insulation properties.
  • a plurality of openings 331 are provided in the passivation film 33.
  • the base portion 321 of each of the plurality of electrodes 32 is individually accommodated in the plurality of openings 331.
  • the passivation film 33 is made of a material containing polyimide.
  • the insulating layer 41 covers the plurality of wiring layers 21, as shown in FIG. 1 and FIGS. 4 to 6.
  • the insulating layer 41 is made of a material containing black and soft resin.
  • An example of the material for the insulating layer 41 is a resin material used for underfill.
  • a portion of the insulating layer 41 is located between the plurality of wiring layers 21 and the semiconductor element 30 in the first direction z.
  • the insulating layer 41 is in contact with the main surface 11 of the base material 10.
  • the insulating layer 41 is in contact with the columnar portions 322 of each of the plurality of electrodes 32 of the semiconductor element 30 and the peripheral surface 301 of the semiconductor element 30 .
  • the insulating layer 41 is further in contact with the upper surface 311 of the main body 31 of the semiconductor element 30.
  • FIG. 8 the insulating layer 41 is further in contact with the upper surface 311 of the main body 31 of the semiconductor element 30.
  • the metal film 42 covers the semiconductor element 30, as shown in FIGS. 1, 4, and 5.
  • the metal film 42 includes a portion located between the insulating layer 41 and the sealing resin 50. As shown in FIG. 8, the metal film 42 is separated from the semiconductor element 30 with an insulating layer 41 in between.
  • the metal film 42 is in contact with the exposed surface 212 of the ground wiring 21A among the plurality of wiring layers 21. Thereby, the metal film 42 is electrically connected to the ground wiring 21A. Therefore, the potential of the metal film 42 is equivalent to the potential of the ground wiring 21A.
  • the metal film 42 has a first film 421 and a second film 422.
  • the first film 421 is in contact with the insulating layer 41.
  • the semiconductor device A10 the first film 421 is in contact with the semiconductor element 30.
  • the composition of the first film 421 includes titanium.
  • the second film 422 is stacked on the first film 421.
  • the composition of the second film 422 includes copper.
  • the sealing resin 50 is located on the opposite side of the plurality of wiring layers 21 with respect to the insulating layer 41 in the first direction z. As shown in FIGS. 1, 4, and 5, the sealing resin 50 surrounds at least the semiconductor element 30 when viewed in the first direction z. In the semiconductor device A10, the sealing resin 50 overlaps the semiconductor element 30 when viewed in the first direction z.
  • the base material 10 is made of a material containing black epoxy resin.
  • the sealing resin 50 has a top surface 51 and a plurality of first side surfaces 52.
  • the top surface 51 faces the same side as the main surface 11 of the base material 10 in the first direction z.
  • the plurality of first side surfaces 52 are connected to the top surface 51.
  • Each of the plurality of first side surfaces 52 includes a first region 521 and a second region 522.
  • the first region 521 is connected to the top surface 51 and faces in a direction perpendicular to the first direction z.
  • the second region 522 is located on the opposite side of the top surface 51 with respect to the first region 521 in the first direction z, and is connected to the first region 521.
  • the first region 521 overlaps the top surface 51 when viewed in the first direction z.
  • the maximum dimension of the insulating layer 41 in the first direction z is smaller than the maximum dimension of the sealing resin 50 in the first direction z.
  • the insulating layer 41 and the first film 421 of the metal film 42 are exposed to the outside from the second region 522 of the plurality of first side surfaces 52.
  • a cavity 53 is provided between the first film 421 and the sealing resin 50 in the first direction z. The cavity 53 communicates with the outside.
  • the thermal conductivity of the insulating layer 41 is lower than that of the sealing resin 50. Furthermore, the insulating layer 41 contains a first filler. The sealing resin 50 contains a second filler. The weight percentage (wt%) of the first filler in the insulating layer 41 is lower than the weight percentage of the second filler in the sealing resin 50.
  • the plurality of covering layers 60 are exposed to the outside, as shown in FIGS. 2 and 3. As shown in FIGS. 3 to 5, some of the plurality of covering layers 60 cover the first exposed surface 221 and second exposed surface 222 of each of the plurality of terminals 22 and each of the plurality of wiring layers 21.
  • the end face 211 is individually covered. Any one of the plurality of coating layers 60 individually covers the third exposed surface 231 of the heat dissipation layer 23. Further, four of the plurality of covering layers 60 individually cover the fourth exposed surface 241 and the fifth exposed surface 242 of each of the plurality of dummy terminals 24.
  • the plurality of covering layers 60 are electrical conductors.
  • the semiconductor device A10 is mounted on the wiring board by conductively bonding the plurality of covering layers 60 to the wiring board via solder.
  • Each of the plurality of covering layers 60 includes a plurality of metal layers.
  • the plurality of metal layers are stacked in the order of a nickel layer and a gold (Au) layer from the one closest to one of the plurality of terminals 22.
  • the plurality of metal layers may be one in which a nickel layer, a palladium (Pd) layer, and a gold layer are stacked in this order from the one closest to one of the plurality of terminals 22. Therefore, the composition of the plurality of coating layers 60 includes gold.
  • FIGS. 9 to 22 The cross-sectional positions in FIGS. 9 to 22 are the same as the cross-sectional positions in FIG. 4.
  • an intermediate layer 82 is formed to cover one side of the support member 81 in the first direction z.
  • the intermediate layer 82 includes a metal thin film made of titanium and in contact with the support member 81, and a metal thin film made of copper and laminated on the metal thin film.
  • the intermediate layer 82 is formed by depositing each of these metal thin films by sputtering.
  • a plurality of conductive layers 83 protruding from the intermediate layer 82 in the first direction z are formed. A portion of each of the plurality of conductive layers 83 becomes one of the plurality of terminals 22 and the heat dissipation layer 23 included in the semiconductor device A10.
  • lithography patterning is performed on the intermediate layer 82.
  • a plurality of conductive layers 83 are deposited by electroplating using the intermediate layer 82 as a conductive path.
  • the mask layer for lithographic patterning is removed. Through the above steps, a plurality of conductive layers 83 are formed.
  • a first resin layer 84 covering the plurality of conductive layers 83 is formed.
  • a portion of the first resin layer 84 becomes the base material 10 included in the semiconductor device A10.
  • the first resin layer 84 is made of a material containing black epoxy resin.
  • the first resin layer 84 is formed by compression molding. At this time, the first resin layer 84 is formed so as to be in contact with the intermediate layer 82 and to cover the entire plurality of conductive layers 83 .
  • a portion of each of the plurality of conductive layers 83 and a portion of the first resin layer 84 are removed by grinding. These portions to be removed are portions located on the side opposite to the side facing the intermediate layer 82 in the first direction z. As a result, the plurality of conductive layers 83 are exposed from the surface of the first resin layer 84 facing in the first direction z.
  • a plurality of wiring layers 21 are formed which are in contact with the surface of the first resin layer 84 facing in the first direction z and each connected to one or more of the plurality of conductive layers 83.
  • the entirety of each portion of the plurality of conductive layers 83 and the first resin layer 84 located on the side opposite to the side facing the intermediate layer 82 in the first direction z is formed.
  • a covering base layer (not shown) is formed.
  • the composition of the base layer is the same as that of the intermediate layer 82 described above.
  • the base layer is formed by sputtering.
  • lithography patterning is performed on the base layer.
  • a plurality of wiring layers 21 are deposited by electrolytic plating using the base layer as a conductive path.
  • the mask layer for lithographic patterning is removed. Through the above steps, a plurality of wiring layers 21 are formed.
  • a plurality of bonding layers 39 are formed, each of which is connected to one of the plurality of wiring layers 21.
  • lithography patterning is performed on the aforementioned base layer and the plurality of wiring layers 21.
  • a plurality of nickel layers are deposited by electrolytic plating using the base layer and the plurality of wiring layers 21 as conductive paths.
  • Each of the plurality of nickel layers corresponds to the seat portion 391 of each of the plurality of bonding layers 39 shown in FIG.
  • a plurality of alloy layers containing tin are individually deposited on the plurality of nickel layers by electrolytic plating using the base layer, the plurality of wiring layers 21, and the plurality of nickel layers as conductive paths.
  • Each of the plurality of alloy layers corresponds to the bonding portion 392 of each of the plurality of bonding layers 39 shown in FIG. 8 .
  • the mask layer for lithographic patterning is removed.
  • the underlying layer is removed by wet etching using a mixed solution of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ).
  • the semiconductor element 30 is conductively bonded to the plurality of wiring layers 21.
  • the semiconductor element 30 is conductively bonded to the plurality of wiring layers 21 by flip-chip bonding.
  • the plurality of electrodes 32 of the semiconductor element 30 are individually temporarily attached to the plurality of bonding layers 39.
  • the bonding portion 392 (see FIG. 8) of each of the plurality of bonding layers 39 is melted by reflow.
  • the molten joint 392 is solidified by cooling.
  • an insulating layer 41 covering the plurality of wiring layers 21 is formed.
  • the weight percentage of the first filler mentioned above in the insulating layer 41 is the same as that of the filler in the second resin layer 85 mentioned later (corresponding to the second filler included in the sealing resin 50 mentioned above). ) is set lower than the weight percentage of At this time, the insulating layer 41 is inserted between the plurality of wiring layers 21 and the semiconductor element 30 in the first direction z. Furthermore, the exposed surface 212 is made to appear on the ground wiring 21A among the plurality of wiring layers 21.
  • a metal film 42 covering the semiconductor element 30 and the insulating layer 41 is formed.
  • a first film 421 (see FIG. 8) made of titanium is formed by sputtering.
  • the first film 421 is formed so as to be in contact with the semiconductor element 30 and the insulating layer 41 .
  • a second film 422 (see FIG. 8) made of copper is formed by sputtering.
  • the second film 422 is formed to cover the entire first film 421 .
  • a second resin layer 85 covering the metal film 42 is formed.
  • a part of the second resin layer 85 becomes the sealing resin 50 included in the semiconductor device A10.
  • the second resin layer 85 is made of a material containing a black epoxy resin containing a filler (the second filler included in the sealing resin 50 described above).
  • the second resin layer 85 is formed by compression molding. At this time, the second resin layer 85 is formed so as to surround at least the semiconductor element 30 when viewed in the first direction z.
  • the support member 81 and the intermediate layer 82 are removed by grinding. At this time, a portion of each of the plurality of conductive layers 83 and a portion of the first resin layer 84 are removed by grinding.
  • a tape 88 is attached to the surface of the second resin layer 85 facing in the first direction z.
  • Tape 88 is a dicing tape.
  • the first blade 891 having a width b1
  • a portion of each of the plurality of conductive layers 83, a portion of the first resin layer 84, a portion of each of the plurality of wiring layers 21, and the insulating layer 41 are removed.
  • a plurality of grooves 851 recessed in the first direction z are formed.
  • the plurality of grooves 851 are formed in a lattice shape along each of the second direction x and the third direction y.
  • each of the plurality of conductive layers 83 becomes one of the plurality of terminals 22 included in the semiconductor device A10 or the heat dissipation layer 23 included in the semiconductor device A10.
  • the first resin layer 84 becomes the base material 10 included in the semiconductor device A10.
  • the surface of the base material 10 that faces the first direction z and is exposed to the outside is the back surface 12 of the base material 10 .
  • a plurality of coating layers 60 are formed to individually cover the surfaces of the plurality of terminals 22 and the heat dissipation layer 23 exposed to the outside from the base material 10.
  • the plurality of covering layers 60 are formed by electroless plating.
  • the second resin layer 85 is cut using a second blade 892 having a width b2.
  • the width b2 is smaller than the width b1 of the first blade 891.
  • the insulating layer 41 is in contact with the entire peripheral surface 301 of the semiconductor element 30. Furthermore, the insulating layer 41 is in contact with the entire upper surface 311 of the main body 31 of the semiconductor element 30 .
  • the dimension of the portion of the insulating layer 41 in contact with the entire upper surface 311 in the first direction z is larger than the dimension of the portion in the first direction z in the semiconductor device A10.
  • the semiconductor device A10 includes an insulating layer 41 that covers the wiring layer 21, a sealing resin 50 that surrounds at least the semiconductor element 30 when viewed in the first direction z, and a sealing resin 50 that covers the semiconductor element 30 and is sealed with the insulating layer 41.
  • the metal film 42 includes a portion located between the metal film 42 and the resin 50. A portion of the insulating layer 41 is located between the wiring layer 21 and the sealing resin 50.
  • the insulating layer 41 is exposed to the outside from the first side surface 52 of the sealing resin 50.
  • the maximum dimension of the insulating layer 41 in the first direction z is smaller than the maximum dimension of the sealing resin 50 in the first direction z.
  • the wiring layer 21 and the metal film 42 are electrically insulated, and the metal film 42 overlaps the peripheral surface 301 of the semiconductor element 30 when viewed in a direction perpendicular to the first direction z. can do. This further improves the noise reduction effect in the semiconductor device A10.
  • the plurality of electrodes 32 of the semiconductor element 30 that are conductively bonded to the wiring layer 21 have a base 321 and a columnar part 322 that protrudes from the base 321 toward the wiring layer 21.
  • the columnar portion 322 is electrically conductively bonded to the wiring layer 21 and is in contact with the insulating layer 41 .
  • the thermal conductivity of the insulating layer 41 is set higher than that of the sealing resin 50, the heat emitted from the semiconductor element 30 is transferred from the columnar part 322 of each of the plurality of electrodes 32 to the insulating layer 41. conduction becomes easier. Furthermore, since the insulating layer 41 is exposed to the outside from the first side surface 52 of the sealing resin 50, it is possible to improve the heat dissipation of the semiconductor device A10.
  • the insulating layer 41 contains a first filler.
  • the sealing resin 50 contains a second filler.
  • the weight percent of the first filler in the insulating layer 41 is lower than the weight percent of the sealing resin 50.
  • the insulating layer 41 is in contact with the peripheral surface 301 of the semiconductor element 30.
  • the metal film 42 is separated from the semiconductor element 30 via the insulating layer 41.
  • the semiconductor device A10 further includes a base material 10 that supports a wiring layer 21, and a terminal 22 accommodated in the base material 10 and connected to the wiring layer 21.
  • the terminals 22 are exposed from the back surface 12 of the base material 10.
  • the semiconductor device A10 further includes a coating layer 60 that covers the portion of the terminal 22 exposed from the base material 10. Covering layer 60 has electrical conductivity.
  • the composition of the coating layer 60 includes gold.
  • the terminal 22 is also exposed from the second side surface 13 of the base material 10.
  • the covering layer 60 also covers the portion of the terminal 22 exposed from the second side surface 13.
  • the semiconductor device A10 further includes a heat dissipation layer 23 housed in the base material 10.
  • the heat dissipation layer 23 is connected to the wiring layer 21.
  • the heat dissipation layer 23 is exposed to the outside from the back surface 12 of the base material 10. With this configuration, heat generated from the semiconductor element 30 is conducted to the heat dissipation layer 23 via the plurality of electrodes 32 and the wiring layer 21. Thereby, it is possible to improve the heat dissipation of the semiconductor device A10.
  • the composition of the metal film 42 includes titanium. By adopting this configuration, it is possible to prevent the metal film 42 from peeling off from the insulating layer 41 even if the insulating layer 41 contains resin. Furthermore, a cavity 53 is provided between the metal film 42 and the sealing resin 50 in the first direction z. The cavity 53 communicates with the outside. By adopting this configuration, it is possible to suppress a decrease in the dielectric strength voltage of the semiconductor device A10 due to the provision of the metal film 42.
  • the semiconductor device A10 further includes a plurality of dummy terminals 24 arranged at the four corners of the base material 10 when viewed in the first direction z.
  • thermal stress acts on the terminals 22.
  • the thermal stress tends to concentrate at the four corners of the semiconductor device A10 when viewed in the first direction z. Therefore, by adopting this configuration, thermal stress can be concentrated on the plurality of dummy terminals 24, so that the thermal stress acting on the terminals 22 can be reduced. This makes it difficult for cracks to occur in the solder used to conductively connect the wiring board and the terminals 22, so that inhibition of conduction between the terminals 22 and the wiring board can be more effectively prevented.
  • FIGS. 24 to 26 A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 24 to 26.
  • the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the XXV-XXV line and the XXVI-XXVI line are each shown by a dashed-dotted line.
  • the configurations of the metal film 42 and the sealing resin 50 are different from the configurations of the semiconductor device A10.
  • the sealing resin 50 is provided with an opening 54 that opens from the top surface 51.
  • the entire semiconductor element 30 is included in the opening 54 when viewed in the first direction z.
  • the metal film 42 is exposed to the outside through the opening 54. Therefore, the metal film 42 is exposed to the outside from the top surface 51.
  • the region of the metal film 42 exposed from the top surface 51 of the sealing resin 50 is located away from the top surface 51 in the first direction z.
  • the area may be flush with the top surface 51.
  • the semiconductor device A20 includes an insulating layer 41 that covers the wiring layer 21, a sealing resin 50 that surrounds at least the semiconductor element 30 when viewed in the first direction z, and a sealing resin 50 that covers the semiconductor element 30 and seals with the insulating layer 41.
  • the metal film 42 includes a portion located between the metal film 42 and the resin 50.
  • a portion of the insulating layer 41 is located between the wiring layer 21 and the sealing resin 50.
  • the insulating layer 41 is exposed to the outside from the first side surface 52 of the sealing resin 50. Therefore, according to this configuration, even in the semiconductor device A20, it is possible to reduce noise while reducing the size of the semiconductor device A20. Further, the semiconductor device A20 has the same configuration as the semiconductor device A10, so that the same effects as the semiconductor device A10 can be achieved.
  • the metal film 42 is exposed to the outside from the top surface 51 of the sealing resin 50. With this configuration, heat generated from the semiconductor element 30 is released to the outside through the metal film 42 in addition to the heat dissipation layer 23. Therefore, the heat dissipation of the semiconductor device A20 can be further improved.
  • FIG. 27 A semiconductor device A30 according to a third embodiment of the present disclosure will be described based on FIGS. 27 to 31.
  • the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the sealing resin 50 is shown in FIG. 27, for convenience of understanding.
  • the semiconductor element 30, the insulating layer 41, and the metal film 42 are further transparent compared to FIG. 27.
  • the transparent sealing resin 50 is shown with imaginary lines.
  • the semiconductor element 30 and the sealing resin 50 that are transmitted through the light are shown by imaginary lines.
  • the XXIX-XXIX line and the XXX-XX line are each shown by a dashed-dotted line.
  • the semiconductor device A30 differs from the semiconductor device A10 in that it further includes a plurality of protruding layers 25.
  • the plurality of protruding layers 25 are located on the opposite side from the plurality of terminals 22 with respect to the plurality of wiring layers 21 in the first direction z. Each of the plurality of protruding layers 25 is connected to one of the plurality of wiring layers 21.
  • the plurality of protruding layers 25 are conductors.
  • the composition of the plurality of protruding layers 25 includes copper.
  • the plurality of protruding layers 25 individually overlap the plurality of terminals 22 when viewed in the first direction z.
  • an insulating layer 41 is located between the plurality of protruding layers 25 and the metal film 42 in the first direction z. Therefore, the metal film 42 is separated from the plurality of protruding layers 25 with the insulating layer 41 interposed therebetween.
  • each of the plurality of protruding layers 25 has a sixth exposed surface 251.
  • the sixth exposed surface 251 faces in a direction perpendicular to the first direction z.
  • the sixth exposed surface 251 is exposed from the first side surface 52 of the sealing resin 50.
  • the sixth exposed surface 251 is flush with any end surface 211 of the plurality of wiring layers 21 .
  • the second exposed surface 222 of any one of the plurality of terminals 22 and the end surface 211 of any one of the plurality of wiring layers 21 as well as the sixth exposed surface 251 are covered with one of the plurality of coating layers 60 .
  • the semiconductor device A30 includes an insulating layer 41 that covers the wiring layer 21, a sealing resin 50 that surrounds at least the semiconductor element 30 when viewed in the first direction z, and a sealing resin 50 that covers the semiconductor element 30 and is sealed with the insulating layer 41.
  • a metal film 42 including a portion located between the metal film 42 and the resin 50 is provided.
  • a portion of the insulating layer 41 is located between the wiring layer 21 and the sealing resin 50. Further, the insulating layer 41 is exposed to the outside from the first side surface 52 of the sealing resin 50. Therefore, according to this configuration, even in the semiconductor device A30, it is possible to reduce noise while reducing the size of the semiconductor device A30. Further, the semiconductor device A30 has the same configuration as the semiconductor device A10, so that it can achieve the same effects as the semiconductor device A10.
  • the semiconductor device A30 further includes a protrusion layer 25 that is a conductor.
  • the protrusion layer 25 is located on the opposite side of the terminal 22 with respect to the wiring layer 21 in the first direction z.
  • the protruding layer 25 overlaps the terminal 22 when viewed in the first direction z.
  • An insulating layer 41 is located between the protrusion layer 25 and the metal film 42.
  • the protruding layer 25 is exposed from the first side surface 52 of the sealing resin 50.
  • a portion of the protruding layer 25 exposed from the first side surface 52 is covered with a covering layer 60.
  • the dimension of the solder fillet formed in contact with the covering layer 60 in the first direction z is further expanded, so that the volume of the solder fillet is increased. Therefore, it is possible to further improve the bonding strength of the semiconductor device A30 to the wiring board.
  • a wiring layer a semiconductor element having a plurality of electrodes facing the wiring layer, and the plurality of electrodes being conductively bonded to the wiring layer; an insulating layer covering the wiring layer; a sealing resin located on the opposite side of the wiring layer with respect to the insulating layer in a first direction and surrounding at least the semiconductor element when viewed in the first direction; a metal film that covers the semiconductor element and includes a portion located between the insulating layer and the sealing resin; A part of the insulating layer is located between the wiring layer and the semiconductor element, The sealing resin has a first side facing in a direction perpendicular to the first direction, The semiconductor device, wherein the insulating layer is exposed to the outside from the first side surface.
  • Appendix 2 The semiconductor device according to appendix 1, wherein a maximum dimension of the insulating layer in the first direction is smaller than a maximum dimension of the sealing resin in the first direction.
  • Appendix 3. The plurality of electrodes have a base and a columnar part protruding from the base toward the wiring layer, The semiconductor device according to appendix 2, wherein the columnar portion is conductively bonded to the wiring layer and in contact with the insulating layer.
  • the insulating layer contains a first filler
  • the sealing resin contains a second filler
  • the semiconductor device according to appendix 2 or 3 wherein a weight percentage of the first filler in the insulating layer is lower than a weight percentage of the second filler in the sealing resin.
  • Appendix 5. 5 The semiconductor device according to appendix 1, wherein a maximum dimension of the insulating layer in the first direction is smaller than a maximum dimension of the sealing resin in the first direction.
  • Appendix 3. The plurality of electrodes have a base
  • Appendix 6. The semiconductor element has a peripheral surface facing in a direction perpendicular to the first direction, 6. The semiconductor device according to any one of appendices 2 to 5, wherein the insulating layer is in contact with the peripheral surface.
  • Appendix 7. The semiconductor element has an upper surface facing the opposite side to the side facing the wiring layer in the first direction, The semiconductor device according to appendix 6, wherein the insulating layer is in contact with the upper surface.
  • the sealing resin has a top surface facing the same side as the top surface in the first direction, 8.
  • Appendix 9. The semiconductor device according to any one of appendices 2 to 8, wherein the metal film has a composition including copper.
  • Appendix 10. The composition of the metal film includes titanium, The semiconductor device according to appendix 9, wherein the metal film is exposed to the outside from the first side surface.
  • Appendix 11. A cavity is provided between the metal film and the sealing resin in the first direction, The semiconductor device according to appendix 10, wherein the cavity communicates with the outside.
  • Appendix 12. further comprising a base material that supports the wiring layer, 12.
  • the base material has a back surface facing the side opposite to the side facing the wiring layer with respect to the first direction, The semiconductor device according to appendix 12, wherein the terminal is exposed from the back surface.
  • the base material has a second side surface facing in a direction perpendicular to the first direction, The semiconductor device according to attachment 13, wherein the terminal is exposed from the second side surface.
  • Appendix 15. further comprising a coating layer that covers a portion of the terminal exposed from the base material, The coating layer is a conductor, The semiconductor device according to appendix 14, wherein the composition of the coating layer includes gold. Appendix 16.
  • A10, A20, A30: Semiconductor device 10 Base material 11: Main surface 12: Back surface 13: Second side surface 21: Wiring layer 21A: Ground wiring 211: End surface 212: Exposed surface 22: Terminal 221: First exposed surface 222: Second exposed surface 23: Heat dissipation layer 231: Third exposed surface 24: Dummy terminal 241: Fourth exposed surface 242: Fifth exposed surface 25: Protrusion layer 251: Sixth exposed surface 30: Semiconductor element 301: Peripheral surface 31: Main body portion 311: Upper surface 32: Electrode 321: Base portion 322: Column portion 33: Passivation film 331: Opening 39: Bonding layer 391: Seat portion 392: Bonding portion 41: Insulating layer 42: Metal film 421: First film 422: First 2 film 50: Sealing resin 51: Top surface 52: First side surface 521: First region 522: Second region 53: Cavity 54: Opening 60: Covering layer 81: Support member 82: Intermediate layer 83: Conductive layer 84: First resin layer

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
PCT/JP2023/022613 2022-07-22 2023-06-19 半導体装置 Ceased WO2024018798A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012204368A (ja) * 2011-03-23 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置およびその製造方法
JP2012204632A (ja) * 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
JP2013207059A (ja) * 2012-03-28 2013-10-07 Renesas Electronics Corp 半導体装置
WO2022080081A1 (ja) * 2020-10-16 2022-04-21 ローム株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012204368A (ja) * 2011-03-23 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置およびその製造方法
JP2012204632A (ja) * 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
JP2013207059A (ja) * 2012-03-28 2013-10-07 Renesas Electronics Corp 半導体装置
WO2022080081A1 (ja) * 2020-10-16 2022-04-21 ローム株式会社 半導体装置

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