WO2024014212A1 - 電子部品 - Google Patents

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Publication number
WO2024014212A1
WO2024014212A1 PCT/JP2023/021861 JP2023021861W WO2024014212A1 WO 2024014212 A1 WO2024014212 A1 WO 2024014212A1 JP 2023021861 W JP2023021861 W JP 2023021861W WO 2024014212 A1 WO2024014212 A1 WO 2024014212A1
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WIPO (PCT)
Prior art keywords
substrate
electronic component
conductor
planar conductor
inductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/021861
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English (en)
French (fr)
Japanese (ja)
Inventor
孝昭 水野
俊幸 中磯
健司 豊島
由雅 吉岡
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202380052142.XA priority Critical patent/CN119563217A/zh
Priority to JP2024533590A priority patent/JP7758199B2/ja
Publication of WO2024014212A1 publication Critical patent/WO2024014212A1/ja
Priority to US19/011,906 priority patent/US20250150050A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0078—Constructional details comprising spiral inductor on a substrate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets

Definitions

  • the present invention relates to an electronic component including a conductor pattern forming a capacitor or inductor on a substrate.
  • An electronic component having a conductor pattern constituting a capacitor or inductor on a substrate is used, for example, as an LC composite component.
  • Patent Document 1 shows an LC composite component in which a capacitor electrode is arranged outside an air core portion of a coil formed of a helical conductor pattern.
  • Patent Document 2 shows an LC composite component in which a capacitor electrode is arranged so as not to overlap the central axis of a coil conductor formed by a spiral conductor pattern.
  • Patent Document 3 discloses an LC in which a capacitor with comb-shaped electrodes is arranged in an upper layer or a lower layer other than the central region of a coil conductor with a spiral conductor pattern, and the comb-shaped electrodes are formed perpendicularly to the conductor wiring for an inductor. A composite part is shown.
  • an object of the present invention is to provide a miniaturized electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor that has a desired size.
  • An electronic component as an example of the present disclosure includes a substrate, an insulating layer extending along the surface of the substrate, and an electronic component formed on the substrate or in the insulating layer and extending planarly parallel to the surface of the substrate.
  • the inductor conductor pattern includes a single or plural planar conductors and an inductor conductor pattern formed on or in the insulator layer, when viewed from a direction perpendicular to the surface of the substrate.
  • Ls the distance between the inductor conductor pattern and the planar conductor closest to the inductor conductor pattern
  • d the value of Ls/d is 1 or more and 60 or less.
  • a miniaturized electronic component that includes an inductor conductor pattern that generates a desired inductance and a planar conductor that has a desired size.
  • FIG. 1 is a perspective view and a front view of an electronic component 101 according to the first embodiment.
  • FIG. 2 is a plan view and a cross-sectional view of the main parts of the electronic component 101.
  • FIG. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the planar conductor 4.
  • FIG. 4 is a diagram showing trends in Ls/d and Q/Q0 found from multiple combinations of Ls and d.
  • 5(A), FIG. 5(B), FIG. 5(C), and FIG. 5(D) are diagrams showing examples of the shape of the region where the inductor conductor pattern 5 is formed and the planar conductor 4 overlaps. .
  • FIG. 1 is a perspective view and a front view of an electronic component 101 according to the first embodiment.
  • FIG. 2 is a plan view and a cross-sectional view of the main parts of the electronic component 101.
  • FIG. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the
  • FIG. 6 is a plan view and a cross-sectional view of the electronic component 102 according to the second embodiment.
  • FIG. 7 is an equivalent circuit diagram of the electronic component 102.
  • FIG. 8 is a diagram showing the structure of each layer of the electronic component 102.
  • 9(A), FIG. 9(B), FIG. 9(C), and FIG. 9(D) are cross-sectional views of the electronic component 102 at each manufacturing process.
  • 10(A), FIG. 10(B), FIG. 10(C), and FIG. 10(D) are cross-sectional views of the electronic component 102 at each manufacturing process.
  • FIG. 11 is a plan view and a cross-sectional view of an electronic component 103 according to the third embodiment.
  • FIG. 12 is a diagram showing the structure of each layer of the electronic component 103.
  • FIG. 13(A), FIG. 13(B), FIG. 13(C), and FIG. 13(D) are cross-sectional views of the electronic component 103 in each manufacturing process.
  • 14(A), FIG. 14(B), and FIG. 14(C) are cross-sectional views of the electronic component 103 at each manufacturing process.
  • FIG. 15 is a plan view and a cross-sectional view of an electronic component 104 according to the fourth embodiment.
  • FIG. 16 is a plan view and a cross-sectional view of an electronic component 105 according to the fifth embodiment.
  • FIG. 17 is an equivalent circuit diagram of the electronic component 105.
  • FIG. 18 is a diagram showing the structure of each layer of the electronic component 105. 19(A), FIG. 19(B), FIG. 19(C), and FIG.
  • FIG. 19(D) are cross-sectional views of the electronic component 105 in each manufacturing process.
  • 20(A), FIG. 20(B), and FIG. 20(C) are cross-sectional views of the electronic component 105 at each manufacturing process.
  • FIG. 21 is a cross-sectional view of the electronic component 106 according to the sixth embodiment.
  • FIG. 1 is a perspective view of an electronic component 101 according to the first embodiment.
  • the outer shape is represented by a chain double-dashed line.
  • the lower part of FIG. 1 is a front view of the electronic component 101 viewed in the Y-axis direction.
  • This electronic component 101 includes an electrically insulating substrate 1, an insulating layer 2 extending along the surface of the substrate 1, and a surface parallel to the surface of the substrate 1 formed on or within the insulating layer 2. It includes a planar conductor 4 that spreads in a shape, and a rectangular spiral coil type inductor conductor pattern 5 formed on a substrate 1 or in an insulating layer 2.
  • FIG. 2 is a plan view of the main part of the electronic component 101, and the lower part of FIG. 2 is a cross-sectional view of the section XX in the plan view.
  • FIG. 3 is a perspective view showing the positional relationship between the inductor conductor pattern 5 and the planar conductor 4. As shown in FIG. However, for convenience of explanation, the distance between the inductor conductor pattern 5 and the planar conductor 4 is deliberately drawn wider.
  • the inductor conductor pattern 5 has a magnetic flux ⁇ opening MH where magnetic flux concentrates.
  • An eddy current EC flows through the planar conductor 4 according to this magnetic flux (high-frequency magnetic flux) ⁇ . This eddy current EC increases as the magnetic flux ⁇ increases.
  • the width of the planar conductor 4 is represented by W.
  • the distance between the inductor conductor pattern 5 and the planar conductor 4 is represented by d
  • the smaller the distance d between the inductor conductor pattern 5 and the planar conductor 4 the larger the eddy current EC becomes.
  • the surface of the substrate 1 is viewed from the vertical direction, and the length in the longitudinal direction of the region where the inductor conductor pattern 5 and the planar conductor 4 overlap is expressed as Ls, the larger Ls is, the more the eddy current EC becomes larger. Therefore, the larger the value of Ls/d, the larger the eddy current EC.
  • Table 1 shows the length Ls in the longitudinal direction of the region where the formation area of the inductor conductor pattern 5 and the planar conductor 4 overlap, the distance d between the inductor conductor pattern 5 and the planar conductor 4, and the Q of the inductor. It is a table showing relationships such as value deterioration.
  • S[ ⁇ m 2 ] is the area where the inductor conductor pattern 5 and the planar conductor 4 overlap when the area is square.
  • Q0 is the Q value of the inductor formed by the inductor conductor pattern 5 in the absence of the planar conductor 4
  • Q/Q0 is the Q value of the inductor formed by the inductor conductor pattern 5 in the absence of the planar conductor 4
  • Q/Q0 is the Q value of the inductor formed by the inductor conductor pattern 5 in the absence of the planar conductor 4.
  • L0 is the inductance of the inductor conductor pattern 5 without the planar conductor 4
  • L/L0 is the inductance of the inductor conductor pattern 5 when the planar conductor with area S [ ⁇ m 2 ] is separated from the inductor conductor pattern 5 by a distance of d [ ⁇ m]. This is the ratio between the L value and L0 when the sensor is placed at the position shown in FIG.
  • FIG. 4 is a diagram showing the tendency of Ls/d and Q/Q0 found from the above-mentioned combinations of Ls and d.
  • the horizontal axis is Ls/d and the vertical axis is Q/Q0.
  • the planar conductor 4 since the value of Ls/d (value of ⁇ (S)/d) is in the range of 1 to 60 and Q/Q0 is 0.3 or more, the planar conductor 4 The Q value of the inductor decreases little due to its presence. Furthermore, when the value of Ls/d is in the range of 1 or more and 55 or less, the decrease in Q/Q0 is further suppressed.
  • the overlapping area of the inductor conductor pattern 5 and the planar conductor 4 is a square, that is, the worst case, so the formation area of the inductor conductor pattern 5 and the planar conductor 4 are square. If the overlapping area with 4 is not square, the length in the longitudinal direction of this overlapping area may be treated as Ls.
  • the length in the longitudinal direction which is the total in a predetermined direction of a plurality of regions where the formation region of the inductor conductor pattern 5 and the planar conductor 4 overlap, may be treated as Ls.
  • FIG. 5(A), FIG. 5(B), FIG. 5(C), and FIG. 5(D) are diagrams showing examples of the shape of the region where the inductor conductor pattern 5 is formed and the planar conductor 4 overlaps. .
  • FIG. 5A if the region of the planar conductor 4 overlapping the formation region of the inductor conductor pattern 5 is L-shaped, the longitudinal dimension of that region is Ls.
  • FIG. 5B if the area of the planar conductor 4 overlapping the formation area of the inductor conductor pattern 5 is circular or oval, the longitudinal dimension in that area is set to Ls.
  • the longitudinal direction of the width L x height Ly of the area Let the dimension of be the above-mentioned Ls.
  • the total length in the longitudinal direction of the overlapping regions in a predetermined direction is Ls. shall be.
  • one of the two planar conductor regions overlapping the formation region of the inductor conductor pattern 5 has a dimension in the X-axis direction of Lx1 and a dimension in the Y-axis direction of Ly1, and the other region
  • the dimension in the X-axis direction is Lx2, and the dimension in the Y-axis direction is Ly2.
  • the value of Ly1+Ly2 is the length Ls in the longitudinal direction.
  • FIG. 6 is a plan view of the electronic component 102 according to the second embodiment, and the lower part of FIG. 6 is a sectional view taken along the line XX in the upper part of FIG.
  • the electronic component 102 includes a substrate 1, an insulator layer 2 extending along the surface of the substrate 1, an inductor formed in the insulator layer 2, and a planar conductor 3 formed on the substrate 1 and extending along the substrate 1. .
  • Terminal electrodes 10A and 10B are formed on the surface of the insulator layer 2. Terminal electrodes 10A and 10B are electrically connected to terminal electrodes 9A and 9B.
  • the inductor is a spiral coil type inductor formed by an inductor conductor pattern 5 along the surface of the substrate 1.
  • the planar conductors 3 and 4 are capacitor electrodes.
  • a capacitor is constituted by the planar conductors 3 and 4 and the dielectric layer 11 sandwiched between these planar conductors 3 and 4. That is, the planar conductors 3 and 4 are capacitor electrodes that constitute a capacitor together with the dielectric layer 11.
  • the formation region of the inductor conductor pattern 5 overlaps with the planar conductor 3 and also overlaps with the planar conductor 4. Since the planar conductor 4 is closer to the inductor conductor pattern 5 among the planar conductors 3 and 4, the distance between the inductor conductor pattern 5 and the planar conductor 4 is represented by d. Moreover, the length in the longitudinal direction of the largest region among the regions where the inductor conductor pattern 5 and the planar conductor 4 overlap is represented by Ls.
  • the value of Ls is 190 ⁇ m, and the distance d between the inductor conductor pattern 5 and the planar conductor 4 is 20 ⁇ m. Therefore, Ls/d is 9.5, which is less than 60 and even less than 55.
  • the ratio of the Q value Q0 when there is no planar conductor 4 to the Q value when the planar conductor 4 is present is Q/Q0. is 0.48, and although there is a decrease in the Q value, there is no extreme decrease, and an electronic component having an inductor with an effective Q value can be obtained.
  • FIG. 7 is an equivalent circuit diagram of the electronic component 102.
  • the electronic component 102 forms a series circuit of the inductor L1 and the capacitor C1.
  • This electronic component 102 can be used as a frequency filter or an impedance matching circuit.
  • FIG. 8 is a diagram showing the structure of each layer of the electronic component 102.
  • layer La is a layer of the substrate 1
  • layer Lb is a formation layer of the planar conductor 3
  • layer Lc is a formation layer of the dielectric layer 11 and the planar conductor connecting conductor 7A
  • layer Ld is a formation layer of the planar conductor 4 and the planar conductor 3.
  • This is a formation layer for the planar conductor connection conductor 7B.
  • the layer Le is a formation layer for the planar conductor connection conductors 7C and 8
  • the layer Lf is a formation layer for the inductor conductor pattern 5 and the terminal electrodes 9A and 9B.
  • the layer Lg is a formation layer for the terminal electrodes 10A and 10B.
  • FIG. 9(A) is a cross-sectional view of the substrate.
  • the substrate not only a semiconductor substrate such as a Si substrate or a GaAs substrate, but also a glass substrate or a ceramic substrate can be used.
  • FIG. 9(B) is a cross-sectional view in a state where the planar conductor 3 is formed. In this step, it is formed by a semiconductor process such as depositing an Al or Cu film on the surface of the substrate 1 and lifting it off, or depositing an Al or Cu film by sputtering or CVD, lithography, and etching.
  • FIG. 9C is a cross-sectional view with the dielectric layer 11 formed.
  • a dielectric layer 11 such as an SiO 2 film or a SiN film is formed on the surface of the planar conductor 3 by a semiconductor process such as sputtering or CVD.
  • a semiconductor process such as sputtering or CVD.
  • an opening is formed in the formation portion of the planar conductor connecting conductor 7A, and the planar conductor connecting conductors 7A, 7B and the planar conductor 4 are formed.
  • an opening is formed by lithography and etching, an Al film or a Cu film is deposited, and lift-off is performed, an Al film or a Cu film is formed by sputtering or CVD, lithography is performed, and etching is performed.
  • a pattern of planar conductors 4 is formed.
  • FIG. 10(A) is a cross-sectional view in a state where the insulator layer 2 is formed and the opening AP is formed.
  • a resin (organic) film, an SiO 2 film, an SiN film, or other inorganic film is formed by a method such as spin coating, CVD, or sputtering, and then an opening AP is formed at a predetermined location by lithography and etching.
  • FIG. 10(B) is a cross-sectional view in a state where the planar conductor connecting conductors 7C and 8 are formed.
  • conductors 7C and 8 for connecting planar conductors are formed in the opening AP shown in FIG. 10(A). For example, it is formed by depositing Cu, lithography, and plating, or by sputtering, lithography, and etching Cu, or by lithography, vapor deposition, and lift-off of Cu. .
  • FIG. 10(C) is a cross-sectional view with the inductor conductor pattern 5 and terminal electrodes 9A and 9B formed.
  • an inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed on the surface of the insulator layer 2. For example, it is formed by depositing Cu, lithography, and plating, or by sputtering, lithography, and etching Cu, or by lithography, vapor deposition, and lift-off of Cu. .
  • FIG. 10(D) is a cross-sectional view with terminal electrodes 10A and 10B formed.
  • the terminal electrodes 10A, 10B are electrodes for mounting, and are formed by applying Ni plating, Au plating, etc. to the surfaces of the terminal electrodes 9A, 9B.
  • a protective film is formed, and the terminal electrodes 10A and 10B are opened to expose the terminal electrodes 10A and 10B.
  • FIG. 11 is a diagram showing the structure of an electronic component 103 according to the third embodiment.
  • ⁇ Plan view> in FIG. 11 is a plan view of the electronic component 103.
  • the ⁇ cross-sectional view> in FIG. 11 is a cross-sectional view taken along the line XX in the plan view of the electronic component 103.
  • the electronic component 103 includes a substrate 1 , an insulator layer 2 extending along the surface of the substrate 1 , an inductor conductor pattern 5 formed in the insulator layer 2 , and a conductor pattern 5 formed on the substrate 1 and extending along the substrate 1 . It includes a dielectric layer 11, a planar conductor 4, a planar conductor connection conductor 8 electrically connected to the planar conductor 4, and planar conductor connection conductors 7A, 7B, and 7C electrically connected to the substrate 1.
  • a dielectric layer 11 is formed on the surface of the substrate 1, and a planar conductor 4 is formed on the surface of this dielectric layer 11. Further, a conductor 7A for connecting a planar conductor is formed at a predetermined position on the surface of the substrate 1.
  • the substrate 1 is a semiconductor substrate with high conductivity. The other configurations are as shown in the second embodiment.
  • the value of Ls is 210 ⁇ m, and the distance d between the inductor conductor pattern 5 and the planar conductor 4 is 30 ⁇ m. Therefore, Ls/d is 7, which is less than 60 and even less than 55.
  • the ratio Q/Q0 of the Q value Q0 when there is no planar conductor 4 and the Q value when the planar conductor 4 is present is 0.61, and the inductor with an effective Q value is An electronic component is obtained.
  • FIG. 12 is a diagram showing the structure of each layer of the electronic component 103.
  • the layer La is a layer of the substrate 1
  • the layer Lb is a formation layer of the planar conductor connection conductor 7A and the dielectric layer 11
  • the layer Lc is the formation layer of the dielectric layer 11 and the planar conductor 4
  • the layer Ld is a formation layer of the dielectric layer 11 and the planar conductor 4.
  • This is a formation layer for the planar conductor connection conductors 7C and 8.
  • the layer Le is a formation layer for the inductor conductor pattern 5 and the terminal electrodes 9A and 9B.
  • the layer Lf is a formation layer for the terminal electrodes 10A and 10B.
  • FIG. 13(A) is a cross-sectional view of the substrate.
  • the substrate not only semiconductor substrates such as Si substrates and GaAs substrates but also glass substrates and ceramic substrates can be used.
  • FIG. 13(B) is a cross-sectional view in a state where the dielectric layer 11 is formed and an opening AP is formed at a predetermined position.
  • FIG. 13(C) is a cross-sectional view of a state in which the planar conductor connecting conductor 7A is formed in the opening AP, and the planar conductor connecting conductor 7B and the planar conductor 4 are formed on the upper surface of the dielectric layer 11. be.
  • 13(D) is a cross-sectional view with the insulator layer 2 formed and the opening AP formed.
  • a resin (organic) film, an SiO 2 film, an SiN film, or other inorganic film is formed by a method such as spin coating, CVD, or sputtering, and then an opening AP is formed at a predetermined location by lithography and etching.
  • FIG. 14(A) is a cross-sectional view in a state where the planar conductor connecting conductors 7C and 8 are formed.
  • conductors 7C and 8 for connecting planar conductors are formed in the opening AP shown in FIG. 13(D).
  • it is formed by depositing Cu, lithography, and plating, or by sputtering, lithography, and etching Cu, or by lithography, vapor deposition, and lift-off of Cu. .
  • FIG. 14(B) is a cross-sectional view with the inductor conductor pattern 5 and terminal electrodes 9A and 9B formed.
  • an inductor conductor pattern 5 and terminal electrodes 9A and 9B are formed on the surface of the insulator layer 2. For example, it is formed by depositing Cu, lithography, and plating, or by sputtering, lithography, and etching Cu, or by lithography, vapor deposition, and lift-off of Cu. .
  • FIG. 14(C) is a cross-sectional view with terminal electrodes 10A and 10B formed.
  • the terminal electrodes 10A, 10B are electrodes for mounting, and are formed by applying Ni plating, Au plating, etc. to the surfaces of the terminal electrodes 9A, 9B. Thereafter, a protective film is formed, and the terminal electrodes 10A and 10B are opened to expose the terminal electrodes 10A and 10B.
  • FIG. 15 is a plan view of the electronic component 104.
  • the ⁇ cross-sectional view> in FIG. 15 is a cross-sectional view taken along the line XX in the plan view of the electronic component 104.
  • the electronic component 104 includes a substrate 1, a dielectric layer 11 formed on the upper surface of the substrate 1, a terminal electrode 9A formed on the lower surface of the substrate 1, an insulator layer 2, and a dielectric layer 11 formed in the insulator layer 2. It includes an inductor conductor pattern 5, a planar conductor 4 extending along the substrate 1, and a planar conductor connection conductor 8 electrically connected to the planar conductor 4.
  • the electronic component 104 of this embodiment uses the capacitance generated between the planar conductor 4 and the terminal electrode 9A as a capacitor. Further, terminal electrodes 9A and 9B on the upper and lower surfaces are used.
  • the value of Ls is 210 ⁇ m, and the value of d is 30 ⁇ m.
  • This electronic component 103 is the same as the electronic component 103 shown in the third embodiment except for the back electrode. Therefore, the value of Ls/d is the same as the result shown in the third embodiment.
  • FIG. 16 is a diagram showing the structure of an electronic component 105 according to the fifth embodiment.
  • ⁇ Plan view> in FIG. 16 is a plan view of the electronic component 105.
  • the ⁇ cross-sectional view> in FIG. 16 is a cross-sectional view taken along the line XX in the plan view of the electronic component 105.
  • the electronic component 105 includes a substrate 1 , an insulating film 20 extending along the surface of the substrate 1 , an inductor conductor pattern 5 formed within the insulating layer 2 , and an insulating film 20 formed on the insulating film 20 . , a conductor 7 for connecting a planar conductor that is electrically connected to the resistor film 21 and the terminal electrode 9A, and a conductor 8 for connecting a planar conductor that is electrically connected to the resistor film 21 and the terminal electrode 9B. and.
  • the resistor film 21 corresponds to a planar conductor according to the present invention.
  • FIG. 17 is an equivalent circuit diagram of the electronic component 105.
  • the electronic component 105 constitutes a composite component including the inductor L1 and the resistive element R1.
  • FIG. 18 is a diagram showing the structure of each layer of the electronic component 105.
  • the layer La is a formation layer of the insulator film 20 and the resistor film 21
  • the layer Lb is the formation layer of the conductors 7 and 8 for connecting planar conductors
  • the layer Lc is the formation layer of the inductor conductor pattern 5 and the terminal electrodes 9A and 9B. , 9C.
  • the layer Ld is a formation layer for the terminal electrodes 10A, 10B, and 10C.
  • FIG. 19(A) is a cross-sectional view of the substrate.
  • FIG. 19(B) is a cross-sectional view with the insulator film 20 formed.
  • FIG. 19C is a cross-sectional view of a state in which a resistor film 21 is formed on an insulator film 20.
  • FIG. 19(D) is a cross-sectional view with the insulator layer 2 formed and the opening AP formed.
  • the resistor film 21 is made of a material having a conductivity between that of the insulator layer and that of the conductor forming the terminal electrode and the conductor pattern for the inductor.
  • the resistor film 21 may be, for example, a film made of NiCr, Si containing impurities, or a layered insulator/conductor.
  • FIG. 20(A) is a cross-sectional view in a state where the planar conductor connecting conductors 7 and 8 are formed. In this step, conductors 7 and 8 for connecting planar conductors are formed in the opening AP shown in FIG. 19(D).
  • FIG. 20(B) is a cross-sectional view with the inductor conductor pattern 5 and terminal electrodes 9A, 9B, and 9C formed.
  • an inductor conductor pattern 5 and terminal electrodes 9A, 9B, and 9C are formed on the surface of the insulator layer 2.
  • FIG. 20(C) is a cross-sectional view in a state where terminal electrodes 10A, 10B, and 10C for mounting are formed.
  • the surfaces of the terminal electrodes 9A, 9B, and 9C are formed by applying Ni plating, Au plating, etc.
  • a protective film is formed, and the terminal electrodes 10A, 10B, 10C are opened to expose the terminal electrodes 10A, 10B, 10C.
  • the value of Ls is 250 ⁇ m
  • the value of d is 30 ⁇ m
  • Ls/d is approximately 8.3.
  • Ls/d is smaller than 55
  • Q/Q0 is 0.52
  • an electronic component with a sufficiently large inductor Q value can be obtained.
  • FIG. 21 is a cross-sectional view of the electronic component 106 according to the sixth embodiment.
  • This electronic component 106 includes a substrate 1 , a dielectric layer 11 extending along the surface of the substrate 1 , planar conductors 3 and 4 formed in the dielectric layer 11 , and spiral conductors formed in the insulator layer 2 . It includes a coil-type inductor conductor pattern 5 and terminal electrodes 9A, 9B, 10A, and 10B. One end of the inductor conductor pattern 5 is electrically connected to the planar conductor 4 and the terminal electrode 9A, and the other end of the inductor conductor pattern 5 is electrically connected to the planar conductor 3 and the terminal electrode 9B.
  • This electronic component 106 constitutes a parallel circuit of an inductor and a capacitor.
  • Ls the length in the longitudinal direction of the region where the inductor conductor pattern 5 and the planar conductor 4 overlap
  • d the distance between the inductor conductor pattern and the sheet conductor
  • the inductor conductor pattern has an opening MH of magnetic flux ⁇ where magnetic flux is concentrated, and a planar conductor is arranged in the whole or part of the opening MH.
  • the planar conductor covers the entire opening MH of the magnetic flux ⁇ is not necessarily shown, the planar conductor may cover the entire opening MH of the magnetic flux ⁇ .
  • an electronic component including a capacitor or a resistive element as a passive component other than an inductor is shown, but an electronic component including a passive component including both a capacitor and a resistive element can be similarly configured. Further, an electronic component including a passive component including a plurality of capacitors and a plurality of inductors can be similarly configured.
  • the present invention can be similarly applied to electronic components used as LC parallel resonant circuits, bandpass filters, diplexers, etc. including a plurality of inductors and capacitors.
  • the substrate is a semiconductor substrate
  • the planar conductor can be similarly applied to electronic components that constitute a semiconductor active element together with the semiconductor substrate.
  • the present invention can be similarly applied to a high frequency power amplifier in which active components are provided on a semiconductor substrate.
  • a conductor, and an inductor conductor pattern formed on or in the insulator layer, and when viewed from a direction perpendicular to the surface of the substrate, the area in which the inductor conductor pattern is formed and the planar shape are Ls represents the length in the longitudinal direction of a single region where the conductor overlaps, or the total longitudinal length in a predetermined direction of a plurality of regions where the inductor conductor pattern formation region and the planar conductor overlap.
  • the value of Ls/d is 1 or more and 60 or less.
  • the method according to ⁇ 1> or ⁇ 2> includes a dielectric layer formed between the substrate and the insulator layer, and the planar conductor is a capacitor electrode that constitutes a capacitor together with the dielectric layer. Electronic components listed.
  • ⁇ 4> The electronic component according to ⁇ 1> or ⁇ 2>, wherein the substrate is a low-resistance semiconductor substrate, and the planar conductor is a capacitor electrode that forms a capacitor together with the semiconductor substrate.
  • ⁇ 5> The electronic component according to ⁇ 1> or ⁇ 2>, wherein the substrate is a semiconductor substrate, and the planar conductor constitutes a semiconductor active element together with the semiconductor substrate.
  • ⁇ 6> The electronic component according to any one of ⁇ 1> to ⁇ 5>, wherein the planar conductor is a resistive thin film.
  • ⁇ 7> The electronic component according to any one of ⁇ 1> to ⁇ 6>, wherein the inductor conductor pattern has a magnetic flux opening where magnetic flux concentrates, and the planar conductor is arranged in the opening.

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Coils Or Transformers For Communication (AREA)
PCT/JP2023/021861 2022-07-13 2023-06-13 電子部品 Ceased WO2024014212A1 (ja)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249832A (ja) * 2002-02-22 2003-09-05 Murata Mfg Co Ltd Ｅｍｉフィルタ
JP2005020577A (ja) * 2003-06-27 2005-01-20 Murata Mfg Co Ltd Ｌｃ共振子
JP2010239380A (ja) * 2009-03-31 2010-10-21 Tdk Corp 積層型電子部品
JP2011233807A (ja) * 2010-04-30 2011-11-17 Panasonic Corp 半導体装置およびその製造方法
WO2015037374A1 (ja) * 2013-09-13 2015-03-19 株式会社村田製作所 インダクタおよび帯域除去フィルタ
JP2019186696A (ja) * 2018-04-06 2019-10-24 株式会社村田製作所 電子部品

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249832A (ja) * 2002-02-22 2003-09-05 Murata Mfg Co Ltd Ｅｍｉフィルタ
JP2005020577A (ja) * 2003-06-27 2005-01-20 Murata Mfg Co Ltd Ｌｃ共振子
JP2010239380A (ja) * 2009-03-31 2010-10-21 Tdk Corp 積層型電子部品
JP2011233807A (ja) * 2010-04-30 2011-11-17 Panasonic Corp 半導体装置およびその製造方法
WO2015037374A1 (ja) * 2013-09-13 2015-03-19 株式会社村田製作所 インダクタおよび帯域除去フィルタ
JP2019186696A (ja) * 2018-04-06 2019-10-24 株式会社村田製作所 電子部品

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