WO2024012453A1 - 驱动电路、显示驱动芯片、显示设备及电子设备 - Google Patents

驱动电路、显示驱动芯片、显示设备及电子设备 Download PDF

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Publication number
WO2024012453A1
WO2024012453A1 PCT/CN2023/106798 CN2023106798W WO2024012453A1 WO 2024012453 A1 WO2024012453 A1 WO 2024012453A1 CN 2023106798 W CN2023106798 W CN 2023106798W WO 2024012453 A1 WO2024012453 A1 WO 2024012453A1
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Prior art keywords
transistor
circuit
resistor
output signal
stage circuit
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Application number
PCT/CN2023/106798
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English (en)
French (fr)
Inventor
胡龙山
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北京集创北方科技股份有限公司
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Priority to KR1020247002628A priority Critical patent/KR20240025643A/ko
Publication of WO2024012453A1 publication Critical patent/WO2024012453A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a driving circuit, a display driving chip, a display device and an electronic device.
  • An operational amplifier is a circuit unit with a very high amplification factor. It is widely used in the field of integrated circuits, so problems that may arise in different application scenarios need to be considered in design.
  • a common problem is that the op amp's load capacitance is uncertain. For example, when an operational amplifier is used in a drive circuit to drive an LED display, it can drive many LEDs, and the number of LEDs is determined by the user. Therefore, when designing the operational amplifier, it is necessary to consider that the load capacitance of the operational amplifier can be approximately is any value; at the same time, in some application scenarios, the operational amplifier can be used as a gain amplifier.
  • the gain amplifier requires a certain amplification factor for the output and input, so another issue is that the transient response of the operational amplifier (the process in which the output changes to a stable state when the input changes) should be smooth, that is, the value of the output voltage does not overshoot, which usually requires The phase margin is greater than 60°. This is very difficult for Miller compensated op amps.
  • the present disclosure proposes a drive circuit, a display drive chip, a display device and an electronic device.
  • the drive circuit can meet the requirements of connecting any load capacitance and smoothing the transient response.
  • a driving circuit including a first-stage circuit, a second-stage circuit and an auxiliary circuit.
  • the first-stage circuit is configured to receive a first input signal and a second input signal and amplify them. , obtain a first output signal and a second output signal and output them to the second-stage circuit; the second-stage circuit is used to output a third output signal according to the first output signal and the second output signal. to drive the load; the second-level circuit is also connected to the first-level circuit through a Miller capacitor; the auxiliary circuit is connected to the first-level circuit and the second-level circuit for reducing the first-level circuit. output impedance of the circuit.
  • the auxiliary circuit includes a first resistor and a second resistor, the first output signal is output from the first end of the first-stage circuit, and the second output signal is output from the The second terminal of the first stage circuit outputs, the first resistor is connected between the power supply voltage and the first terminal of the first stage circuit; the second resistor is connected to the second terminal of the first stage circuit. and between the ground.
  • the auxiliary circuit further includes a first transistor and a second transistor, and the first transistor and the first resistor are connected in series between the power supply voltage and the first end of the first-stage circuit.
  • the current flowing through the first resistor also flows through the first pole and the second pole of the first transistor; the gate of the first transistor is connected to the One of the first pole and the second pole of the first transistor is far away from the power supply voltage; the first transistor is used to reduce the current flowing through the first resistor; the second transistor and the second resistor are connected in series.
  • the current flowing through the second resistor also flows through the first pole and the second pole of the second transistor; the gate electrode of the second transistor is connected One of the first pole and the second pole of the second transistor is far away from the ground; the second transistor is used to reduce the current flowing through the second resistor.
  • the auxiliary circuit further includes a third transistor and a fourth transistor, and the third transistor, the first transistor, and the first resistor are connected in series between the power supply voltage and the first stage. Between the first ends of the circuit, the current flowing through the first resistor also flows through the first pole and the second pole of the third transistor, and the gate of the third transistor receives the first bias signal;
  • the third transistor is used to control the maximum value of the current flowing through the first resistor to be less than the current value of the tail current of the first stage circuit;
  • the fourth transistor, the second transistor, and the second resistor is connected in series between the second terminal of the first-stage circuit and ground, and the current flowing through the second resistor also flows through the first and second poles of the fourth transistor.
  • the gate of the fourth transistor The fourth transistor is used to control the maximum value of the current flowing through the second resistor to be less than the current value of the tail current of the first-stage circuit.
  • the first bias signal when the first bias signal causes the third transistor to operate in the linear region, the first output signal decreases and the current flowing through the first resistor increases; When the first output signal decreases to cause the third transistor to operate in the saturation region, the current flowing through the first resistor reaches the maximum value; when the second bias signal causes the fourth transistor to operate in the linear region, When the second output signal increases, the current flowing through the second resistor increases; when the second output signal increases to cause the fourth transistor to operate in the saturation region, the current flowing through the second resistor increases. The current reaches its maximum value.
  • the second-stage circuit includes a fifth transistor and a sixth transistor, the first electrode of the fifth transistor is connected to the power supply voltage, and the second electrode serves as the first electrode of the second-stage circuit. terminal to output the third output signal, and the gate as the second terminal of the second-stage circuit to receive the first output signal; the first terminal of the sixth transistor is connected to the second terminal of the fifth transistor. pole, the second pole is connected to ground, and the gate serves as the third terminal of the second-stage circuit to receive the second output signal; wherein the fifth transistor and the sixth transistor have different polarities, and the The fifth transistor has the same polarity as the first transistor, and the sixth transistor has the same polarity as the second transistor.
  • a display driving chip including a plurality of display units and at least one of the above-mentioned driving circuits.
  • the plurality of display units are connected to the third level of the second-level circuit of the driving circuit. Three ends.
  • a display device including the above-mentioned display driver chip.
  • the display unit includes a display panel
  • the display panel includes a liquid crystal display panel, a micro-light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, or a quantum dot light-emitting diode display panel.
  • an electronic device including the above-mentioned display device.
  • the first input signal and the second input signal are received through the first-level circuit and amplified, and the first output signal and the second output signal are obtained and output to the second-level circuit, thereby realizing the amplification function. , and provides bias for the second-level circuit; through the second-level circuit, the second output signal is output according to the first output signal and the second output signal.
  • the drive circuit of the embodiment of the present disclosure is a Miller compensated drive circuit; through the auxiliary circuit and the first-level circuit and The second-level circuit connection is used to reduce the output impedance of the first-level circuit, so that when the load capacitance changes, the minimum value of the phase margin of the drive circuit increases, achieving smooth transient response, that is, achieving Miller compensation.
  • the drive circuit meets the requirements of connecting any load capacitance and providing smooth transient response.
  • FIG. 1 shows an exemplary block diagram of a prior art two-stage operational amplifier.
  • FIG. 2 shows an exemplary structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 3 shows an exemplary structural schematic diagram of the first-stage circuit 210 according to an embodiment of the present disclosure.
  • FIG. 4 shows an exemplary structural diagram of the second-stage circuit 220 according to an embodiment of the present application.
  • FIG. 5 shows an exemplary structural diagram of the auxiliary circuit 230 according to an embodiment of the present disclosure.
  • FIG. 6 shows another exemplary structural diagram of the auxiliary circuit 230 according to an embodiment of the present disclosure.
  • FIG. 7 shows another exemplary structure diagram of the auxiliary circuit 230 according to an embodiment of the present disclosure.
  • exemplary means "serving as an example, example, or illustrative.” Any embodiment described herein as “exemplary” is not necessarily to be construed as superior or superior to other embodiments.
  • FIG. 1 shows an exemplary block diagram of a prior art two-stage operational amplifier.
  • the amplifier can be divided into an input stage circuit and an output stage circuit.
  • the input stage circuit is used to provide a large voltage gain
  • the output stage circuit is used to provide a large current driving capability for the drive circuit.
  • a Miller capacitor Cm is connected across the input and output ends of the output stage circuit to achieve phase compensation of the operational amplifier pole.
  • VN and VP are the input signals of the two-stage operational amplifier
  • OUT is the output signal of the two-stage operational amplifier
  • VB is the bias voltage
  • AVDD the supply voltage
  • CL is the load capacitance
  • Cm is the Miller capacitance.
  • the specific value of the load capacitance CL in the actual application of the operational amplifier cannot be determined in advance. Therefore, when designing the operational amplifier, it is necessary to consider that the load capacitance can be approximately any value.
  • operational amplifiers are used as gain amplifiers, so the design of the operational amplifier also needs to consider smooth transient response, that is, the output signal does not overshoot (usually requiring a phase margin greater than 60°). This compensates for prior art Miller capacitors It is very difficult for an operational amplifier.
  • the present disclosure proposes a drive circuit, a display drive chip, a display device and an electronic device.
  • the drive circuit can meet the requirements of connecting any load capacitance and has a smooth transient response. needs.
  • FIG. 2 shows an exemplary structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • the driving circuit includes a first-stage circuit 210, a second-stage circuit 220 and an auxiliary circuit 230,
  • the first-stage circuit 210 is configured to receive the first input signal Vin1 and the second input signal Vin2 and amplify them to obtain the first output signal Vout1 and the second output signal Vout2 and output them to the second-stage circuit 220 .
  • the first-stage circuit 210 in the embodiment of the present disclosure may be a voltage gain amplification circuit implemented based on the existing technology.
  • FIG. 3 shows an exemplary structural schematic diagram of a first-stage circuit 210 according to an embodiment of the present disclosure.
  • the circuit 210 includes a differential input unit, a tail current source and a voltage amplification unit.
  • the differential input unit includes P-type transistors T1 and T2.
  • the gates of the transistors T1 and T2 are respectively connected to differential input signals (the first input signal Vin1 and the second input signal Vin1).
  • the sources of transistors T1 and T2 are connected and connected to ground through the tail current source, and the drains of transistors T1 and T2 are connected to the voltage amplification unit to amplify the signal through the current mirror structure formed by the transistors in the voltage amplification unit. Processing, providing the bias voltage (the first output signal Vout1 and the second output signal Vout2) to the second stage circuit 220.
  • the tail current source can be realized by the P-type transistor T3.
  • the gate of the transistor T3 can receive a control signal for controlling the output of the tail current I3.
  • the source can be connected to the ground, and the drain can be connected to the first terminal of the transistor T1 and T2. pole.
  • VDD represents the supply voltage.
  • the first-level circuit 210 may also include more structures that can be implemented with the existing technology, as long as the first input signal Vin1 and The second input signal Vin2 is amplified and the first output signal Vout1 and the second output signal Vout2 are output to provide bias for the second-stage circuit.
  • This disclosure does not limit the specific structure of the first-stage circuit 210.
  • the second-stage circuit 220 is used to output the third output signal Vout3 to drive the load CL according to the first output signal Vout1 and the second output signal Vout2; the second-stage circuit 220 is also connected to the first-stage circuit through Miller capacitors C1 and C2. 210.
  • the second-level circuit 220 may be implemented based on existing technology.
  • FIG. 4 shows an exemplary structural diagram of the second-stage circuit 220 according to an embodiment of the present application.
  • the circuit 220 may include transistors T5 and T6 with different polarities. Taking the transistor T5 as a PMOS transistor and the transistor T6 as an NMOS transistor as an example, the first electrode (source) of the transistor T5 is connected to the power supply voltage, and the gate of the transistor T5 is connected to the power supply voltage. The first electrode (source electrode) of the transistor T6 is connected to the ground, and the gate electrode receives the second output signal Vout2.
  • the second stage (drain) of the transistor T5 is connected to the second stage (drain) of the transistor T6 and serves as the third terminal of the second stage circuit 220.
  • the third terminal is also connected to the load CL, that is, the third output signal Vout3 can as a signal provided to load CL.
  • the second stage (drain) of transistor T5 and the second stage (drain) of transistor T6 are also connected to the first stage circuit 210 through Miller capacitors C1 and C2 respectively to achieve phase compensation of circuit poles.
  • the specific compensation method can be It is implemented based on existing technology and will not be described again here.
  • the auxiliary circuit 230 (including 230a and 230b) is connected to the first-stage circuit 210 and the second-stage circuit 220, and is used to reduce the output impedance of the first-stage circuit 210.
  • the output impedance of the first-stage circuit 210 is related to the phase margin of the drive circuit.
  • the relationship between the two is as follows: during the change of the load capacitance CL, the smaller the output impedance of the first-stage circuit 210, the smaller the phase margin of the drive circuit. The larger the minimum value of the margin.
  • the phase margin is greater than 60%, the transient response of the driving circuit can be considered smooth. Therefore, by reducing the output impedance of the first-stage circuit 210 through the auxiliary circuit 230, the transient response of the driving circuit can be optimized.
  • the first input signal and the second input signal are received through the first-level circuit and amplified, and the first output signal and the second output signal are obtained and output to the second-level circuit, thereby realizing the amplification function.
  • the second-level circuit outputs a third output signal according to the first output signal and the second output signal, which can drive the load;
  • the second-level circuit is also connected to the third-level circuit through a Miller capacitor.
  • the driving circuit of the embodiment of the present disclosure is a Miller compensated driving circuit; it is connected to the first-level circuit and the second-level circuit through an auxiliary circuit, which is used to reduce the output impedance of the first-level circuit and cause the load capacitance to change.
  • the minimum value of the phase margin of the drive circuit increases, achieving smooth transient response. That is, the Miller compensated drive circuit meets the requirement of connecting any load capacitance and smoothing the transient response.
  • the auxiliary circuit 230 in the embodiment of the present disclosure has various structures. Several exemplary structures and advantages of the auxiliary circuit 230 will be introduced below with reference to Figures 5-7.
  • FIG. 5 shows an exemplary structural diagram of the auxiliary circuit 230 according to an embodiment of the present disclosure.
  • the auxiliary circuit 230 includes a first resistor R1 and a second resistor R2, the first output signal Vout1 is output by the first terminal a1 of the first-stage circuit 210, and the second output signal The signal Vout2 is output from the second terminal a2 of the first-stage circuit 210.
  • the first resistor R1 is connected between the power supply voltage VDD and the first terminal a1 of the first-stage circuit 210; the second resistor R2 is connected between the first terminal a2 and the first terminal a2 of the first-stage circuit 210. Between the second end a2 and the ground.
  • the first-stage circuit 210 has two output terminals a1 and a2. Therefore, when designing the auxiliary circuit 230, it is necessary to consider reducing the output impedance of the two output terminals a1 and a2 respectively.
  • the simplest way is to connect the two output terminals a1 and a2 to resistors respectively, that is, as shown in Figure 5, connect the first resistor R1 between the first terminal a1 of the first-stage circuit 210 and the power supply voltage VDD, so that the first resistor R1 Two resistors R2 are connected between the second terminal a2 of the first-stage circuit 210 and the ground GND.
  • the auxiliary circuit 230 may include a first resistor R1 and a second resistor R2.
  • the embodiment of the present disclosure does not limit the resistance values of the first resistor R1 and the second resistor R2.
  • the structure of the auxiliary circuit 230 is relatively simple, easy to implement, and low in cost.
  • the current I2 flowing through the second resistor R2 is based on the threshold voltage of the transistor T6.
  • Transistor T5 and transistor T6 are two transistors of opposite polarity, so the threshold voltages of the two may be inconsistent, which will cause the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 to be unequal.
  • the current difference is large, a relatively large offset voltage will be introduced, reducing the stability of the drive circuit.
  • FIG. 6 shows another exemplary structural diagram of the auxiliary circuit 230 according to an embodiment of the present disclosure.
  • the auxiliary circuit 230 also includes a first transistor M1 and a second transistor M2,
  • the first transistor M1 and the first resistor R1 are connected in series between the power supply voltage VDD and the first terminal a1 of the first stage circuit 210.
  • the current I1 flowing through the first resistor also flows through the first pole m11 and the first pole m11 of the first transistor M1.
  • Diode m12; the gate m13 of the first transistor M1 is connected to one of the first pole m11 and the second pole m12 of the first transistor M1 which is far away from the power supply voltage VDD; the first transistor M1 is used to reduce the current I1 flowing through the first resistor ;
  • the second transistor M2 and the second resistor R2 are connected in series between the second terminal a2 of the first stage circuit 120 and the ground.
  • the current I2 flowing through the second resistor R2 also flows through the first pole m21 and the second pole m21 of the second transistor M2. pole m22; the gate m13 of the second transistor M2 is connected to one of the first pole m21 and the second pole m22 of the second transistor M2 that is far from the ground; the second transistor M2 is used to reduce the current I2 flowing through the second resistor R2.
  • the first transistor M1 may be a P-type transistor
  • the first electrode m11 of the first transistor M1 may be a drain, connected to the first resistor R1
  • the second electrode m12 may be a source, connected to the power supply voltage VDD.
  • the one far away from the power supply voltage VDD can be the first pole m11
  • the first resistor is also connected to the first terminal a1 of the first-stage circuit
  • the second transistor M1 can be an N-type transistor
  • the first pole m21 of the second transistor M2 can be The source electrode is connected to the ground.
  • the second electrode m22 can be the drain electrode, which is connected to the second resistor R2.
  • the one far away from the ground can be the second electrode m22.
  • the second resistor is also connected to the second terminal a2 of the first-stage circuit.
  • the first transistor and the second transistor may also be transistors of other polarities, and this disclosure is not limited thereto.
  • the first resistor can also be connected to the power supply voltage
  • the first transistor can also be connected to the first terminal a1 of the first-stage circuit
  • the second resistor can also be connected to ground
  • the second resistor can also be connected to the ground.
  • the transistor can also be connected to the second terminal a2 of the first-stage circuit, as long as the above-mentioned first transistor M1 and the first resistor R1 are connected in series between the power supply voltage VDD and the first terminal a1 of the first-stage circuit 210, the second transistor M2 and The second resistor R2 is connected in series between the second terminal a2 of the first-stage circuit 120 and the ground.
  • This disclosure provides a specific connection method for the first transistor M1 and the first resistor R1, as well as the second transistor and the second resistor R2.
  • the specific connection method of resistor R2 is not limited.
  • the second-stage circuit includes a fifth transistor T5 and a sixth transistor T6,
  • the first pole of the fifth transistor T5 is connected to the power supply voltage VDD, the second pole serves as the first terminal b1 of the second-stage circuit 220, and outputs the third output signal, and the gate serves as the second terminal b2 of the second-stage circuit 220, receiving the third An output signal Vout1;
  • the first electrode of the sixth transistor T6 is connected to the second electrode a2 of the fifth transistor T5, the second electrode is connected to ground, and the gate is used as the third terminal of the second-stage circuit to receive the second output signal Vout2;
  • the fifth transistor T5 and the sixth transistor T6 have different polarities, the fifth transistor T5 and the first transistor M1 have the same polarity, and the sixth transistor T6 and the second transistor M2 have the same polarity.
  • the fifth transistor is the transistor T5 mentioned above
  • the sixth transistor is the transistor T6 mentioned above
  • the fifth transistor T5 and the sixth transistor T6 are transistors of different polarities
  • the fifth transistor T5 and the sixth transistor T6 are transistors with different polarities.
  • the polarity of one transistor M1 may be the same, and the polarity of the sixth transistor T6 and the second transistor M2 may be the same.
  • the fifth transistor T5 and the first transistor M1 may be P-type transistors
  • the sixth transistor T6 and the second transistor M2 may be P-type transistors.
  • the second transistor M2 may be an N-type transistor.
  • the first transistor M1 can be regarded as a diode when connected in the manner shown in Figure 6.
  • the first transistor M1 is a P-type transistor
  • its threshold voltage is the same as that of the fifth transistor T5 (the threshold voltages of transistors with the same polarity are also the same).
  • one of the first pole m11 and the second pole m12 of the first transistor M1 close to the power supply voltage VDD (in the example of FIG. 6 is the second pole m12) serves as the cathode of the diode, and the other pole (in the example of FIG.
  • the first pole m11 as the anode of the diode
  • the first transistor M1 serves as a diode and is connected in reverse in the circuit
  • the first transistor M1 is connected in series with the first resistor R1
  • the first transistor M1 flows through the first resistor R1
  • the current I1 of The threshold voltage of the transistor is also the same
  • the first pole m21 and the second pole m22 of the second transistor M2 One pole far away from the ground serves as the anode of the diode, and the other pole serves as the cathode of the diode, that is, the second transistor M2 serves as a diode and is connected in reverse in the circuit, and the second transistor M2 is connected in series with the second resistor R2, so in this case , the current I2 flowing through the second resistor R2 is also very small.
  • the driver The offset voltage of the circuit can be reduced to a very low level, thereby improving the stability of the drive circuit.
  • the circuit shown in Figure 6 is more suitable for drive circuits with large quiescent current. If the application scenario requires a micro-power drive circuit, the tail current I3 in the first-stage circuit needs to be designed to be relatively small, then Figure 6 The circuit will cause the voltage conversion rate (slew rate) of the drive circuit to become smaller. The reason is that when the driving circuit changes the voltage, if you want to make the output voltage (third output signal Vout3) higher, then you must make the first output signal Vout1 lower (or make the second output signal Vout2 higher).
  • FIG. 7 shows another exemplary structure diagram of the auxiliary circuit 230 according to an embodiment of the present disclosure.
  • the auxiliary circuit 230 also includes a third transistor M3 and a fourth transistor M4,
  • the third transistor M3 is connected in series with the first transistor M1 and the first resistor R1 between the power supply voltage VDD and the first terminal a1 of the first stage circuit 210.
  • the current flowing through the first resistor R1 also flows through the third transistor M3.
  • the first pole m31 and the second pole m32, the gate m33 of the third transistor M3 receives the first bias signal VBP; the third transistor M3 is used to control the maximum value of the current I1 flowing through the first resistor R1 to be smaller than the first stage circuit 210 The current value of the tail current I3;
  • the fourth transistor M4, the second transistor, and the second resistor R2 are connected in series between the second terminal a2 of the first-stage circuit 210 and the ground.
  • the current I2 flowing through the second resistor R2 also flows through the third terminal of the fourth transistor M4.
  • One pole m41 and a second pole m42, the gate of the fourth transistor M4 receives the second bias signal VBN; the fourth transistor M4 is used to control the maximum value of the current I2 flowing through the second resistor R2 to be smaller than the first stage circuit The current value of the tail current I3 of 210.
  • the first transistor M1 may be a P-type transistor
  • the first electrode m11 of the first transistor M1 may be a drain, connected to the first resistor R1
  • the second electrode m12 may be a source, connected to the third transistor.
  • the first electrode m31 of M3; the third transistor M3 may be a P-type transistor; the first electrode m31 of the third transistor M3 may be a drain electrode; the second electrode m32 may be a source electrode, connected to the power supply voltage VDD.
  • the second transistor M1 may be an N-type transistor, the first electrode m21 of the second transistor M2 may be the source electrode, connected to the second electrode m42 of the four-transistor M4, and the second electrode m22 may be the drain electrode, connected to the second resistor R2;
  • the fourth transistor M4 may be an N-type transistor, the first electrode m41 of the fourth transistor M4 may be a source electrode, connected to ground, and the second electrode m42 may be a drain electrode.
  • the first transistor, the second transistor, the third transistor and the fourth transistor may also be transistors of other polarities, and the disclosure is not limited thereto.
  • the first resistor can also be connected in series between the first transistor and the third transistor
  • the second resistor can also be connected in series between the fourth transistor and the second transistor, etc.
  • the connection method between the two terminals a2 and ground is sufficient.
  • This disclosure provides specific connection methods between the third transistor M3, the first transistor M1, and the first resistor R1, as well as the fourth transistor M4, the second transistor, and the second resistor R2. The specific connection method is not limited.
  • the first output signal Vout1 decreases and the current I1 flowing through the first resistor R1 increases;
  • the first bias signal VBP and the second bias signal VBN may be set to fixed values, generated by a prior art bias circuit (not shown) capable of stably outputting a bias voltage and provided to the auxiliary circuit 230 (Including 230a and 230b).
  • the third transistor M3 and the fourth transistor M4 are respectively pressed into the deep linear region by the first bias signal VBP and the second bias signal VBN.
  • the current I1 flowing through the first resistor R1 and the current I1 flowing through the first resistor R1 The current I2 of the two resistors R2 is very small and will not cause the drive circuit to introduce an offset voltage; when the drive circuit needs to perform voltage conversion, taking the first output signal Vout1 as an example, the voltage value of the first output signal Vout1 decreases and flows through the first output signal Vout1.
  • the current I1 of the resistor R1 will increase; but when the voltage value of the first output signal Vout1 drops to a certain value, the third transistor M3 enters the saturation region, and the current I1 flowing through the first resistor R1 will no longer increase.
  • the current I1 flowing through the first resistor R1 reaches the maximum value at this time; as long as the maximum value is less than the tail current I3 of the first-stage circuit 210, the voltage value of the first output signal Vout1 can continue to decrease and will not This introduces the problem that the voltage conversion rate of the drive circuit becomes smaller.
  • the second output signal Vout2 when the voltage value of the second output signal Vout2 rises, the current I2 flowing through the second resistor R2 will increase; but when the voltage value of the second output signal Vout2 rises to a certain value, , the fourth transistor M4 enters the saturation region. At this time, the current I2 flowing through the second resistor R2 will no longer increase, that is, the current I2 flowing through the second resistor R2 reaches the maximum value at this time; as long as the maximum value is less than the If the tail current I3 of the primary circuit 210 is reduced, the voltage value of the second output signal Vout2 can continue to decrease, without causing the problem of the voltage conversion rate of the driving circuit becoming smaller.
  • auxiliary circuit 230 may also include more structures, as long as the output impedance of the first-stage circuit 210 can be reduced.
  • This disclosure The specific structure of the auxiliary circuit 230 is not limited.
  • the present disclosure also provides a display driving chip, which includes a plurality of display units and at least one of the above-mentioned driving circuits.
  • the plurality of display units are connected to the third end of the second-stage circuit 220 of the driving circuit.
  • the third end of the second-stage circuit 220 may be the end of the second-stage circuit 220 connected to the load, that is, the end where the third output signal Vout3 is output.
  • the multiple display units are the loads mentioned above, and their capacitance values are the load capacitance of the driving circuit.
  • the present disclosure also provides a display device, which includes the above-mentioned display driver chip.
  • the display driver chip according to the embodiment of the present invention can be formed as a universal driver chip and can be applied to display panels with different sub-pixel arrangements, thereby reducing design costs and manufacturing costs.
  • the display unit includes a display panel
  • the display panel includes a liquid crystal display display panel, micro-LED display panel, LED display panel, mini LED display panel, quantum dot LED display panel, organic LED display panel, cathode ray tube display panel, digital light processing display panel, field emission display panel, At least one of a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small-pitch display panel.
  • the present disclosure also provides an electronic device, including the above-mentioned display device.
  • the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be connected in cascade to achieve driving. .
  • the electronic device can also be user equipment (User Equipment, UE), mobile device, user terminal, terminal, handheld device, computing device or vehicle-mounted device, etc.
  • terminals are: monitors, smart phones. Or portable devices, mobile phones (Mobile Phone), tablets, laptops, handheld computers, mobile Internet devices (Mobile Internet devices, MID), wearable devices, virtual reality (Virtual Reality, VR) devices, augmented reality (Augmentedreality, AR) Equipment, wireless terminals in Industrial Control, wireless terminals in Self-driving, wireless terminals in Remote Medical Surgery, wireless terminals in Smart Grid, transportation security ( Wireless terminals in Transportation Safety, wireless terminals in Smart City, wireless terminals in Smart Home, wireless terminals in the Internet of Vehicles, etc.
  • the server can be a local server or a cloud server.

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Abstract

本公开涉及一种驱动电路、显示驱动芯片、显示设备及电子设备，驱动电路包括第一级电路、第二级电路和辅助电路，第一级电路用于接收第一输入信号和第二输入信号并进行放大，得到第一输出信号和第二输出信号并输出至第二级电路；第二级电路用于，根据第一输出信号和第二输出信号输出第三输出信号以驱动负载；第二级电路还通过米勒电容连接第一级电路；辅助电路与第一级电路和第二级电路连接，用于降低第一级电路的输出阻抗。该驱动电路作为米勒补偿的驱动电路，能够满足连接任意的负载电容、且瞬态响应平滑的需求。

Description

驱动电路、显示驱动芯片、显示设备及电子设备
本申请要求于2022年7月12日提交中国专利局、申请号为202210821620.6、申请名称为“驱动电路、显示驱动芯片、显示设备及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及集成电路领域，尤其涉及一种驱动电路、显示驱动芯片、显示设备及电子设备。
背景技术
运算放大器是具有很高放大倍数的电路单元。其在集成电路领域应用很广泛，因此在设计上需考虑不同的应用场景下可能出现的问题。一个常见的问题是，运算放大器的负载电容是不确定的。例如，在驱动电路中使用运算放大器用于驱动LED显示时，能够驱动很多LED，而LED的个数又是由用户决定的，因此在设计运算放大器时，需要考虑该运算放大器的负载电容近似可以是任意值；同时，在一些应用场景中，运算放大器可被用作增益放大器使用。增益放大器要求输出和输入具有一定的放大倍数，因此另一个问题是运算放大器的瞬态响应(输入变化时输出变化至稳定状态的过程)应该平滑，即输出电压的数值没有过冲，这通常要求相位裕度大于60°。这对于米勒补偿的运算放大器来说，是非常困难的事情。
因此，设计一种能够满足上述需求的米勒补偿的驱动电路，成为本领域的研究热点。
发明内容
有鉴于此，本公开提出了一种驱动电路、显示驱动芯片、显示设备及电子设备，该驱动电路作为米勒补偿的驱动电路，能够满足连接任意的负载电容、且瞬态响应平滑的需求。
根据本公开的一方面，提供了一种驱动电路，包括第一级电路、第二级电路和辅助电路，所述第一级电路用于，接收第一输入信号和第二输入信号并进行放大，得到第一输出信号和第二输出信号并输出至所述第二级电路；所述第二级电路用于，根据所述第一输出信号和所述第二输出信号，输出第三输出信号以驱动负载；所述第二级电路还通过米勒电容连接所述第一级电路；所述辅助电路与所述第一级电路和所述第二级电路连接，用于降低所述第一级电路的输出阻抗。
在一种可能的实现方式中，所述辅助电路包括第一电阻和第二电阻，所述第一输出信号由所述第一级电路的第一端输出，所述第二输出信号由所述第一级电路的第二端输出，所述第一电阻连接在电源电压与所述第一级电路的第一端之间；所述第二电阻连接在所述第一级电路的第二端和地之间。
在一种可能的实现方式中，所述辅助电路还包括第一晶体管和第二晶体管，所述第一晶体管和所述第一电阻串联在电源电压与所述第一级电路的第一端之间，流过所述第一电阻的电流也流过所述第一晶体管的第一极和第二极；所述第一晶体管的栅极连接所 述第一晶体管的第一极和第二极中远离电源电压的一个；所述第一晶体管用于降低流过所述第一电阻的电流；所述第二晶体管和所述第二电阻串联在所述第一级电路的第二端和地之间，流过所述第二电阻的电流也流过所述第二晶体管的第一极和第二极；所述第二晶体管的栅极连接所述第二晶体管的第一极和第二极中远离地的一个；所述第二晶体管用于降低流过所述第二电阻的电流。
在一种可能的实现方式中，所述辅助电路还包括第三晶体管和第四晶体管，所述第三晶体管和所述第一晶体管、所述第一电阻串联在电源电压与所述第一级电路的第一端之间，流过所述第一电阻的电流也流过所述第三晶体管的第一极和第二极，所述第三晶体管的栅极接收第一偏置信号；所述第三晶体管用于控制流过所述第一电阻的电流的最大值小于所述第一级电路的尾电流的电流值；所述第四晶体管和所述第二晶体管、所述第二电阻串联在所述第一级电路的第二端和地之间，流过所述第二电阻的电流也流过所述第四晶体管的第一极和第二极，所述第四晶体管的栅极接收第二偏置信号；所述第四晶体管用于控制流过所述第二电阻的电流的最大值小于所述第一级电路的尾电流的电流值。
在一种可能的实现方式中，所述第一偏置信号使所述第三晶体管工作于线性区时，所述第一输出信号降低，流过所述第一电阻的电流增大；所述第一输出信号降低至使所述第三晶体管工作于饱和区时，流过所述第一电阻的电流达到最大值；所述第二偏置信号使所述第四晶体管工作于线性区时，所述第二输出信号升高，流过所述第二电阻的电流增大；所述第二输出信号升高至使所述第四晶体管工作于饱和区时，流过所述第二电阻的电流达到最大值。
在一种可能的实现方式中，所述第二级电路包括第五晶体管和第六晶体管，所述第五晶体管的第一极连接电源电压，第二极作为所述第二级电路的第一端，输出所述第三输出信号，栅极作为所述第二级电路的第二端，接收所述第一输出信号；所述第六晶体管的第一极连接所述第五晶体管的第二极，第二极连接地，栅极作为所述第二级电路的第三端，接收所述第二输出信号；其中，所述第五晶体管与所述第六晶体管的极性不同，所述第五晶体管与所述第一晶体管的极性相同，所述第六晶体管与所述第二晶体管的极性相同。
根据本公开的另一方面，提供了一种显示驱动芯片，包括多个显示单元及至少一个以上所述的驱动电路，所述多个显示单元连接在所述驱动电路的第二级电路的第三端。
根据本公开的另一方面，提供了一种显示设备，包括以上所述的显示驱动芯片。
在一种可能的实现方式中，所述显示单元包括显示面板，所述显示面板包括液晶显示面板、微发光二极管显示面板、发光二极管显示面板、迷你发光二极管显示面板、量子点发光二极管显示面板、有机发光二极管显示面板、阴极射线管显示面板、数字光处理显示面板、场发射显示面板、电浆显示面板、电泳显示面板、电润湿显示面板以及小间距显示面板中至少一种。
根据本公开的另一方面，提供了一种电子设备，包括以上所述的显示设备。
根据本公开实施例的驱动电路，通过第一级电路接收第一输入信号和第二输入信号并进行放大，得到第一输出信号和第二输出信号并输出至第二级电路，可实现放大功能，并为第二级电路提供偏置；通过第二级电路根据第一输出信号和第二输出信号，输出第 三输出信号，可驱动负载；第二级电路还通过米勒电容连接所述第一级电路；因此本公开实施例的驱动电路是米勒补偿的驱动电路；通过辅助电路与第一级电路和第二级电路连接，用于降低第一级电路的输出阻抗，使得负载电容变化的过程中，驱动电路的相位裕度的最小值增大，实现瞬态响应平滑，即实现了米勒补偿的驱动电路满足连接任意的负载电容、且瞬态响应平滑的需求。
根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本公开的示例性实施例、特征和方面，并且用于解释本公开的原理。
图1示出现有技术的两级运算放大器的示例性结构图。
图2示出根据本公开实施例的驱动电路的示例性结构图。
图3示出根据本公开实施例的第一级电路210的示例性结构示意图。
图4示出根据本申请实施例的第二级电路220的示例性结构图。
图5示出根据本公开实施例的辅助电路230的一种示例性结构图。
图6示出根据本公开实施例的辅助电路230的另一种示例性结构图。
图7示出根据本公开实施例的辅助电路230的另一种示例性结构图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
图1示出现有技术的两级运算放大器的示例性结构图。
如图1所示，该放大器可以分为输入级电路和输出级电路，输入级电路用于提供很大的电压增益，输出级电路用于为驱动电路提供大的电流驱动能力。输出级电路的输入端和输出端之间跨接一个米勒电容Cm，用于实现运算放大器极点的相位补偿。其中VN和VP是该两级运算放大器的输入信号，OUT是该两级运算放大器的输出信号，VB是偏置电压，AVDD是电源电压，CL是负载电容，Cm是米勒电容。
在设计运算放大器时，对于该运算放大器实际应用中的负载电容CL的具体数值是不能够事先确定的。因此运算放大器在设计时需考虑负载电容近似可以是任意值。在一些场景中运算放大器作为增益放大器使用，因此运算放大器的设计还需考虑瞬态响应平滑，即输出信号没有过冲(通常要求相位裕度大于60°)。这对于现有技术的米勒电容做补偿 的运算放大器来说，是非常困难的事情。
为了解决这一技术问题，本公开提出了一种驱动电路、显示驱动芯片、显示设备及电子设备，该驱动电路作为米勒补偿的驱动电路，能够满足连接任意的负载电容、且瞬态响应平滑的需求。
图2示出根据本公开实施例的驱动电路的示例性结构图。
如图2所示，在一种可能的实现方式中，驱动电路包括第一级电路210、第二级电路220和辅助电路230，
第一级电路210用于，接收第一输入信号Vin1和第二输入信号Vin2并进行放大，得到第一输出信号Vout1和第二输出信号Vout2并输出至第二级电路220。
本公开实施例的第一级电路210可以是基于现有技术实现的电压增益放大电路。图3示出根据本公开实施例的第一级电路210的示例性结构示意图。该电路210包括差分输入单元、尾电流源和电压放大单元，差分输入单元包括P型晶体管T1、T2，晶体管T1、T2的栅极分别接入差分输入信号(第一输入信号Vin1和第二输入信号Vin2)，晶体管T1、T2的源极相连接并通过尾电流源连接到地，晶体管T1、T2的漏极连接电压放大单元，以通过电压放大单元中由晶体管形成的电流镜结构进行信号放大处理，向第二级电路220提供偏置电压(第一输出信号Vout1和第二输出信号Vout2)。其中，尾电流源可通过P型晶体管T3来实现，该晶体管T3的栅极可接收控制信号，用于控制尾电流I3的输出，源极可连接地，漏极连接晶体管T1、T2的第一极。VDD表示电源电压。
本领域人员应理解，图3中的结构仅为第一级电路210的一个示例，第一级电路210还可以包括更多的现有技术可实现的结构，只要能够实现第一输入信号Vin1和第二输入信号Vin2的放大，输出第一输出信号Vout1和第二输出信号Vout2，以为第二级电路提供偏置即可，本公开对于第一级电路210的具体结构不做限制。
第二级电路220用于，根据第一输出信号Vout1和第二输出信号Vout2，输出第三输出信号Vout3以驱动负载CL；第二级电路220还通过米勒电容C1、C2连接第一级电路210。
第二级电路220可以是基于现有技术实现。图4示出根据本申请实施例的第二级电路220的示例性结构图。如图4所示，该电路220可包括异极性的晶体管T5、T6，以晶体管T5为PMOS晶体管、晶体管T6为NMOS晶体管为例，晶体管T5的第一极(源极)连接电源电压，栅极接收第一输出信号Vout1，晶体管T6的第一极(源极)连接地，栅极接收第二输出信号Vout2。晶体管T5的第二级(漏极)和晶体管T6的第二极(漏极)相连接并作为第二级电路220的第三端，第三端还连接负载CL，即第三输出信号Vout3可作为提供给负载CL的信号。晶体管T5的第二级(漏极)和晶体管T6的第二极(漏极)还分别通过米勒电容C1和C2连接第一级电路210，以实现电路极点的相位补偿，其具体补偿方式可以基于现有技术来实现，在此不再赘述。
辅助电路230(包括230a和230b)与第一级电路210和第二级电路220连接，用于降低第一级电路210的输出阻抗。
第一级电路210的输出阻抗，与驱动电路的相位裕度相关联，二者的关联关系如下：在负载电容CL变化的过程中，第一级电路210的输出阻抗越小，驱动电路的相位裕度的最小值越大。而相位裕度大于60％时可认为驱动电路的瞬态响应平滑，因此，通过辅助电路230降低第一级电路210的输出阻抗，可实现优化驱动电路的瞬态响应。
根据本公开实施例的驱动电路，通过第一级电路接收第一输入信号和第二输入信号并进行放大，得到第一输出信号和第二输出信号并输出至第二级电路，可实现放大功能，并为第二级电路提供偏置；通过第二级电路根据第一输出信号和第二输出信号，输出第三输出信号，可驱动负载；第二级电路还通过米勒电容连接所述第一级电路；因此本公开实施例的驱动电路是米勒补偿的驱动电路；通过辅助电路与第一级电路和第二级电路连接，用于降低第一级电路的输出阻抗，使得负载电容变化的过程中，驱动电路的相位裕度的最小值增大，实现瞬态响应平滑，即实现了米勒补偿的驱动电路满足连接任意的负载电容、且瞬态响应平滑的需求。
本公开实施例中的辅助电路230有多种结构。下面结合图5-7分别介绍几种辅助电路230示例性结构及其优点。
图5示出根据本公开实施例的辅助电路230的一种示例性结构图。
如图5所示，在一种可能的实现方式中，辅助电路230包括第一电阻R1和第二电阻R2，第一输出信号Vout1由第一级电路210的第一端a1输出，第二输出信号Vout2由第一级电路210的第二端a2输出，第一电阻R1连接在电源电压VDD与第一级电路210的第一端a1之间；第二电阻R2连接在第一级电路210的第二端a2和地之间。
举例来说，由图3和图4可知，第一级电路210有两个输出端a1和a2，因此在设计辅助电路230时，需要考虑分别降低两个输出端a1和a2的输出阻抗。最简单的方式是使两个输出端a1和a2分别连接电阻，即如图5所示，使第一电阻R1连接在第一级电路210的第一端a1与电源电压VDD之间，使第二电阻R2连接在第一级电路210的第二端a2和地GND之间。则辅助电路230(包括230a和230b)可包括第一电阻R1和第二电阻R2。本公开实施例对于第一电阻R1和第二电阻R2的阻值不作限制。在此情况下，辅助电路230的结构比较简单，易于实现且成本较低。
然而，图5所示的电路中，由于辅助电路230(包括230a和230b)中第一电阻R1和第二电阻R2的存在，会有电流流过第一电阻R1和第二电阻R2。且对于晶体管T5而言，其栅源电压与其阈值电压有关，源极电压是电源电压VDD为定值，因此晶体管T5的栅极电压与其阈值电压有关；流过第一电阻R1的电流I1应该等于电源电压VDD与晶体管T5的栅极电压之差与第一电阻R1阻值的比值，所以可认为流过第一电阻R1的电流I1以晶体管T5的阈值电压作为基准。同理，可认为流过第二电阻R2的电流I2以晶体管T6的阈值电压作为基准。晶体管T5和晶体管T6是异极性的两个晶体管，因此二者的阈值电压可能不一致，会造成流过第一电阻R1的电流I1和流过第二电阻R2的电流I2不相等，这两个电流差值较大时会引入比较大的失调电压，降低驱动电路的稳定性。
因此，本公开提出辅助电路230的另一种设计方式。图6示出根据本公开实施例的辅助电路230的另一种示例性结构图。
如图6所示，在一种可能的实现方式中，辅助电路230还包括第一晶体管M1和第二晶体管M2，
第一晶体管M1和第一电阻R1串联在电源电压VDD与第一级电路210的第一端a1之间，流过第一电阻的电流I1也流过第一晶体管M1的第一极m11和第二极m12；第一晶体管M1的栅极m13连接第一晶体管M1的第一极m11和第二极m12中远离电源电压VDD的一个；第一晶体管M1用于降低流过第一电阻的电流I1；
第二晶体管M2和第二电阻R2串联在第一级电路120的第二端a2和地之间，流过第二电阻R2的电流I2也流过第二晶体管M2的第一极m21和第二极m22；第二晶体管M2的栅极m13连接第二晶体管M2的第一极m21和第二极m22中远离地的一个；第二晶体管M2用于降低流过第二电阻R2的电流I2。
在图6的示例中，第一晶体管M1可以是P型晶体管，第一晶体管M1的第一极m11可以是漏极，连接第一电阻R1，第二极m12可以是源极，连接电源电压VDD，远离电源电压VDD的一个可以是第一极m11，第一电阻还连接第一级电路的第一端a1；第二晶体管M1可以是N型晶体管，第二晶体管M2的第一极m21可以是源极，连接地，第二极m22可以是漏极，连接第二电阻R2，远离地的一个可以是第二极m22，第二电阻还连接第一级电路的第二端a2。本领域技术人员应理解，第一晶体管和第二晶体管也可以是其他极性的晶体管，本公开对此不作限制。
可以理解的是，除图6中的连接方式之外，第一电阻也可以连接电源电压、第一晶体管也可以连接第一级电路的第一端a1，第二电阻也可以连接地，第二晶体管也可以连接第一级电路的第二端a2，只要满足上述第一晶体管M1和第一电阻R1串联在电源电压VDD与第一级电路210的第一端a1之间，第二晶体管M2和第二电阻R2串联在第一级电路120的第二端a2和地之间的连接方式即可，本公开对于第一晶体管M1、第一电阻R1的具体连接方式，以及第二晶体管、第二电阻R2的具体连接方式不作限制。
下面结合第二级电路的结构介绍图6所示的辅助电路降低流过第一电阻的电流以及流过第二电阻的电流的原理。
在一种可能的实现方式中，第二级电路包括第五晶体管T5和第六晶体管T6，
第五晶体管T5的第一极连接电源电压VDD，第二极作为第二级电路220的第一端b1，输出第三输出信号，栅极作为第二级电路220的第二端b2，接收第一输出信号Vout1；
第六晶体管T6的第一极连接第五晶体管T5的第二极a2，第二极连接地，栅极作为第二级电路的第三端，接收第二输出信号Vout2；
其中，第五晶体管T5与第六晶体管T6的极性不同，第五晶体管T5与第一晶体管M1的极性相同，第六晶体管T6与第二晶体管M2的极性相同。
举例来说，第五晶体管即上文所述的晶体管T5，第六晶体管即上文所述的晶体管T6，第五晶体管T5与第六晶体管T6是不同极性的晶体管，第五晶体管T5与第一晶体管M1的极性可以相同，第六晶体管T6与第二晶体管M2的极性可以相同，例如本公开实施例中第五晶体管T5与第一晶体管M1可以是P型晶体管，第六晶体管T6与第二晶体管M2可以是N型晶体管。
其中，第一晶体管M1以图6所示的方式连接时可看作二极管，第一晶体管M1是P型晶体管时，其阈值电压与第五晶体管T5一样(极性相同的晶体管阈值电压也相同)，第一晶体管M1的第一极m11和第二极m12中靠近电源电压VDD的一极(在图6的示例中为第二极m12)作为二极管的负极，另一极(在图6的示例中为第一极m11)作为二极管的正极，即第一晶体管M1作为二极管且反接在电路中，且第一晶体管M1串接第一电阻R1，因此在此情况下，流过第一电阻R1的电流I1非常小；同理，第二晶体管M2以图6所示的方式连接时可看作二极管，第二晶体管M2是N型晶体管时，其阈值电压与第六晶体管M6一样(极性相同的晶体管阈值电压也相同)，第二晶体管M2的第一极m21和第二极m22 中远离地的一极作为二极管的正极，另一极作为二极管的负极，即第二晶体管M2作为二极管且反接在电路中，且第二晶体管M2串接第二电阻R2，因此在此情况下，流过第二电阻R2的电流I2也非常小。由于流过第一电阻R1的电流I1和流过第二电阻R2的电流I2都很小，因此即便I1和I2不相等，二者的差值也不会很大，在这种情况下，驱动电路的失调电压可以被降至很低，从而能提驱动电路的稳定性。
然而，图6所示的电路更适用于静态电流大的驱动电路，如果应用场景需求微功耗的驱动电路，则需要使得第一级电路中的尾电流I3设计的比较小，那么图6的电路会导致驱动电路的电压变换速率(压摆率)变小。原因在于，驱动电路进行电压变化时，若想使得输出电压(第三输出信号Vout3)变高，那么必然需要使得第一输出信号Vout1数值变低(或使得第二输出信号Vout2数值变高)，在图6的电路中是通过把尾电流I3全部镜像过去，以把第一输出信号Vout1拉低(或把第二输出信号Vout2拉高)，但是在拉低第一输出信号Vout1(或拉高第二输出信号Vout2)的时候，流过第一电阻R1的电流I1(或流过第二电阻R2的电流I2)会变大，当流过第一电阻的电流I1(或流过第二电阻R2的电流I2)变大到和尾电流I3一样大的时候，第一输出信号Vout2就不会再被拉低(或第二输出信号Vout2就不会再被拉高)，最终导致驱动电路的电压变换速率变小。
因此，本公开提出辅助电路的另一种设计方式。图7示出根据本公开实施例的辅助电路230的另一种示例性结构图。
如图7所示，在一种可能的实现方式中，辅助电路230还包括第三晶体管M3和第四晶体管M4，
第三晶体管M3和第一晶体管M1、第一电阻R1串联在电源电压VDD与第一级电路210的第一端a1之间，流过第一电阻R1的电流也流过第三晶体管M3的第一极m31和第二极m32，第三晶体管M3的栅极m33接收第一偏置信号VBP；第三晶体管M3用于控制流过第一电阻R1的电流I1的最大值小于第一级电路210的尾电流I3的电流值；
第四晶体管M4和第二晶体管、第二电阻R2串联在所述第一级电路210的第二端a2和地之间，流过第二电阻R2的电流I2也流过第四晶体管M4的第一极m41和第二极m42，所述第四晶体管M4的栅极接收第二偏置信号VBN；第四晶体管M4用于控制流过第二电阻R2的电流I2的最大值小于第一级电路210的尾电流I3的电流值。
在图7的示例中，第一晶体管M1可以是P型晶体管，第一晶体管M1的第一极m11可以是漏极，连接第一电阻R1，第二极m12可以是源极，连接第三晶体管M3的第一极m31；第三晶体管M3可以是P型晶体管，第三晶体管M3的第一极m31可以是漏极，第二极m32可以是源极，连接电源电压VDD。第二晶体管M1可以是N型晶体管，第二晶体管M2的第一极m21可以是源极，连接四晶体管M4的第二极m42，第二极m22可以是漏极，连接第二电阻R2；第四晶体管M4可以是N型晶体管，第四晶体管M4的第一极m41可以是源极，连接地，第二极m42可以是漏极。本领域技术人员应理解，第一晶体管、第二晶体管、第三晶体管和第四晶体管也可以是其他极性的晶体管，本公开对此不作限制。
可以理解的是，除图7中的连接方式之外，第一电阻也可以串联在第一晶体管和第三晶体管之间，第二电阻也可以串联在第四晶体管和第二晶体管之间等等，只要满足上述第三晶体管M3和第一晶体管M1、第一电阻R1串联在电源电压VDD与第一级电路210的第一端a1之间，第四晶体管M4和第二晶体管、第二电阻R2串联在所述第一级电路210的第 二端a2和地之间的连接方式即可，本公开对于第三晶体管M3和第一晶体管M1、第一电阻R1的具体连接方式，以及第四晶体管M4和第二晶体管、第二电阻R2的具体连接方式不作限制。
下面结合图7介绍第三晶体管M3和第四晶体管M4控制流过第一电阻R1的电流I1和流过第二电阻R2的电流I2的示例性方式。
在一种可能的实现方式中，第一偏置信号VBP使第三晶体管M3工作于线性区时，第一输出信号Vout1降低，流过第一电阻R1的电流I1增大；
第一输出信号Vout1降低至使第三晶体管M3工作于饱和区时，流过第一电阻R1的电流I1达到最大值；
第二偏置信号VBN使第四晶体管M4工作于线性区时，第二输出信号Vout2升高，流过第二电阻R2的电流I2增大；
第二输出信号Vout2升高至使第四晶体管M4工作于饱和区时，流过第二电阻R2的电流I2达到最大值。
举例来说，第一偏置信号VBP和第二偏置信号VBN可以设置为固定值，通过现有技术的能够稳定输出偏置电压的偏置电路(未示出)产生并提供给辅助电路230(包括230a和230b)。在正常状态下，第三晶体管M3和第四晶体管M4分别被第一偏置信号VBP和第二偏置信号VBN压入深度线性区，此时流过第一电阻R1的电流I1和流过第二电阻R2的电流I2很小，不会使驱动电路引入失调电压；当驱动电路需进行电压变换时，以第一输出信号Vout1为例，第一输出信号Vout1的电压值下降，流过第一电阻R1的电流I1会增大；但是当第一输出信号Vout1的电压值下降到一定值的时候，第三晶体管M3进入饱和区，此时流过第一电阻R1的电流I1就不会再增大，也即此时流过第一电阻R1的电流I1达到最大值；只要该最大值小于第一级电路210的尾电流I3，那么第一输出信号Vout1的电压值就可以继续下降，不会引入驱动电路的电压变换速率变小的问题。
同理，以第二输出信号Vout2为例，第二输出信号Vout2电压值上升，流过第二电阻R2的电流I2会增大；但是当第二输出信号Vout2的电压值上升到一定值的时候，第四晶体管M4进入饱和区，此时流过第二电阻R2的电流I2就不会再增大，也即此时流过第二电阻R2的电流I2达到最大值；只要该最大值小于第一级电路210的尾电流I3，那么第二输出信号Vout2的电压值就可以继续下降，不会引入驱动电路的电压变换速率变小的问题。
本领域人员应理解，图5-7中的结构仅为辅助电路230的示例，辅助电路230还可以包括更多的结构，只要能够实现减小第一级电路210的输出阻抗即可，本公开对于辅助电路230的具体结构不做限制。
本公开还提供一种显示驱动芯片，包括多个显示单元及至少一个以上所述的驱动电路，所述多个显示单元连接在所述驱动电路的第二级电路220的第三端。其中第二级电路220的第三端可以是第二级电路220与负载相连接的一端，也即第三输出信号Vout3输出的一端。多个显示单元即为上文中所述的负载，其电容值即为驱动电路的负载电容。
本公开还提供一种显示设备，其包括以上所述的显示驱动芯片。根据本发明实施例的显示驱动芯片可以形成为通用驱动芯片，可以适用于不同子像素排列的显示面板，从而可以降低设计成本和制造成本。
在一种可能的实现方式中，所述显示单元包括显示面板，所述显示面板包括液晶显 示面板、微发光二极管显示面板、发光二极管显示面板、迷你发光二极管显示面板、量子点发光二极管显示面板、有机发光二极管显示面板、阴极射线管显示面板、数字光处理显示面板、场发射显示面板、电浆显示面板、电泳显示面板、电润湿显示面板以及小间距显示面板中至少一种。
本公开还提供一种电子设备，包括以上所述的显示设备。
示例性地，本实施例中的电子设备包括但不限于台式电脑、电视机、具有大尺寸屏幕的移动设备如手机、平板电脑等其他常见的需要多个芯片级联连接来实现驱动的电子设备。
示例性的，电子设备还可以是用户设备(User Equipment，UE)、移动设备、用户终端、终端、手持设备、计算设备或者车载设备等，示例性的，一些终端的举例为：显示器、智能手机或便携设备、手机(Mobile Phone)、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(Mobile Internetdevice，MID)、可穿戴设备，虚拟现实(Virtual Reality，VR)设备、增强现实(Augmentedreality，AR)设备、工业控制(Industrial Control)中的无线终端、无人驾驶(Selfdriving)中的无线终端、远程手术(Remote medical Surgery)中的无线终端、智能电网(Smart Grid)中的无线终端、运输安全(Transportation Safety)中的无线终端、智慧城市(Smart City)中的无线终端、智慧家庭(Smart Home)中的无线终端、车联网中的无线终端等。例如，服务器可以是本地服务器，也可以是云服务器。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (10)

  1. 一种驱动电路，其特征在于，包括第一级电路、第二级电路和辅助电路，
    所述第一级电路用于，接收第一输入信号和第二输入信号并进行放大，得到第一输出信号和第二输出信号并输出至所述第二级电路；
    所述第二级电路用于，根据所述第一输出信号和所述第二输出信号，输出第三输出信号以驱动负载；所述第二级电路还通过米勒电容连接所述第一级电路；
    所述辅助电路与所述第一级电路和所述第二级电路连接，用于降低所述第一级电路的输出阻抗。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述辅助电路包括第一电阻和第二电阻，所述第一输出信号由所述第一级电路的第一端输出，所述第二输出信号由所述第一级电路的第二端输出，
    所述第一电阻连接在电源电压与所述第一级电路的第一端之间；
    所述第二电阻连接在所述第一级电路的第二端和地之间。
  3. 根据权利要求2所述的驱动电路，其特征在于，所述辅助电路还包括第一晶体管和第二晶体管，
    所述第一晶体管和所述第一电阻串联在电源电压与所述第一级电路的第一端之间，流过所述第一电阻的电流也流过所述第一晶体管的第一极和第二极；所述第一晶体管的栅极连接所述第一晶体管的第一极和第二极中远离电源电压的一个；所述第一晶体管用于降低流过所述第一电阻的电流；
    所述第二晶体管和所述第二电阻串联在所述第一级电路的第二端和地之间，流过所述第二电阻的电流也流过所述第二晶体管的第一极和第二极；所述第二晶体管的栅极连接所述第二晶体管的第一极和第二极中远离地的一个；所述第二晶体管用于降低流过所述第二电阻的电流。
  4. 根据权利要求3所述的驱动电路，其特征在于，所述辅助电路还包括第三晶体管和第四晶体管，
    所述第三晶体管和所述第一晶体管、所述第一电阻串联在电源电压与所述第一级电路的第一端之间，流过所述第一电阻的电流也流过所述第三晶体管的第一极和第二极，所述第三晶体管的栅极接收第一偏置信号；所述第三晶体管用于控制流过所述第一电阻的电流的最大值小于所述第一级电路的尾电流的电流值；
    所述第四晶体管和所述第二晶体管、所述第二电阻串联在所述第一级电路的第二端和地之间，流过所述第二电阻的电流也流过所述第四晶体管的第一极和第二极，所述第四晶体管的栅极接收第二偏置信号；所述第四晶体管用于控制流过所述第二电阻的电流的最大值小于所述第一级电路的尾电流的电流值。
  5. 根据权利要求4所述的驱动电路，其特征在于，
    所述第一偏置信号使所述第三晶体管工作于线性区时，所述第一输出信号降低，流过所述第一电阻的电流增大；
    所述第一输出信号降低至使所述第三晶体管工作于饱和区时，流过所述第一电阻的电流达到最大值；
    所述第二偏置信号使所述第四晶体管工作于线性区时，所述第二输出信号升高，流过所述第二电阻的电流增大；
    所述第二输出信号升高至使所述第四晶体管工作于饱和区时，流过所述第二电阻的电流达到最大值。
  6. 根据权利要求3-5中任一项所述的驱动电路，其特征在于，所述第二级电路包括第五晶体管和第六晶体管，
    所述第五晶体管的第一极连接电源电压，第二极作为所述第二级电路的第一端，输出所述第三输出信号，栅极作为所述第二级电路的第二端，接收所述第一输出信号；
    所述第六晶体管的第一极连接所述第五晶体管的第二极，第二极连接地，栅极作为所述第二级电路的第三端，接收所述第二输出信号；
    其中，所述第五晶体管与所述第六晶体管的极性不同，所述第五晶体管与所述第一晶体管的极性相同，所述第六晶体管与所述第二晶体管的极性相同。
  7. 一种显示驱动芯片，其特征在于，包括多个显示单元及至少一个根据权利要求1-6中任一项所述的驱动电路，所述多个显示单元连接在所述驱动电路的第二级电路的第三端。
  8. 一种显示设备，其特征在于，包括权利要求7所述的显示驱动芯片。
  9. 根据权利要求8所述的显示设备，其特征在于，所述显示单元包括显示面板，所述显示面板包括液晶显示面板、微发光二极管显示面板、发光二极管显示面板、迷你发光二极管显示面板、量子点发光二极管显示面板、有机发光二极管显示面板、阴极射线管显示面板、数字光处理显示面板、场发射显示面板、电浆显示面板、电泳显示面板、电润湿显示面板以及小间距显示面板中至少一种。
  10. 一种电子设备，其特征在于，包括根据权利要求8或9所述的显示设备。
PCT/CN2023/106798 2022-07-12 2023-07-11 驱动电路、显示驱动芯片、显示设备及电子设备 WO2024012453A1 (zh)

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