WO2024011726A1 - 用于量子测控电路的数模转换器 - Google Patents

用于量子测控电路的数模转换器 Download PDF

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WO2024011726A1
WO2024011726A1 PCT/CN2022/115761 CN2022115761W WO2024011726A1 WO 2024011726 A1 WO2024011726 A1 WO 2024011726A1 CN 2022115761 W CN2022115761 W CN 2022115761W WO 2024011726 A1 WO2024011726 A1 WO 2024011726A1
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bit
low
digital
digital signal
array
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PCT/CN2022/115761
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French (fr)
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雒超
胡思睿
曹刚
郭国平
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中国科学技术大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

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  • the present disclosure relates to the field of integrated circuit technology, and in particular to a digital-to-analog converter used in quantum measurement and control circuits and operating in an extremely low temperature environment.
  • microwave signals are usually obtained by IQ mixing using arbitrary signal generators and microwave sources at room temperature, so a large number of microwave equipment (microwave sources, arbitrary signal generators, voltage sources, mixers, attenuators, power dividers) are required. device, etc.), and then interconnect room-temperature equipment and low-temperature quantum chips through coaxial cables. This method is feasible when controlling a small number of qubits, but it is difficult to deal with quantum chips that integrate a large number of qubits.
  • the present disclosure provides a digital-to-analog converter for a quantum measurement and control circuit, including: an input register, a thermometer decoder, a virtual decoder, a switch drive array, and a current source array.
  • the input register is configured to receive digital signals and perform synchronous processing to obtain high-order digital signal data and low-order digital signal data;
  • the thermometer decoder is connected to the input register and is configured to receive high-order digital signal data and convert it into the first digital signal;
  • a virtual decoder is connected to the input register and is configured to receive low-order digital signal data and perform delay processing to obtain a second digital signal;
  • the switch driving array includes a high-order switch driving array and a low-order switch driving array.
  • the current source array includes a high current source array and a low current source array.
  • a high-level switch drive array is connected to the high-level current source array and the thermometer decoder, and is configured to output a high-level control signal under the action of the first digital signal to control the high-level current source array to output a high-level current signal;
  • a low-level switch drive array connected to the low-level current source array and the virtual decoder, configured to output a low-level control signal under the action of the second digital signal to control the high-level current source array to output a low-level current signal;
  • the high-level current signal and low-level current signal are used to act on the load to generate a voltage signal.
  • the input register receives a 10-bit digital signal and outputs 6-bit high-bit digital signal data and 4-bit low-bit digital signal data.
  • thermometer decoder receives the 6-bit high-order digital signal data and converts it into a 63-bit thermometer code.
  • the virtual decoder is configured to ensure that the first digital signal and the second digital signal arrive at the high-order switch driving array and the low-order switch driving array synchronously.
  • the thermometer decoder includes: a row decoder that converts three-digit binary to a seven-bit thermometer code; and a column decoder that converts a three-digit binary to a seven-digit thermometer code; the thermometer decoder passes row,
  • the column selection method realizes the conversion of 6-bit high-order digital signal data into 63-bit thermometer code.
  • the high-level switch driving array and the low-level switch driving array include multiple low cross-point switch driving circuits.
  • Each low-crossing point switch driving circuit includes: a first NMOS transistor NM1, a second NMOS transistor NM2, and a second NMOS transistor NM2.
  • the first NMOS tube NM1 The gate receives the clock signal, the drain is connected to the positive input node Din+, and the source is connected to the gate of the first PMOS transistor PM1, the gate of the third NMOS transistor NM3, and one end of the inverter group; the first PMOS transistor PM1 The drain is connected to the drain of the third NMOS transistor NM3, and the source of the third NMOS transistor NM3 is connected to ground;
  • the gate of the second NMOS transistor NM2 receives the clock signal, the drain is connected to the negative input node Din-, and the sources are connected to The gate of the second PMOS transistor PM2, the gate of the sixth NMOS transistor NM6, and the other end of the inverter group; the drain of the second PMOS transistor PM2 is
  • the high-order current source array and the low-order current source array adopt a cascode structure.
  • the low-level current source array adopts a binary structure
  • the high-level current source array adopts a thermometer structure
  • the digital-to-analog converter further includes a bias module, connected to the high-order current source array and the low-order current source array, and configured to provide a bias voltage.
  • the digital-to-analog converter further includes a clock drive circuit connected to the input register, the high-level switch drive array, and the low-level switch drive array, and is configured to receive an external clock and provide the input register, the high-level switch drive array, and The low-level switch driver array provides a clock signal with sufficient driving capability.
  • the present disclosure provides a digital-to-analog converter for quantum measurement and control circuits, which replaces any signal generator working at room temperature and directly synthesizes the control signals required for qubits in an extremely low temperature environment, thereby reducing the complexity of the quantum computer measurement and control circuit.
  • This digital-to-analog converter can be directly used in the digital-to-analog converter of quantum measurement and control circuits at extremely low temperatures, and can replace any signal generator at room temperature. Therefore, the control signals required by qubits can be directly synthesized in extremely low temperature environments, reducing the number of quantum computer measurement and control circuits.
  • thermometer decoder uses a row-column decoding method to reduce design complexity.
  • Figure 1 is a schematic diagram of the composition of a digital-to-analog converter used in a quantum measurement and control circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a thermometer decoder according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a switch driving circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a current source array according to an embodiment of the present disclosure.
  • the present disclosure provides a digital-to-analog converter for quantum measurement and control circuits.
  • the design of the circuit structure avoids the influence of device performance changes caused by extremely low temperatures. In view of the changes in transistor characteristics at low temperatures, the compact cmos system available at extremely low temperatures is used. Model (traditional commercial models bsim, psp, ekv, etc. are suitable for temperatures of -40/50°C to 120°C), and innovate in device parameter settings, selection and circuit structure to make digital-to-analog converters for quantum measurement and control circuits More suitable for low temperature environment applications.
  • a digital-to-analog converter for a quantum measurement and control circuit.
  • the digital-to-analog converter includes: an input register, a thermometer decoder, a virtual decoder, and a switch. Drive array, current source array.
  • the input register is used to receive digital signals and perform synchronous processing to obtain high-order digital signal data and low-order digital signal data;
  • thermometer decoder connected to the input register, is used to receive high-order digital signal data and convert it into a first digital signal
  • a virtual decoder connected to the input register, is used to receive low-order digital signal data and perform delay processing to obtain the second digital signal;
  • the switch drive array includes: a high-level switch drive array and a low-level switch drive array.
  • the current source array includes: a high current source array and a low current source array.
  • a high-level switch drive array is connected to the high-level current source array and the thermometer decoder, and is used to output a high-level control signal under the action of the first digital signal to control the high-level current source array to output a high-level current signal;
  • the low-level switch driving array is connected to the low-level current source array and the virtual decoder, and is used to output a low-level control signal under the action of the second digital signal to control the high-level current source array to output a low-level current signal;
  • the high-level current signal and the low-level current signal are used to act on the load to generate a voltage signal.
  • the input register receives a 10-bit digital signal and outputs 6-bit high-bit digital signal data and 4-bit low-bit digital signal data.
  • thermometer decoder receives the 6-bit high-order digital signal data and converts it into a 63-bit thermometer code.
  • the virtual decoder is used to ensure that the first digital signal and the second digital signal arrive at the high-order switch driving array and the low-order switch driving array synchronously.
  • the thermometer decoder converts 6-bit high-order digital signal data into a 63-bit thermometer code through row and column selection.
  • the thermometer decoder includes: a row decoder that converts three-bit binary into a seven-bit thermometer code; and a column decoder that converts a three-bit binary into a seven-bit thermometer code.
  • the thermometer decoder uses two three-digit binary to seven-bit thermometer code decoders, and then implements a 6-63 thermometer decoder through row and column selection. This method reduces the design complexity.
  • each low-crossing point switch driving circuit includes: a first NMOS transistor NM1, a first The second NMOS transistor NM2, the first PMOS transistor PM1, the third NMOS transistor NM3, the second PMOS transistor PM2, the sixth NMOS transistor NM6, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the inverter group connected end to end;
  • the gate of the first NMOS transistor NM1 receives the clock signal
  • the drain is connected to the positive input node Din+
  • the source is connected to the gate of the first PMOS transistor PM1, the gate of the third NMOS transistor NM3, and the inverter group.
  • One end of the first PMOS transistor PM1 is connected to the drain of the third NMOS transistor NM3, and the source of the third NMOS transistor NM3 is grounded; the gate of the second NMOS transistor NM2 receives the clock signal, and the drain is connected to the negative input node Din-, the source is connected to the gate of the second PMOS transistor PM2, the gate of the sixth NMOS transistor NM6, and the other end of the inverter group; the drain of the second PMOS transistor PM2 is connected to the sixth NMOS transistor NM6 The drain of the sixth NMOS transistor NM6 is grounded; the source of the fourth NMOS transistor NM4 is grounded, the drain is connected to the drain of the first PMOS transistor PM1 and is jointly connected to the negative output node OUT-, and the gate is connected to Positive output node OUT+; the source of the fifth NMOS transistor NM5 is connected to ground, the drain is connected to the drain of the second PMOS transistor PM2 and is jointly connected to the positive output node OUT-, and the
  • NM4 and NM5 provide a positive feedback path, which will accelerate the conversion of the output signal of the positive output node OUT+ or the output signal of the negative output node OUT- to a low level, so the structure can achieve a low crossover point output, it is easier to realize the operation of digital-to-analog converters used in quantum measurement and control circuits in extremely low-temperature environments; the two inverters I1 and I2 connected end to end have a certain latch function and can maintain the original output when CLK is low level , can also reduce the desynchronization between Din+ and Din-.
  • the current source array adopts a "4+6" segmented structure
  • the lower 4-bit current source array adopts a binary structure
  • the upper 6-bit current source array adopts a thermometer structure to achieve performance and functionality. balance between consumption and cost.
  • the current source adopts a cascode structure, which improves the output impedance of the current source and is beneficial to performance improvement.
  • the digital-to-analog converter further includes a bias module connected to the high-level current source array and the low-level current source array for providing a bias voltage.
  • the digital-to-analog converter also includes a clock drive circuit, connected to the input register, the high-level switch drive array, and the low-level switch drive array, for receiving an external clock, and for the input register, high-level switch
  • the driving array and low-level switch driving array provide clock signals with sufficient driving capabilities.
  • the clock driver circuit can receive an external clock and provide clock signals to the internal modules through multi-stage inverters of increasing size.
  • the bias module is used to provide bias voltage for the internal current source array.
  • the transistors used in the above scheme have been characterized by testing at extremely low temperatures (4K), and a BSIM model that can be used with commercial EDA tools has been established for the design of digital-to-analog converters for quantum measurement and control circuits at extremely low temperatures.
  • the input 10-bit digital signal (such as B0-B9) is first synchronized through the 10-bit input register (Input Register), and then the high six bits (B4- B9) Use the 6-63 Thermometer Decoder (Binary-Thermometer Decoder) to convert the 6-bit binary code to the 63-bit thermometer code, while the lower 4 bits (B0-B3) data are passed through the virtual decoder (Dummy Decoder). Ensure that the high and low bit data arrive at the downstream circuit at the same time, and the digital signals after thermometer decoding and delay will control the high and low bit switch driver arrays (Switch Driver Array) respectively.
  • Thermometer Decoder Binary-Thermometer Decoder
  • the switch drive circuit performs synchronous processing on the input digital signal, and on the other hand, it optimizes the switch control signal to improve DAC performance.
  • the high and low switch driver outputs will respectively control the current output of the high current source array (MSB Current Source Array) and the low current source array (LSB Current Source Array). Finally, the output current of the current source array will be summed to the external 50 ⁇ load RL to generate Voltage.
  • the clock driver circuit (Clock Dirver) is used to receive an external clock and provide a clock signal with sufficient driving capability for the DAC internal input register and switch driver circuit to synchronously process digital signals.
  • the bias circuit (Bias) provides DC bias for the current source array.
  • the present disclosure provides a digital-to-analog converter for a quantum measurement and control circuit, which can directly synthesize the control signals required by qubits in an extremely low temperature environment, thereby reducing the complexity of the quantum computer measurement and control circuit.

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Abstract

本公开提供一种用于量子测控电路的数模转换器，包括：输入寄存器，被配置用于接收数字信号并进行同步处理得到高位数字信号数据和低位数字信号数据；温度计译码器与输入寄存器相连,被配置用于接收高位数字信号数据并转换为第一数字信号；虚拟译码器与输入寄存器相连，被配置用于接收低位数字信号数据并进行延时处理得到第二数字信号；高位开关驱动阵列，与高位电流源阵列和温度计译码器相连，被配置用于在第一数字信号的作用下输出高位控制信号以控制高位电流源阵列输出高位电流信号；以及低位开关驱动阵列，与低位电流源阵列和虚拟译码器相连，被配置用于在第二数字信号的作用下输出低位控制信号以控制低位电流源阵列输出低位电流信号，电流信号作用于负载从而产生电压信号。

Description

用于量子测控电路的数模转换器 技术领域
本公开涉及集成电路技术领域，尤其涉及一种应用于量子测控电路的、工作于极低温环境下的数模转换器。
背景技术
目前超导量子比特需要工作在一个密闭的稀释制冷机中，该制冷机提供超导量子比特所需的低温环境(10mK左右)，其中每个量子比特都需要特定的微波信号进行控制。这些微波信号通常是使用室温下的任意信号发生器和微波源通过IQ混频的方式得到，因此需要大量微波设备(微波源、任意信号发生器、电压源、混频器、衰减器、功分器等)产生这些微波控制信号，再通过同轴电缆进行室温设备与低温量子芯片的互连，这种方法在控制少量量子比特的情况下可行，但面对集成了大量量子比特的量子芯片来说是不可行的：首先，大量微波设备使得系统复杂度、成本提高；其次，大量互连线连接了高低温区，导致过多的热量通过互连线泄露至低温量子芯片，造成量子比特的退相干，影响比特性能；最后，过长的线缆带来较大的信号延迟，不利于量子计算机信号的高速传递。
发明内容
本公开提供一种用于量子测控电路的数模转换器，包括：输入寄存器，温度计译码器，虚拟译码器，开关驱动阵列，电流源阵列。
输入寄存器被配置用于接收数字信号并进行同步处理得到高位数字信号数据和低位数字信号数据；温度计译码器与所述输入寄存器相连，被配置用于接收高位数字信号数据并转换为第一数字信号；虚拟译码器与所述输入寄存器相连，被配置用于接收低位数字信号数据并进行延时处理得到第二数字信号；开关驱动阵列包括高位开关驱动阵列，低位开关驱动阵列。电流源阵列包括高位电流源阵列，低位电流源阵列。高位开关驱动阵列，与高位电流源阵列和所述温度计译码器相连，被配置用于在所述第一数字信号的作用下输出高位控制信号以控制所述高位电流源阵列输出高位电流信号；以及低位开关驱动阵列，与低位电流源阵列和所述虚拟译码器相连，被配置用于在第二数字信号的作用下输出低位控制信号以控制所述高位电流源阵列输出低位电流信号；所述高位电流信号和低位电流信号用于作用于负载从而产生电压信号。
根据本公开实施例，输入寄存器接收10比特数字信号，输出6位高位数字信号数据和4 位低位数字信号数据。
根据本公开实施例，温度计译码器接收所述6位高位数字信号数据并转换为63位温度计码。
根据本公开实施例，所述虚拟译码器被配置用于确保第一数字信号和第二数字信号同步抵达高位开关驱动阵列和低位开关驱动阵列。
根据本公开实施例，所述温度计译码器包括：三位二进制转七位温度计码的行译码器；以及三位二进制转七位温度计码的列译码器；温度计译码器通过行、列选择的方式实现6位高位数字信号数据转换为63位温度计码。
根据本公开实施例，高位开关驱动阵列和低位开关驱动阵列中包括多个低交叉点开关驱动电路，每个低交叉点开关驱动电路，包括：第一NMOS管NM1，第二NMOS管NM2，第一PMOS管PM1，第三NMOS管NM3、第二PMOS管PM2，第六NMOS管NM6，第四NMOS管NM4，第五NMOS管NM5，以及首尾相连的反相器组；第一NMOS管NM1的栅极接收时钟信号，漏极接连正输入节点Din+，源极分别连接至第一PMOS管PM1的栅极、第三NMOS管NM3的栅极，以及反相器组的一端；第一PMOS管PM1的漏极连接至第三NMOS管NM3的漏极，第三NMOS管NM3的源极接地；第二NMOS管NM2的栅极接收时钟信号，漏极连接负输入节点Din-，源极分别连接至第二PMOS管PM2的栅极、第六NMOS管NM6的栅极，以及反相器组的另一端；第二PMOS管PM2的漏极连接至第六NMOS管NM6的漏极，第六NMOS管NM6的源极接地；第四NMOS管NM4的源极接地，漏极与第一PMOS管PM1的漏极相连并共同连接至负输出节点OUT-，栅极连接至正输出节点OUT+；第五NMOS管NM5的源极接地，漏极与第二PMOS管PM2的漏极相连并共同连接至正输出节点OUT-，栅极连接至负输出节点OUT-；第四NMOS管NM4和第五NMOS管NM5提供正反馈通路。
根据本公开实施例，高位电流源阵列和低位电流源阵列采用共源共栅结构。
根据本公开实施例，低位电流源阵列采用二进制结构，高位电流源阵列采用温度计结构。
根据本公开实施例，数模转换器，还包括偏置模块，与所述高位电流源阵列和低位电流源阵列相连，被配置用于提供偏置电压。
根据本公开实施例，数模转换器，还包括时钟驱动电路，与输入寄存器、高位开关驱动阵列、低位开关驱动阵列相连，被配置用于接收外部时钟，并为输入寄存器、高位开关驱动阵列、低位开关驱动阵列提供足够驱动能力的时钟信号。
本公开提供的一种用于量子测控电路的数模转换器，代替室温下工作的任意信号发生器， 在极低温环境直接合成量子比特需要的控制信号，减少量子计算机测控电路的复杂度。该数模转换器可直接用于极低温下量子测控电路的数模转换器，可代替室温的任意信号发生器，因此可在极低温环境直接合成量子比特需要的控制信号，减少量子计算机测控电路的复杂度；使用的工艺经过极低温下测试表征，因此电路仿真能够很好的预测实际极低温性能，使得该数模转换器能够工作在极低温环境中；通过分段译码的方法，使得该数模转换器在性能、功耗和成本之间的平衡；温度计译码器使用了行列译码的方法减少了设计的复杂程度。
附图说明
图1为本公开实施例的用于量子测控电路的数模转换器的组成示意图。
图2为本公开实施例的温度计译码器的示意图。
图3为本公开实施例的开关驱动电路的示意图。
图4为本公开实施例的电流源阵列的示意图。
具体实施方式
本公开提供了一种用于量子测控电路的数模转换器，在电路结构的设计上避免极低温带来的器件性能变化的影响，针对低温下晶体管特性变化，基于极低温下可用的cmos紧凑模型(传统的商用模型bsim、psp、ekv等适用温度为-40/50℃～120℃)，在器件的参数设置、选型以及电路结构进行创新以使得用于量子测控电路的数模转换器更适合低温环境应用。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
在本公开实施例中，提供一种用于量子测控电路的数模转换器，如图1所示，所述数模转换器，包括：输入寄存器，温度计译码器，虚拟译码器，开关驱动阵列，电流源阵列。
输入寄存器用于接收数字信号并进行同步处理得到高位数字信号数据和低位数字信号数据；
温度计译码器，与所述输入寄存器相连，用于接收高位数字信号数据并转换为第一数字信号；
虚拟译码器，与所述输入寄存器相连，用于接收低位数字信号数据并进行延时处理得到第二数字信号；
开关驱动阵列包括：高位开关驱动阵列，低位开关驱动阵列。
电流源阵列包括：高位电流源阵列和低位电流源阵列。
高位开关驱动阵列，与高位电流源阵列和所述温度计译码器相连，用于在所述第一数字 信号的作用下输出高位控制信号以控制所述高位电流源阵列输出高位电流信号；
低位开关驱动阵列与低位电流源阵列和所述虚拟译码器相连，用于在第二数字信号的作用下输出低位控制信号以控制所述高位电流源阵列输出低位电流信号；
所述高位电流信号和低位电流信号用于作用于负载从而产生电压信号。
根据本公开实施例，输入寄存器接收10比特数字信号，输出6位高位数字信号数据和4位低位数字信号数据。
根据本公开实施例，温度计译码器接收所述6位高位数字信号数据并转换为63位温度计码。虚拟译码器用于确保第一数字信号和第二数字信号同步抵达高位开关驱动阵列和低位开关驱动阵列。
根据本公开实施例，如图2所示，温度计译码器通过行、列选择的方式实现6位高位数字信号数据转换为63位温度计码。温度计译码器包括：三位二进制转七位温度计码的行译码器；以及三位二进制转七位温度计码的列译码器。温度计译码器利用两个三位二进制转七位温度计码译码器，再通过行列选择的方式实现6-63温度计译码器，这种方法减少了设计复杂度。
根据本公开实施例，高位开关驱动阵列和低位开关驱动阵列中包括多个低交叉点开关驱动电路，如图3所示，每个低交叉点开关驱动电路，包括：第一NMOS管NM1，第二NMOS管NM2，第一PMOS管PM1，第三NMOS管NM3、第二PMOS管PM2，第六NMOS管NM6，第四NMOS管NM4，第五NMOS管NM5，以及首尾相连的反相器组；其中：第一NMOS管NM1的栅极接收时钟信号，漏极接连正输入节点Din+，源极分别连接至第一PMOS管PM1的栅极、第三NMOS管NM3的栅极，以及反相器组的一端；第一PMOS管PM1的漏极连接至第三NMOS管NM3的漏极，第三NMOS管NM3的源极接地；第二NMOS管NM2的栅极接收时钟信号，漏极连接负输入节点Din-，源极分别连接至第二PMOS管PM2的栅极、第六NMOS管NM6的栅极，以及反相器组的另一端；第二PMOS管PM2的漏极连接至第六NMOS管NM6的漏极，第六NMOS管NM6的源极接地；第四NMOS管NM4的源极接地，漏极与第一PMOS管PM1的漏极相连并共同连接至负输出节点OUT-，栅极连接至正输出节点OUT+；第五NMOS管NM5的源极接地，漏极与第二PMOS管PM2的漏极相连并共同连接至正输出节点OUT-，栅极连接至负输出节点OUT-；第四NMOS管NM4和第五NMOS管NM5提供正反馈通路。
通过上述低交叉点开关驱动电路，时钟信号CLK为高电平时，正输入节点Din+的输入信号与负输入节点Din-的输入信号将分别通过PM1和NM3、PM2和NM6反向输出至负输出节 点OUT-和正输出节点OUT+，而NM4和NM5提供正反馈通路，它们会加速正输出节点OUT+的输出信号或负输出节点OUT-的输出信号向低电平的转化，因此该结构能够实现低交叉点输出，更易于实现用于量子测控电路的数模转换器的极低温环境下的工作；两首尾相连的反相器I1、I2具有一定的锁存功能，能够在CLK为低电平时保持原本输出，也能够减少Din+与Din-之间不同步。
根据本公开实施例，如图4所示，电流源阵列采用“4+6”分段结构，低4位电流源阵列采用二进制结构，高6位电流源阵列采用温度计结构，以取得性能、功耗和成本之间的平衡。电流源采用共源共栅结构，提高电流源的输出阻抗，有利于性能提高。
根据本公开实施例，如图1所示，数模转换器还包括偏置模块，与所述高位电流源阵列和低位电流源阵列相连，用于提供偏置电压。
根据本公开实施例，如图1所示，数模转换器还包括时钟驱动电路，与输入寄存器、高位开关驱动阵列、低位开关驱动阵列相连，用于接收外部时钟，并为输入寄存器、高位开关驱动阵列、低位开关驱动阵列提供足够驱动能力的时钟信号。时钟驱动电路可接收外部时钟，并且经过多级尺寸递增的反相器为内部模块提供时钟信号。偏置模块用于为内部的电流源阵列提供偏置电压。
上述方案中所使用的晶体管均通过极低温下(4K)测试表征，建立了可用于商用EDA工具的BSIM模型，用于该极低温用于量子测控电路的数模转换器的设计。
综上，通过本公开的用于量子测控电路的数模转换器，输入10比特数字信号(例如B0-B9)首先通过10位输入寄存器(Input Register)进行同步处理，之后高六位(B4-B9)利用6-63温度计译码器(Binary-Thermometer Decoder)进行6位二进制码到63位温度计码的转换，而低4位(B0-B3)数据则通过虚拟译码器(Dummy Decoder)以保证高低位数据抵达后级电路时间一致，温度计译码和延时后的数字信号将分别控制高低位的开关驱动阵列(Switch Driver Array)。开关驱动电路一方面对输入数字信号进行同步处理，另一方面优化开关控制信号以提高DAC性能。高低位的开关驱动器输出将分别控制高位电流源阵列(MSB Current Source Array)和低位电流源阵列(LSB Current Source Array)的电流输出，最后电流源阵列的输出电流将汇总至外部50Ω负载RL上产生电压。时钟驱动电路(Clock Dirver)用于接收外部时钟，并且为DAC内部输入寄存器和开关驱动电路提供足够驱动能力的时钟信号，对数字信号进行同步处理。偏置电路(Bias)为电流源阵列提供直流偏置。
至此，已经结合附图对本公开实施例进行了详细描述。需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进 行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
依据以上描述，本领域技术人员应当对本公开用于量子测控电路的数模转换器有了清楚的认识。
综上所述，本公开提供了一种用于量子测控电路的数模转换器，可在极低温环境直接合成量子比特需要的控制信号，减少量子计算机测控电路的复杂度。
以上所述本公开的具体实施方式，并不构成对本公开保护范围的限定。任何根据本公开的技术构思所作出的各种其他相应的改变与变形，均应包含在本公开权利要求的保护范围内。

Claims (10)

  1. 一种用于量子测控电路的数模转换器，包括：
    输入寄存器，被配置用于接收数字信号并进行同步处理得到高位数字信号数据和低位数字信号数据；
    温度计译码器，与所述输入寄存器相连，被配置用于接收高位数字信号数据并转换为第一数字信号；
    虚拟译码器，与所述输入寄存器相连，被配置用于接收低位数字信号数据并进行延时处理得到第二数字信号；
    开关驱动阵列，包括：
    高位开关驱动阵列，与高位电流源阵列和所述温度计译码器相连，被配置用于在所述第一数字信号的作用下输出高位控制信号以控制所述高位电流源阵列输出高位电流信号；以及
    低位开关驱动阵列，与低位电流源阵列和所述虚拟译码器相连，被配置用于在第二数字信号的作用下输出低位控制信号以控制所述高位电流源阵列输出低位电流信号；
    所述高位电流信号和低位电流信号用于作用于负载从而产生电压信号。
  2. 根据权利要求1所述的数模转换器，输入寄存器接收10比特数字信号，输出6位高位数字信号数据和4位低位数字信号数据。
  3. 根据权利要求1所述的数模转换器，温度计译码器接收所述6位高位数字信号数据并转换为63位温度计码。
  4. 根据权利要求1所述的数模转换器，所述虚拟译码器被配置用于确保第一数字信号和第二数字信号同步抵达高位开关驱动阵列和低位开关驱动阵列。
  5. 根据权利要求1所述的数模转换器，所述温度计译码器包括：
    三位二进制转七位温度计码的行译码器；以及
    三位二进制转七位温度计码的列译码器；
    温度计译码器通过行、列选择的方式实现6位高位数字信号数据转换为63位温度计码。
  6. 根据权利要求1所述的数模转换器，所述高位开关驱动阵列和低位开关驱动阵列中包括多个低交叉点开关驱动电路，每个低交叉点开关驱动电路，包括：第一NMOS管NM1， 第二NMOS管NM2，第一PMOS管PM1，第三NMOS管NM3、第二PMOS管PM2，第六NMOS管NM6，第四NMOS管NM4，第五NMOS管NM5，以及首尾相连的反相器组；
    第一NMOS管NM1的栅极接收时钟信号，漏极接连正输入节点Din+，源极分别连接至第一PMOS管PM1的栅极、第三NMOS管NM3的栅极，以及反相器组的一端；
    第一PMOS管PM1的漏极连接至第三NMOS管NM3的漏极，第三NMOS管NM3的源极接地；
    第二NMOS管NM2的栅极接收时钟信号，漏极连接负输入节点Din-，源极分别连接至第二PMOS管PM2的栅极、第六NMOS管NM6的栅极，以及反相器组的另一端；
    第二PMOS管PM2的漏极连接至第六NMOS管NM6的漏极，第六NMOS管NM6的源极接地；
    第四NMOS管NM4的源极接地，漏极与第一PMOS管PM1的漏极相连并共同连接至负输出节点OUT-，栅极连接至正输出节点OUT+；
    第五NMOS管NM5的源极接地，漏极与第二PMOS管PM2的漏极相连并共同连接至正输出节点OUT-，栅极连接至负输出节点OUT-；
    第四NMOS管NM4和第五NMOS管NM5提供正反馈通路。
  7. 根据权利要求1所述的数模转换器，高位电流源阵列和低位电流源阵列采用共源共栅结构。
  8. 根据权利要求7所述的数模转换器，低位电流源阵列采用二进制结构，高位电流源阵列采用温度计结构。
  9. 根据权利要求1所述的数模转换器，还包括偏置模块，与所述高位电流源阵列和低位电流源阵列相连，被配置用于提供偏置电压。
  10. 根据权利要求1所述的数模转换器，还包括时钟驱动电路，与输入寄存器、高位开关驱动阵列、低位开关驱动阵列相连，被配置用于接收外部时钟，并为输入寄存器、高位开关驱动阵列、低位开关驱动阵列提供足够驱动能力的时钟信号。
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