WO2024007381A1 - 半导体结构及其形成方法、存储器 - Google Patents

半导体结构及其形成方法、存储器 Download PDF

Info

Publication number
WO2024007381A1
WO2024007381A1 PCT/CN2022/108178 CN2022108178W WO2024007381A1 WO 2024007381 A1 WO2024007381 A1 WO 2024007381A1 CN 2022108178 W CN2022108178 W CN 2022108178W WO 2024007381 A1 WO2024007381 A1 WO 2024007381A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
ion implantation
substrate
phase change
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/108178
Other languages
English (en)
French (fr)
Inventor
廖昱程
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US18/155,656 priority Critical patent/US12622183B2/en
Publication of WO2024007381A1 publication Critical patent/WO2024007381A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a method of forming the same, and a memory.
  • Phase Change Memory is a new type of memory that utilizes the huge resistance difference between the crystalline and amorphous states of phase change materials to achieve information storage.
  • Phase change materials have higher resistance in the amorphous state, and their molecular structures are in a disordered state; phase change materials have lower resistance in the crystalline state, and their internal molecular structures are in an ordered state.
  • the difference in resistance between the two states is usually Reach 2 orders of magnitude.
  • phase change materials between two resistance states can be achieved through current-induced Joule heating.
  • PCM has the advantages of strong stability, low power consumption, high storage density, and compatibility with traditional CMOS processes, it has attracted the attention of more and more researchers and enterprises. With its huge advantages, PCM is considered to be one of the most promising next-generation non-volatile memories. How to improve the storage density and storage speed of PCM has become an urgent problem that needs to be solved.
  • embodiments of the present disclosure provide a semiconductor structure, a method of forming the same, and a memory.
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • a phase change memory unit located on the substrate
  • the phase change memory unit includes: a phase change material layer and a heating layer, the heating layer being located between the phase change material layer and a substrate;
  • the heating layer includes a first portion made of a first conductive material and a second portion made of a second conductive material, the first portion surrounding at least a side wall of the second portion.
  • the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.
  • the side walls and at least part of the upper surface of the phase change memory unit are also covered with an insulation layer.
  • the phase change memory unit further includes:
  • a diode is perpendicular to the substrate, the diode is located between the substrate and the heating layer, and the conduction direction of the diode is from the heating layer to the substrate.
  • the diode includes:
  • a first ion implantation structure located on the substrate
  • a second ion implantation structure located on the first ion implantation structure
  • the ion type of the first ion implantation structure is opposite to the ion type of the second ion implantation structure.
  • the second ion implantation structure includes:
  • the upper second ion implantation structure and the lower second ion implantation structure have different ion concentrations than the lower second ion implantation structure.
  • the substrate includes:
  • a doping structure located on the buried oxide layer, the doping structure being in direct contact with the first ion implantation structure;
  • a shallow trench isolation structure is located between adjacent doped structures.
  • the doped structure includes:
  • the third ion implantation structure is located on the surface of the P well and is in direct contact with the first ion implantation structure.
  • the semiconductor structure further includes:
  • An interlayer dielectric layer is located between each of the phase change memory units;
  • the first conductive structure penetrates the interlayer dielectric layer and is connected to the third ion implantation structure.
  • the semiconductor structure further includes:
  • phase change memory unit a second conductive structure connected to the phase change memory unit
  • the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate
  • the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate.
  • the conductive lines are connected, and the second direction intersects the first direction.
  • embodiments of the present disclosure provide a method for forming a semiconductor structure, including:
  • phase change memory unit is formed on the substrate; the phase change memory unit includes:
  • a phase change material layer and a heating layer is located between the phase change material layer and the substrate, and the heating layer includes a first portion made of a first conductive material and a third portion made of a second conductive material. Two parts, the first part at least surrounds the side wall of the second part.
  • the method further includes:
  • An insulation layer is formed to cover the side wall and at least part of the upper surface of the phase change memory unit.
  • the phase change memory unit further includes: a diode; forming the phase change memory unit on the substrate includes:
  • the phase change material layer is formed on the heating layer.
  • forming a diode on the substrate perpendicular to the substrate includes:
  • the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;
  • the first ion implantation layer and the second ion implantation layer are etched to form a first ion implantation structure and a second ion implantation structure to form the diode.
  • forming the second ion implantation layer includes:
  • An upper second ion implantation layer is formed on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from the ion concentration of the lower second ion implantation layer.
  • forming the heating layer on the diode includes:
  • the first conductive layer other than the second part is etched to form the first part.
  • the substrate includes a back substrate, a buried oxide layer on the back substrate, and a top layer of silicon on the buried oxide layer; a phase change memory cell is formed on the substrate.
  • the method also includes:
  • the top layer of silicon is doped to form a doped layer;
  • the doped layer includes an N well layer, a P well layer and a third ion implantation layer;
  • Etching the doped layer to form a plurality of doped structures the doped structures including N wells, P wells and a third ion implantation structure, the third ion implantation structure is connected to the first ion implantation structure;
  • a shallow trench isolation structure is formed to fill the grooves between adjacent doped structures.
  • the method further includes:
  • a first conductive structure is formed, penetrating the interlayer dielectric layer and connecting the third ion implantation structure.
  • the method further includes:
  • the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate.
  • the conductive lines are connected; the second direction intersects the first direction.
  • embodiments of the present disclosure also provide a memory, which includes a memory cell array containing the semiconductor structure as described in any of the above embodiments, and a peripheral circuit structure located above or outside the memory cell array. .
  • the heating layer is formed using two conductive materials, and the heating layer has a first part and a second part, and the first part at least surrounds the side wall of the second part.
  • the second part can also be used to surround the first part so that the heated heat is not easily lost, which is more conducive to further improving the heating efficiency.
  • the time required for the phase state conversion of the phase change material layer can be shortened, so the phase state conversion can occur faster, thereby increasing the data writing rate.
  • Figure 1 is a schematic diagram of a phase change memory provided in some embodiments.
  • FIGS. 2 to 4 are schematic cross-sectional views of a semiconductor structure provided in embodiments of the present disclosure.
  • FIG. 5 to 8 are schematic top cross-sectional views of the heating layer provided by embodiments of the present disclosure.
  • 9 to 13 are schematic cross-sectional views of a semiconductor structure provided by embodiments of the present disclosure.
  • Figure 14 is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic diagram of a substrate provided by an embodiment of the present disclosure.
  • 16 to 38 are schematic cross-sectional views of a semiconductor structure provided by embodiments of the present disclosure.
  • Figure 39 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 40 is a simplified circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 41 is a current-voltage curve of a memory cell with a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 42 is a schematic diagram of a memory formed by a semiconductor structure provided by an embodiment of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the deposition process described in the embodiments of the present disclosure includes, but is not limited to, the deposition process may include, but is not limited to: chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical vapor deposition ( Plasma Enhanced CVD (PECVD), sputtering (Sputtering), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD) and their combinations, etc.
  • CVD chemical vapor deposition
  • PVD Physical vapor deposition
  • PECVD Plasma Enhanced CVD
  • Sputtering sputtering
  • MOCVD Metal Organic Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the growth processes described in the embodiments of the present disclosure include but are not limited to: vapor phase epitaxy (Vapor Phase Epitaxy, VPE), liquid phase epitaxy (Liquid Phase Epitaxy, LPE), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), ion beam epitaxy, Solid phase epitaxy and its combinations, etc.
  • VPE vapor phase epitaxy
  • LPE liquid phase epitaxy
  • MBE molecular beam epitaxy
  • ion beam epitaxy Solid phase epitaxy and its combinations, etc.
  • etching processes described in the embodiments of the present disclosure include, but are not limited to: dry etching, wet etching and combinations thereof.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a three-dimensional PCM memory, or other memory chips or processing chips containing PCM memory cells.
  • Phase change memory is a new type of memory that utilizes the huge resistance difference between the crystalline and amorphous states of phase change materials to achieve information storage.
  • Phase change materials have higher resistance in the amorphous state, and their molecular structures are in a disordered state; phase change materials have lower resistance in the crystalline state, and their internal molecular structures are in an ordered state.
  • the difference in resistance between the two states is usually Reach 2 orders of magnitude.
  • PCM phase change materials between two resistance states (high resistance and low resistance) can be achieved through current-induced Joule heating. Because PCM has the advantages of strong stability, low power consumption, high storage density, and compatibility with traditional CMOS processes, it has attracted the attention of more and more researchers and enterprises. With its huge advantages, PCM is considered to be one of the most promising next-generation non-volatile memories.
  • the phase change memory unit 100 in the phase change memory includes a planar MOS transistor 110 and a phase change unit 120 .
  • the phase change unit 120 includes a KH (Key Heater, shaped heater) structure.
  • the resistance value of the phase change material in the phase change material layer 130 in the phase change unit 120 can be changed by the shaped heater.
  • the phase change material has high resistivity in the amorphous state and can be used to store data "1".
  • Phase change materials have low resistivity in the crystalline state and can be used to store data "0". This utilizes the reversible phase change of phase change materials to store information.
  • the embodiment of the present disclosure provides a semiconductor structure, as shown in Figure 2.
  • the semiconductor structure includes: a substrate 210; a phase change memory unit 300 located on the substrate 210; a phase change material layer 310 and a heating layer 320.
  • the layer 320 is located between the phase change material layer 310 and the substrate 210; the heating layer 320 includes a first part 321 made of a first conductive material and a second part 322 made of a second conductive material, the first part 321 at least surrounding the second part 322 side walls.
  • the substrate 210 may include a P-type semiconductor material substrate (such as a silicon (Si) substrate or a germanium (Ge) substrate, etc.), an N-type semiconductor substrate (such as an indium phosphide (InP) substrate), or a compound semiconductor material.
  • a substrate such as a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
  • substrates such as silicon-on-insulator or germanium-on-insulator may be preferably used to reduce substrate leakage current.
  • the substrate 210 may have an array composed of a plurality of phase change memory cells 300, and the phase change memory cells are used to implement functions such as data storage, reading and writing.
  • Each phase change memory unit 300 may include a phase change material layer 310 and a heating layer 320 between the phase change material layer 310 and the substrate 210 .
  • the phase change material layer 310 that can be used to store data has at least two clearly distinguishable solid phase structures.
  • one state can be an amorphous state, and the phase change material layer 310 can have high resistance when it is in an amorphous state, and The other state may be a crystalline state, and the phase change material layer may have low resistance when in the crystalline state.
  • the stored data "0" and "1" are distinguished by the significantly different resistance values of the phase change material layer 310 in the amorphous state and the crystalline state.
  • the transition from the metastable amorphous state to the stable crystalline state can be obtained by heating the amorphous state to the crystallization temperature and heating for a long enough time to fully crystallize. From the stable crystalline state to the amorphous state, the crystalline structure can be heated to melt and rapidly cooled, that is, it undergoes a rapid annealing process to condense and obtain the amorphous state.
  • the phase change material layer 310 can be made of glass containing one or more chalcogenides. Chalcogenides include four elements from Group VIA of the periodic table of elements, namely oxygen (O) and sulfur (S). , selenium (Se) and tellurium (Te).
  • the material of the phase change material layer 310 includes but is not limited to GeSbTe (germanium antimony tellurium) series alloy, which may at least include one or more of the following alloys: Ga/Sb (gallium/antimony), In/Sb (indium/antimony) , In/Se (indium/selenium), Sb/Te (antimony/tellurium), Ge/Te (germanium/tellurium), Ge/Sb/Te (germanium/antimony/tellurium), In/Sb/Te (indium/antimony / tellurium), Ga/Se/Te (gallium/selenium/tellurium), Sn/Sb/Te (tin/antimony/tellurium), In/Sb/Ge (indium/antimony/germanium), Ag/In/Sb/Te (Silver/indium/antimony/tellurium), Ge/Sn/Sb/Te (germanium/tin/antimony/tell
  • the phase change memory unit 300 also includes a heating layer 320, which may be located under the phase change material layer 310.
  • the heating layer 320 is used to heat the phase change material layer 310 to change the phase state of the phase change material layer.
  • the heating layer 320 in the embodiment of the present disclosure includes a first part 321 made of a first conductive material and a second part 322 made of a second conductive material; the first part 321 at least surrounds the side walls of the second part 322.
  • the second part 322 penetrates the first part 321 and contacts the substrate 210 and has a contact surface.
  • the bottom of second portion 322 is connected to first portion 321 without contacting the substrate.
  • the second portion 322 extends through the first portion 321 and partially contacts the substrate 210 .
  • the top cross-sectional views of the heating layer 320 are shown in Figures 5 to 8.
  • the top view of the heating layer 320 may be a quadrilateral (including a square)
  • the top view of the second part 322 may be a quadrilateral (including a square).
  • the top view of part 321 can be a quadrilateral with a quadrilateral cut out in the middle.
  • the top view of the first part 321 may be a quadrilateral (including a square)
  • the top view of the second part 322 may be an ellipse (including a circle)
  • the top view of the first part 321 may be a quadrilateral with an oval cut out in the middle.
  • the top view of the first part 321 may be an ellipse (including a circle), the top view of the second part 322 may be an ellipse (including a circle), and the top view of the first part 321 may be an ellipse with the middle cut out. Oval.
  • the top view of the first part 321 may be an ellipse (including a circle)
  • the top view of the second part 322 may be a quadrilateral (including a square)
  • the top view of the first part 321 may be an ellipse with the quadrilateral cut out in the middle.
  • the above are only four examples of the top cross-sectional view of the heating layer 320.
  • the top cross-sectional view of the heating layer 320 or the first part 321 may also include triangles and other polygons, which will not be described again here.
  • the first part 321 at least surrounds the side walls of the second part 322, thereby reducing the heat loss after the conductive material used in the second part is heated, thereby improving the heating efficiency.
  • the heating layer 320 is formed using two conductive materials, and the heating layer 320 has a first part 321 and a second part 322, and the first part 321 at least surrounds the side wall of the second part 322.
  • the advantages of the conductive material used in the second part can not only be used to improve the heating efficiency, but also the structural advantage of the first part surrounding the second part can be used to make the heated heat less likely to dissipate, which is more conducive to further improving the heating efficiency.
  • the phase change time of the phase change material layer 310 is shorter, and the phase change can occur faster, so the data writing rate can be increased.
  • the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.
  • the first conductive material and the second conductive material may be: tungsten, titanium, copper, and compounds of the above materials.
  • the first conductivity of the first conductive material may be smaller than the second conductivity of the second conductive material. That is, when the first conductive material is selected, the first conductivity of the first conductive material is also immediately determined. Sure.
  • the second conductive material can be selected from materials whose conductivity is greater than the first conductivity, which can ensure that most of the current flows to the second part when the heater is in use.
  • the first thermal conductivity of the first conductive material is determined.
  • the second conductive material may also be selected from conductive materials that meet the following conditions: the second thermal conductivity of the second conductive material is greater than the first thermal conductivity of the first conductive material. This makes the thermal conductivity of the second part stronger than that of the first part, so that the heat in the first part is not easily lost.
  • the first conductive material may be TaN
  • the second conductive material may be TiN.
  • TaN not only has a good anti-heat dissipation effect, it is also a kind of conductor, and the TiN/TaN structure has a good current ratio.
  • the embodiments of the present disclosure not only increase the resistance of the heating layer by adopting a structure in which the first part at least surrounds the sidewall of the second part, but also adopt a third thermal conductivity coefficient that satisfies the requirement that the first conductive material is smaller than the second conductive material.
  • the material with high thermal conductivity further concentrates the heat source in the heater, thereby enhancing the heating effect.
  • the sidewalls and at least part of the upper surface of the phase change memory unit are also covered with an insulation layer.
  • the third thermal conductivity of the material used in the insulation layer can be smaller than the first thermal conductivity of the first conductive material, which makes the heat dissipation effect of the insulation layer worse than that of the first conductive material, even if the heat source of the heater will not be easily dissipated. thereby increasing the heating effect. And through the coating of the insulation layer, the heating effect can be assisted.
  • the insulation layer may be made of insulating material, preferably SiN (silicon nitride).
  • the phase change memory unit 300 also includes: a diode 330, perpendicular to the substrate 210; the diode 330 is located between the substrate 210 and the heating layer 320, and the conduction direction of the diode 320 is Heating layer 320 is directed toward substrate 210 .
  • the diode 330 is located between the substrate 210 and the heating layer 320 and is placed perpendicularly to the surface of the substrate 210 so that current can flow from the heating layer 320 to the substrate 210 , that is, the direction of current flow can be perpendicular to the surface of the substrate 210 .
  • the number of diodes 330 may be one or multiple, and multiple diodes 330 may be connected in series between the substrate 210 and the heating layer 320 . When the diode 330 is turned on, it can generate current to drive the phase change memory unit 300 to perform data writing, reading, erasing and other operations.
  • the diode 330 includes: a first ion implantation structure 331 located on the substrate 210 ; a second ion implantation structure 332 located on the first ion implantation structure 331 ; the first ion implantation structure
  • the ion type of 331 is opposite to that of the second ion implantation structure 332 .
  • the first ion implantation structure 331 may be formed by doping on the substrate 210 , or may be formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210 .
  • the types of impurities doped can be divided into two categories: N-type and P-type.
  • N-type mainly includes phosphorus (P), arsenic (As) and antimony (Sb).
  • P-type mainly includes boron (B) and indium (In).
  • the second ion implantation structure 332 may be formed by doping on the substrate 210 , or may be formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210 .
  • the types of impurities doped can be divided into two categories: N-type and P-type.
  • N-type mainly includes phosphorus (P), arsenic (As) and antimony (Sb).
  • P-type mainly includes boron (B) and indium (In).
  • first ion implantation structure 331 and the second ion implantation structure 332 are used to form the diode 330, the implanted types of the first ion implantation structure 331 and the second ion implantation structure 332 are opposite.
  • the first ion implantation structure 331 may be N-type doped
  • the second ion implantation structure 332 may be P-type doping.
  • the first implantation depth to form the first ion implantation structure 331 is deeper than A second implantation depth at which the second ion implantation 332 is performed is formed.
  • the first ion implantation structure 331 and the second ion implantation structure 332 are both formed by doping the epitaxial layer formed by epitaxial growth of the substrate 210, then the first ion implantation structure 331 and the second ion implantation structure 332 may be formed through the first epitaxial growth. an epitaxial layer, and then doping the first epitaxial layer to form a first ion implantation structure. Then, the first epitaxial layer is doped to form a first ion implantation structure 331, and the second epitaxial layer is doped to form a second ion implantation structure 332.
  • the second ion implantation structure 332 includes: an upper second ion implantation structure 3322 and a lower second ion implantation structure 3321.
  • the ion concentration of the upper second ion implantation structure 3322 is the same as that of the lower second ion implantation structure 3321.
  • the ion concentration 3321 of the ion implanted structure is different.
  • the second ion implantation structure 332 may include at least two layers. When it is two layers, it has an upper second ion implantation structure 3322 and a lower second ion implantation structure 3321.
  • the type of doping ions of the upper second ion implantation structure 3322 and the type of doping ions of the lower second ion implantation structure may be the same. For example, if the doping ions of the upper second ion implantation structure 3322 are P-type doping ions, then the doping ions of the lower second ion implantation structure may also be P-type doping ions.
  • the ion concentration of the upper second ion implantation structure 3322 is different from the ion concentration 3321 of the lower second ion implantation structure.
  • the ion concentration of the upper second ion implantation structure 3322 may be greater than the ion concentration 3321 of the lower second ion implantation structure.
  • Doping the upper second ion implantation structure 3322 with a higher concentration of ions can be used to increase the conductivity of the PN junction in the diode 330 .
  • the lower second ion implantation structure 3321 may utilize its doped ion concentration or its thickness to adjust the threshold voltage of the diode 330 .
  • Using a multi-layer structure to form the second ion implantation structure 332 can improve the performance of the diode 330 .
  • the substrate includes: a back substrate 213; a buried oxide layer 212 located on the back substrate 213; and a doping structure 350 located on the back substrate 213.
  • the doped structure 350 is in direct contact with the first ion implantation structure; the shallow trench isolation structure 360 is located between adjacent doped structures 350.
  • the doping structure 350 is in direct contact with the above-mentioned first ion implantation structure to connect a plurality of phase change memory cells arranged along the first direction. That is, the contact points or contact surfaces of the plurality of phase change memory cells along the first direction and the doped structure 350 are at the same potential.
  • the first direction may be any direction parallel to the substrate surface. In some embodiments, the first direction may be the same as the direction of a subsequently formed word line or bit line.
  • the doping structure 350 may be formed by doping the top silicon on the buried oxide layer 212 multiple times.
  • the substrate has a doping structure 350; as shown in Figure 12 ( Figure 12 is a cross-sectional view of the semiconductor structure along the Y direction), the semiconductor structure also includes: a shallow trench isolation structure 360 , located between adjacent doped structures 350; here, the shallow trench isolation structure 360 is used to isolate adjacent doped structures 350.
  • the shallow trench isolation structure 360 is used to isolate adjacent doped structures 350 along the Y direction, so that the phase change memory cells 300 that do not overlap in the Y direction are electrically isolated from each other.
  • the relationship between the Y direction and the X direction can be perpendicular or intersecting.
  • the material of the shallow trench isolation structure 360 may be an insulating material, such as silicon oxide, nitride and combinations thereof.
  • the doping structure includes: N well 351, located on the buried oxide layer 212; P well 352, located on the N well 351; third ion implantation structure 353, located on the surface of the P well 352 in direct contact with the first ion implanted structure.
  • the N-well layer, the P-well layer and the third ion-implantation structure layer may be formed by performing three ion implantations with different depths on the top silicon.
  • the N-well layer is doped with N-type ions
  • the P-well layer is doped with P-type ions.
  • the type of doping ions in the third ion implantation structure layer can be the same as the type of doping ions implanted in the first ion implantation structure.
  • the N well layer, the P well layer and the third ion implantation structure layer are etched to form the doping structure 350 composed of the N well 351, the P well 352 and the third ion implantation structure 353.
  • the third ion implantation structure 353 is in contact with the first ion implantation structure, so that current can flow from the third ion implantation structure 353 into the first ion implantation structure.
  • the third ion implantation layer may be formed by heavy doping, so the subsequently formed third ion implantation structure is also heavily doped, which has the characteristics of low resistivity, small resistance, and enhanced conductivity.
  • the N well and the P well are used to form a reverse biased PN junction to isolate the phase change memory cell 300 from the buried oxide layer 212 and the back substrate 213 to avoid leakage.
  • the semiconductor structure also includes: an interlayer dielectric layer 370, located between each phase change memory unit 300; a first conductive structure 380, penetrating the interlayer dielectric layer 370 and connecting the third ion Inject structure 353.
  • interlayer dielectric layer 370 between each phase change memory unit 300.
  • the interlayer dielectric layer 370 is used to electrically isolate each phase change memory unit 300 and reduce parasitic capacitance.
  • the material of the interlayer dielectric layer 370 may be an insulating material.
  • Each third ion implantation structure 353 may be connected to a first conductive structure 380 penetrating the interlayer dielectric layer 370 .
  • the first conductive structure 380 at least includes a first contact structure 382 (CT, Contact), which may be one or a plurality of contact structures stacked on each other.
  • CT first contact structure 382
  • the first contact structure 382 may further include a first conductive plug 383.
  • the first conductive plug 383 is used to reduce ohmic contact between adjacent first contact structures 382 or between the first contact structure 382 and other structures.
  • the material of the first contact structure 382 may be metal.
  • the material of the first conductive plug 383 may be metal, such as Ti and/or TiN.
  • the semiconductor structure further includes: a second conductive structure 390 connected to the phase change memory unit 300 ; wherein the first conductive structure 380 is connected to a first conductive structure 390 extending in a first direction parallel to the substrate.
  • a conductive line 381 is connected to the second conductive structure 390 and a second conductive line 391 extending in a second direction parallel to the substrate, the second direction intersecting the first direction.
  • the same second conductive structure 390 can also be shared on multiple phase change memory cells overlapping in the first direction (X direction), and adjacent second conductive structures 390 can be connected along the second direction (Y direction). directions) parallel to each other.
  • the second conductive structure at least includes a second contact structure 392, which may be one or a plurality of contact structures stacked on each other.
  • Each second contact structure 392 also includes a second conductive plug 393.
  • the second conductive plug 393 is used to reduce ohmic contact between adjacent second contact structures 392 or between the second contact structure 392 and other structures.
  • the material of the second contact structure 392 may be metal.
  • the second conductive plug 393 may be made of metal, such as Ti or TiN.
  • the second conductive structure further includes a second conductive line 391 extending along the Y-th direction.
  • the first conductive structure 380 also includes a first conductive line 381 extending along the X-th direction.
  • the first conductive lines 381 may be used to form word lines or bit lines.
  • the second conductive lines 391 may also be used to form word lines or bit lines.
  • the first conductive line 381 and the second conductive line 391 do not spatially intersect. That is, there may be an interlayer dielectric layer between the first conductive line 381 and the second conductive line 391 .
  • the first conductive line 381 may be a word line
  • the second conductive line 391 may be a bit line.
  • An embodiment of the present disclosure also provides a method for forming a semiconductor structure, as shown in Figure 14, including:
  • Step S101 Provide a substrate
  • Step S102 Form a phase change memory unit on the substrate; the phase change memory unit includes:
  • the heating layer is located between the phase change material layer and the substrate, and the heating layer includes a first part made of a first conductive material and a second part made of a second conductive material, the second part at least surrounds The first part of the side wall.
  • step S101 is performed to provide a substrate, and the surface of the substrate is any surface perpendicular to the thickness direction of the substrate.
  • the thickness direction of the substrate or the direction perpendicular to the surface of the substrate is the Z direction
  • any direction along the substrate surface is defined as the X direction
  • the direction along the substrate surface that intersects with the X direction is the Y direction.
  • the substrate used in the embodiment of the present disclosure may be an SOI substrate 210 as shown in FIG. 16 .
  • the substrate 210 includes a top layer of silicon 211 , a buried oxide layer 212 and a back substrate 213 .
  • the top silicon 211 can be ultra-thin single crystal silicon
  • the buried oxide layer 212 can be silicon oxide
  • the back substrate 213 can be single crystal silicon.
  • the substrate Before performing step S102, the substrate may also be cleaned to remove impurities on the surface.
  • step S102 is performed to form a phase change material layer to be processed and a heating layer to be processed through a growth process or a deposition process; wherein the heating layer to be processed is located on the substrate, and the phase change material layer to be processed is located on the heating layer to be processed. layer. Then, the phase change material layer to be processed and the heating layer to be processed are etched through an etching process to form the required phase change material layer and the required heating layer to form a phase change memory unit.
  • the heating layer in the embodiment of the present disclosure includes a first part made of a first conductive material and a second part made of a second conductive material; the first part at least surrounds the side wall of the second part.
  • the embodiments of the present disclosure can combine the advantages of the two conductive materials to make the reset current of the phase change memory lower and the heating efficiency higher.
  • the heater in the embodiment of the present disclosure is composed of a second part that at least surrounds the side wall of the first part. This structure is more conducive to reducing heat loss and further improving heating efficiency.
  • the method further includes:
  • Step S201 Form a thermal insulation layer to cover the side wall and at least part of the upper surface of the phase change memory unit.
  • a thermal insulation layer may be formed on the sidewalls and at least part of the upper surface of the phase change memory cell through a deposition process.
  • step S201 can also be executed alternately with step S102, that is, after forming the heating layer of the phase change memory unit, first form a first insulation layer on the side wall of the heating layer, and then after forming the phase change material layer, A second heat preservation layer is then formed on the sidewalls and at least part of the upper surface of the phase change material layer.
  • the first thermal insulation layer and the second thermal insulation layer jointly form a thermal insulation layer covering the side wall and at least part of the upper surface of the phase change memory unit.
  • the phase change memory unit further includes: a diode; the phase change memory unit formed on the substrate includes:
  • Step S301 Form a diode perpendicular to the substrate on the substrate;
  • Step S302 Form a heating layer on the diode
  • Step S303 Form a phase change material layer on the heating layer.
  • the phase change memory unit also includes: a diode located between the substrate and the heating layer. Therefore, step S102 can also be divided into step S301, step S302 and step S303.
  • step S301 is performed to form a diode perpendicular to the substrate on the substrate.
  • step S302 is performed to form a heating layer on the diode.
  • step S303 is performed to form a phase change material layer on the heating layer.
  • forming a diode on the substrate perpendicular to the substrate in step S301 includes:
  • Step S401 Form a first ion implantation layer on the substrate
  • Step S402 Form a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;
  • Step S403 Etch the first ion implantation layer and the second ion implantation layer to form a first ion implantation structure and a second ion implantation structure to form a diode.
  • Executing step S301 may include step S401, step S402 and step S403.
  • step S401 may be performed first to form a first ion implantation layer through a growth process (eg, epitaxial growth) and an ion implantation process.
  • a growth process eg, epitaxial growth
  • step S402 is continued to form a second ion implantation on the first ion implantation layer through a growth process (for example, epitaxial growth) and an ion implantation process.
  • a growth process for example, epitaxial growth
  • an epitaxial growth layer can be formed through a growth process, and then the epitaxial growth layer is subjected to two ion implantations at different depths to form a first ion implantation layer and a second ion implantation layer.
  • the ion types of the two are opposite.
  • step S403 is performed to etch the first ion implantation layer and the second ion implantation layer to form a diode composed of the first ion implantation structure and the second ion implantation structure.
  • photoresist can be coated on the second ion implantation layer, and a mask (the pattern on the mask is opaque) is used to align with the photoresist layer.
  • the photoresist is a positive resist
  • the exposed part of the photoresist changes from an insoluble substance to a soluble substance.
  • the soluble part can be removed with chemical solvents, leaving an island area on the photoresist layer, which corresponds to the opaque part of the mask.
  • the shape of this island is the diode shape.
  • the diode includes a first ion implantation structure and a second ion implantation structure.
  • forming the second ion implantation layer in step S402 includes:
  • Step S501 Form a lower second ion implantation layer
  • Step S502 Form an upper second ion implantation layer located on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from the ion concentration of the lower second ion implantation layer.
  • step S402 may be replaced by step S501 and step S502.
  • step S501 may be performed first: forming a lower second ion implantation layer through a growth process (eg, epitaxial growth) and an ion implantation process. Then proceed to step S502: forming an upper second ion implantation layer through a growth process (eg, epitaxial growth) and an ion implantation process.
  • a growth process eg, epitaxial growth
  • an ion implantation process e.g., epitaxial growth
  • an epitaxial growth layer can be formed through a growth process, and then three ion implantations of different depths are performed on the epitaxial growth layer to form a first ion implantation layer, a lower second ion implantation layer, and an upper second ion implantation layer.
  • the types of ions implanted in the upper second ion implantation layer and the ions implanted in the lower ion implantation layer may be the same, but the concentrations of the ions implanted in the two may be different.
  • the ion concentration of the upper second ion implantation structure may be greater than the ion concentration of the lower second ion implantation structure. Doping the upper second ion implantation structure with a higher concentration of ions can be used to increase the conductivity of the diode PN junction.
  • the lower second ion-implanted structure can use its doped ion concentration or its thickness to adjust the threshold voltage of the diode.
  • the diode forming heating layer in step S302 includes:
  • Step S601 forming a first conductive layer on the second ion implantation layer
  • Step S602 Etch the first conductive layer to form multiple groove structures
  • Step S603 Fill the groove structure with a second conductive material to form a second part
  • Step S604 Etch the first conductive layer except the second part to form the first part.
  • step S403 may not be executed first, but step S302 may be continued.
  • Step S302 includes step S601, step S602, step S603 and step S604.
  • step S601 is performed, using a deposition process to deposit a first conductive material (for example, TaN) to form a first conductive layer located on the second ion implantation layer. Then step S602 is performed to etch the first conductive layer to form a plurality of groove structures; the groove structures may or may not penetrate the first conductive layer.
  • step S603 using a deposition process to fill the second conductive material in the groove structure to form a second part; in some embodiments, when filling the groove structure with the second conductive material (for example, TiN), the second conductive material The material can also cover the surface of the first conductive layer. In this case, the CMP process can be used to remove the second conductive material covering the surface of the first conductive layer.
  • step S604 to etch the first conductive layer other than the first part to form the first part.
  • photoresist can be coated on the first conductive layer formed with the first portion, and a mask (the pattern on the mask is opaque) is used to align with the photoresist layer.
  • the photoresist When it is a positive resist, the exposed part of the photoresist changes from an insoluble substance to a soluble substance.
  • the soluble part can be removed with chemical solvents, leaving an island area on the photoresist layer, which corresponds to the opaque part of the mask.
  • the shape of this island area is the shape of the heating layer.
  • the TiN/TaN structure is used to create a contact with a reduced cross-sectional area, which is also beneficial to shrinkage in terms of process.
  • the substrate includes a back substrate, a buried oxide layer located on the back substrate, and a top silicon layer located on the buried oxide layer; before performing step S102 to form a phase change memory cell on the substrate, the method further include:
  • Step S701 Doping the top silicon to form a doping layer; the doping layer includes an N well layer, a P well layer and a third ion implantation layer.
  • Step S702 Etch the doping layer to form multiple doping structures.
  • the doping structures include N wells, P wells and a third ion implantation structure.
  • the third ion implantation structure is connected to the first ion implantation structure along the first direction; forming a shallow Trench isolation structures fill the grooves between adjacent doped structures.
  • step S701 may also be performed to form a doping layer located on the buried oxide layer; the doping layer is formed by performing multiple ion implantations and/or thermal diffusion processes on the top silicon.
  • Step S702 is then performed to etch the doping layer in a first direction parallel to the substrate to form a doping structure composed of a plurality of N wells, P wells and a third ion implantation structure.
  • the third ion implantation structure is connected to the first ion implantation structure along the first direction, that is, the plurality of third ion implantation structures are parallel to each other along the first direction.
  • the formed third ion implantation structure is connected to a plurality of first ion implantation structures, so that a plurality of phase change memory cells located in the same first direction are connected to the same third ion implantation structure.
  • the method further includes:
  • Step S801 Fill the grooves between adjacent doped structures to form a shallow trench isolation structure.
  • the doped structures extend along the first direction but are also arranged along the second direction, so adjacent doped structures have grooves in the first direction and the second direction.
  • Step S801 is performed, using a deposition process to deposit oxide, nitride or a combination thereof to fill the groove to form a shallow trench isolation structure, so that adjacent doped structures have shallow trenches in the first direction and the second direction.
  • Tank isolation structure The shallow trench isolation structure is used to electrically isolate the doped structure and subsequent devices (eg, phase change memory cells) formed on the doped structure.
  • the method further includes:
  • Step S901 Form an interlayer dielectric layer and fill it between multiple phase change memory cells;
  • Step S902 Form a first conductive structure, penetrate the interlayer dielectric layer and connect to the third ion implantation structure.
  • step S901 may be performed after step S102 is performed.
  • An insulating material is deposited using a deposition process to form an interlayer dielectric layer between multiple phase change memory cells.
  • step S102 and step S901 may be performed alternately.
  • an insulating material may first be deposited between the diode and the heating layer to form a first interlayer dielectric layer.
  • an insulating material is continued to be deposited between the phase change material layers to form a second interlayer dielectric layer.
  • the first interlayer dielectric layer and the second interlayer dielectric layer together constitute an interlayer dielectric layer.
  • step S902 is performed to etch the interlayer dielectric layer, and the third ion implantation layer can be used as an etching stop layer.
  • a groove structure penetrating the interlayer dielectric layer is formed, which can be filled with conductive material using a deposition process to form a first conductive structure penetrating the interlayer dielectric layer and connecting to the third ion implantation structure.
  • the first conductive structure includes at least a first contact structure. In some embodiments, the first conductive structure may further include a first conductive plug over the first contact structure.
  • the method further includes:
  • Step S1001 Form a second conductive structure and connect the phase change memory unit
  • the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate, and the second direction is connected to The first direction intersects.
  • step S1001 may also be continued to form a second conductive structure connected to the surface of the phase change memory cell.
  • the second conductive structure includes at least a second contact structure.
  • the second conductive structure may further include a second conductive plug over the second contact structure.
  • a deposition process may also be used to form a first conductive line on the first conductive structure, and the first conductive line extends in a first direction parallel to the substrate.
  • a deposition process may also be used to form a second conductive line on the second conductive structure, and the second conductive line extends along a second direction parallel to the substrate.
  • the first conductive line may be a bit line and the second conductive line may be a word line.
  • the first conductive line may be a word line and the second conductive line may be a bit line.
  • step S101 is performed to provide a substrate 210 as shown in FIG. 15 , which may be an SOI substrate.
  • a substrate 210 as shown in FIG. 15 , which may be an SOI substrate.
  • the SOI substrate 210 includes: a back substrate 213, a buried oxide layer 212 and a top layer of silicon 211.
  • step S701 is performed to perform three ion implantation doping layers with different depths on the top silicon from the upper surface of the substrate; the doping layer includes an N well layer, a P well layer and a third ion implantation layer.
  • the ion implantation depth of the N-well layer is greater than the ion implantation depth of the P-well layer, which is greater than the ion implantation depth of the scattered ion implantation layer.
  • step S702 is performed to etch the doping layer to form a plurality of doping structures.
  • the doping structures include an N well, a P well and a third ion implantation structure.
  • the third ion implantation structure is connected to the first ion implantation structure along the first direction.
  • the doped layer is etched along the X direction to form multiple doped structures. At this time, there are grooves between adjacent doped structures.
  • step S801 is performed to fill the shallow trench isolation structure formed by the grooves between adjacent doped structures.
  • the non-device area of the doped structure in the Y direction can also be etched. After etching, two grooves on both sides of the device area can be formed in the Y direction, between the two grooves. A phase change memory cell array can be formed on the doping structure of the device region. Then a deposition process is used to fill the grooves on both sides of the device area to form two shallow trench isolation structures in the Y direction.
  • the numbers in the above embodiments are only for illustration, and other numbers of groove structures can also be formed in the Y direction of the non-device area.
  • FIG. 16 is a cross-sectional view of the semiconductor structure along the X direction
  • FIG. 17 is a cross-sectional view of the semiconductor structure along the Y direction.
  • FIG. 16 shows the back substrate 213, the buried oxide layer 212, and the doping structure 350 (including the N well 351, the P well 352, and the third ion implantation structure 353) in order. Both ends of the doped structure 350 also include two shallow trench isolation structures 360. The area between the two shallow trench isolation structures 360 can be used as a device area, which is subsequently used to form semiconductor components, such as phase change memory cells.
  • the back substrate 213 Seen along the positive direction of the Z-axis in FIG. 17 , there are in order the back substrate 213 , the buried oxide layer 212 , a plurality of shallow trench isolation structures 360 and the doped structures 350 located between the shallow trench isolation structures 360 .
  • the shallow trench isolation structure 360 and the doping structure 350 are located in the same horizontal direction in the Z direction.
  • step S401 is performed, continuing epitaxial growth on the semiconductor structure as shown in Figures 16 and 17 to form a first epitaxially grown silicon layer, and then injecting highly doped N-type ions to form the structure as shown in Figures 18 and 19 the first ion implantation layer 331.
  • 18 is a cross-sectional view of the semiconductor structure along the X direction
  • FIG. 19 is a cross-sectional view of the semiconductor structure along the Y direction.
  • step S501 continue epitaxial growth on the first ion implantation layer 331 to form a second epitaxially grown silicon layer, and then inject N-type ions to form the lower second ion implantation layer 3321 as shown in Figures 18 and 19. .
  • step S502 continue epitaxial growth on the lower second ion implantation layer 3321 to form a third epitaxially grown silicon layer, and then inject highly doped P-type ions to form the upper layer of the second ion implantation layer 3321 as shown in Figures 18 and 19. Second ion implantation layer 3332.
  • Step S601 is then performed to deposit a first conductive material (eg, TaN) using a deposition process (eg, chemical vapor deposition) to form a first conductive layer located on the second ion implantation layer.
  • a first conductive material eg, TaN
  • a deposition process eg, chemical vapor deposition
  • step S602 is performed to process the first conductive layer through processes such as photomask and etching to form a plurality of groove structures penetrating the first conductive layer.
  • the surface of the formed groove structure can then be cleaned to remove the native oxide layer on the surface.
  • Step S603 is then performed to deposit a second conductive material (eg, TiN) in the groove structure using a deposition process (eg, atomic layer deposition) to form the second portion 322 as shown in FIGS. 20 and 21 .
  • a deposition process eg, atomic layer deposition
  • FIGS. 20 and 21 are cross-sectional views of the semiconductor structure along the Y direction.
  • TiN is also deposited on the TaN layer (ie, the first conductive layer). At this time, the TiN deposited on the TaN layer (ie, the first conductive layer) can be chemically and mechanically polished until the TaN layer is exposed.
  • the stop layer is a third ion implantation structure to form the heating layer 320 and the diode 330 as shown in Figures 22 and 23.
  • the three-dimensional structure of the heating layer 320 is shown in Figure 24, which includes a second part 322 and a first part 321.
  • the second part 322 can be a cylindrical structure
  • the first part 321 can be a rectangular parallelepiped with a cylinder cut out in the middle. It can be seen that, The first part 321 covers the entire side wall of the second part 322.
  • step S201 is performed to deposit a thermal insulation material (eg, SiN) to form a first thermal insulation layer 410 .
  • a thermal insulation material eg, SiN
  • the first thermal insulation layer may cover the sidewalls of the diode 330 , the sidewalls of the heating layer 320 , the surface of the heating layer 320 and the surface of the third ion implantation structure 353 .
  • the first thermal insulation layer may cover the sidewalls of the diode 330 , the sidewalls of the heating layer 320 , the surface of the heating layer 320 and the surface of the shallow trench isolation 360 .
  • the surface of the groove structure between the first structure may also be cleaned to remove the native oxide layer on the surface.
  • step S901 is performed to deposit an insulating material (eg, silicon nitride) between the diode and the heating layer to form a first interlayer dielectric layer.
  • the first interlayer dielectric layer 370 may also cover the first heat preservation layer 410 on the heating layer 330 .
  • an etching process eg, CMP
  • CMP etching process
  • the first insulation layer 410 covers the heating layer 330 and the sidewalls of the diode 320 and the upper surface of the third ion implantation layer 353 .
  • the first thermal insulation layer 410 covers the heating layer 330 and the sidewalls of the diode 320 and the upper surface of the shallow trench isolation structure 360 .
  • step S303 is performed, first using a deposition process to deposit a phase change material (for example, GST) to form a phase change material layer, and then processing the phase change material layer through photomask, etching and other processes to form the phase change material layer as shown in Figures 29 and 30
  • the phase change material structure 310 is located on the heating layer 320.
  • the width (along the X direction) and the length (along the Y direction) of the phase change material structure 310 may be larger than the heating layer 320 , that is, the phase change material structure 310 may completely cover the upper surface of the heating layer 330 .
  • the distance between adjacent phase change material structures formed using the method of the embodiment of the present disclosure can be reduced to 0.07 ⁇ m.
  • the spacing between each phase change memory unit and the number of stacked layers of phase change memory units are small, so the efficiency is greatly improved.
  • the storage density of memory cells per unit area can be reduced to 0.07 ⁇ m.
  • step S201 is performed again to deposit a thermal insulation material (SiN) between the phase change material structures 310 to form a second thermal insulation layer 420 as shown in FIGS. 31 and 32 .
  • the second thermal insulation layer 420 covers the sides of the phase change material structure 310 The walls and upper surface also cover the upper surface of the first interlayer dielectric layer 370 .
  • step S901 is performed again to deposit an insulating material (for example, silicon oxide) on the second thermal insulation layer 420 to form a second interlayer dielectric layer 371 as shown in FIGS. 33 and 34 .
  • an insulating material for example, silicon oxide
  • step S902 and step S1001 are performed to form a first conductive structure that penetrates the first interlayer dielectric layer and the second interlayer dielectric layer and connects the third ion implantation structure as shown in Figure 35 and Figure 36 and forms a connected phase change memory.
  • a second conductive structure on the surface of the unit.
  • photomask, etching and other processes are performed along the Y direction between the phase change memory cell array and the shallow trench isolation (one of the two shallow trench isolations along the X direction can be selected), and a third ion implantation is performed.
  • the structure serves as an etching stop layer to form multiple groove structures that overlap in the X direction and are parallel in the Y direction.
  • the groove structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer and connects the third ion implantation structure.
  • phase change memory cell array use photomask, etching and other processes along the X and Y directions, and use the phase change material structure as the etching stop layer to form an opening structure located on the phase change material structure.
  • the opening structure The width (along the X direction) is less than or equal to the width of the phase change material structure, and the length (along the Y direction) of the opening is also less than or equal to the length of the phase change material structure.
  • a deposition process (eg, atomic layer deposition) is used to deposit conductive material into the groove structure and the opening structure to form the first contact structure 382 and the first conductive plug 383 and the second contact structure 392 and the second conductive plug 393.
  • a conductive material is deposited on the second conductive plug 393, and a photomask and an etching process are performed to form a second conductive line 391 covering the second conductive plug 393.
  • the second conductive line 391 extends in the Y direction.
  • the second conductive lines 391 are parallel to each other along the X direction.
  • the distance between adjacent second conductive lines 391 formed using the method of the embodiment of the present disclosure can be reduced to 0.07 ⁇ m.
  • Figures 35 and 36 continue to deposit insulating material (for example, silicon oxide) to form a third interlayer dielectric layer 372 as shown in Figures 37 and 38.
  • insulating material for example, silicon oxide
  • the mask process, etching process, etc. form a groove structure connecting the first contact plug 383 through the third dielectric layer 372 .
  • a further first contact structure 382 and a further first contact plug 383 are formed over the first contact plug 383 using a deposition process (eg, atomic layer deposition).
  • the upper surface of the first contact plug 383 is flush with the upper surface of the third interlayer dielectric layer 372 .
  • first conductive lines 381 parallel to each other along the X direction are formed on the third interlayer dielectric layer through a photomask process and an etching process.
  • Insulating materials used in the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer in the embodiments of the present disclosure may be the same or different.
  • bit lines extend along the Y direction, and adjacent bit lines are parallel to each other along the X direction.
  • the word lines extend along the X direction, and adjacent word lines are parallel to each other along the Y direction.
  • the semiconductor structure formed using the method of the embodiment of the present disclosure has a simple process and is easy to form. Since it is formed on an SOI substrate, in addition to the above advantages, the semiconductor structure also has the advantages of SOI (for example, less latch-up effect, less leakage current, etc.).
  • the circuit diagram corresponding to the semiconductor structure of Figures 37 and 38 can be simplified as Figure 40, in which the memory unit 500 includes a phase change memory unit and a diode. Multiple diodes located in the same row can be connected to the same word line, and multiple phase change memory cells located in the same column can be connected to the same bit line.
  • Programming the memory cell 500 includes applying a programming voltage V pgm (for example, 0.5V) to the bit line where the selected memory cell 500 is located, and applying a ground voltage (for example, 0V) to other unselected bit lines. At the same time, a ground voltage (for example, 0V) is applied to the word line where the selected memory cell 500 is located, and a certain voltage (for example, 0.5V) is applied to unselected word lines.
  • V pgm for example, 0.5V
  • the reading operation of the memory cell includes: applying a read voltage (V read ) to the bit line where the selected memory cell 500 is located, and applying a ground voltage (for example, 0V) to other unselected bit lines. At the same time, a ground voltage (for example, 0V) is applied to the word line where the selected memory cell 500 is located, and a certain voltage (for example, 0.5V) is applied to unselected word lines. Among them, V read is less than V pgm.
  • Curve 1 is the current-voltage curve when reading the memory cell.
  • Curve 2 is the current-voltage curve when writing a memory cell.
  • the current-voltage curve in Figure 41 shows that the read voltage must be smaller than the write voltage (the range of the write voltage is such as the shaded area). In this way, when the voltage is read, the phase change memory will not be caused by excessive voltage. Change of state.
  • write operations are divided into RESET operations and SET operations, and the voltage range is roughly in the shaded area. Then the writing operation is performed through different pulse times, in which the SET operation can be a longer pulse time, and the RESET operation can be a shorter pulse time.
  • the memory 40 includes a memory cell array 20 containing the semiconductor structure 10 as in any of the above embodiments, and a memory cell array 20 located above or outside the memory cell array 20 . Peripheral circuit 30 structure.
  • All or part of the semiconductor structure 10 in the above embodiments can be used to form the memory cell array 20, and the memory cells of the memory cell array 20 include phase change memory cells.
  • Peripheral circuitry 30 may include any suitable analog, digital, and mixed-signal circuitry to perform related operations on memory cell array 20 . Operations include reading, writing, erasing, etc.
  • Memory 40 may be a phase change memory.
  • the memory has a three-dimensional structure, which has higher storage density, lower power consumption and easier access operations.
  • the heater of the memory has a smaller volume, making the heating efficiency higher and the writing speed faster.
  • the memory also has other advantages of the semiconductor structure of any embodiment of the present disclosure.
  • the heating layer is formed using two conductive materials, and the heating layer has a first part and a second part, and the first part at least surrounds the side wall of the second part.
  • the second part can also be used to surround the first part so that the heated heat is not easily lost, which is more conducive to further improving the heating efficiency.
  • the time required for the phase state conversion of the phase change material layer can be shortened, so the phase state conversion can occur faster, thereby increasing the data writing rate.

Landscapes

  • Semiconductor Memories (AREA)

Abstract

一种半导体结构及其形成方法、存储器。所述半导体结构包括：衬底（210）；相变存储单元（300），位于所述衬底（210）上；所述相变存储单元（300）包括：相变材料层（310）和加热层（320），所述加热层（320）位于所述相变材料层（310）和所述衬底（210）之间；所述加热层包括由第一导电材料构成的第一部分（321）和由第二导电材料构成的第二部分（322），所述第一部分（321）至少包围所述第二部分（322）的侧壁。

Description

半导体结构及其形成方法、存储器
相关申请的交叉引用
本公开基于申请号为202210786445.1、申请日为2022年07月04日、发明名称为“半导体结构及其形成方法、存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，具体地，涉及一种半导体结构及其形成方法、存储器。
背景技术
相变存储器(Phase Change Memory，PCM)是利用相变材料在晶态和非晶态的巨大电阻差异实现信息存储的新型存储器。相变材料在非晶态时具有较高电阻，其分子结构为无序状态；相变材料在晶态时具有较低电阻，其内部分子结构为有序状态，两态之间的电阻差异通常达到2个数量级。
通过电流诱导的焦耳热，可以实现相变材料在两个电阻态(高电阻和低电阻)之间的快速转变。
因PCM具有稳定性强、功耗低、存储密度高、与传统的CMOS工艺兼容等优点，从而受到越来越多研究者和企业的关注。PCM以其巨大的优势，被认为是最具潜力的下一代非易失性存储器之一。如何提高PCM的存储密度以及存储速度等等，成为了亟需解决的问题。
发明内容
有鉴于此，本公开实施例提出一种半导体结构及其形成方法、存储器。
第一方面，本公开实施例提供一种半导体结构，包括：
衬底；
相变存储单元，位于所述衬底上；
所述相变存储单元包括：相变材料层和加热层，所述加热层位于所述相变材料层和衬底之间；
所述加热层包括由第一导电材料构成的第一部分和由第二导电材料构成的第二部分，所述第一部分至少包围所述第二部分的侧壁。
在一些实施例中，所述第一导电材料的第一导电系数小于所述第二导电材料的第二导电系数。
在一些实施例中，所述相变存储单元的侧壁及至少部分上表面还覆盖有保温层。
在一些实施例中，所述相变存储单元还包括：
二极管，垂直于所述衬底，所述二极管位于所述衬底与所述加热层之间，所述二极管的导通方向为由所述加热层指向所述衬底。
在一些实施例中，所述二极管包括：
第一离子注入结构，位于所述衬底上；
第二离子注入结构，位于所述第一离子注入结构上；
所述第一离子注入结构的离子类型与所述第二离子注入结构的离子类型相反。
在一些实施例中，所述第二离子注入结构包括：
上层第二离子注入结构和下层第二离子注入结构，所述上层第二离子注入结构的离子浓度与所述下层第二离子注入结构的离子浓度不同。
在一些实施例中，所述衬底包括：
背衬底；
埋氧层，位于所述背衬底上；
掺杂结构，位于所述埋氧层上，所述掺杂结构与所述第一离子注入结构直接接触；
浅沟槽隔离结构，位于相邻所述掺杂结构之间。
在一些实施例中，所述掺杂结构包括：
N阱，位于所述埋氧层上；
P阱，位于所述N阱上；
第三离子注入结构，位于所述P阱表面与所述第一离子注入结构直接接触。
在一些实施例中，所述半导体结构还包括：
层间介质层，位于各所述相变存储单元之间；
第一导电结构，贯穿所述层间介质层且连接所述第三离子注入结构。
在一些实施例中，所述半导体结构还包括：
第二导电结构，连接所述相变存储单元；
其中，所述第一导电结构与沿平行于所述衬底的第一方向延伸的第一导电线连接，所述第二导电结构与沿平行于所述衬底的第二方向延伸的第二导电线连接，所述第二方向与所述第一方向相交。
第二方面，本公开实施例提供一种半导体结构的形成方法，包括：
提供衬底；
在所述衬底上形成相变存储单元；所述相变存储单元包括：
相变材料层和加热层，所述加热层位于所述相变材料层和所述衬底之间，且所述加热层包括由第一导电材料构成的第一部分和第二导电材料构成的第二部分，所述第一部分至少包围所述第二部分的侧壁。
在一些实施例中，所述方法还包括：
形成保温层覆盖所述相变存储单元的侧壁和至少部分上表面。
在一些实施例中，所述相变存储单元还包括：二极管；在所述衬底上形成相变存储单元包括：
在所述衬底上形成垂直于所述衬底的二极管；
在所述二极管上形成所述加热层；
在所述加热层上形成所述相变材料层。
在一些实施例中，在所述衬底上形成垂直于所述衬底的二极管包括：
在所述衬底上形成第一离子注入层；
在所述第一离子注入层上形成第二离子注入层；所述第一离子注入层的离子类型与所述第二离子注入层的离子类型相反；
刻蚀所述第一离子注入层与所述第二离子注入层形成第一离子注入结构与第二离子注入结构，以构成所述二极管。
在一些实施例中，形成第二离子注入层包括：
形成下层第二离子注入层；
在所述下层第二离子注入层上形成上层第二离子注入层；所述上层第二离子注入层的离子浓度与所述下层第二离子注入层的离子浓度不同。
在一些实施例中，在所述二极管上形成所述加热层包括：
在所述第二离子注入层上形成第一导电层；
刻蚀所述第一导电层形成多个凹槽结构；
在所述凹槽结构中填充所述第二导电材料，形成所述第二部分；
刻蚀所述第二部分以外的所述第一导电层，形成所述第一部分。
在一些实施例中，所述衬底包括背衬底、位于所述背衬底上的埋氧层以及位于所述埋氧层上的顶层硅；在所述衬底上形成相变存储单元的步骤之前，所述方法还包括：
对所述顶层硅进行掺杂形成掺杂层；所述掺杂层包括N阱层、P阱层以及第三离子注入层；
刻蚀所述掺杂层形成多个掺杂结构，所述掺杂结构包括N阱、P阱以及第三离子注入结构，所述第三离子注入结构与所述第一离子注入结构连接；
形成浅沟槽隔离结构，填充相邻所述掺杂结构之间的凹槽。
在一些实施例中，所述方法还包括：
形成层间介质层，填充在多个所述相变存储单元之间；
形成第一导电结构，贯穿所述层间介质层且连接所述第三离子注入结构。
在一些实施例中，所述方法还包括：
形成第二导电结构，连接所述相变存储单元；
其中，所述第一导电结构与沿平行于所述衬底的第一方向延伸的第一导电线连接；所述第二导电结构与沿平行于所述衬底的第二方向延伸的第二导电线连接；所述第二方向与所述第一方向相交。
第三方面，本公开实施例还提供了一种存储器，所述存储器包括含有如上述实施例任一所述的半导体结构的存储单元阵列，以及位于所述存储单元阵列上方或者外侧的外围电路结构。
本公开实施例中，利用两种导电材料形成了加热层，并且加热层具有第一部分和第二部分，并且第一部分至少包围第二部分的侧壁。这样不但可以利用第一部分的导电材料的优势提高加热效率，还可以利用第二部分包围第一部分使得加热后的热量不易散失，更有利于进一步提高加热效率。加热效率提高后，可使得相变材料层发生相态转换所需的时间更短，故可以更快地发生相态转换，从而可以提高数据写入的速率。
附图说明
图1为在一些实施例中提供的一种相变存储器的示意图；
图2至4为本公开实施例中提供的一种半导体结构的剖面示意图；
图5至8为本公开实施例提供的加热层的俯视剖面图的示意图；
图9至13为本公开实施例提供的一种半导体结构的剖面示意图；
图14为本公开实施例提供的一种半导体结构的形成方法流程图；
图15为本公开实施例提供的一种衬底的示意图；
图16至38为本公开实施例提供的一种半导体结构的剖面示意图；
图39为本公开实施例提供的一种半导体结构的俯视图；
图40为本公开实施例提供的一种半导体结构的电路简化图；
图41为本公开实施例提供的一种半导体结构的存储单元的电流-电压曲线图；
图42为本公开实施例提供的半导体结构形成的一种存储器的简要示意图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、硅锗、锗、砷化嫁、磷化锢等。替代地，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本公开实施例所述的沉积工艺包括但不限于沉积工艺可以包括但不限于：化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、等离子体增强化学气相沉积(Plasma Enhanced CVD，PECVD)、溅镀(Sputtering)、有机金属化学气相沉积(Metal Organic Chemical Vapor Deposition，MOCVD)、原子层沉积(Atomic Layer Deposition，ALD)及其组合等。
本公开实施例所述的生长工艺包括但不限于：气相外延(Vapour Phase Epitaxy，VPE)、液相外延(Liquid Phase Epitaxy，LPE)、分子束外延(Molecular Beam Epitaxy，MBE)、离子束外延、固相外延及其组合等等。
本公开实施例所述的刻蚀工艺包括但不限于：干法刻蚀、湿法刻蚀及其组合。
本公开实施例涉及的半导体结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里，最终的器件可以包括三维PCM存储器，或包含有PCM存储单元的其他存储芯片或处理芯片。
相变存储器是利用相变材料在晶态和非晶态的巨大电阻差异实现信息存储的新型存储器。相变材料在非晶态时具有较高电阻，其分子结构为无序状态；相变材料在晶态时具有较低电阻，其内部分子结构为有序状态，两态之间的电阻差异通常达到2个数量级。
通过电流诱导的焦耳热，可以实现相变材料在两个电阻态(高电阻和低电阻)之间的快速转变。因PCM具有稳定性强、功耗低、存储密度高、与传统的CMOS工艺兼容等优点，从而受到越来越多研究者和企业的关注。PCM以其巨大的优势，被认为是最具潜力的下一代非易失性存储器之一。
在一些实施例中，如图1所示，相变存储器中的相变存储单元100包括一个平面MOS管110 和一个相变单元120。该相变单元120包括KH(Key Heater，成型的加热器)结构。相变单元120中的相变材料层130中的相变材料的阻值可以通过该成型加热器而改变，相变材料在非晶态时具有高的电阻率，可用于存储数据“1”，相变材料在晶态时具有低的电阻率低，可用于存储数据“0”。如此便利用了相变材料的可逆转的相变来存储信息。
本公开实施例提供一种半导体结构，如图2所示，该半导体结构包括：衬底210；相变存储单元300，位于衬底210上；相变材料层310和加热层320，所述加热层320位于相变材料层310和衬底210之间；加热层320包括由第一导电材料构成的第一部分321和由第二导电材料构成的第二部分322，第一部分321至少包围第二部分322的侧壁。
衬底210可以包括P型半导体材料衬底(例如为硅(Si)衬底或者锗(Ge)衬底等)、N型半导体衬底(例如磷化铟(InP)衬底)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)、绝缘体上硅(SOI)衬底以及绝缘体上锗(GeOI)衬底等。本公开实施例可以优先选用绝缘体上硅或绝缘体上锗之类衬底，以减小衬底漏电流。
衬底210上可具有由多个相变存储单元300构成的阵列，相变存储单元用于实现数据的存储以及读写等功能。
每个相变存储单元300都可以包括相变材料层310以及位于相变材料层310和衬底210之间的加热层320。其中，可用于存储数据的相变材料层310存在至少两种可明显区分的固体相结构，例如，一个状态可为非晶状态，相变材料层310为非晶状态时可具有高电阻，而另一状态可为晶体状态，相变材料层为晶体状态时可具有低电阻。利用相变材料层310在非晶态和晶态两种状态时差异明显的电阻值来区别所存储的数据“0”和“1”。从亚稳态的非晶态到稳定状态的晶态的转变可通过对非晶态加热至结晶温度并加热足够长的时间使其充分结晶而得到。而从稳定的晶态到非晶态可将晶态结构加热至熔化并使其快速冷却，即经历一个快速退火过程凝结而得到非晶态。相变材料层310可使用含一种或多种硫族化物的玻璃(Chalcogenide glass)制成，硫族化物包括元素周期表第VIA族的四个元素，即氧(O)、硫(S)、硒(Se)及碲(Te)。相变材料层310的材料包括但不限于GeSbTe(锗锑碲)系合金，至少可以包括以下合金中的一种或多种：Ga/Sb(镓/锑)、In/Sb(铟/锑)、In/Se(铟/硒)、Sb/Te(锑/碲)、Ge/Te(锗/碲)、Ge/Sb/Te(锗/锑/碲)、In/Sb/Te(铟/锑/碲)、Ga/Se/Te(镓/硒/碲)、Sn/Sb/Te(锡/锑/碲)、In/Sb/Ge(铟/锑/锗)、Ag/In/Sb/Te(银/铟/锑/碲)、Ge/Sn/Sb/Te(锗/锡/锑/碲)、Ge/Sb/Se/Te(锗/锑/硒/碲)及Te/Ge/Sb/S(碲/锗/锑/硫)。
相变存储单元300还包括加热层320，加热层320可位于相变材料层310下，加热层320用于加热相变材料层310，以改变相变材料层的相态。
本公开实施例中的加热层320包括由第一导电材料构成的第一部分321和由第二导电材料构成的第二部分322；第一部分321至少包围第二部分322的侧壁。通过使用两种导电材料，可以结合两种导电材料的优点，使得相变存储器的复位电流更低，加热效率更高，而加热效率提高，可使用更低的工作电压对相变存储单元进行状态切换。
在一些实施例中，如图2所示，第二部分322贯穿第一部分321并与衬底210接触，且具有接触面。
在一些实施例中，如图3所示，第二部分322的底部与第一部分321连接，而未接触衬底。
在一些实施例中，如图4所示，第二部分322贯穿第一部分321并与衬底210部分接触。
加热层320的俯视剖面图如图5至图8所示，如图5所示，加热层320的俯视图可为四边形(包括正方形)，第二部分322的俯视图可为四边形(包括正方形)，第一部分321的俯视图可为中间挖去四边形的四边形。如图6所示，第一部分321的俯视图可为四边形(包括正方形)，第二部分322的俯视图可为椭圆形(包括圆形)，第一部分321的俯视图可为中间挖去椭圆形的四边形。如图7所示，第一部分321的俯视图可为椭圆形(包括圆形)，第二部分322的俯视图可为椭圆形(包括圆形)，第一部分321的俯视图可为中间挖去椭圆形的椭圆形。如图8所示，第一部分321的俯视图可为椭圆形(包括圆形)，第二部分322的俯视图可为四边形(包括正方形)，第一部分321的俯视图可为中间挖去四边形的椭圆形。以上只是加热层320的俯视剖面图的4个示例，加热层320或第一部分321的俯视剖面图还可以包括三角形和其他多边形等，在此不再赘述。
但无论是哪一种结构，第一部分321都至少包围第二部分322的侧壁，从而可以减少第二部分所用导电材料被加热后热量的损失，从而提高加热效率。
本公开实施例中，利用两种导电材料形成了加热层320，并且加热层320具有第一部分321和第二部分322，并且第一部分321至少包围第二部分322的侧壁。这样不但可以利用第二部分所用的导电材料的优势提高加热效率，还可以利用第一部分包围第二部分的结构优势使得加热后的热量不易散失，更有利于进一步提高加热效率。加热效率提高后，相变材料层310发生相态转换的时间更短，可以更快地发生相态转换，故可以提高数据写入的速率。
在一些实施例中，第一导电材料的第一导电系数小于第二导电材料的第二导电系数。
第一导电材料以及第二导电材料可以为：钨、钛、铜以及以上物质的化合物。
本公开实施例中，第一导电材料的第一导电系数可以小于第二导电材料的第二导电系数，即当选定了第一导电材料时，第一导电材料的第一导电系数也随即被确定。第二导电材料可以在导电系数大于第一导电系数中的材料中选择，这可以保证在加热器使用时，让大部分电流流向第二部分。
在一些实施例中，当选定了第一导电材料时，第一导电材料的第一导热系数随即被确定。在选取第二导电材料时，还可以在满足如下条件的导电材料中选取第二导电材料，该条件为：第二导电材料的第二导热系数大于第一导电材料的第一导热系数。这样使得第二部分的导热能力比第一部分的导热能力强，从而使得第一部分中的热量不易散失。
示例性地，第一导电材料可以为TaN，第二导电材料可以为TiN。TaN不但有很好的防散热效应，其也是导体的一种，且TiN/TaN结构具有好的电流配比。
本公开实施例不但因为采用了第一部分至少包围第二部分的侧壁的结构可以使得加热层的电阻增大外，还通过采用满足第一导电材料的第一导热系数小于第二导电材料的第二导热系数的材料，进一步使得热源集中在了加热器中，从而使得加热效应增强。
在一些实施例中，相变存储单元的侧壁及至少部分上表面还覆盖有保温层。保温层使用的材料的第三导热系数可以小于第一导电材料的第一导热系数，这样使得保温层的散热效果更差于第一导电材料，即使得加热器的热源不会轻易的散掉，进而增加加热效应。并且透过保温层的包覆作用，可以帮助加热效应。
在一些实施例中，保温层可以选用绝缘材料，优选地，可以选择SiN(氮化硅)。
在一些实施例中，如图9所示，相变存储单元300还包括：二极管330，垂直于衬底210；二极管330位于衬底210与加热层320之间，二极管320的导通方向为由加热层320指向衬底210。
二极管330位于衬底210与加热层320之间且垂直于衬底210的表面放置，使得电流可以从加热层320流向衬底210，即电流的流向可以是垂直衬底210表面的。二极管330的数量可以为一个也可以为多个，多个二极管330可以串联在衬底210与加热层320之间。二极管330导通时可以产生电流从而驱动相变存储单元300进行数据的写入、读取与擦除等操作。
在一些实施例中，如图9所示，二极管330包括：第一离子注入结构331，位于衬底210上；第二离子注入结构332，位于第一离子注入结构331上；第一离子注入结构331的离子类型与第二离子注入结构332的离子类型的相反。
第一离子注入结构331可以是在衬底210上掺杂形成的，也可以是通过对衬底210外延生长所形成的外延层进行掺杂形成的。掺杂的杂质种类可以分为N型和P型两类。N型主要包括磷(P)、砷(As)以及锑(Sb)等。P型主要包括硼(B)以及铟(In)等。
第二离子注入结构332可以是在衬底210上掺杂形成的，也可以是通过对衬底210外延生长所形成的外延层进行掺杂形成的。掺杂的杂质种类可以分为N型和P型两类。N型主要包括磷(P)、砷(As)以及锑(Sb)等。P型主要包括硼(B)以及铟(In)等。
这里需要注意的是，因为第一离子注入结构331与第二离子注入结构332是用于形成二极管330的，故第一离子注入结构331与第二离子注入结构332的所注入的类型是相反的。在本公开实施例中，上述第一离子注入结构331可以是N型掺杂，第二离子注入结构332可以是P型掺杂。
在一些实施例中，若第一离子注入结构331和第二离子注入结构332都是通过在衬底上掺杂形成的，那么形成第一离子注入结构331所进行的第一注入深度要深于形成第二离子注入332所进行的第二注入深度。
在一些实施例中，若第一离子注入结构331和第二离子注入结构332都是通过对衬底210外延生长所形成的外延层掺杂形成的，那么可以首先通过第一次外延生长形成第一外延层，然后对第一外延层进行掺杂形成第一离子注入结构。然后对第一外延层进行掺杂形成第一离子注入结构331，对第二外延层进行掺杂形成第二离子注入结构332。
在一些实施例中，如图10所示，第二离子注入结构332包括：上层第二离子注入结构3322和下层第二离子注入结构3321，上层第二离子注入结构3322的离子浓度与下层第二离子注入结构的离子浓度3321不同。
第二离子注入结构332可以包括至少两层，当其为两层时，其具有上层第二离子注入结构3322和下层第二离子注入结构3321。上层第二离子注入结构3322的掺杂离子的类型与下层第二离子注入结构掺杂离子的类型可以是相同的。例如，上层第二离子注入结构3322的掺杂离子为P型掺杂离子，则下层第二离子注入结构掺杂离子也可为P型掺杂离子。
在一些实施例中，上层第二离子注入结构3322的离子浓度与下层第二离子注入结构的离子浓度3321不同。例如，上层第二离子注入结构3322的离子浓度可以大于下层第二离子注入结构的离子浓度3321。对上层第二离子注入结构3322掺杂较高浓度的离子可用于增加二极管330中PN结的电导率。下层第二离子注入结构3321可以利用其掺杂的离子浓度或其厚度来调节二极管330的阈值电压。采用多层结构形成第二离子注入结构332可以提高二极管330的性能。
在一些实施例中，如图11所示(图11为衬底的三维结构示意图)，衬底包括：背衬底213；埋 氧层212，位于背衬底213上；掺杂结构350，位于埋氧层212上，掺杂结构350与第一离子注入结构直接接触；浅沟槽隔离结构360，位于相邻掺杂结构350之间。
掺杂结构350与上述第一离子注入结构直接接触以连接沿第一方向排布的多个相变存储单元。即沿第一方向的多个相变存储单元与掺杂结构350的接触点或接触面是等电位的。第一方向可为沿平行于衬底表面的任一方向，在一些实施例中，第一方向可与后续形成的字线或位线方向相同。
掺杂结构350可以是对埋氧层212上的顶层硅进行多次掺杂后形成的。
在一些实施例中，如图11所示，衬底具有掺杂结构350；如图12所示(图12为半导体结构沿Y方向的剖面图)，半导体结构还包括：浅沟槽隔离结构360，位于相邻掺杂结构350之间；这里，浅沟槽隔离结构360用于隔离相邻的掺杂结构350。
具体地，浅沟槽隔离结构360用于沿Y方向隔离相邻的掺杂结构350，使在Y方向不重叠的相变存储单元300之间彼此电性隔离。Y方向与X方向的关系可以为垂直或相交。
浅沟槽隔离结构360的材质可为绝缘材料，例如氧化硅、氮化物及其组合物等。
在一些实施例中，如图11所示，掺杂结构包括：N阱351，位于埋氧层212上；P阱352，位于N阱351上；第三离子注入结构353，位于P阱352表面与第一离子注入结构直接接触。
在一些实施例中，可通过对顶层硅进行三次深度不同的离子注入形成N阱层、P阱层以及第三离子注入结构层。其中N阱层掺杂有N型离子，P阱层掺杂有P型离子，第三离子注入结构层的掺杂离子的类型与第一离子注入结构注入的掺杂离子的类型可以相同。
刻蚀N阱层、P阱层以及第三离子注入结构层以形成N阱351、P阱352以及第三离子注入结构353所构成的掺杂结构350。第三离子注入结构353与第一离子注入结构之间接触，从而电流可从第三离子注入结构353流入第一离子注入结构中。第三离子注入层可以是重掺杂形成的，故后续形成的第三离子注入结构也是重掺杂的，其具有电阻率低，电阻小，导电能力增强的特点。
N阱与P阱用于形成反偏的PN结以隔离相变存储单元300与埋氧层212以及背衬底213，避免漏电现象。
在一些实施例中，如图13所示，半导体结构还包括：层间介质层370，位于各相变存储单元300之间；第一导电结构380，贯穿层间介质层370且连接第三离子注入结构353。
各相变存储单元300之间还可具有层间介质层370，层间介质层370用于对各相变存储单元300之间进行电性隔离，减少寄生电容。层间介质层370的材质可为绝缘材料。
每个第三离子注入结构353都可连接一贯穿层间介质层370的第一导电结构380。
第一导电结构380至少包括第一接触结构382(CT，Contact)，第一接触结构可以为一个也可以为相互堆叠的多个接触结构。
第一接触结构382上可还包括第一导电插塞383，第一导电插塞383用于降低相邻第一接触结构382之间或第一接触结构382与其他结构之间的欧姆接触。
第一接触结构382的材质可以为金属材质。
第一导电插塞383的材质可以为金属，例如Ti和或TiN。
在一些实施例中，如图13所示，半导体结构还包括：第二导电结构390，连接相变存储单元300；其中，第一导电结构380与沿平行于衬底的第一方向延伸的第一导电线381连接，第二导电结构390与沿平行于衬底的第二方向延伸的第二导电线391连接，第二方向与第一方向相交。
在一些实施例中，在第一方向(X方向)上重叠的多个相变存储单元上还可共用同一第二导电结构390，相邻的第二导电结构390之间沿第二方向(Y方向)相互平行。
第二导电结构至少包括第二接触结构392，第二接触结构可以为一个也可以为相互堆叠的多个接触结构。各第二接触结构392之上还包括第二导电插塞393，第二导电插塞393用于降低相邻第二接触结构392之间或第二接触结构392与其他结构之间的欧姆接触。第二接触结构392的材质可以为金属材质。第二导电插塞393的材质可以为金属，例如Ti和或TiN。
在一些实施例中，第二导电结构还包括第二导电线391，第二导电线沿第Y方向延伸。第一导电结构380还包括第一导电线381，第一导电线381沿第X方向延伸。第一导电线381可用于形成字线或位线。第二导电线391也可用于形成字线或位线。在一些实施例中，第一导电线381与第二导电线391在空间上不相交。即第一导电线381与第二导电线391之间还可具有层间介质层。本公开实施例中，第一导电线381可为字线，则第二导电线391可为位线。通过对位线和/或字线施加不同的电压，则可以实现对相变存储单元进行数据的存储和读取。
本公开实施例还提供一种半导体结构的形成方法，如图14所示，包括：
步骤S101、提供衬底；
步骤S102、在衬底上形成相变存储单元；相变存储单元包括：
相变材料层和加热层，加热层位于相变材料层和衬底之间，且加热层包括由第一导电材料构成的第一部分和第二导电材料构成的第二部分，第二部分至少包围第一部分的侧壁。
首先，执行步骤S101，提供一衬底，衬底的表面为与衬底厚度方向垂直的任意一个表面。定义 衬底的厚度方向或者与衬底的表面垂直的方向为Z方向，定义沿衬底表面的任一方向为X方向，沿衬底表面与X方向相交的方向为Y方向。本公开实施例中所使用的衬底可为如图16所示的SOI衬底210，该衬底210包括顶层硅211、埋氧层212以及背衬底213。其中，顶层硅211可为超薄单晶硅，埋氧层212可为氧化硅、背衬底213可为单晶硅。
在执行步骤S102之前，还可以对衬底进行清洗以去除表面的杂质。
然后执行步骤S102，通过生长工艺或沉积工艺形成待处理的相变材料层和待处理的加热层；其中，待处理的加热层位于衬底上，待处理的相变材料层位于待处理的加热层上。然后，通过刻蚀工艺对待处理的相变材料层和待处理的加热层进行刻蚀处理形成所需的相变材料层和所需的加热层以形成相变存储单元。
本公开实施例中的加热层包括由第一导电材料构成的第一部分和第二导电材料构成的第二部分；第一部分至少包围第二部分的侧壁。
本公开实施例通过使用两种导电材料，可以结合两种导电材料的优点使得相变存储器的复位电流更低，加热效率更高。本公开实施例中的加热器由第二部分至少包围第一部分的侧壁组成，这种结构更有利于减少热量的散失，进一步提高加热效率。
在一些实施例中，该方法还包括：
步骤S201、形成保温层覆盖相变存储单元的侧壁和至少部分上表面。
在一些实施例中，可以在执行完步骤S102后，通过沉积工艺在相变存储单元的侧壁和至少部分上表面形成保温层。
在一些实施例中，步骤S201也可以和步骤S102交替执行，即在形成相变存储单元的加热层后，先对加热层的侧壁形成第一保温层，然后在形成相变材料层后，再对相变材料层的侧壁和至少部分上表面形成第二保温层。由第一保温层和第二保温层共同构成覆盖相变存储单元的侧壁和至少部分上表面的保温层。
在一些实施例中，相变存储单元还包括：二极管；在衬底上形成的相变存储单元包括：
步骤S301、在衬底上形成垂直于衬底的二极管；
步骤S302、在二极管上形成加热层；
步骤S303、在加热层上形成相变材料层。
相变存储单元还包括：位于衬底与加热层之间的二极管。故步骤S102还可以拆分为步骤S301、步骤S302以及步骤S303。
首先执行步骤S301，在衬底上形成垂直于衬底的二极管。然后执行步骤S302，在二极管上形成加热层。最后执行步骤S303、在加热层上形成相变材料层。
在一些实施例中，步骤S301中在衬底上形成垂直于衬底的二极管包括：
步骤S401、在衬底上形成第一离子注入层；
步骤S402、在第一离子注入层上形成第二离子注入层；第一离子注入层的离子类型与第二离子注入层的离子类型相反；
步骤S403、刻蚀第一离子注入层与第二离子注入层形成第一离子注入结构与第二离子注入结构，以构成二极管。
执行步骤S301可以包括步骤S401、步骤S402以及步骤S403。
在一些实施例中，可首先执行步骤S401，通过生长工艺(例如，外延生长)和离子注入工艺形成第一离子注入层。
然后继续执行步骤S402，在第一离子注入层上通过生长工艺(例如，外延生长)和离子注入工艺形成第二离子注入。
在一些实施例中，可通过生长工艺形成外延生长层，然后对该外延生长层进行不同深度的两次离子注入，形成第一离子注入层和第二离子注入层。
因为第一离子注入层和第二离子注入层后续用于形成二极管，故两者的离子类型相反。
形成第一离子注入层和第二离子注入层后，执行步骤S403，刻蚀第一离子注入层与第二离子注入层形成由第一离子注入结构与第二离子注入结构构成的二极管。具体地，可在第二离子注入层上涂覆光刻胶，使用掩膜版(掩膜版上的图案是不透光的)与光刻胶层对准，当光刻胶为正胶时，光刻胶被曝光的部分由非溶性物质变成了可溶性物质。通过化学溶剂可以把可以溶解的部分去掉，这样就会在光刻胶层上留下一个岛区，这个岛区和掩膜版不透光的部分对应。这个岛区的形状即为二极管形状。该二极管包括第一离子注入结构与第二离子注入结构。
在一些实施例中，步骤S402中形成第二离子注入层包括：
步骤S501、形成下层第二离子注入层；
步骤S502、形成位于下层第二离子注入层上的上层第二离子注入层；上层第二离子注入层的离子浓度与下层第二离子注入层的离子浓度不同。
在一些实施例中，步骤S402可替换为步骤S501和步骤S502。
在一些实施例中，在执行完步骤S401后，可先执行步骤S501：通过生长工艺(例如，外延生长)和离子注入工艺形成下层第二离子注入层。然后执行继续步骤S502：通过生长工艺(例如，外延生长)和离子注入工艺形成上层第二离子注入层。
在一些实施例中，可通过生长工艺形成外延生长层，然后对该外延生长层进行不同深度的三次离子注入，形成第一离子注入层、下层第二离子注入层以及上层第二离子注入层。上层第二离子注入层所注入的离子与下层离子注入层所注入的离子的类型可以是相同的，但两者所注入的离子的浓度可以是不同。
在一些实施例中，上层第二离子注入结构的离子浓度可以大于下层第二离子注入结构的离子浓度。上层第二离子注入结构掺杂较高浓度的离子可用于增加二极管PN结的电导率。下层第二离子注入结构可以利用其掺杂的离子浓度或其厚度来调节二极管的阈值电压。
在一些实施例中，步骤S302中二极管形成加热层包括：
步骤S601、在第二离子注入层上形成第一导电层；
步骤S602、刻蚀第一导电层形成多个凹槽结构；
步骤S603、在凹槽结构中填充第二导电材料，形成第二部分；
步骤S604、刻蚀第二部分以外的第一导电层，形成第一部分。
在一些实施例中，执行步骤S401和步骤S402后，可先不执行步骤S403，而是继续执行步骤S302。步骤S302包括步骤S601、步骤S602、步骤S603以及步骤S604。
首先执行步骤S601，利用沉积工艺沉积第一导电材料(例如，TaN)形成位于第二离子注入层上的第一导电层。然后执行步骤S602，刻蚀第一导电层形成多个凹槽结构；该凹槽结构可以贯穿第一导电层也可以不贯穿第一导电层。继续执行步骤S603，在凹槽结构中利用沉积工艺填充第二导电材料，形成第二部分；在一些实施例中，在对凹槽结构填充第二导电材料(例如，TiN)时，第二导电材料还可以覆盖至第一导电层的表面，此时可以利用CMP工艺去除覆盖至第一导电层表面的第二导电材料。继续执行步骤S604、刻蚀第一部分以外的第一导电层，形成第一部分。具体地，可在形成有第一部分的第一导电层上涂覆光刻胶，使用掩膜版(掩膜版上的图案是不透光的)与光刻胶层对准，当光刻胶为正胶时，光刻胶被曝光的部分由非溶性物质变成了可溶性物质。通过化学溶剂可以把可以溶解的部分去掉，这样就会在光刻胶层上留下一个岛区，这个岛区和掩膜版不透光的部分对应。这个岛区的形状即为加热层的形状。本公开实施例中，利用TiN/TaN结构塑造一个接触截面积缩小，在工艺上也有利于微缩。
在一些实施例中，衬底包括背衬底、位于背衬底上的埋氧层以及位于埋氧层上的顶层硅；在执行步骤S102在衬底上形成相变存储单元的之前，方法还包括：
步骤S701、对顶层硅进行掺杂形成掺杂层；掺杂层包括N阱层、P阱层以及第三离子注入层。
步骤S702、刻蚀掺杂层形成多个掺杂结构，掺杂结构包括N阱、P阱以及第三离子注入结构，第三离子注入结构与第一离子注入结构沿第一方向连接；形成浅沟槽隔离结构，填充相邻掺杂结构之间的凹槽。
在执行步骤S102之前，还可以执行步骤S701、形成位于埋氧层上的掺杂层；通过对顶层硅进行多次离子注入和/或热扩散工艺形成掺杂层。然后执行步骤S702，可以沿平行于衬底的第一方向刻蚀掺杂层形成由多个N阱、P阱以及第三离子注入结构构成的掺杂结构。第三离子注入结构与第一离子注入结构沿第一方向连接，即多个第三离子注入结构沿第一方向相互平行。所形成的第三离子注入结构与多个第一离子注入结构连接，使得多个位于同一第一方向的相变存储单元与同一第三离子注入结构连接。
在一些实施例中，该方法还包括：
步骤S801、填充相邻掺杂结构之间的凹槽形成浅沟槽隔离结构。
掺杂结构沿第一方向延伸，但也是沿第二方向排布的，所以相邻的掺杂结构在第一方向和第二方向上都有凹槽。执行步骤S801、利用沉积工艺沉积氧化物、氮化物或其组合物填充该凹槽，以形成浅沟槽隔离结构，故相邻的掺杂结构在第一方向和第二方向上都有浅沟槽隔离结构。浅沟槽隔离结构用于对掺杂结构、以及后续形成在掺杂结构之上的器件(例如，相变存储单元)进行电性隔离。
在一些实施例中，该方法还包括：
步骤S901、形成层间介质层，填充在多个相变存储单元之间；
步骤S902、形成第一导电结构，贯穿层间介质层且连接第三离子注入结构。
在一些实施例中，可以在执行步骤S102之后执行步骤S901。利用沉积工艺沉积绝缘材质在多个相变存储单元之间形成层间介质层。
在一些实施例中，可在交替执行步骤S102和步骤S901，例如，可在形成二极管和加热层后，首先在二极管和加热层之间沉积绝缘材质形成第一层间介质层。然后在形成相变材料层后，继续在相变材料层之间沉积绝缘材质形成第二层间介质层。由第一层间介质层和第二层间介质层共同构成层间介质层。
然后执行步骤S902，对层间介质层进行刻蚀，可将第三离子注入层作为刻蚀的停止层。刻蚀后形成贯穿层间介质层的凹槽结构，可利用导电材料使用沉积工艺对其进行填充，形成贯穿层间介质层且连接第三离子注入结构的第一导电结构。第一导电结构至少包括第一接触结构。在一些实施例中，第一导电结构还可以包括第一接触结构之上的第一导电插塞。
在一些实施例中，该方法还包括：
步骤S1001、形成第二导电结构，连接相变存储单元；
其中，第一导电结构与沿平行于衬底的第一方向延伸的第一导电线连接；第二导电结构与沿平行于衬底的第二方向延伸的第二导电线连接，第二方向与第一方向相交。
在执行步骤S102之后，还可以继续执行步骤S1001以形成连接相变存储单元表面的第二导电结构。第二导电结构至少包括第二接触结构。在一些实施例中，第二导电结构还可以包括第二接触结构之上的第二导电插塞。
在一些实施例中，第一导电结构上还可以使用沉积工艺形成第一导电线，第一导电线沿平行于衬底的第一方向延伸。第二导电结构上还可以使用沉积工艺形成第二导电线，第二导电线沿平行于衬底的第二方向延伸。在一些实施例中，第一导电线可为位线，第二导电线可为字线。或者，第一导电线可为字线，第二导电线可为位线。
本公开实施例还有如下示例：
首先执行步骤S101，提供如图15所示的衬底210，该衬底可以为SOI衬底。定义衬底的厚度方向或者与衬底的表面垂直的方向为Z方向，定义沿衬底表面的任一方向为X方向，沿衬底表面与X方向相交的方向为Y方向。提供衬底后还可以对衬底进行清洗，洗去表面的杂质。SOI衬底210包括：背衬底213、埋氧层212以及顶层硅211。
然后执行步骤S701，从衬底的上表面对顶层硅进行三次深度不同的离子注入掺杂层；掺杂层包括N阱层、P阱层以及第三离子注入层。其中，N阱层的离子注入深度大于P阱层的离子注入深度大于四散离子注入层的离子注入深度。
然后执行步骤S702，刻蚀掺杂层形成多个掺杂结构，掺杂结构包括N阱、P阱以及第三离子注入结构，第三离子注入结构与第一离子注入结构沿第一方向连接。沿X方向对掺杂层进行刻蚀，以形成多个掺杂结构。此时，相邻的掺杂结构之间具有凹槽。
然后执行步骤S801，填充相邻掺杂结构之间的凹槽形成的浅沟槽隔离结构。
本公开实施例中，还可以对掺杂结构在Y方向的非器件区进行刻蚀，刻蚀后在Y方向上可形成两个在器件区两侧的凹槽，在两个凹槽之间的器件区的掺杂结构上可继续形成相变存储单元阵列。然后使用沉积工艺填充器件区两侧的凹槽形成Y方向上的两个浅沟槽隔离结构。以上实施例中的数量仅为示意，在非器件区的Y方向上还可以形成其他数量的凹槽结构。
执行完上述步骤的半导体结构如图16和图17所示，其中，图16为该半导体结构沿X方向的剖面图，图17为该半导体结构沿Y方向的剖面图。
图16沿Z轴正方向看，依次为背衬底213、埋氧层212、掺杂结构350(包括N阱351、P阱352以及第三离子注入结构353)。掺杂结构350的两端还包括两个浅沟槽隔离结构360。两个浅沟槽隔离结构360之间的区域可以作为器件区，后续用于形成半导体元件，例如相变存储单元。
图17沿Z轴正方向看，依次为背衬底213、埋氧层212、多个浅沟槽隔离结构360以及位于浅沟槽隔离结构360之间的掺杂结构350。浅沟槽隔离结构360与掺杂结构350在Z方向位于同一水平方向上。
然后执行步骤S401、在如图16和图17所示的半导体结构上继续进行外延生长形成第一外延生长的硅层后注入高掺杂的N型离子，以形成如图18和图19所示的第一离子注入层331。其中，图18为该半导体结构沿X方向的剖面图，图19为该半导体结构沿Y方向的剖面图。
然后执行步骤S501、在第一离子注入层331上继续进行外延生长形成第二外延生长的硅层后注入N型离子，以形成如图18和图19中所示的下层第二离子注入层3321。
然后执行步骤S502、在下层第二离子注入层3321上继续进行外延生长形成第三外延生长的硅层后注入高掺杂的P型离子，以形成如图18和图19中所示的上层第二离子注入层3332。
然后执行步骤S601、使用沉积工艺(例如，化学气相沉积)沉积第一导电材料(例如，TaN)形成位于第二离子注入层上的第一导电层。
然后执行步骤S602、通过光罩、刻蚀等工艺处理第一导电层形成贯穿第一导电层的多个凹槽结构。然后还可以对形成的凹槽结构的表面进行清洗，以去除其表面的原生氧化层。
然后执行步骤S603、在凹槽结构中使用沉积工艺(例如，原子层沉积)沉积第二导电材料(如，TiN)形成如图20和图21所示的第二部分322。其中，图20为该半导体结构沿X方向的剖面图，图21为该半导体结构沿Y方向的剖面图。在一些实施例中，TiN还会沉积到TaN层(即第一导电层)上，此时可以对沉积在TaN层(即第一导电层)上的TiN进行化学机械抛光，直到TaN层显露。
然后执行步骤S604和步骤S403、使用光罩、刻蚀工艺刻蚀第二部分以外的部分第一导电层和 该部分第一导电层下的第一离子注入层与第二离子注入层，刻蚀停止层为第三离子注入结构，以形成如图22和图23所示的加热层320和二极管330。其中，加热层320的三维结构如图24所示，其包括第二部分322和第一部分321，第二部分322可为圆柱结构，第一部分321可为中间挖去圆柱的长方体，可以看出，第一部分321覆盖第二部分322的全部侧壁。
然后执行步骤S201，沉积保温材料(例如，SiN)以形成第一保温层410。沿X方向看，如图25所示，第一保温层可覆盖二极管330的侧壁、加热层320的侧壁、加热层320的表面以及第三离子注入结构353的表面。沿Y方向看，如图26所示，第一保温层可覆盖二极管330的侧壁、加热层320的侧壁、加热层320的表面以及浅沟槽隔离360的表面。
在一些实施例中，在执行步骤S201之前，还可以对第一结构(加热层和二极管)之间的凹槽结构的表面进行清洗，以去除其表面的原生氧化层。
然后执行步骤S901，在二极管和加热层之间沉积绝缘材质(例如，氮化硅)形成第一层间介质层。沉积第一层间介质层时，第一层间介质层370还可以覆盖加热层330上的第一保温层410。此时可以使用刻蚀工艺(例如，CMP)去除加热层330上的第一保温层410和第一层间介质层370，直到暴露加热层330。步骤S901执行完毕后可形成如图27和图28所示的半导体结构。其中，图27为该半导体结构沿X方向的剖面图，图28为该半导体结构沿Y方向的剖面图。
沿X方向看，如图27所示，第一保温层410覆盖加热层330和二极管320的侧壁以及第三离子注入层353的上表面。相邻的第一结构(加热层300和二极管320)之间具有第一层间介质层370。
沿Y方向看，如图28所示，第一保温层410覆盖加热层330和二极管320的侧壁以及浅沟槽隔离结构360的上表面。相邻的第一结构(加热层300和二极管320)之间具有第一层间介质层370。
然后执行步骤S303，首先使用沉积工艺沉积相变材料(例如，GST)形成相变材料层，然后通过光罩、刻蚀等工艺处理该相变材料层，以形成如图29和图30所示的位于加热层320上的相变材料结构310。在一些实施例中，相变材料结构310的宽度(沿X方向上的)和长度(沿Y方向上的)可以大于加热层320，即相变材料结构310可完全覆盖加热层330的上表面。
使用本公开实施例的方法形成的相邻相变材料结构之间的距离可缩小至0.07μm，各相变存储单元之间的间距和相变存储单元的堆叠层数较小，故大大提高了单位面积上存储单元的存储密度。
然后再次执行步骤S201，在相变材料结构310之间沉积保温材料(SiN)以形成如图31和图32所示的第二保温层420，第二保温层420覆盖相变材料结构310的侧壁和上表面还覆盖第一层间介质层370的上表面。
然后执行再次步骤S901，在上述第二保温层420上沉积绝缘材料(例如，氧化硅)，以形成如图33和图34所示的第二层间介质层371。
然后执行步骤S902和步骤S1001，形成如图35和图36所示的贯穿第一层间介质层和第二层间介质层且连接第三离子注入结构的第一导电结构和形成连接相变存储单元表面的第二导电结构。
具体地，在相变存储单元阵列与浅沟槽隔离(沿X方向具有两个浅沟槽隔离可以任选一个)之间沿Y方向进行光罩、刻蚀等工艺，并以第三离子注入结构作为刻蚀停止层，形成在X方向上重叠，在Y方向上平行的多个凹槽结构，该凹槽结构贯穿第一层间介质层和第二层间介质层且连接第三离子注入结构。
在相变存储单元阵列上，沿X方向和Y方向，使用光罩、刻蚀等工艺，并以相变材料结构作为刻蚀停止层，形成位于相变材料结构上的开口结构，该开口结构的宽度(沿X方向)小于或等于相变材料结构的宽度，该开口的长度(沿Y方向)也小于或等于相变材料结构的长度。
然后利用沉积工艺(例如，原子层沉积)沉积导电材料至上述凹槽结构和开口结构中形成第一接触结构382和第一导电插塞383以及第二接触结构392和第二导电插塞393。
然后在第二导电插塞393上沉积导电材料，并经过光罩和刻蚀工艺以形成覆盖第二导电插塞393的第二导电线391。如图36所示，第二导电线391沿Y方向延伸。如图35所示，各第二导电线391沿X方向相互平行。
使用本公开实施例的方法形成的相邻第二导电线391之间的距离可减少至0.07μm。
在图35和图36的基础上，继续沉积绝缘材料(例如，氧化硅)形成如图37和图38所示的第三层间介质层372，在第三层间介质层372上，通过光罩工艺和刻蚀工艺等形成贯穿第三介质层372连接第一接触插塞383的凹槽结构。
使用沉积工艺(例如，原子层沉积)形成位于第一接触插塞383之上的又一个第一接触结构382和又一个第一接触插塞383。该第一接触插塞383的上表面与第三层间介质层372的上表面平齐。
然后在第三层间介质层上通过光罩工艺和刻蚀工艺等形成沿X方向相互平行的第一导电线381。
本公开实施例中的第一层间介质层、第二层间介质层以及第三层间介质层所用的绝缘材料可以是相同的也可以是不同的。
图37和图38的半导体结构的俯视图如图39所示：位线沿Y方向延伸，相邻的位线沿X方向相互平行。
字线沿X方向延伸，相邻的字线沿Y方向相互平行。
综上，使用本公开实施例的方法形成的半导体结构的工艺简单，易于形成，且由于形成在SOI衬底上，则该半导体结构在拥有以上优点外，还具备SOI的优势(例如，更少的闩锁效应，更少的漏电流等等)。图37和图38的半导体结构所对应的电路图可以简化为图40，其中存储单元500包括一个相变存储单元和一个二极管。位于同一行的多个二极管可连接同一字线，位于同一列的多个相变存储单元可以连接同一位线。
对存储单元500进行编程操作包括：对选择的存储单元500所在的位线施加编程电压V pgm(例如，0.5V)，对其他未选中的位线施加地电压(例如，0V)。同时对选中的存储单元500所在的字线加地电压(例如，0V)，对未选择的字线施加一定的电压(例如，0.5V)。
对存储单元进行读取操作包括：对选择的存储单元500所在的位线施加读取电压(V read)，对其他未选中的位线施加地电压(例如，0V)。同时对选择的存储单元500所在的字线施加地电压(例如，0V)，对未选择的字线施加一定的电压(例如，0.5V)。其中，V read小于V pgm。
存储单元的IV曲线如图41所示：
曲线1为对存储单元进行读取操作时的电流-电压曲线。
曲线2为对存储单元进行写入操作时的电流-电压曲线。
图41中的电流-电压曲线表明：读取电压必须小于写入电压(写入电压的范围如阴影区域)，如此一来，在读取电压时，不会因为电压过大而导致相变存储器转态。一般来说，写入操作分为RESET操作和SET操作，而电压范围大概在阴影区域。再通过不同脉冲时间做写入动作，其中，SET操作可为较长脉冲时间，RESET可为较短脉冲时间。
最后，本公开实施例还提供了一种存储器，如图42所示，该存储器40包括含有如上述实施例任一的半导体结构10的存储单元阵列20，以及位于存储单元阵列20上方或者外侧的外围电路30结构。
上述实施例中的半导体结构10的全部或局部结构可以用于构成存储单元阵列20，存储单元阵列20的存储单元包括相变存储单元。
外围电路30可以包括任何合适的模拟、数字以及混合信号电路，以对存储单元阵列20进行相关操作。操作包括读、写、擦等等。
存储器40可以为相变存储器。
该存储器为三维结构，其具有更高的存储密度、更低功耗和更容易的存取操作，该存储器的加热器具有更小的体积，使得加热效率更高，写入速度更快，该存储器还具有本公开实施例任一的半导体结构的其他优点。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例中，利用两种导电材料形成了加热层，并且加热层具有第一部分和第二部分，并且第一部分至少包围第二部分的侧壁。这样不但可以利用第一部分的导电材料的优势提高加热效率，还可以利用第二部分包围第一部分使得加热后的热量不易散失，更有利于进一步提高加热效率。加热效率提高后，可使得相变材料层发生相态转换所需的时间更短，故可以更快地发生相态转换，从而可以提高数据写入的速率。

Claims (20)

  1. 一种半导体结构，所述半导体结构包括：
    衬底；
    相变存储单元，位于所述衬底上；
    所述相变存储单元包括：相变材料层和加热层，所述加热层位于所述相变材料层和所述衬底之间；
    所述加热层包括由第一导电材料构成的第一部分和由第二导电材料构成的第二部分，所述第一部分至少包围所述第二部分的侧壁。
  2. 根据权利要求1所述的半导体结构，其中，所述第一导电材料的第一导电系数小于所述第二导电材料的第二导电系数。
  3. 根据权利要求1所述的半导体结构，其中，所述相变存储单元的侧壁及至少部分上表面还覆盖有保温层。
  4. 根据权利要求1所述的半导体结构，其中，所述相变存储单元还包括：
    二极管，垂直于所述衬底，所述二极管位于所述衬底与所述加热层之间，所述二极管的导通方向为由所述加热层指向所述衬底。
  5. 根据权利要求4所述的半导体结构，其中，所述二极管包括：
    第一离子注入结构，位于所述衬底上；
    第二离子注入结构，位于所述第一离子注入结构上；
    所述第一离子注入结构的离子类型与所述第二离子注入结构的离子类型相反。
  6. 根据权利要求5所述的半导体结构，其中，所述第二离子注入结构包括：
    上层第二离子注入结构和下层第二离子注入结构，所述上层第二离子注入结构的离子浓度与所述下层第二离子注入结构的离子浓度不同。
  7. 根据权利要求5所述的半导体结构，其中，所述衬底包括：
    背衬底；
    埋氧层，位于所述背衬底上；
    掺杂结构，位于所述埋氧层上，所述掺杂结构与所述第一离子注入结构直接接触；
    浅沟槽隔离结构，位于相邻所述掺杂结构之间。
  8. 根据权利要求7所述的半导体结构，其中，所述掺杂结构包括：
    N阱，位于所述埋氧层上；
    P阱，位于所述N阱上；
    第三离子注入结构，位于所述P阱表面与所述第一离子注入结构直接接触。
  9. 根据权利要求8所述的半导体结构，其中，所述半导体结构还包括：
    层间介质层，位于各所述相变存储单元之间；
    第一导电结构，贯穿所述层间介质层且连接所述第三离子注入结构。
  10. 根据权利要求9所述的半导体结构，其中，所述半导体结构还包括：
    第二导电结构，连接所述相变存储单元；
    其中，所述第一导电结构与沿平行于所述衬底的第一方向延伸的第一导电线连接，所述第二导电结构与沿平行于所述衬底的第二方向延伸的第二导电线连接，所述第二方向与所述第一方向相交。
  11. 一种半导体结构的形成方法，所述方法包括：
    提供衬底；
    在所述衬底上形成相变存储单元；所述相变存储单元包括：
    相变材料层和加热层，所述加热层位于所述相变材料层和所述衬底之间，且所述加热层包括由第一导电材料构成的第一部分和第二导电材料构成的第二部分，所述第一部分至少包围所述第二部分的侧壁。
  12. 根据权利要求11所述的形成方法，其中，所述方法还包括：
    形成保温层覆盖所述相变存储单元的侧壁和至少部分上表面。
  13. 根据权利要求11所述的形成方法，其中，所述相变存储单元还包括：二极管；在所述衬底上形成相变存储单元包括：
    在所述衬底上形成垂直于所述衬底的二极管；
    在所述二极管上形成所述加热层；
    在所述加热层上形成所述相变材料层。
  14. 根据权利要求13所述的形成方法，其中，在所述衬底上形成垂直于所述衬底的二极管包括：
    在所述衬底上形成第一离子注入层；
    在所述第一离子注入层上形成第二离子注入层；所述第一离子注入层的离子类型与所述第二离子注入层的离子类型相反；
    刻蚀所述第一离子注入层与所述第二离子注入层形成第一离子注入结构与第二离子注入结构，以构成所述二极管。
  15. 根据权利要求14所述的形成方法，其中，形成第二离子注入层包括：
    形成下层第二离子注入层；
    在所述下层第二离子注入层上形成上层第二离子注入层；所述上层第二离子注入层的离子浓度与所述下层第二离子注入层的离子浓度不同。
  16. 根据权利要求14所述的形成方法，其中，在所述二极管上形成所述加热层包括：
    在所述第二离子注入层上形成第一导电层；
    刻蚀所述第一导电层形成多个凹槽结构；
    在所述凹槽结构中填充所述第二导电材料，形成所述第二部分；
    刻蚀所述第二部分以外的所述第一导电层，形成所述第一部分。
  17. 根据权利要求14所述的形成方法，其中，所述衬底包括背衬底、位于所述背衬底上的埋氧层以及位于所述埋氧层上的顶层硅；在所述衬底上形成相变存储单元的步骤之前，所述方法还包括：
    对所述顶层硅进行掺杂形成掺杂层；所述掺杂层包括N阱层、P阱层以及第三离子注入层；
    刻蚀所述掺杂层形成多个掺杂结构，所述掺杂结构包括N阱、P阱以及第三离子注入结构，所述第三离子注入结构与所述第一离子注入结构连接；
    形成浅沟槽隔离结构，填充相邻所述掺杂结构之间的凹槽。
  18. 根据权利要求17所述的形成方法，其中，所述方法还包括：
    形成层间介质层，填充在多个所述相变存储单元之间；
    形成第一导电结构，贯穿所述层间介质层且连接所述第三离子注入结构。
  19. 根据权利要求18所述的形成方法，其中，所述方法还包括：
    形成第二导电结构，连接所述相变存储单元；
    其中，所述第一导电结构与沿平行于所述衬底的第一方向延伸的第一导电线连接；所述第二导电结构与沿平行于所述衬底的第二方向延伸的第二导电线连接，所述第二方向与所述第一方向相交。
  20. 一种存储器，所述存储器包括含有如权利要求1至10任一所述的半导体结构的存储单元阵列，以及位于所述存储单元阵列上方或者外侧的外围电路结构。
PCT/CN2022/108178 2022-07-04 2022-07-27 半导体结构及其形成方法、存储器 Ceased WO2024007381A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/155,656 US12622183B2 (en) 2022-07-04 2023-01-17 Phase change memory (PCM) cell structure having heating layer and formation method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210786445.1A CN117412664A (zh) 2022-07-04 2022-07-04 半导体结构及其形成方法、存储器
CN202210786445.1 2022-07-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/155,656 Continuation US12622183B2 (en) 2022-07-04 2023-01-17 Phase change memory (PCM) cell structure having heating layer and formation method therefor

Publications (1)

Publication Number Publication Date
WO2024007381A1 true WO2024007381A1 (zh) 2024-01-11

Family

ID=89454034

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/108178 Ceased WO2024007381A1 (zh) 2022-07-04 2022-07-27 半导体结构及其形成方法、存储器

Country Status (2)

Country Link
CN (1) CN117412664A (zh)
WO (1) WO2024007381A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101504967A (zh) * 2008-02-05 2009-08-12 旺宏电子股份有限公司 中心加热相变化存储器结构及其制造方法
US20110073829A1 (en) * 2009-09-30 2011-03-31 Hynix Semiconductor Inc. Phase change memory device having a heater with a temperature dependent resistivity, method of manufacturing the same, and circuit of the same
US20130240820A1 (en) * 2010-07-30 2013-09-19 SK Hynix Inc. Phase change random access memory and fabrication method of heating electrode for the same
US8624215B2 (en) * 2005-12-20 2014-01-07 University Of Southampton Phase change memory devices and methods comprising gallium, lanthanide and chalcogenide compounds
CN112635667A (zh) * 2020-12-30 2021-04-09 上海集成电路装备材料产业创新中心有限公司 一种相变存储器单元及其制备方法
US20210242401A1 (en) * 2020-01-31 2021-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and programming method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8624215B2 (en) * 2005-12-20 2014-01-07 University Of Southampton Phase change memory devices and methods comprising gallium, lanthanide and chalcogenide compounds
CN101504967A (zh) * 2008-02-05 2009-08-12 旺宏电子股份有限公司 中心加热相变化存储器结构及其制造方法
US20110073829A1 (en) * 2009-09-30 2011-03-31 Hynix Semiconductor Inc. Phase change memory device having a heater with a temperature dependent resistivity, method of manufacturing the same, and circuit of the same
US20130240820A1 (en) * 2010-07-30 2013-09-19 SK Hynix Inc. Phase change random access memory and fabrication method of heating electrode for the same
US20210242401A1 (en) * 2020-01-31 2021-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and programming method thereof
CN112635667A (zh) * 2020-12-30 2021-04-09 上海集成电路装备材料产业创新中心有限公司 一种相变存储器单元及其制备方法

Also Published As

Publication number Publication date
CN117412664A (zh) 2024-01-16

Similar Documents

Publication Publication Date Title
US8394670B2 (en) Vertical diodes for non-volatile memory device
US7768016B2 (en) Carbon diode array for resistivity changing memories
CN103633108A (zh) 三维层叠存储器件
CN102820299A (zh) 存储器件
KR101781624B1 (ko) 가변 저항 메모리 소자 및 그 제조 방법
US20140183434A1 (en) Variable resistance memory devices and methods of forming the same
US10026780B2 (en) Superlattice memory and crosspoint memory device
CN101483185B (zh) 存储器单元和存储器阵列
US20090008622A1 (en) Phase Change Memory Devices and Methods of Fabricating the Same
US20200027925A1 (en) Variable resistance memory device including symmetrical memory cell arrangements and method of forming the same
US20250142890A1 (en) Transistor including an active region and methods for forming the same
US20250176445A1 (en) Switching device having bi-directional drive characteristics and method of operating same
CN110660822B (zh) 可变电阻存储器装置
KR20140077500A (ko) 수직형 반도체 소자 및 그 제조 방법
CN102810632A (zh) 一种并联电阻型存储器及其制备方法
KR20130142522A (ko) 수직형 메모리 소자 및 그 제조 방법
US20120220087A1 (en) Variable resistance memory devices and methods of manufacturing the same
CN101673755B (zh) 使用复合结构二极管的相变存储器单元及制备方法
CN101976677B (zh) 基于ZnO肖特基二极管的相变随机存储器阵列及制作方法
US20240379872A1 (en) Thin film transistor including a compositionally-modulated active region and methods for forming the same
US20160104746A1 (en) Methods of fabricating a variable resistance memory device using masking and selective removal
WO2024007381A1 (zh) 半导体结构及其形成方法、存储器
US12622183B2 (en) Phase change memory (PCM) cell structure having heating layer and formation method therefor
US20240008376A1 (en) Semiconductor structure and formation method therefor, and memory
CN101752312B (zh) 具有双浅沟道隔离槽的高密度二极管阵列的制造方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22949959

Country of ref document: EP

Kind code of ref document: A1