WO2024007381A1 - Semiconductor structure and method for forming same, and memory - Google Patents

Abstract

A semiconductor structure and a method for forming same, and a memory. The semiconductor structure comprises: a substrate (210); and phase change storage units (300), located on the substrate (210). Each phase change storage unit (300) comprises a phase change material layer (310) and a heating layer (320), and the heating layer (320) is located between the phase change material layer (310) and the substrate (210); and the heating layer comprises a first part (321) made of a first conductive material and a second part (322) made of a second conductive material, and the first part (321) at least surrounds the side wall of the second part (322).

Description

Semiconductor structure and method of forming same, memory

Cross-references to related applications

This disclosure is based on a Chinese patent application with the application number 202210786445.1, the filing date is July 4, 2022, and the invention name is "Semiconductor Structure and Formation Method, Memory", and claims the priority of the Chinese patent application. The Chinese patent The entire contents of this application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a method of forming the same, and a memory.

Background technique

Phase Change Memory (PCM) is a new type of memory that utilizes the huge resistance difference between the crystalline and amorphous states of phase change materials to achieve information storage. Phase change materials have higher resistance in the amorphous state, and their molecular structures are in a disordered state; phase change materials have lower resistance in the crystalline state, and their internal molecular structures are in an ordered state. The difference in resistance between the two states is usually Reach 2 orders of magnitude.

The rapid transition of phase change materials between two resistance states (high resistance and low resistance) can be achieved through current-induced Joule heating.

Because PCM has the advantages of strong stability, low power consumption, high storage density, and compatibility with traditional CMOS processes, it has attracted the attention of more and more researchers and enterprises. With its huge advantages, PCM is considered to be one of the most promising next-generation non-volatile memories. How to improve the storage density and storage speed of PCM has become an urgent problem that needs to be solved.

Contents of the invention

In view of this, embodiments of the present disclosure provide a semiconductor structure, a method of forming the same, and a memory.

In a first aspect, embodiments of the present disclosure provide a semiconductor structure, including:

substrate;

A phase change memory unit located on the substrate;

The phase change memory unit includes: a phase change material layer and a heating layer, the heating layer being located between the phase change material layer and a substrate;

The heating layer includes a first portion made of a first conductive material and a second portion made of a second conductive material, the first portion surrounding at least a side wall of the second portion.

In some embodiments, the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.

In some embodiments, the side walls and at least part of the upper surface of the phase change memory unit are also covered with an insulation layer.

In some embodiments, the phase change memory unit further includes:

A diode is perpendicular to the substrate, the diode is located between the substrate and the heating layer, and the conduction direction of the diode is from the heating layer to the substrate.

In some embodiments, the diode includes:

A first ion implantation structure located on the substrate;

a second ion implantation structure located on the first ion implantation structure;

The ion type of the first ion implantation structure is opposite to the ion type of the second ion implantation structure.

In some embodiments, the second ion implantation structure includes:

The upper second ion implantation structure and the lower second ion implantation structure have different ion concentrations than the lower second ion implantation structure.

In some embodiments, the substrate includes:

backing substrate;

a buried oxide layer located on the back substrate;

a doping structure located on the buried oxide layer, the doping structure being in direct contact with the first ion implantation structure;

A shallow trench isolation structure is located between adjacent doped structures.

In some embodiments, the doped structure includes:

N well, located on the buried oxide layer;

P well, located on the N well;

The third ion implantation structure is located on the surface of the P well and is in direct contact with the first ion implantation structure.

In some embodiments, the semiconductor structure further includes:

An interlayer dielectric layer is located between each of the phase change memory units;

The first conductive structure penetrates the interlayer dielectric layer and is connected to the third ion implantation structure.

In some embodiments, the semiconductor structure further includes:

a second conductive structure connected to the phase change memory unit;

Wherein, the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate, and the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate. The conductive lines are connected, and the second direction intersects the first direction.

In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, including:

provide a substrate;

A phase change memory unit is formed on the substrate; the phase change memory unit includes:

A phase change material layer and a heating layer, the heating layer is located between the phase change material layer and the substrate, and the heating layer includes a first portion made of a first conductive material and a third portion made of a second conductive material. Two parts, the first part at least surrounds the side wall of the second part.

In some embodiments, the method further includes:

An insulation layer is formed to cover the side wall and at least part of the upper surface of the phase change memory unit.

In some embodiments, the phase change memory unit further includes: a diode; forming the phase change memory unit on the substrate includes:

forming a diode on the substrate perpendicular to the substrate;

forming the heating layer on the diode;

The phase change material layer is formed on the heating layer.

In some embodiments, forming a diode on the substrate perpendicular to the substrate includes:

forming a first ion implantation layer on the substrate;

forming a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;

The first ion implantation layer and the second ion implantation layer are etched to form a first ion implantation structure and a second ion implantation structure to form the diode.

In some embodiments, forming the second ion implantation layer includes:

Forming a lower second ion implantation layer;

An upper second ion implantation layer is formed on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from the ion concentration of the lower second ion implantation layer.

In some embodiments, forming the heating layer on the diode includes:

forming a first conductive layer on the second ion implantation layer;

Etching the first conductive layer to form a plurality of groove structures;

Filling the second conductive material in the groove structure to form the second part;

The first conductive layer other than the second part is etched to form the first part.

In some embodiments, the substrate includes a back substrate, a buried oxide layer on the back substrate, and a top layer of silicon on the buried oxide layer; a phase change memory cell is formed on the substrate. Before step, the method also includes:

The top layer of silicon is doped to form a doped layer; the doped layer includes an N well layer, a P well layer and a third ion implantation layer;

Etching the doped layer to form a plurality of doped structures, the doped structures including N wells, P wells and a third ion implantation structure, the third ion implantation structure is connected to the first ion implantation structure;

A shallow trench isolation structure is formed to fill the grooves between adjacent doped structures.

In some embodiments, the method further includes:

Form an interlayer dielectric layer and fill it between a plurality of the phase change memory cells;

A first conductive structure is formed, penetrating the interlayer dielectric layer and connecting the third ion implantation structure.

In some embodiments, the method further includes:

Form a second conductive structure to connect the phase change memory unit;

Wherein, the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate. The conductive lines are connected; the second direction intersects the first direction.

In a third aspect, embodiments of the present disclosure also provide a memory, which includes a memory cell array containing the semiconductor structure as described in any of the above embodiments, and a peripheral circuit structure located above or outside the memory cell array. .

In the embodiment of the present disclosure, the heating layer is formed using two conductive materials, and the heating layer has a first part and a second part, and the first part at least surrounds the side wall of the second part. In this way, not only can the advantages of the conductive material of the first part be used to improve the heating efficiency, but the second part can also be used to surround the first part so that the heated heat is not easily lost, which is more conducive to further improving the heating efficiency. After the heating efficiency is improved, the time required for the phase state conversion of the phase change material layer can be shortened, so the phase state conversion can occur faster, thereby increasing the data writing rate.

Description of the drawings

Figure 1 is a schematic diagram of a phase change memory provided in some embodiments;

2 to 4 are schematic cross-sectional views of a semiconductor structure provided in embodiments of the present disclosure;

5 to 8 are schematic top cross-sectional views of the heating layer provided by embodiments of the present disclosure;

9 to 13 are schematic cross-sectional views of a semiconductor structure provided by embodiments of the present disclosure;

Figure 14 is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

Figure 15 is a schematic diagram of a substrate provided by an embodiment of the present disclosure;

16 to 38 are schematic cross-sectional views of a semiconductor structure provided by embodiments of the present disclosure;

Figure 39 is a top view of a semiconductor structure provided by an embodiment of the present disclosure;

Figure 40 is a simplified circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure;

Figure 41 is a current-voltage curve of a memory cell with a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 42 is a schematic diagram of a memory formed by a semiconductor structure provided by an embodiment of the present disclosure.

Detailed ways

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described in more detail, by way of example, in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present disclosure.

It will be understood that the meanings of "on," "over," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" means not only It means "on" something without intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something with intervening features or layers.

In addition, for convenience of description, spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In embodiments of the present disclosure, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces. A layer can include multiple sub-layers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.

In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

The deposition process described in the embodiments of the present disclosure includes, but is not limited to, the deposition process may include, but is not limited to: chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical vapor deposition ( Plasma Enhanced CVD (PECVD), sputtering (Sputtering), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD) and their combinations, etc.

The growth processes described in the embodiments of the present disclosure include but are not limited to: vapor phase epitaxy (Vapor Phase Epitaxy, VPE), liquid phase epitaxy (Liquid Phase Epitaxy, LPE), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), ion beam epitaxy, Solid phase epitaxy and its combinations, etc.

The etching processes described in the embodiments of the present disclosure include, but are not limited to: dry etching, wet etching and combinations thereof.

The semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure. Here, the final device may include a three-dimensional PCM memory, or other memory chips or processing chips containing PCM memory cells.

Phase change memory is a new type of memory that utilizes the huge resistance difference between the crystalline and amorphous states of phase change materials to achieve information storage. Phase change materials have higher resistance in the amorphous state, and their molecular structures are in a disordered state; phase change materials have lower resistance in the crystalline state, and their internal molecular structures are in an ordered state. The difference in resistance between the two states is usually Reach 2 orders of magnitude.

The rapid transition of phase change materials between two resistance states (high resistance and low resistance) can be achieved through current-induced Joule heating. Because PCM has the advantages of strong stability, low power consumption, high storage density, and compatibility with traditional CMOS processes, it has attracted the attention of more and more researchers and enterprises. With its huge advantages, PCM is considered to be one of the most promising next-generation non-volatile memories.

In some embodiments, as shown in FIG. 1 , the phase change memory unit 100 in the phase change memory includes a planar MOS transistor 110 and a phase change unit 120 . The phase change unit 120 includes a KH (Key Heater, shaped heater) structure. The resistance value of the phase change material in the phase change material layer 130 in the phase change unit 120 can be changed by the shaped heater. The phase change material has high resistivity in the amorphous state and can be used to store data "1". Phase change materials have low resistivity in the crystalline state and can be used to store data "0". This utilizes the reversible phase change of phase change materials to store information.

The embodiment of the present disclosure provides a semiconductor structure, as shown in Figure 2. The semiconductor structure includes: a substrate 210; a phase change memory unit 300 located on the substrate 210; a phase change material layer 310 and a heating layer 320. The layer 320 is located between the phase change material layer 310 and the substrate 210; the heating layer 320 includes a first part 321 made of a first conductive material and a second part 322 made of a second conductive material, the first part 321 at least surrounding the second part 322 side walls.

The substrate 210 may include a P-type semiconductor material substrate (such as a silicon (Si) substrate or a germanium (Ge) substrate, etc.), an N-type semiconductor substrate (such as an indium phosphide (InP) substrate), or a compound semiconductor material. A substrate (such as a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In embodiments of the present disclosure, substrates such as silicon-on-insulator or germanium-on-insulator may be preferably used to reduce substrate leakage current.

The substrate 210 may have an array composed of a plurality of phase change memory cells 300, and the phase change memory cells are used to implement functions such as data storage, reading and writing.

Each phase change memory unit 300 may include a phase change material layer 310 and a heating layer 320 between the phase change material layer 310 and the substrate 210 . The phase change material layer 310 that can be used to store data has at least two clearly distinguishable solid phase structures. For example, one state can be an amorphous state, and the phase change material layer 310 can have high resistance when it is in an amorphous state, and The other state may be a crystalline state, and the phase change material layer may have low resistance when in the crystalline state. The stored data "0" and "1" are distinguished by the significantly different resistance values of the phase change material layer 310 in the amorphous state and the crystalline state. The transition from the metastable amorphous state to the stable crystalline state can be obtained by heating the amorphous state to the crystallization temperature and heating for a long enough time to fully crystallize. From the stable crystalline state to the amorphous state, the crystalline structure can be heated to melt and rapidly cooled, that is, it undergoes a rapid annealing process to condense and obtain the amorphous state. The phase change material layer 310 can be made of glass containing one or more chalcogenides. Chalcogenides include four elements from Group VIA of the periodic table of elements, namely oxygen (O) and sulfur (S). , selenium (Se) and tellurium (Te). The material of the phase change material layer 310 includes but is not limited to GeSbTe (germanium antimony tellurium) series alloy, which may at least include one or more of the following alloys: Ga/Sb (gallium/antimony), In/Sb (indium/antimony) , In/Se (indium/selenium), Sb/Te (antimony/tellurium), Ge/Te (germanium/tellurium), Ge/Sb/Te (germanium/antimony/tellurium), In/Sb/Te (indium/antimony / tellurium), Ga/Se/Te (gallium/selenium/tellurium), Sn/Sb/Te (tin/antimony/tellurium), In/Sb/Ge (indium/antimony/germanium), Ag/In/Sb/Te (Silver/indium/antimony/tellurium), Ge/Sn/Sb/Te (germanium/tin/antimony/tellurium), Ge/Sb/Se/Te (germanium/antimony/selenium/tellurium) and Te/Ge/Sb/ S (tellurium/germanium/antimony/sulfur).

The phase change memory unit 300 also includes a heating layer 320, which may be located under the phase change material layer 310. The heating layer 320 is used to heat the phase change material layer 310 to change the phase state of the phase change material layer.

The heating layer 320 in the embodiment of the present disclosure includes a first part 321 made of a first conductive material and a second part 322 made of a second conductive material; the first part 321 at least surrounds the side walls of the second part 322. By using two conductive materials, the advantages of the two conductive materials can be combined, so that the reset current of the phase change memory is lower and the heating efficiency is higher. The heating efficiency is improved, and a lower operating voltage can be used to change the state of the phase change memory cell. switch.

In some embodiments, as shown in FIG. 2 , the second part 322 penetrates the first part 321 and contacts the substrate 210 and has a contact surface.

In some embodiments, as shown in Figure 3, the bottom of second portion 322 is connected to first portion 321 without contacting the substrate.

In some embodiments, as shown in FIG. 4 , the second portion 322 extends through the first portion 321 and partially contacts the substrate 210 .

The top cross-sectional views of the heating layer 320 are shown in Figures 5 to 8. As shown in Figure 5, the top view of the heating layer 320 may be a quadrilateral (including a square), and the top view of the second part 322 may be a quadrilateral (including a square). The top view of part 321 can be a quadrilateral with a quadrilateral cut out in the middle. As shown in FIG. 6 , the top view of the first part 321 may be a quadrilateral (including a square), the top view of the second part 322 may be an ellipse (including a circle), and the top view of the first part 321 may be a quadrilateral with an oval cut out in the middle. As shown in FIG. 7 , the top view of the first part 321 may be an ellipse (including a circle), the top view of the second part 322 may be an ellipse (including a circle), and the top view of the first part 321 may be an ellipse with the middle cut out. Oval. As shown in FIG. 8 , the top view of the first part 321 may be an ellipse (including a circle), the top view of the second part 322 may be a quadrilateral (including a square), and the top view of the first part 321 may be an ellipse with the quadrilateral cut out in the middle. The above are only four examples of the top cross-sectional view of the heating layer 320. The top cross-sectional view of the heating layer 320 or the first part 321 may also include triangles and other polygons, which will not be described again here.

However, no matter which structure is used, the first part 321 at least surrounds the side walls of the second part 322, thereby reducing the heat loss after the conductive material used in the second part is heated, thereby improving the heating efficiency.

In the embodiment of the present disclosure, the heating layer 320 is formed using two conductive materials, and the heating layer 320 has a first part 321 and a second part 322, and the first part 321 at least surrounds the side wall of the second part 322. In this way, the advantages of the conductive material used in the second part can not only be used to improve the heating efficiency, but also the structural advantage of the first part surrounding the second part can be used to make the heated heat less likely to dissipate, which is more conducive to further improving the heating efficiency. After the heating efficiency is improved, the phase change time of the phase change material layer 310 is shorter, and the phase change can occur faster, so the data writing rate can be increased.

In some embodiments, the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.

The first conductive material and the second conductive material may be: tungsten, titanium, copper, and compounds of the above materials.

In embodiments of the present disclosure, the first conductivity of the first conductive material may be smaller than the second conductivity of the second conductive material. That is, when the first conductive material is selected, the first conductivity of the first conductive material is also immediately determined. Sure. The second conductive material can be selected from materials whose conductivity is greater than the first conductivity, which can ensure that most of the current flows to the second part when the heater is in use.

In some embodiments, when the first conductive material is selected, the first thermal conductivity of the first conductive material is determined. When selecting the second conductive material, the second conductive material may also be selected from conductive materials that meet the following conditions: the second thermal conductivity of the second conductive material is greater than the first thermal conductivity of the first conductive material. This makes the thermal conductivity of the second part stronger than that of the first part, so that the heat in the first part is not easily lost.

For example, the first conductive material may be TaN, and the second conductive material may be TiN. TaN not only has a good anti-heat dissipation effect, it is also a kind of conductor, and the TiN/TaN structure has a good current ratio.

The embodiments of the present disclosure not only increase the resistance of the heating layer by adopting a structure in which the first part at least surrounds the sidewall of the second part, but also adopt a third thermal conductivity coefficient that satisfies the requirement that the first conductive material is smaller than the second conductive material. The material with high thermal conductivity further concentrates the heat source in the heater, thereby enhancing the heating effect.

In some embodiments, the sidewalls and at least part of the upper surface of the phase change memory unit are also covered with an insulation layer. The third thermal conductivity of the material used in the insulation layer can be smaller than the first thermal conductivity of the first conductive material, which makes the heat dissipation effect of the insulation layer worse than that of the first conductive material, even if the heat source of the heater will not be easily dissipated. thereby increasing the heating effect. And through the coating of the insulation layer, the heating effect can be assisted.

In some embodiments, the insulation layer may be made of insulating material, preferably SiN (silicon nitride).

In some embodiments, as shown in Figure 9, the phase change memory unit 300 also includes: a diode 330, perpendicular to the substrate 210; the diode 330 is located between the substrate 210 and the heating layer 320, and the conduction direction of the diode 320 is Heating layer 320 is directed toward substrate 210 .

The diode 330 is located between the substrate 210 and the heating layer 320 and is placed perpendicularly to the surface of the substrate 210 so that current can flow from the heating layer 320 to the substrate 210 , that is, the direction of current flow can be perpendicular to the surface of the substrate 210 . The number of diodes 330 may be one or multiple, and multiple diodes 330 may be connected in series between the substrate 210 and the heating layer 320 . When the diode 330 is turned on, it can generate current to drive the phase change memory unit 300 to perform data writing, reading, erasing and other operations.

In some embodiments, as shown in FIG. 9 , the diode 330 includes: a first ion implantation structure 331 located on the substrate 210 ; a second ion implantation structure 332 located on the first ion implantation structure 331 ; the first ion implantation structure The ion type of 331 is opposite to that of the second ion implantation structure 332 .

The first ion implantation structure 331 may be formed by doping on the substrate 210 , or may be formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210 . The types of impurities doped can be divided into two categories: N-type and P-type. N-type mainly includes phosphorus (P), arsenic (As) and antimony (Sb). P-type mainly includes boron (B) and indium (In).

The second ion implantation structure 332 may be formed by doping on the substrate 210 , or may be formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210 . The types of impurities doped can be divided into two categories: N-type and P-type. N-type mainly includes phosphorus (P), arsenic (As) and antimony (Sb). P-type mainly includes boron (B) and indium (In).

It should be noted here that since the first ion implantation structure 331 and the second ion implantation structure 332 are used to form the diode 330, the implanted types of the first ion implantation structure 331 and the second ion implantation structure 332 are opposite. . In the embodiment of the present disclosure, the first ion implantation structure 331 may be N-type doped, and the second ion implantation structure 332 may be P-type doping.

In some embodiments, if the first ion implantation structure 331 and the second ion implantation structure 332 are both formed by doping on the substrate, then the first implantation depth to form the first ion implantation structure 331 is deeper than A second implantation depth at which the second ion implantation 332 is performed is formed.

In some embodiments, if the first ion implantation structure 331 and the second ion implantation structure 332 are both formed by doping the epitaxial layer formed by epitaxial growth of the substrate 210, then the first ion implantation structure 331 and the second ion implantation structure 332 may be formed through the first epitaxial growth. an epitaxial layer, and then doping the first epitaxial layer to form a first ion implantation structure. Then, the first epitaxial layer is doped to form a first ion implantation structure 331, and the second epitaxial layer is doped to form a second ion implantation structure 332.

In some embodiments, as shown in Figure 10, the second ion implantation structure 332 includes: an upper second ion implantation structure 3322 and a lower second ion implantation structure 3321. The ion concentration of the upper second ion implantation structure 3322 is the same as that of the lower second ion implantation structure 3321. The ion concentration 3321 of the ion implanted structure is different.

The second ion implantation structure 332 may include at least two layers. When it is two layers, it has an upper second ion implantation structure 3322 and a lower second ion implantation structure 3321. The type of doping ions of the upper second ion implantation structure 3322 and the type of doping ions of the lower second ion implantation structure may be the same. For example, if the doping ions of the upper second ion implantation structure 3322 are P-type doping ions, then the doping ions of the lower second ion implantation structure may also be P-type doping ions.

In some embodiments, the ion concentration of the upper second ion implantation structure 3322 is different from the ion concentration 3321 of the lower second ion implantation structure. For example, the ion concentration of the upper second ion implantation structure 3322 may be greater than the ion concentration 3321 of the lower second ion implantation structure. Doping the upper second ion implantation structure 3322 with a higher concentration of ions can be used to increase the conductivity of the PN junction in the diode 330 . The lower second ion implantation structure 3321 may utilize its doped ion concentration or its thickness to adjust the threshold voltage of the diode 330 . Using a multi-layer structure to form the second ion implantation structure 332 can improve the performance of the diode 330 .

In some embodiments, as shown in Figure 11 (Figure 11 is a schematic diagram of the three-dimensional structure of the substrate), the substrate includes: a back substrate 213; a buried oxide layer 212 located on the back substrate 213; and a doping structure 350 located on the back substrate 213. On the buried oxide layer 212, the doped structure 350 is in direct contact with the first ion implantation structure; the shallow trench isolation structure 360 is located between adjacent doped structures 350.

The doping structure 350 is in direct contact with the above-mentioned first ion implantation structure to connect a plurality of phase change memory cells arranged along the first direction. That is, the contact points or contact surfaces of the plurality of phase change memory cells along the first direction and the doped structure 350 are at the same potential. The first direction may be any direction parallel to the substrate surface. In some embodiments, the first direction may be the same as the direction of a subsequently formed word line or bit line.

The doping structure 350 may be formed by doping the top silicon on the buried oxide layer 212 multiple times.

In some embodiments, as shown in Figure 11, the substrate has a doping structure 350; as shown in Figure 12 (Figure 12 is a cross-sectional view of the semiconductor structure along the Y direction), the semiconductor structure also includes: a shallow trench isolation structure 360 , located between adjacent doped structures 350; here, the shallow trench isolation structure 360 is used to isolate adjacent doped structures 350.

Specifically, the shallow trench isolation structure 360 is used to isolate adjacent doped structures 350 along the Y direction, so that the phase change memory cells 300 that do not overlap in the Y direction are electrically isolated from each other. The relationship between the Y direction and the X direction can be perpendicular or intersecting.

The material of the shallow trench isolation structure 360 may be an insulating material, such as silicon oxide, nitride and combinations thereof.

In some embodiments, as shown in Figure 11, the doping structure includes: N well 351, located on the buried oxide layer 212; P well 352, located on the N well 351; third ion implantation structure 353, located on the surface of the P well 352 in direct contact with the first ion implanted structure.

In some embodiments, the N-well layer, the P-well layer and the third ion-implantation structure layer may be formed by performing three ion implantations with different depths on the top silicon. The N-well layer is doped with N-type ions, and the P-well layer is doped with P-type ions. The type of doping ions in the third ion implantation structure layer can be the same as the type of doping ions implanted in the first ion implantation structure.

The N well layer, the P well layer and the third ion implantation structure layer are etched to form the doping structure 350 composed of the N well 351, the P well 352 and the third ion implantation structure 353. The third ion implantation structure 353 is in contact with the first ion implantation structure, so that current can flow from the third ion implantation structure 353 into the first ion implantation structure. The third ion implantation layer may be formed by heavy doping, so the subsequently formed third ion implantation structure is also heavily doped, which has the characteristics of low resistivity, small resistance, and enhanced conductivity.

The N well and the P well are used to form a reverse biased PN junction to isolate the phase change memory cell 300 from the buried oxide layer 212 and the back substrate 213 to avoid leakage.

In some embodiments, as shown in Figure 13, the semiconductor structure also includes: an interlayer dielectric layer 370, located between each phase change memory unit 300; a first conductive structure 380, penetrating the interlayer dielectric layer 370 and connecting the third ion Inject structure 353.

There may also be an interlayer dielectric layer 370 between each phase change memory unit 300. The interlayer dielectric layer 370 is used to electrically isolate each phase change memory unit 300 and reduce parasitic capacitance. The material of the interlayer dielectric layer 370 may be an insulating material.

Each third ion implantation structure 353 may be connected to a first conductive structure 380 penetrating the interlayer dielectric layer 370 .

The first conductive structure 380 at least includes a first contact structure 382 (CT, Contact), which may be one or a plurality of contact structures stacked on each other.

The first contact structure 382 may further include a first conductive plug 383. The first conductive plug 383 is used to reduce ohmic contact between adjacent first contact structures 382 or between the first contact structure 382 and other structures.

The material of the first contact structure 382 may be metal.

The material of the first conductive plug 383 may be metal, such as Ti and/or TiN.

In some embodiments, as shown in FIG. 13 , the semiconductor structure further includes: a second conductive structure 390 connected to the phase change memory unit 300 ; wherein the first conductive structure 380 is connected to a first conductive structure 390 extending in a first direction parallel to the substrate. A conductive line 381 is connected to the second conductive structure 390 and a second conductive line 391 extending in a second direction parallel to the substrate, the second direction intersecting the first direction.

In some embodiments, the same second conductive structure 390 can also be shared on multiple phase change memory cells overlapping in the first direction (X direction), and adjacent second conductive structures 390 can be connected along the second direction (Y direction). directions) parallel to each other.

The second conductive structure at least includes a second contact structure 392, which may be one or a plurality of contact structures stacked on each other. Each second contact structure 392 also includes a second conductive plug 393. The second conductive plug 393 is used to reduce ohmic contact between adjacent second contact structures 392 or between the second contact structure 392 and other structures. The material of the second contact structure 392 may be metal. The second conductive plug 393 may be made of metal, such as Ti or TiN.

In some embodiments, the second conductive structure further includes a second conductive line 391 extending along the Y-th direction. The first conductive structure 380 also includes a first conductive line 381 extending along the X-th direction. The first conductive lines 381 may be used to form word lines or bit lines. The second conductive lines 391 may also be used to form word lines or bit lines. In some embodiments, the first conductive line 381 and the second conductive line 391 do not spatially intersect. That is, there may be an interlayer dielectric layer between the first conductive line 381 and the second conductive line 391 . In the embodiment of the present disclosure, the first conductive line 381 may be a word line, and the second conductive line 391 may be a bit line. By applying different voltages to the bit lines and/or word lines, data can be stored and read in the phase change memory cells.

An embodiment of the present disclosure also provides a method for forming a semiconductor structure, as shown in Figure 14, including:

Step S101. Provide a substrate;

Step S102: Form a phase change memory unit on the substrate; the phase change memory unit includes:

Phase change material layer and heating layer, the heating layer is located between the phase change material layer and the substrate, and the heating layer includes a first part made of a first conductive material and a second part made of a second conductive material, the second part at least surrounds The first part of the side wall.

First, step S101 is performed to provide a substrate, and the surface of the substrate is any surface perpendicular to the thickness direction of the substrate. Definition: The thickness direction of the substrate or the direction perpendicular to the surface of the substrate is the Z direction, any direction along the substrate surface is defined as the X direction, and the direction along the substrate surface that intersects with the X direction is the Y direction. The substrate used in the embodiment of the present disclosure may be an SOI substrate 210 as shown in FIG. 16 . The substrate 210 includes a top layer of silicon 211 , a buried oxide layer 212 and a back substrate 213 . Among them, the top silicon 211 can be ultra-thin single crystal silicon, the buried oxide layer 212 can be silicon oxide, and the back substrate 213 can be single crystal silicon.

Before performing step S102, the substrate may also be cleaned to remove impurities on the surface.

Then step S102 is performed to form a phase change material layer to be processed and a heating layer to be processed through a growth process or a deposition process; wherein the heating layer to be processed is located on the substrate, and the phase change material layer to be processed is located on the heating layer to be processed. layer. Then, the phase change material layer to be processed and the heating layer to be processed are etched through an etching process to form the required phase change material layer and the required heating layer to form a phase change memory unit.

The heating layer in the embodiment of the present disclosure includes a first part made of a first conductive material and a second part made of a second conductive material; the first part at least surrounds the side wall of the second part.

By using two conductive materials, the embodiments of the present disclosure can combine the advantages of the two conductive materials to make the reset current of the phase change memory lower and the heating efficiency higher. The heater in the embodiment of the present disclosure is composed of a second part that at least surrounds the side wall of the first part. This structure is more conducive to reducing heat loss and further improving heating efficiency.

In some embodiments, the method further includes:

Step S201: Form a thermal insulation layer to cover the side wall and at least part of the upper surface of the phase change memory unit.

In some embodiments, after step S102 is performed, a thermal insulation layer may be formed on the sidewalls and at least part of the upper surface of the phase change memory cell through a deposition process.

In some embodiments, step S201 can also be executed alternately with step S102, that is, after forming the heating layer of the phase change memory unit, first form a first insulation layer on the side wall of the heating layer, and then after forming the phase change material layer, A second heat preservation layer is then formed on the sidewalls and at least part of the upper surface of the phase change material layer. The first thermal insulation layer and the second thermal insulation layer jointly form a thermal insulation layer covering the side wall and at least part of the upper surface of the phase change memory unit.

In some embodiments, the phase change memory unit further includes: a diode; the phase change memory unit formed on the substrate includes:

Step S301: Form a diode perpendicular to the substrate on the substrate;

Step S302: Form a heating layer on the diode;

Step S303: Form a phase change material layer on the heating layer.

The phase change memory unit also includes: a diode located between the substrate and the heating layer. Therefore, step S102 can also be divided into step S301, step S302 and step S303.

First, step S301 is performed to form a diode perpendicular to the substrate on the substrate. Then step S302 is performed to form a heating layer on the diode. Finally, step S303 is performed to form a phase change material layer on the heating layer.

In some embodiments, forming a diode on the substrate perpendicular to the substrate in step S301 includes:

Step S401: Form a first ion implantation layer on the substrate;

Step S402: Form a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;

Step S403: Etch the first ion implantation layer and the second ion implantation layer to form a first ion implantation structure and a second ion implantation structure to form a diode.

Executing step S301 may include step S401, step S402 and step S403.

In some embodiments, step S401 may be performed first to form a first ion implantation layer through a growth process (eg, epitaxial growth) and an ion implantation process.

Then step S402 is continued to form a second ion implantation on the first ion implantation layer through a growth process (for example, epitaxial growth) and an ion implantation process.

In some embodiments, an epitaxial growth layer can be formed through a growth process, and then the epitaxial growth layer is subjected to two ion implantations at different depths to form a first ion implantation layer and a second ion implantation layer.

Because the first ion implantation layer and the second ion implantation layer are subsequently used to form a diode, the ion types of the two are opposite.

After forming the first ion implantation layer and the second ion implantation layer, step S403 is performed to etch the first ion implantation layer and the second ion implantation layer to form a diode composed of the first ion implantation structure and the second ion implantation structure. Specifically, photoresist can be coated on the second ion implantation layer, and a mask (the pattern on the mask is opaque) is used to align with the photoresist layer. When the photoresist is a positive resist, , the exposed part of the photoresist changes from an insoluble substance to a soluble substance. The soluble part can be removed with chemical solvents, leaving an island area on the photoresist layer, which corresponds to the opaque part of the mask. The shape of this island is the diode shape. The diode includes a first ion implantation structure and a second ion implantation structure.

In some embodiments, forming the second ion implantation layer in step S402 includes:

Step S501: Form a lower second ion implantation layer;

Step S502: Form an upper second ion implantation layer located on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from the ion concentration of the lower second ion implantation layer.

In some embodiments, step S402 may be replaced by step S501 and step S502.

In some embodiments, after step S401 is performed, step S501 may be performed first: forming a lower second ion implantation layer through a growth process (eg, epitaxial growth) and an ion implantation process. Then proceed to step S502: forming an upper second ion implantation layer through a growth process (eg, epitaxial growth) and an ion implantation process.

In some embodiments, an epitaxial growth layer can be formed through a growth process, and then three ion implantations of different depths are performed on the epitaxial growth layer to form a first ion implantation layer, a lower second ion implantation layer, and an upper second ion implantation layer. The types of ions implanted in the upper second ion implantation layer and the ions implanted in the lower ion implantation layer may be the same, but the concentrations of the ions implanted in the two may be different.

In some embodiments, the ion concentration of the upper second ion implantation structure may be greater than the ion concentration of the lower second ion implantation structure. Doping the upper second ion implantation structure with a higher concentration of ions can be used to increase the conductivity of the diode PN junction. The lower second ion-implanted structure can use its doped ion concentration or its thickness to adjust the threshold voltage of the diode.

In some embodiments, the diode forming heating layer in step S302 includes:

Step S601, forming a first conductive layer on the second ion implantation layer;

Step S602: Etch the first conductive layer to form multiple groove structures;

Step S603: Fill the groove structure with a second conductive material to form a second part;

Step S604: Etch the first conductive layer except the second part to form the first part.

In some embodiments, after executing step S401 and step S402, step S403 may not be executed first, but step S302 may be continued. Step S302 includes step S601, step S602, step S603 and step S604.

First, step S601 is performed, using a deposition process to deposit a first conductive material (for example, TaN) to form a first conductive layer located on the second ion implantation layer. Then step S602 is performed to etch the first conductive layer to form a plurality of groove structures; the groove structures may or may not penetrate the first conductive layer. Continue to step S603, using a deposition process to fill the second conductive material in the groove structure to form a second part; in some embodiments, when filling the groove structure with the second conductive material (for example, TiN), the second conductive material The material can also cover the surface of the first conductive layer. In this case, the CMP process can be used to remove the second conductive material covering the surface of the first conductive layer. Continue to step S604 to etch the first conductive layer other than the first part to form the first part. Specifically, photoresist can be coated on the first conductive layer formed with the first portion, and a mask (the pattern on the mask is opaque) is used to align with the photoresist layer. When the photoresist When it is a positive resist, the exposed part of the photoresist changes from an insoluble substance to a soluble substance. The soluble part can be removed with chemical solvents, leaving an island area on the photoresist layer, which corresponds to the opaque part of the mask. The shape of this island area is the shape of the heating layer. In the embodiment of the present disclosure, the TiN/TaN structure is used to create a contact with a reduced cross-sectional area, which is also beneficial to shrinkage in terms of process.

In some embodiments, the substrate includes a back substrate, a buried oxide layer located on the back substrate, and a top silicon layer located on the buried oxide layer; before performing step S102 to form a phase change memory cell on the substrate, the method further include:

Step S701: Doping the top silicon to form a doping layer; the doping layer includes an N well layer, a P well layer and a third ion implantation layer.

Step S702: Etch the doping layer to form multiple doping structures. The doping structures include N wells, P wells and a third ion implantation structure. The third ion implantation structure is connected to the first ion implantation structure along the first direction; forming a shallow Trench isolation structures fill the grooves between adjacent doped structures.

Before performing step S102, step S701 may also be performed to form a doping layer located on the buried oxide layer; the doping layer is formed by performing multiple ion implantations and/or thermal diffusion processes on the top silicon. Step S702 is then performed to etch the doping layer in a first direction parallel to the substrate to form a doping structure composed of a plurality of N wells, P wells and a third ion implantation structure. The third ion implantation structure is connected to the first ion implantation structure along the first direction, that is, the plurality of third ion implantation structures are parallel to each other along the first direction. The formed third ion implantation structure is connected to a plurality of first ion implantation structures, so that a plurality of phase change memory cells located in the same first direction are connected to the same third ion implantation structure.

In some embodiments, the method further includes:

Step S801: Fill the grooves between adjacent doped structures to form a shallow trench isolation structure.

The doped structures extend along the first direction but are also arranged along the second direction, so adjacent doped structures have grooves in the first direction and the second direction. Step S801 is performed, using a deposition process to deposit oxide, nitride or a combination thereof to fill the groove to form a shallow trench isolation structure, so that adjacent doped structures have shallow trenches in the first direction and the second direction. Tank isolation structure. The shallow trench isolation structure is used to electrically isolate the doped structure and subsequent devices (eg, phase change memory cells) formed on the doped structure.

In some embodiments, the method further includes:

Step S901: Form an interlayer dielectric layer and fill it between multiple phase change memory cells;

Step S902: Form a first conductive structure, penetrate the interlayer dielectric layer and connect to the third ion implantation structure.

In some embodiments, step S901 may be performed after step S102 is performed. An insulating material is deposited using a deposition process to form an interlayer dielectric layer between multiple phase change memory cells.

In some embodiments, step S102 and step S901 may be performed alternately. For example, after the diode and the heating layer are formed, an insulating material may first be deposited between the diode and the heating layer to form a first interlayer dielectric layer. Then, after the phase change material layer is formed, an insulating material is continued to be deposited between the phase change material layers to form a second interlayer dielectric layer. The first interlayer dielectric layer and the second interlayer dielectric layer together constitute an interlayer dielectric layer.

Then step S902 is performed to etch the interlayer dielectric layer, and the third ion implantation layer can be used as an etching stop layer. After etching, a groove structure penetrating the interlayer dielectric layer is formed, which can be filled with conductive material using a deposition process to form a first conductive structure penetrating the interlayer dielectric layer and connecting to the third ion implantation structure. The first conductive structure includes at least a first contact structure. In some embodiments, the first conductive structure may further include a first conductive plug over the first contact structure.

In some embodiments, the method further includes:

Step S1001: Form a second conductive structure and connect the phase change memory unit;

Wherein, the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate, and the second direction is connected to The first direction intersects.

After performing step S102, step S1001 may also be continued to form a second conductive structure connected to the surface of the phase change memory cell. The second conductive structure includes at least a second contact structure. In some embodiments, the second conductive structure may further include a second conductive plug over the second contact structure.

In some embodiments, a deposition process may also be used to form a first conductive line on the first conductive structure, and the first conductive line extends in a first direction parallel to the substrate. A deposition process may also be used to form a second conductive line on the second conductive structure, and the second conductive line extends along a second direction parallel to the substrate. In some embodiments, the first conductive line may be a bit line and the second conductive line may be a word line. Alternatively, the first conductive line may be a word line and the second conductive line may be a bit line.

The disclosed embodiments also include the following examples:

First, step S101 is performed to provide a substrate 210 as shown in FIG. 15 , which may be an SOI substrate. Define the thickness direction of the substrate or the direction perpendicular to the surface of the substrate as the Z direction, define any direction along the substrate surface as the X direction, and define the direction along the substrate surface that intersects with the X direction as the Y direction. After the substrate is provided, the substrate can also be cleaned to remove impurities on the surface. The SOI substrate 210 includes: a back substrate 213, a buried oxide layer 212 and a top layer of silicon 211.

Then step S701 is performed to perform three ion implantation doping layers with different depths on the top silicon from the upper surface of the substrate; the doping layer includes an N well layer, a P well layer and a third ion implantation layer. Wherein, the ion implantation depth of the N-well layer is greater than the ion implantation depth of the P-well layer, which is greater than the ion implantation depth of the scattered ion implantation layer.

Then step S702 is performed to etch the doping layer to form a plurality of doping structures. The doping structures include an N well, a P well and a third ion implantation structure. The third ion implantation structure is connected to the first ion implantation structure along the first direction. The doped layer is etched along the X direction to form multiple doped structures. At this time, there are grooves between adjacent doped structures.

Then step S801 is performed to fill the shallow trench isolation structure formed by the grooves between adjacent doped structures.

In the embodiment of the present disclosure, the non-device area of the doped structure in the Y direction can also be etched. After etching, two grooves on both sides of the device area can be formed in the Y direction, between the two grooves. A phase change memory cell array can be formed on the doping structure of the device region. Then a deposition process is used to fill the grooves on both sides of the device area to form two shallow trench isolation structures in the Y direction. The numbers in the above embodiments are only for illustration, and other numbers of groove structures can also be formed in the Y direction of the non-device area.

The semiconductor structure after performing the above steps is shown in FIG. 16 and FIG. 17 , wherein FIG. 16 is a cross-sectional view of the semiconductor structure along the X direction, and FIG. 17 is a cross-sectional view of the semiconductor structure along the Y direction.

Seen along the positive direction of the Z-axis, FIG. 16 shows the back substrate 213, the buried oxide layer 212, and the doping structure 350 (including the N well 351, the P well 352, and the third ion implantation structure 353) in order. Both ends of the doped structure 350 also include two shallow trench isolation structures 360. The area between the two shallow trench isolation structures 360 can be used as a device area, which is subsequently used to form semiconductor components, such as phase change memory cells.

Seen along the positive direction of the Z-axis in FIG. 17 , there are in order the back substrate 213 , the buried oxide layer 212 , a plurality of shallow trench isolation structures 360 and the doped structures 350 located between the shallow trench isolation structures 360 . The shallow trench isolation structure 360 and the doping structure 350 are located in the same horizontal direction in the Z direction.

Then step S401 is performed, continuing epitaxial growth on the semiconductor structure as shown in Figures 16 and 17 to form a first epitaxially grown silicon layer, and then injecting highly doped N-type ions to form the structure as shown in Figures 18 and 19 the first ion implantation layer 331. 18 is a cross-sectional view of the semiconductor structure along the X direction, and FIG. 19 is a cross-sectional view of the semiconductor structure along the Y direction.

Then perform step S501, continue epitaxial growth on the first ion implantation layer 331 to form a second epitaxially grown silicon layer, and then inject N-type ions to form the lower second ion implantation layer 3321 as shown in Figures 18 and 19. .

Then perform step S502, continue epitaxial growth on the lower second ion implantation layer 3321 to form a third epitaxially grown silicon layer, and then inject highly doped P-type ions to form the upper layer of the second ion implantation layer 3321 as shown in Figures 18 and 19. Second ion implantation layer 3332.

Step S601 is then performed to deposit a first conductive material (eg, TaN) using a deposition process (eg, chemical vapor deposition) to form a first conductive layer located on the second ion implantation layer.

Then step S602 is performed to process the first conductive layer through processes such as photomask and etching to form a plurality of groove structures penetrating the first conductive layer. The surface of the formed groove structure can then be cleaned to remove the native oxide layer on the surface.

Step S603 is then performed to deposit a second conductive material (eg, TiN) in the groove structure using a deposition process (eg, atomic layer deposition) to form the second portion 322 as shown in FIGS. 20 and 21 . 20 is a cross-sectional view of the semiconductor structure along the X direction, and FIG. 21 is a cross-sectional view of the semiconductor structure along the Y direction. In some embodiments, TiN is also deposited on the TaN layer (ie, the first conductive layer). At this time, the TiN deposited on the TaN layer (ie, the first conductive layer) can be chemically and mechanically polished until the TaN layer is exposed.

Then perform steps S604 and S403, use a photomask and an etching process to etch the part of the first conductive layer other than the second part and the first ion implantation layer and the second ion implantation layer under the part of the first conductive layer, etching The stop layer is a third ion implantation structure to form the heating layer 320 and the diode 330 as shown in Figures 22 and 23. The three-dimensional structure of the heating layer 320 is shown in Figure 24, which includes a second part 322 and a first part 321. The second part 322 can be a cylindrical structure, and the first part 321 can be a rectangular parallelepiped with a cylinder cut out in the middle. It can be seen that, The first part 321 covers the entire side wall of the second part 322.

Then step S201 is performed to deposit a thermal insulation material (eg, SiN) to form a first thermal insulation layer 410 . Viewed along the X direction, as shown in FIG. 25 , the first thermal insulation layer may cover the sidewalls of the diode 330 , the sidewalls of the heating layer 320 , the surface of the heating layer 320 and the surface of the third ion implantation structure 353 . Viewed along the Y direction, as shown in FIG. 26 , the first thermal insulation layer may cover the sidewalls of the diode 330 , the sidewalls of the heating layer 320 , the surface of the heating layer 320 and the surface of the shallow trench isolation 360 .

In some embodiments, before performing step S201, the surface of the groove structure between the first structure (heating layer and diode) may also be cleaned to remove the native oxide layer on the surface.

Then step S901 is performed to deposit an insulating material (eg, silicon nitride) between the diode and the heating layer to form a first interlayer dielectric layer. When depositing the first interlayer dielectric layer, the first interlayer dielectric layer 370 may also cover the first heat preservation layer 410 on the heating layer 330 . At this time, an etching process (eg, CMP) may be used to remove the first insulation layer 410 and the first interlayer dielectric layer 370 on the heating layer 330 until the heating layer 330 is exposed. After step S901 is completed, the semiconductor structure as shown in FIG. 27 and FIG. 28 can be formed. 27 is a cross-sectional view of the semiconductor structure along the X direction, and FIG. 28 is a cross-sectional view of the semiconductor structure along the Y direction.

Viewed along the X direction, as shown in FIG. 27 , the first insulation layer 410 covers the heating layer 330 and the sidewalls of the diode 320 and the upper surface of the third ion implantation layer 353 . There is a first interlayer dielectric layer 370 between adjacent first structures (heating layer 300 and diode 320).

Viewed along the Y direction, as shown in FIG. 28 , the first thermal insulation layer 410 covers the heating layer 330 and the sidewalls of the diode 320 and the upper surface of the shallow trench isolation structure 360 . There is a first interlayer dielectric layer 370 between adjacent first structures (heating layer 300 and diode 320).

Then step S303 is performed, first using a deposition process to deposit a phase change material (for example, GST) to form a phase change material layer, and then processing the phase change material layer through photomask, etching and other processes to form the phase change material layer as shown in Figures 29 and 30 The phase change material structure 310 is located on the heating layer 320. In some embodiments, the width (along the X direction) and the length (along the Y direction) of the phase change material structure 310 may be larger than the heating layer 320 , that is, the phase change material structure 310 may completely cover the upper surface of the heating layer 330 .

The distance between adjacent phase change material structures formed using the method of the embodiment of the present disclosure can be reduced to 0.07 μm. The spacing between each phase change memory unit and the number of stacked layers of phase change memory units are small, so the efficiency is greatly improved. The storage density of memory cells per unit area.

Then step S201 is performed again to deposit a thermal insulation material (SiN) between the phase change material structures 310 to form a second thermal insulation layer 420 as shown in FIGS. 31 and 32 . The second thermal insulation layer 420 covers the sides of the phase change material structure 310 The walls and upper surface also cover the upper surface of the first interlayer dielectric layer 370 .

Then step S901 is performed again to deposit an insulating material (for example, silicon oxide) on the second thermal insulation layer 420 to form a second interlayer dielectric layer 371 as shown in FIGS. 33 and 34 .

Then step S902 and step S1001 are performed to form a first conductive structure that penetrates the first interlayer dielectric layer and the second interlayer dielectric layer and connects the third ion implantation structure as shown in Figure 35 and Figure 36 and forms a connected phase change memory. A second conductive structure on the surface of the unit.

Specifically, photomask, etching and other processes are performed along the Y direction between the phase change memory cell array and the shallow trench isolation (one of the two shallow trench isolations along the X direction can be selected), and a third ion implantation is performed. The structure serves as an etching stop layer to form multiple groove structures that overlap in the X direction and are parallel in the Y direction. The groove structure penetrates the first interlayer dielectric layer and the second interlayer dielectric layer and connects the third ion implantation structure.

On the phase change memory cell array, use photomask, etching and other processes along the X and Y directions, and use the phase change material structure as the etching stop layer to form an opening structure located on the phase change material structure. The opening structure The width (along the X direction) is less than or equal to the width of the phase change material structure, and the length (along the Y direction) of the opening is also less than or equal to the length of the phase change material structure.

Then, a deposition process (eg, atomic layer deposition) is used to deposit conductive material into the groove structure and the opening structure to form the first contact structure 382 and the first conductive plug 383 and the second contact structure 392 and the second conductive plug 393.

Then, a conductive material is deposited on the second conductive plug 393, and a photomask and an etching process are performed to form a second conductive line 391 covering the second conductive plug 393. As shown in FIG. 36, the second conductive line 391 extends in the Y direction. As shown in FIG. 35 , the second conductive lines 391 are parallel to each other along the X direction.

The distance between adjacent second conductive lines 391 formed using the method of the embodiment of the present disclosure can be reduced to 0.07 μm.

On the basis of Figures 35 and 36, continue to deposit insulating material (for example, silicon oxide) to form a third interlayer dielectric layer 372 as shown in Figures 37 and 38. On the third interlayer dielectric layer 372, through light The mask process, etching process, etc. form a groove structure connecting the first contact plug 383 through the third dielectric layer 372 .

A further first contact structure 382 and a further first contact plug 383 are formed over the first contact plug 383 using a deposition process (eg, atomic layer deposition). The upper surface of the first contact plug 383 is flush with the upper surface of the third interlayer dielectric layer 372 .

Then, first conductive lines 381 parallel to each other along the X direction are formed on the third interlayer dielectric layer through a photomask process and an etching process.

Insulating materials used in the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer in the embodiments of the present disclosure may be the same or different.

The top view of the semiconductor structure of Figures 37 and 38 is as shown in Figure 39: the bit lines extend along the Y direction, and adjacent bit lines are parallel to each other along the X direction.

The word lines extend along the X direction, and adjacent word lines are parallel to each other along the Y direction.

In summary, the semiconductor structure formed using the method of the embodiment of the present disclosure has a simple process and is easy to form. Since it is formed on an SOI substrate, in addition to the above advantages, the semiconductor structure also has the advantages of SOI (for example, less latch-up effect, less leakage current, etc.). The circuit diagram corresponding to the semiconductor structure of Figures 37 and 38 can be simplified as Figure 40, in which the memory unit 500 includes a phase change memory unit and a diode. Multiple diodes located in the same row can be connected to the same word line, and multiple phase change memory cells located in the same column can be connected to the same bit line.

Programming the memory cell 500 includes applying a programming voltage V _pgm (for example, 0.5V) to the bit line where the selected memory cell 500 is located, and applying a ground voltage (for example, 0V) to other unselected bit lines. At the same time, a ground voltage (for example, 0V) is applied to the word line where the selected memory cell 500 is located, and a certain voltage (for example, 0.5V) is applied to unselected word lines.

The reading operation of the memory cell includes: applying a read voltage (V _read ) to the bit line where the selected memory cell 500 is located, and applying a ground voltage (for example, 0V) to other unselected bit lines. At the same time, a ground voltage (for example, 0V) is applied to the word line where the selected memory cell 500 is located, and a certain voltage (for example, 0.5V) is applied to unselected word lines. Among them, V _read is less than V _pgm.

The IV curve of the memory cell is shown in Figure 41:

Curve 1 is the current-voltage curve when reading the memory cell.

Curve 2 is the current-voltage curve when writing a memory cell.

The current-voltage curve in Figure 41 shows that the read voltage must be smaller than the write voltage (the range of the write voltage is such as the shaded area). In this way, when the voltage is read, the phase change memory will not be caused by excessive voltage. Change of state. Generally speaking, write operations are divided into RESET operations and SET operations, and the voltage range is roughly in the shaded area. Then the writing operation is performed through different pulse times, in which the SET operation can be a longer pulse time, and the RESET operation can be a shorter pulse time.

Finally, an embodiment of the present disclosure also provides a memory. As shown in FIG. 42 , the memory 40 includes a memory cell array 20 containing the semiconductor structure 10 as in any of the above embodiments, and a memory cell array 20 located above or outside the memory cell array 20 . Peripheral circuit 30 structure.

All or part of the semiconductor structure 10 in the above embodiments can be used to form the memory cell array 20, and the memory cells of the memory cell array 20 include phase change memory cells.

Peripheral circuitry 30 may include any suitable analog, digital, and mixed-signal circuitry to perform related operations on memory cell array 20 . Operations include reading, writing, erasing, etc.

Memory 40 may be a phase change memory.

The memory has a three-dimensional structure, which has higher storage density, lower power consumption and easier access operations. The heater of the memory has a smaller volume, making the heating efficiency higher and the writing speed faster. The memory also has other advantages of the semiconductor structure of any embodiment of the present disclosure.

The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

Specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be covered by the present disclosure. within the scope of protection. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

In the embodiment of the present disclosure, the heating layer is formed using two conductive materials, and the heating layer has a first part and a second part, and the first part at least surrounds the side wall of the second part. In this way, not only can the advantages of the conductive material of the first part be used to improve the heating efficiency, but the second part can also be used to surround the first part so that the heated heat is not easily lost, which is more conducive to further improving the heating efficiency. After the heating efficiency is improved, the time required for the phase state conversion of the phase change material layer can be shortened, so the phase state conversion can occur faster, thereby increasing the data writing rate.

Claims (20)

1. A semiconductor structure, the semiconductor structure includes:

   substrate;

   A phase change memory unit located on the substrate;

   The phase change memory unit includes: a phase change material layer and a heating layer, the heating layer being located between the phase change material layer and the substrate;

   The heating layer includes a first portion made of a first conductive material and a second portion made of a second conductive material, the first portion surrounding at least a side wall of the second portion.
2. The semiconductor structure of claim 1, wherein the first conductive material has a first conductivity that is less than a second conductivity of the second conductive material.
3. The semiconductor structure according to claim 1, wherein the sidewalls and at least part of the upper surface of the phase change memory cell are also covered with a thermal insulation layer.
4. The semiconductor structure of claim 1, wherein the phase change memory cell further includes:

   A diode is perpendicular to the substrate, the diode is located between the substrate and the heating layer, and the conduction direction of the diode is from the heating layer to the substrate.
5. The semiconductor structure of claim 4, wherein the diode includes:

   A first ion implantation structure located on the substrate;

   a second ion implantation structure located on the first ion implantation structure;

   The ion type of the first ion implantation structure is opposite to the ion type of the second ion implantation structure.
6. The semiconductor structure of claim 5, wherein the second ion implantation structure includes:

   The upper second ion implantation structure and the lower second ion implantation structure have different ion concentrations than the lower second ion implantation structure.
7. The semiconductor structure of claim 5, wherein the substrate includes:

   backing substrate;

   a buried oxide layer located on the back substrate;

   a doping structure located on the buried oxide layer, the doping structure being in direct contact with the first ion implantation structure;

   A shallow trench isolation structure is located between adjacent doped structures.
8. The semiconductor structure of claim 7, wherein the doped structure includes:

   N well, located on the buried oxide layer;

   P well, located on the N well;

   The third ion implantation structure is located on the surface of the P well and is in direct contact with the first ion implantation structure.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:

   An interlayer dielectric layer is located between each of the phase change memory units;

   The first conductive structure penetrates the interlayer dielectric layer and is connected to the third ion implantation structure.
10. The semiconductor structure of claim 9, wherein the semiconductor structure further comprises:

    a second conductive structure connected to the phase change memory unit;

    Wherein, the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate, and the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate. The conductive lines are connected, and the second direction intersects the first direction.
11. A method of forming a semiconductor structure, the method comprising:

    provide a substrate;

    A phase change memory unit is formed on the substrate; the phase change memory unit includes:

    A phase change material layer and a heating layer, the heating layer is located between the phase change material layer and the substrate, and the heating layer includes a first portion made of a first conductive material and a third portion made of a second conductive material. Two parts, the first part at least surrounds the side wall of the second part.
12. The forming method according to claim 11, wherein the method further comprises:

    An insulation layer is formed to cover the side wall and at least part of the upper surface of the phase change memory unit.
13. The formation method according to claim 11, wherein the phase change memory unit further includes: a diode; forming the phase change memory unit on the substrate includes:

    forming a diode on the substrate perpendicular to the substrate;

    forming the heating layer on the diode;

    The phase change material layer is formed on the heating layer.
14. The formation method of claim 13, wherein forming a diode on the substrate perpendicular to the substrate includes:

    forming a first ion implantation layer on the substrate;

    forming a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;

    The first ion implantation layer and the second ion implantation layer are etched to form a first ion implantation structure and a second ion implantation structure to form the diode.
15. The formation method according to claim 14, wherein forming the second ion implantation layer includes:

    Forming a lower second ion implantation layer;

    An upper second ion implantation layer is formed on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from the ion concentration of the lower second ion implantation layer.
16. The formation method of claim 14, wherein forming the heating layer on the diode includes:

    forming a first conductive layer on the second ion implantation layer;

    Etching the first conductive layer to form a plurality of groove structures;

    Filling the second conductive material in the groove structure to form the second part;

    The first conductive layer other than the second part is etched to form the first part.
17. The formation method according to claim 14, wherein the substrate includes a back substrate, a buried oxide layer located on the back substrate, and a top layer of silicon located on the buried oxide layer; on the substrate Before forming the phase change memory cell, the method further includes:

    The top layer of silicon is doped to form a doped layer; the doped layer includes an N well layer, a P well layer and a third ion implantation layer;

    Etching the doped layer to form a plurality of doped structures, the doped structures including N wells, P wells and a third ion implantation structure, the third ion implantation structure is connected to the first ion implantation structure;

    A shallow trench isolation structure is formed to fill the grooves between adjacent doped structures.
18. The forming method according to claim 17, wherein the method further comprises:

    Form an interlayer dielectric layer and fill it between a plurality of the phase change memory cells;

    A first conductive structure is formed, penetrating the interlayer dielectric layer and connecting the third ion implantation structure.
19. The forming method according to claim 18, wherein the method further comprises:

    Form a second conductive structure to connect the phase change memory unit;

    Wherein, the first conductive structure is connected to a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate. The conductive lines are connected, and the second direction intersects the first direction.
20. A memory including a memory cell array containing the semiconductor structure according to any one of claims 1 to 10, and a peripheral circuit structure located above or outside the memory cell array.

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