CN101976677B - Phase change random access memory array based on ZnO schottky diodes and manufacturing method thereof - Google Patents
Phase change random access memory array based on ZnO schottky diodes and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a phase change random access memory array based on ZnO schottky diodes and a manufacturing method thereof. The phase random access memory array is characterized by comprising a semiconductor substrate, an insulation buffer layer, a plurality of word lines, a plurality of ZnO schottky diodes, second conductor layers, phase change storage layers and a plurality of bit lines, wherein the insulation buffer layer is located on the semiconductor substrate; the word lines are located on the insulation buffer layer; the ZnO schottky diodes are electrically connected to the word lines; each second conductor layer is respectively located on each ZnO schottky diode; each phase change storage layer is respectively located on each second conductor layer; the bit lines are electrically connected to the phase change storage layer; and each ZnO schottky diode consists of a first conductor layer and an n-type ZnO polycrystalline state film. In the invention, the ZnO schottky diodes formed by the n-type ZnO polycrystalline state films and metal layers are adopted as a gating component so that a phase change memory has higher density, lower power consumption and higher performance; in the manufacturing method, a low temperature process for the n-type ZnO polycrystalline state film by atomic layer deposition is utilized; and the manufacturing method is competitive in cost and is hopefully and widely applied to three-dimensional stack phase change memories.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to a kind of phase-change random access memory (PCRAM) and manufacturing approach thereof, especially a kind of high density phase change random asccess memory array and manufacturing approach thereof based on the ZnO Schottky diode gating that forms under the low temperature.
Background technology
The phase-change random access memory technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett.; 21,1450～1453,1968) and the beginning of the seventies (Appl.Phys.Lett.; 18; 254～257,1971) phase-change thin film that proposes can be applied to that the conception of phase change memory medium sets up, and is that a kind of cost is low, speed is fast, storage density is high, manufacturing process is simple and the electrical storage device of stable performance; And its preparation is compatible mutually with prior standard CMOS technology, therefore receives global extensive concern.
The basic principle of phase-change random access memory (being called for short PCRAM) is to utilize electric impulse signal to act on the device cell electrode; Make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place; Through differentiating amorphous state high resistance and polycrystalline attitude low-resistance value; Realize the storage of " 0 " and one state, thus the writing, wipe and read operation of completion information.Phase-change random access memory owing to have reads at a high speed, high cycle-index, non-volatile, advantages such as device size is little, strong motion low in energy consumption, anti-and radioresistance; Thought flash memories that most possible replacement is present and become following memory main product especially great application prospect is arranged by international semiconductor TIA in national defence and field of aerospace.
The phase-change random access memory memory cell is being implemented in the electric operating process; It is generally acknowledged in SET (setting) process (corresponding to crystallization); Applying a low and wide electric pulse heats phase-change material; When the temperature of material was higher than crystallization temperature (650K) and is lower than fusion temperature (893K), phase-change material will crystallization, had the polycrystalline attitude than low-resistance value thereby form; And in RESET (resetting) process (corresponding to decrystallized); Then need apply a high and narrow electric pulse heats; Make fusion temperature that the temperature of material is higher than phase-change material to interrupt original chemical bond in the polycrystalline material; Quenching process (cooling rate reaches 1011K/s) through a quenching makes the atom in the material have little time to become again key to arrange subsequently; Formed the unordered amorphous state of shortrange order long-range, and this amorphous state has very high resistivity with respect to the polycrystalline attitude, resistance value is very high.Phase-change random access memory is exactly to utilize the difference of the high resistance and low resistance value of amorphous state and polycrystalline attitude that can reversible transition to realize the storage of data " 0 " and " 1 ".In reading (READ) process, electric pulse very a little less than, the time is very short, is not enough to cause any phase transformation of generation in the phase-change material, so can not destroy wherein canned data.
Mechanism's great majority of being engaged at present the phase-change random access memory R&D work in the world are (Ovonyx of major company of semicon industry; Intel; Samsung, IBM and AMD etc.), the focus that they pay close attention to all concentrates in the commercialization that realizes phase-change random access memory how as early as possible.Wherein, realize high density, mass memory array at a high speed is the direction of research.Compare the 1T1R structure that in the past MOSFET (complementary metal oxide field-effect transistor) drives phase-change memory cell, adopt diode to drive the 1D1R structure of phase change cells, advantage such as it is little, low in energy consumption to have an area, and circuit speed is fast.Given this, the present invention will be to realizing at a high speed, high density, low-power consumption mass memory array and propose making a kind of low temperature under based on ZnO Schottky diode gating phase-change random access memory array.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of phase-change random access memory array based on the ZnO Schottky diode and preparation method thereof.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of phase-change random access memory array based on the ZnO Schottky diode comprises:
The Semiconductor substrate of first conduction type;
Be positioned at the buffer insulation layer on the said Semiconductor substrate;
Be positioned at the word line of many on the said buffer insulation layer second conduction types that are parallel to each other;
Be positioned on the said word line, be electrically connected on a plurality of ZnO Schottky diodes of said word line, said ZnO Schottky diode is made up of first conductor layer and the n type ZnO polycrystalline attitude film that is attached thereto;
Lay respectively at second conductor layer on each said ZnO Schottky diode;
Lay respectively at the phase change memory on each second conductor layer;
Be positioned on the said phase change memory, be electrically connected on the multiple bit lines of said phase change memory, said bit line spatial vertical is in said word line.
Wherein, said first conduction type is the p type, and second conduction type is the n type.
Be filled with dielectric isolation layer between many said word lines, be preferably TEOS (tetraethoxysilane) material.
First conductor layer in the said ZnO Schottky diode adopts bigger metal official letter to count material, like copper, platinum or silver; Second conductor layer on the said ZnO Schottky diode adopts aluminium or aluminum copper alloy material.
Said ZnO Schottky diode and on second conductor layer around be provided with the first dielectric isolation structure, said first dielectric isolation structure and said ZnO Schottky diode and on second conductor layer between be provided with the first medium barrier layer; Be provided with the second dielectric isolation structure around the said phase change memory, be provided with the second medium barrier layer between said second dielectric isolation structure and the said phase change memory.The said first dielectric isolation structure and the second dielectric isolation structure adopt SiO
2Or dielectric material such as SiON.The said first medium barrier layer and the second medium barrier layer adopt materials such as silicon nitride or SiON.
Preferably, the upper and lower surfaces of said word line and bit line is respectively equipped with the barrier layer, and TaN is adopted on said barrier layer, and materials such as TiN or Ti/TiN are to guarantee the reliability of metallic conductor.
In addition, the present invention also provides a kind of manufacture method of the phase-change random access memory array based on the ZnO Schottky diode, comprises the steps:
(1) on Semiconductor substrate, forms the buffer insulation layer;
(2) utilize deposition and chemical wet etching technology on said buffer insulation layer, to form many word lines that are parallel to each other, and between many said word lines, fill dielectric isolation layer, carry out chemico-mechanical polishing then and make flattening surface;
(3) on said word line, form first conductor layer, utilize ald (ALD) technology that ZnO is formed n type ZnO polycrystalline attitude film with monatomic form first conductor layer surface that is plated in layer then, depositing temperature is not higher than 200 ℃; On n type ZnO polycrystalline attitude film, form second conductor layer again, thereby form a plurality of pillar cells that comprise first conductor layer, n type ZnO polycrystalline attitude film and second conductor layer through etching technics, a plurality of said pillar cells are formed columnar arrays;
(4) inner wall surface prepares the first medium barrier layer earlier in the gap of this columnar arrays, utilizes dielectric material that the gap is filled up to form the first dielectric isolation structure then, carries out chemico-mechanical polishing afterwards and makes flattening surface;
(5) preparation one deck dielectric material on the said first dielectric isolation structure; Utilize chemical wet etching technology to offer a plurality of through holes then; Second conductor layer of pillar cell under it is exposed; And at the through-hole wall surface preparation second medium barrier layer, in through hole, fill phase-change material afterwards and form phase change memory, the dielectric material around the phase change memory and the second medium barrier layer becomes the second dielectric isolation structure;
(6) utilize chemico-mechanical polishing planarization phase change memory laminar surface, make bit line then above that, said bit line spatial vertical is in said word line.
Wherein, when step (3) utilized technique for atomic layer deposition to form n type ZnO polycrystalline attitude film, underlayer temperature was 60～200 ℃, and the chamber vacuum degree is 4x10
-9～6x10
-9Torr, gas flow are 0.06～0.08L/s; Presoma is diethyl zinc and H
2O, chemical equation is:
Zn(C
2H
5)
2+H
2O→ZnO+2C
2H
6
Preferably, deposition rate is 0.12～0.16nm/ cycle, and the deposition cycle cycle comprises: introduce presoma H
2Burst length 14～16ms of O is for H
2Scavenging period 8～20s of O, the burst length 20～90ms of introducing presoma diethyl zinc is for the scavenging period 7～9s of diethyl zinc.
Preferably, when making word line and bit line, lower surface prepares the barrier layer above that respectively.
As preferred version of the present invention, on every word line, make conductive plunger word line is drawn, realize that bit line and word line are positioned on the substrate.
Compared to prior art, beneficial effect of the present invention is:
In the middle of the diode of numerous kinds, the ZnO Schottky diode often is used to the photoelectric device field, belongs to majority carrier device, has characteristics such as cut-in voltage is low, response speed is fast.Discover; Because unadulterated ZnO semi-conducting material itself just has n type conductivity; The ZnO semiconductive thin film is deposited on the metallic conductor can directly forms Schottky diode, thereby avoided high-temperature technology processes such as doping that diffusion or ion inject and annealing.Therefore, the Schottky diode that utilizes ZnO semiconductor and metal to form is compared with the diode that selective epitaxial process forms, and technological temperature is lower.And the diode that adopts the ZnO semiconductor to form, its characteristic size can reach 2F
2, being significantly less than the diode that epitaxy technique forms, its cut-in voltage also cut-in voltage than pn junction diode is low.
Phase-change random access memory array of the present invention adopts a kind of direct ZnO Schottky diode that is formed by ZnO semiconductor and metal level as the gating element; Realize that diode drives the 1D1R structure of phase change cells; Advantages such as it is little to have area, low in energy consumption, and circuit speed is fast.In addition; Because the ZnO semiconductive thin film can directly deposit on metal word lines and form diode; During this phase change memory array formed, treatment temperature was no more than 350 ℃, and this low temperature process helps a plurality of storage arrays are piled up; Realize three-dimensional stacked structure, thereby further improve device density.Therefore, the present invention can make phase-change random access memory have higher density, lower power consumption and the performance of Geng Gao.
The present invention also provides the low temperature manufacture craft of this phase-change random access memory array based on the ZnO Schottky diode; Discover the specific process conditions of having only employing ald (ALD); Under lower growth temperature (200 ℃), just can obtain the ZnO semi-conducting material of n type low conductivity, and then form Schottky barrier with special metal.The present invention makes Schottky diode through the technology of ald n type ZnO polycrystalline attitude film under the cryogenic conditions; On cost, has competitiveness; More be expected in the cubic phase transition storage circuit of three-dimensional, be used widely, significant to the development of phase-change random access memory.
Description of drawings
Fig. 1 is first phase-change random access memory cell (1D1R) structural representation of ZnO Schottky diode gating.
Fig. 2 is the three-dimensional structure sketch map of 1D1R.
Fig. 3 is the three-dimensional structure sketch map of phase change memory array.
Fig. 4 is 1D1R 4x4 memory cell array circuit theory diagrams.
Fig. 5 is a ZnO Schottky diode characteristic curve (relation curve of current density and voltage) among the embodiment.
Fig. 6 is the cutaway view of phase-change random access memory array among the embodiment.
Fig. 7 is the cutaway view along the phase-change random access memory array of AA ' direction among Fig. 6.
Fig. 8 is a phase-change random access memory three-dimensional structure sketch map among the embodiment.
Embodiment
Combine accompanying drawing in the reference implementation example, more fully to describe the present invention hereinafter.At this accompanying drawing is the sketch map of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure, but comprises the shape that obtains; The deviation that causes such as manufacturing; For example the curve that obtains of dry etching has crooked or mellow and full characteristics usually, but in embodiment of the invention diagram, all representes with rectangle or cube; Expression among the figure is schematically, but this should not be considered to limit scope of the present invention.Reference number similar among the figure can be represented similar structure division.
The present invention adopts a kind of ZnO Schottky diode to constitute the 1D1R structure that diode drives phase change cells, and is as shown in Figure 1, and ZnO Schottky diode gating phase-change material, second conductor mainly work to connect diode and phase change memory.In embodiments of the present invention, the schematic three dimensional views of 1D1R structure is as shown in Figure 2, and the bearing of trend that is parallel to bit line is the x direction, and the bearing of trend that is parallel to word line is the y direction, and the stacking direction that makes progress is the z direction.Fig. 3 is the three-dimensional structure sketch map of phase change memory array, and is vertical each other with many parallel word lines on the y direction at many parallel bit lines of x direction, and what connect bit line and word line is the column structure that ZnO Schottky diode and phase change memory constitute.Fig. 4 is the 1D1R structural equivalents circuit diagram corresponding to the 4x4 of Fig. 3.
Fig. 5 is a kind of current density of ZnO Schottky diode and the test curve of voltage; Wherein this ZnO Schottky diode is made up of the n type ZnO polycrystalline attitude film and first conductor layer; First conductor layer adopts Ag, on the interface of Ag and ZnO, forms Schottky barrier, and second conductor layer is Al.Under 1 volt voltage, the current density through diode has reached 100A/cm
2Current density is index with the voltage that adds between the upper/lower electrode to be increased, and can realize driving the effect of phase-change memory cell.
The concrete structure of this phase-change random access memory array based on the ZnO Schottky diode in the embodiment of the present invention is as shown in Figure 6, and it is the cutaway view on the xz direction, and this structure comprises:
The Si substrate 100 of first conduction type (present embodiment is preferably the p type);
Be positioned at the buffer insulation layer 102 on the Si substrate 100;
Be positioned at the word line 208 of many second conduction types parallel to each other (present embodiment is the n type) on the buffer insulation layer 102;
Be positioned on the word line 208, be electrically connected on a plurality of ZnO Schottky diodes of word line 208, said ZnO Schottky diode is made up of first conductor layer 113 and the n type ZnO polycrystalline attitude film 114 that is attached thereto;
Lay respectively at second conductor layer 112 on each said ZnO Schottky diode;
Lay respectively at the phase change memory 218 on each second conductor layer 112;
Be positioned on the phase change memory 218, be electrically connected on the multiple bit lines 209 of said phase change memory 218, said bit line 209 spatial vertical are in said word line 208.
Wherein, be filled with dielectric isolation layer 202 between many word lines 208, be preferably the TEOS material.First conductor layer 113 in the said ZnO Schottky diode adopts bigger metal official letter to count material, like copper, platinum or silver; Second conductor layer 114 on the said ZnO Schottky diode adopts aluminium or aluminum copper alloy material.First conductor layer 113, n type ZnO polycrystalline attitude film 114 and on second conductor layer 112 around be provided with the first dielectric isolation structure that forms by dielectric material 108, the first dielectric isolation structure and this ZnO Schottky diode and on second conductor layer 112 between be provided with the first medium barrier layer 212.Around phase change memory 218, be provided with the second dielectric isolation structure that forms by dielectric material 108, be provided with the second medium barrier layer 210 between said second dielectric isolation structure and the phase change memory 218.The said first dielectric isolation structure and the second dielectric isolation structure adopt SiO
2Or dielectric material such as SiON.The said first medium barrier layer 212 and the second medium barrier layer 210 adopt materials such as silicon nitride or SiON.Upper and lower surfaces at word line 208 and bit line 209 is respectively equipped with barrier layer 204, and TaN is adopted on said barrier layer 204, and materials such as TiN or Ti/TiN are to guarantee the reliability of metallic conductor.
Fig. 7 is according to embodiment of the present invention, sees into along AA ' direction, comprises the yz direction cutaway view of the memory cell of Metal Zn O Schottky diode and phase change memory.
The manufacture method of above-mentioned phase-change random access memory array comprises the steps:
(1) deposition one deck buffer insulation layer 102 on the Si of p type substrate 100.
(2) upper epidermis at buffer insulation layer 102 deposits first etching stop layer 201; It can be materials such as SiN or SiON that this first etching stops layer 201; Form word line layer through methods such as physical vapor deposition (PVD)s, and prepare barrier layer 204 at the word line layer upper and lower surfaces; Wherein word line layer can be copper or aluminium copper, and technological temperature is no more than 350 ℃.Utilize technology such as photoetching to form many word lines parallel to each other 208, and between many said word lines 208, fill dielectric isolation layer 202, can be TEOS, carry out chemico-mechanical polishing (CMP) then and make flattening surface.
(3) on said word line 208, form one deck first conductor material, utilize ald (ALD) technology that ZnO is formed n type ZnO polycrystalline attitude film with monatomic form first conductor material surface that is plated in layer then, depositing temperature is not higher than 200 ℃; On n type ZnO polycrystalline attitude film, form one deck second conductor material; Then said first conductor material, n type ZnO polycrystalline attitude film and second conductor material are carried out through photoetching process and dry etch process; For example can adopt electron beam exposure technology to form figure; Forming columnar arrays, each unit of this columnar arrays comprises first conductor layer 113, n type ZnO polycrystalline attitude film 114 and second conductor layer 112.Wherein, also can adopt modes such as plating to form high density, undersized first conductor layer 113.First conductor layer 113 need be aimed at word line 208, is electrically connected to form.
(4) inner wall surface prepares the first medium barrier layer 212 earlier in the gap of this columnar arrays, PVD technology for example capable of using preparation; Utilize dielectric material 108 that the gap is filled up to form the first dielectric isolation structure then, utilize the CMP technology that the medium beyond the gap is removed afterwards, expose second conductor layer 112;
(5) make second etching on step (4) resulting structures surface and stop layer 213, material can be Si
3N
4Prepare one deck dielectric material 108 again; Utilize chemical wet etching technology to offer a plurality of through holes then, second conductor layer 112 of pillar cell under it is exposed, and at the through-hole wall surface preparation second medium barrier layer 210; Adopt the method for magnetron sputtering in through hole, to fill phase-change material 108 formation phase change memory 218 afterwards, the dielectric material around the phase change memory 218 and the second medium barrier layer 210 becomes the second dielectric isolation structure.The second medium barrier layer 210 can be Si
3N
4Perhaps SiON material, this structure helps the phase-change material fixed in shape, and Te is to the infiltration of dielectric material 108 when preventing the magnetron sputtering deposition phase-change material simultaneously.Dielectric material 108 can be SiO
2Perhaps SiON.
(6) utilize chemico-mechanical polishing planarization phase change memory laminar surface, the phase-change material beyond the through hole needs the CMP method to remove.Make bit line 209 then above that, said bit line 209 spatial vertical are in said word line 208.The top layer up and down of bit line 109 is depositing Ti/TiN barrier layer 204 respectively, to guarantee the reliability of bit line 209 metallic conductors.
Wherein, step (3) utilizes technique for atomic layer deposition to form ZnO polycrystalline attitude film, and thickness is no more than 100nm, and deposition parameter (thickness, composition, structure) is easy to control, and smooth film interface can form good the contact with second conductor.
When utilizing technique for atomic layer deposition to form ZnO polycrystalline attitude film, underlayer temperature is 60～200 ℃, and the chamber vacuum degree is 4x10
-9～6x10
-9Torr, gas flow are 0.06～0.08L/s; Presoma is diethyl zinc (chemical formula Zn (C
2H
5)
2, also make DEZn) and H
2O, chemical equation is:
Zn(C
2H
5)
2+H
2O→ZnO+2C
2H
6
Preferably, deposition rate is 0.12～0.16nm/ cycle, and the deposition cycle cycle comprises introduces presoma H
2Burst length 14～16ms of O is for H
2The scavenging period of O is 8～20s, introduces the burst length 20～90ms of presoma diethyl zinc, is 7～9s for the scavenging period of diethyl zinc.Long scavenging period makes that the ZnO film free electronic concentration that is deposited is little in these process conditions, has the n type, semiconductor material that is suitable for doing Schottky diode of high mobility.When selecting zinc methide (DMZn) as the zinc precursor body source in addition, the growth temperature of ZnO film is a room temperature.On the interface of special metal and ZnO semiconductive thin film, form Schottky barrier like this, the rectification characteristic under its forward bias is as shown in Figure 5.
In one embodiment, adopting the preferred technological temperature of ALD deposition n type ZnO polycrystalline attitude film is 100 ℃, and underlayer temperature is 60 to 200 ℃, and the chamber vacuum degree is 5x10
-9Torr, gas flow are 0.07L/s.Deposition rate is about the 0.14nm/ cycle, and the deposition cycle cycle comprises introduces presoma H
2The burst length of O is 15ms, for H
2The scavenging period of O is 8～20s, and the burst length of introducing presoma DEZn is 20～90ms and is 8s for the scavenging period of DEZn.
Fig. 8 is the phase-change random access memory three-dimensional structure sketch map of a kind of preferred version of the present invention, on every word line, makes conductive plunger word line is drawn, with the homonymy of bit line at silicon substrate.The word line of being drawn is connected with peripheral drive circuit with bit line.
Preceding text have been set forth non-volatile phase-change memory cell of the present invention under the background of ZnO Schottky diode gating phase-change random access memory array, it helps the application of three-dimensional stacked structure under the background of low manufacturing temperature.
This paper has set forth detailed manufacturing approach, and the phase-change random access memory array that can use other analog structures and different materials to realize all belongs in the scope of the invention.
Other process conditions that relate among the present invention are the common process condition, belong to the category that those skilled in the art are familiar with, and repeat no more at this.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (5)
1. the manufacture method based on the phase-change random access memory array of ZnO Schottky diode is characterized in that, comprises the steps:
(1) on Semiconductor substrate, forms the buffer insulation layer;
(2) utilize deposition and chemical wet etching technology on said buffer insulation layer, to form many word lines that are parallel to each other, and between many said word lines, fill dielectric isolation layer, carry out chemico-mechanical polishing then and make flattening surface;
(3) on said word line, form first conductor layer, utilize technique for atomic layer deposition that ZnO is formed n type ZnO polycrystalline attitude film with monatomic form first conductor layer surface that is plated in layer then, depositing temperature is not higher than 200 ℃; On n type ZnO polycrystalline attitude film, form second conductor layer again, thereby form a plurality of pillar cells that comprise first conductor layer, n type ZnO polycrystalline attitude film and second conductor layer through etching technics, a plurality of said pillar cells are formed columnar arrays;
(4) inner wall surface prepares the first medium barrier layer earlier in the gap of this columnar arrays, utilizes dielectric material that the gap is filled up to form the first dielectric isolation structure then, carries out chemico-mechanical polishing afterwards and makes flattening surface;
(5) preparation one deck dielectric material on the said first dielectric isolation structure; Utilize chemical wet etching technology to offer a plurality of through holes then; Second conductor layer of pillar cell under it is exposed; And at the through-hole wall surface preparation second medium barrier layer, in through hole, fill phase-change material afterwards and form phase change memory, the dielectric material around the phase change memory and the second medium barrier layer becomes the second dielectric isolation structure;
(6) utilize chemico-mechanical polishing planarization phase change memory laminar surface, make bit line then above that, said bit line spatial vertical is in said word line.
2. according to the manufacture method of the said phase-change random access memory array based on the ZnO Schottky diode of claim 1; It is characterized in that: when step (3) utilizes technique for atomic layer deposition to form n type ZnO polycrystalline attitude film; Underlayer temperature is 60～200 ℃, and the chamber vacuum degree is 4x10
-9～6x10
-9Torr, gas flow are 0.06～0.08L/s; Presoma is diethyl zinc and H
2O, chemical equation is: Zn (C
2H
5)
2+ H
2O → ZnO+2C
2H
6
3. according to the manufacture method of the said phase-change random access memory array based on the ZnO Schottky diode of claim 2; It is characterized in that: when step (3) utilizes technique for atomic layer deposition to form n type ZnO polycrystalline attitude film; Deposition rate is 0.12～0.16nm/ cycle, and the deposition cycle cycle comprises: introduce presoma H
2Burst length 14～16ms of O is for H
2Scavenging period 8～20s of O, the burst length 20～90ms of introducing presoma diethyl zinc is for the scavenging period 7～9s of diethyl zinc.
4. according to the manufacture method of the said phase-change random access memory array based on the ZnO Schottky diode of claim 1, it is characterized in that: when making word line and bit line, lower surface prepares the barrier layer above that respectively.
5. according to the manufacture method of the said phase-change random access memory array based on the ZnO Schottky diode of claim 1, it is characterized in that: on every word line, make conductive plunger word line is drawn, realize that bit line and word line are positioned on the substrate.
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