CN104078563A - Phase change memory, forming method of phase change memory and phase change memory array - Google Patents
Phase change memory, forming method of phase change memory and phase change memory array Download PDFInfo
- Publication number
- CN104078563A CN104078563A CN201310105912.0A CN201310105912A CN104078563A CN 104078563 A CN104078563 A CN 104078563A CN 201310105912 A CN201310105912 A CN 201310105912A CN 104078563 A CN104078563 A CN 104078563A
- Authority
- CN
- China
- Prior art keywords
- layer
- phase
- annular electrode
- electrode
- phase change
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a phase change memory, a forming method of a phase change memory and a phase change memory array. The forming method of the phase change memory comprises the steps of providing a semiconductor substrate, a first dielectric layer located on the surface of the semiconductor substrate, and an annular electrode located on the surface of the semiconductor substrate in the first dielectric layer; forming a blocking layer covering part of the annular electrode; forming a second dielectric layer covering part of the blocking layer and part of the annular electrode, wherein the second dielectric layer is thicker than the blocking layer, and a unique contact line exists between the lateral wall of the second dielectric layer and the top surface of the annular electrode; forming a phase change material layer; etching back the phase change material layer till the top surface of the annular electrode is exposed, wherein the part, located on the surface of the lateral wall of the second dielectric layer, of the phase change material layer forms a phase change layer. The phase change memory is low in operation power consumption.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of phase transition storage and forming method thereof, phase change memory array.
Background technology
Along with popularizing of the development of information technology, particularly mobile phone and other portable electric appts, non-volatile memory chip application has been penetrated into the every aspect of modern humans's life.Flash memory (Flash Memory) has obtained significant progress as a kind of typical nonvolatile memory between ten several years in the past, but at semiconductor technology, enter after 22nm node, the flash memory technology based on floating boom stored charge has run into difficulty in size aspect dwindling.Now, phase transition storage (PCM:Phase Change Memory) technology, because it has larger superiority in all many-sides such as cellar area, read or write speed, read-write number of times and data hold times with respect to flash memory technology, becomes the focus of current non-volatility memorizer research.
Please refer to Fig. 1, Fig. 1 shows the cross-sectional view of a kind of phase transition storage of prior art, comprising: Semiconductor substrate 100, comprises semiconductor device, metal interconnection structure and isolation structure in described Semiconductor substrate 100; Be positioned at the bottom electrode 101 of described Semiconductor substrate 100, the flush of the surface of described bottom electrode 101 and described Semiconductor substrate 100, described bottom electrode 101 is connected with semiconductor device or metal interconnection structure electricity in Semiconductor substrate 100; Be positioned at the first medium layer 102 in described Semiconductor substrate 100; Be positioned at the small electrode 103 of described first medium layer 102, described small electrode 103 is connected with described bottom electrode 101 electricity, the cross-sectional area of described small electrode 103 is less than the cross-sectional area of described bottom electrode 101, the flush of the surface of described small electrode 103 and described first medium layer 102; Be positioned at the phase-change material layers 105 on described small electrode 103; Be positioned at the transition metal layer 106 on described phase-change material layers 105, described transition metal layer 106 plays bonding and heat insulation effect; Be positioned at the top electrode 107 on described transition metal layer 106, described top electrode 107 is connected with external circuit; The second medium layer 104 of coated described phase-change material layers 105, described transition metal layer 106 and described top electrode 107, the flush of the surface of described second medium layer 104 and described top electrode 107.
In the phase transition storage course of work, by the semiconductor device in Semiconductor substrate 100, power, electric current is flowed through in the process of bottom electrode 101, small electrode 103, phase-change material layers 105, transition metal layer 106 and top electrode 107 and is produced Joule heat, to phase-change material layers 105 heating, impel to be positioned at described small electrode 103 tops phase-change material around and to undergo phase transition, between crystalline state and amorphous state, change.Phase transition storage is exactly to utilize the crystalline state of phase-change material and amorphous state resistance value to carry out recorded information.
But phase-change material is amorphous process by crystal transition, phase-change material need to be heated to rear quenching on fusion temperature, in this process, need larger electric current.Therefore, the power consumption of phase-change memory of prior art is high.
Summary of the invention
The problem that technical solution of the present invention solves is that the power consumption of phase-change memory of prior art is high.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of phase transition storage, comprise: Semiconductor substrate is provided, be positioned at the first medium layer of described semiconductor substrate surface, be positioned at the annular electrode of described semiconductor substrate surface, first medium layer, described annular electrode upper surface and described first medium layer flush, and described first medium layer is filled described annular electrode inside; The barrier layer of annular electrode described in formation cover part; The second medium layer that forms barrier layer and the described annular electrode of part described in cover part, the thickness of described second medium layer is greater than the thickness on described barrier layer, and the sidewall of described second medium layer and the top surface of described annular electrode have unique contact wire; Form phase-change material layers, described phase-change material layers covers top surface and the sidewall of described first medium layer, described annular electrode and described second medium layer; Return phase-change material layers described in etching until expose the top surface of described annular electrode, the phase-change material layers that is positioned at described second medium layer sidewall surfaces forms phase change layer.
Optionally, be also included in and form after phase-change material layers, on described phase-change material layers, form contact metal layer, and in phase-change material layers described in returning etching, return contact metal layer described in etching.
Optionally, the material of described contact metal layer is titanium nitride.
Optionally, be also included in described Semiconductor substrate and form bottom electrode, described bottom electrode is connected with described annular electrode electricity.
Optionally, the formation method of described annular electrode comprises: at described semiconductor substrate surface, form the 3rd dielectric layer; The 3rd dielectric layer described in etching, forms the first opening, and described the first opening exposes the top surface of described bottom electrode; Form annular electrode material layer, the bottom of the first opening and the top surface of sidewall and described the 3rd dielectric layer described in described annular electrode layer of material covers; Form the 4th dielectric layer that covers described annular electrode material layer, described the 4th dielectric layer is filled full the first opening; The 4th dielectric layer and described annular electrode material layer described in chemico-mechanical polishing, until expose the top surface of described the 3rd dielectric layer, described the first open bottom and the remaining annular electrode material layer of sidewall surfaces looping electrode, described the 3rd dielectric layer and residue the 4th dielectric layer form first medium layer.
Optionally, also comprise: described in time etching, after phase-change material layers, form the 5th layer of dielectric material that covers described first medium layer, annular electrode, barrier layer, phase change layer and second medium layer; The 5th layer of dielectric material described in chemico-mechanical polishing is until expose the top surface of described phase change layer, formation the 5th dielectric layer.
Optionally, be also included in and form after the 5th dielectric layer, on described the 5th dielectric layer, form top electrode, described top electrode is connected with described phase change layer electricity.
Optionally, described second medium layer is the stacked structure of silicon oxide layer and silicon nitride layer, and described silicon oxide layer is positioned on described silicon nitride layer.
Optionally, the technique that forms described phase-change material layers is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Optionally, described phase-change material layers is Ge
isb
jte
k, or doped with the Ge of nitrogen, oxygen or carbon
isb
jte
k, i wherein, j, k is atomic percent, and 0≤i < 1,0≤j < 1,0≤k < 1, i+j+k=1.
Corresponding, the present invention also provides a kind of phase transition storage, comprising: Semiconductor substrate, and described semiconductor substrate surface has first medium layer; Be positioned at the annular electrode of described semiconductor substrate surface, first medium layer, described annular electrode upper surface and described first medium layer flush, and described first medium layer is filled described annular electrode inside; Be positioned on described first medium layer, and the barrier layer of annular electrode described in cover part; Be positioned on described first medium layer, and the second medium layer of barrier layer and the described annular electrode of part described in cover part, the thickness of described second medium layer is greater than the thickness on described barrier layer, and the sidewall of described second medium layer and the top surface of described annular electrode have unique contact wire; Be positioned at the phase change layer of described second medium layer sidewall surfaces, described phase change layer contacts with described annular electrode.
Optionally, also comprise the contact metal layer that is positioned at described phase change layer sidewall surfaces, the material of described contact metal layer is titanium nitride.
Optionally, also comprise the bottom electrode that is positioned at described Semiconductor substrate, described bottom electrode is connected with described annular electrode electricity.
Optionally, also comprise the 5th dielectric layer being positioned on described first medium layer, annular electrode, barrier layer and phase change layer, described the 5th top surface of dielectric layer and the top surface of described phase change layer flush.
Optionally, also comprise the top electrode being positioned on described the 5th dielectric layer, described top electrode is connected with described phase change layer electricity.
Optionally, the material of described phase change layer is Ge
isb
jte
k, or doped with the Ge of nitrogen, oxygen or carbon
isb
jte
k, i wherein, j, k is atomic percent, and 0≤i < 1,0≤j < 1,0≤k < 1, i+j+k=1.
Corresponding, the present invention also provides a kind of phase change memory array, comprise: some above-mentioned phase transition storages, described phase transition storage is ranks and distributes, wherein the phase transition storage of every adjacent two row shares same barrier layer, and the phase transition storage of every adjacent two row shares same second medium layer and same top electrode.
Compared with prior art, technical solution of the present invention has the following advantages:
In the forming process of the phase transition storage of the embodiment of the present invention, first on annular electrode, form barrier layer; Form again second medium layer, barrier layer and the described annular electrode of part described in described second medium layer cover part, and the sidewall of described second medium layer and the top surface of described annular electrode have unique contact wire, guaranteed that the contact-making surface of the follow-up phase change layer forming in described second medium layer sidewall surfaces by side wall etching technics and described annular electrode is unique.Because the width of described phase change layer can pass through the THICKNESS CONTROL of sediment phase change material layer, can obtain and be less than the minimum dimension that existing photoetching process can reach, and then reduced phase change layer and described annular electrode contact area, reduced the volume of the phase-change material that undergoes phase transition in phase transition process, reached the object that reduces phase transition storage operation power consumption.
Further, in the embodiment of the present invention, the thickness that the width of the sidepiece of described annular electrode also can deposit annular electrode material layer by control regulates, and can obtain less size.After follow-up formation phase change layer, the contact area of described phase change layer and annular electrode is decided by the width of described annular electrode sidepiece and the width of described phase change layer, makes described contact area less, and the operation power consumption of phase transition storage is lower.
The phase transition storage of the embodiment of the present invention adopts the formation method of above-mentioned phase transition storage to form, and also has advantages of low-power consumption.The phase change memory array of the embodiment of the present invention is by above-mentioned phase transition storage ranks are arranged, and the phase transition storage of every adjacent two row shares same barrier layer, and the phase transition storage of every adjacent two row shares same second medium layer and same top electrode.Can reduce the process complexity of barrier layer in phase change memory array forming process, second medium layer and top electrode.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the phase transition storage of prior art;
Fig. 2 to Figure 14 is the structural representation of forming process of the phase transition storage of the embodiment of the present invention;
Figure 15 is the structural representation of the phase change memory array of the embodiment of the present invention.
Embodiment
From background technology, in prior art, in phase transition storage operating process, need larger electric current, cause power consumption of phase-change memory high.
The present inventor forms the method for phase transition storage by research prior art, please continue to refer to Fig. 1, find that in prior art, phase-change material layers 105 is positioned on described small electrode 103, phase-change material layers 105 is determined by the size of small electrode 103 completely with the contact area of described small electrode 103.In the phase transition storage course of work, the phase change region in phase-change material layers 105, the area size that phase-change material of transformation occurs between crystalline state and amorphous state has determined the size of phase transition storage operation power consumption.But prior art forms the process of phase transition storage and is limited to photoetching process, the size of small electrode 103 is still larger, the contact area of small electrode 103 and phase-change material layers 105 is larger, causes in the phase transition storage course of work phase change region large, and the power consumption of phase transition storage is too high.
Based on above research, technical solution of the present invention has proposed a kind of formation method of phase transition storage, first on annular electrode, form barrier layer, form again second medium layer, barrier layer and the described annular electrode of part described in described second medium layer cover part, then by side wall etching (Spacer Etch) technique, in described second medium layer sidewall surfaces, form phase change layer, because the sidewall of described second medium layer and the top surface of described annular electrode have unique contact wire, therefore the contact-making surface of described phase change layer and described annular electrode is also unique, and the width of described phase change layer can be by controlling the thickness of described phase-change material layers, acquisition is less than the minimum dimension that existing photoetching process can reach, reduced the contact area of phase change layer and annular electrode, reduced the volume of the phase-change material undergoing phase transition in phase transition process, reduced the operation power consumption of phase transition storage.
Below in conjunction with accompanying drawing, describe specific embodiment in detail, above-mentioned object and advantage of the present invention will be clearer.It should be noted that, the object that these accompanying drawings are provided is to contribute to understand embodiments of the invention, and should not be construed as restriction improperly of the present invention.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, dwindle or other changes.
Fig. 2 to Figure 14 is the structural representation of forming process of the phase transition storage of the embodiment of the present invention.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, in the interior formation bottom electrode 201 of described Semiconductor substrate 200, the flush of the surface of described bottom electrode 201 and described Semiconductor substrate 200.
Described Semiconductor substrate 200 can be monocrystalline silicon or monocrystalline germanium substrate, and described Semiconductor substrate 200 can be also SiGe, GaAs or silicon-on-insulator substrate (SOI) substrate.In described Semiconductor substrate 200, be formed with semiconductor device, metal interconnection structure and isolation structure.In the present embodiment, described Semiconductor substrate 200 is monocrystalline substrate, and described Semiconductor substrate 200 surfaces have insulating barrier (not shown), by insulating barrier described in etching, the through hole of formation and described semiconductor device or metal interconnection structural correspondence, in described through hole, deposits conductive material forms bottom electrode 201.Semiconductor device in described Semiconductor substrate 200 or metal interconnection structure are connected with described bottom electrode 201 electricity, and to the phase transition storage of follow-up formation, provide voltage or electric current by bottom electrode 201.In the present embodiment, the material of described bottom electrode 201 can be tungsten, copper, aluminium or doped silicon material.
Please refer to Fig. 3, on described Semiconductor substrate 200 surfaces, form the 3rd dielectric layers 202, the 3rd dielectric layer 202 described in etching, forms the first opening 203, and described the first opening 203 exposes the top surface of described bottom electrode 201.
Concrete, adopt the technique of chemical vapor deposition (CVD) or physical vapor deposition (PVD) in described Semiconductor substrate 200, to form the 3rd dielectric layer 202, the material of described the 3rd dielectric layer 202 is silica, silicon nitride or silicon oxynitride.In the present embodiment, the material of described the 3rd dielectric layer 202 is silica.On described the 3rd dielectric layer 202, form the first photoetching offset plate figure (not shown), take described the first photoetching offset plate figure as the 3rd dielectric layer 202 described in mask etching, until expose described Semiconductor substrate 200 surfaces and described bottom electrode 201 surfaces, form the first opening 203, remove described the first photoetching offset plate figure.
Please refer to Fig. 4, form annular electrode material layer 214, described annular electrode material layer 214 covers described the first opening 203(with reference to figure 3) bottom and the top surface of sidewall and described the 3rd dielectric layer 202; Form the 4th dielectric layer 205 that covers described annular electrode material layer 214, described the 4th dielectric layer 205 is filled full the first opening 203.
Concrete, adopt the technique of chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald to form annular electrode material layer 214, the thickness of described annular electrode material layer 214 is less than the degree of depth of described the first opening 203, described annular electrode material layer 214 covers bottom and the sidewall of described the first opening 203, and the top surface of described the 3rd dielectric layer 202.In the present embodiment, the material of described annular electrode material layer 214 can be titanium nitride, titanium, tungsten, copper or aluminium.Then, adopt the technique of physical vapour deposition (PVD) or chemical vapour deposition (CVD) to form the 4th dielectric layer 205 that covers described annular electrode material layer 214, described the 4th dielectric layer 205 is filled full described the first opening 203.The material of described the 4th dielectric layer 205 is identical with the material of described the 3rd dielectric layer 202, and in the present embodiment, the material of described the 4th dielectric layer 205 is silica.
Please refer to Fig. 5 and Fig. 6, Fig. 6 be Fig. 5 vertical view, described the 4th dielectric layer 205 of chemico-mechanical polishing (CMP) and described annular electrode material layer 214(are with reference to figure 4), until expose the top surface of described the 3rd dielectric layer 202, the remaining annular electrode material layer 214 looping electrodes 204 of described the first open bottom and sidewall surfaces, described the 3rd dielectric layer 202 and residue the 4th dielectric layer 205 form first medium layer 206.
Described in employing chemico-mechanical polishing, after the 4th dielectric layer 205 and described annular electrode material layer 214, remain annular electrode material layer 214 looping electrodes 204, residue the 4th dielectric layer 205 and the common formation first medium of described the 3rd dielectric layer 202 layer 206.Described annular electrode 204 has bottom and sidepiece, the bottom of described annular electrode 204 is connected with described bottom electrode 201 electricity, described annular electrode 204 is positioned at described first medium layer 206, and the upper surface of described annular electrode 204 flushes with the top surface of described first medium layer 206.
It should be noted that, the side width of described annular electrode 204 is the thickness of described annular electrode material layer 214, and the thickness of described annular electrode material layer 214 can be controlled by forming the technique of annular electrode material layer 214, for example, by controlling physical vapour deposition (PVD) or the technological parameter of chemical vapour deposition (CVD) and the thickness that sedimentation time is determined annular electrode material layer 214, while particularly adopting atom layer deposition process to form described annular electrode material layer 214, can be relatively easy to its THICKNESS CONTROL in nanometer scale, the minimum dimension that can reach much smaller than existing photoetching process.After follow-up formation phase change layer, the minimum dimension that the contact-making surface of described annular electrode 204 and phase change layer also can reach much smaller than existing photoetching process, can reduce the power consumption in phase transition storage operating process.The sidepiece of described annular electrode 204 is straight-flanked ring, square loop, annulus or irregular figure ring along the section shape of Semiconductor substrate in-plane.In the present embodiment, described annular electrode 204 is straight-flanked ring along the section shape of Semiconductor substrate in-plane.
Please refer to Fig. 7, Fig. 7 continue to form phase transition storage on the basis of Fig. 6, forms the barrier layer 207 of annular electrode 204 described in cover part.
Adopt technique deposited barrier material layer (not shown) on described first medium layer 206 of chemical vapour deposition (CVD) or physical vapour deposition (PVD), described barrier material layer covers described annular electrode 207, and the material of described barrier material layer is silica, silicon nitride or silicon oxynitride.On described barrier material layer, form the second photoetching offset plate figure (not shown), take described the second photoetching offset plate figure as barrier material layer described in mask etching, until expose described first medium layer 206, remove described the second photoetching offset plate figure, residue barrier material layer forms barrier layer 207.Due to annular electrode 204 described in 207 cover parts, described barrier layer, after follow-up formation second medium layer, the part annular electrode 204 being covered by described barrier layer 207 is isolated with described second medium layer, make the sidewall of described second medium layer and the top surface of described annular electrode 204 there is unique contact wire, the follow-up sidewall surfaces at described second medium layer forms after phase change layer, and the contact-making surface of described phase change layer and described annular electrode is also unique.
Please refer to Fig. 8, Fig. 9 and Figure 10, wherein Fig. 9 be Fig. 8 along the generalized section of AA1 direction, Figure 10 is that Fig. 8 is along the generalized section of BB1 direction.The second medium layer 208 of barrier layer 207 and the described annular electrode 204 of part described in formation cover part, the thickness of described second medium layer 208 is greater than the thickness on described barrier layer 207, and the top surface of the sidewall of described second medium layer 208 and described annular electrode 204 has unique contact wire.
Adopt the technique of chemical vapour deposition (CVD) or physical vapour deposition (PVD) on described first medium layer 206, annular electrode 204 and barrier layer 207, to deposit second medium material layer (not shown); On described second medium material layer, form the 3rd photoetching offset plate figure (not shown), described the 3rd photoetching offset plate figure is corresponding with second medium layer to be formed position; Take described the 3rd photoetching offset plate figure as second medium material layer described in mask etching, until expose part first medium layer 206, part annular electrode 204 and part barrier layer 207, remove described the 3rd photoetching offset plate figure, residue second medium material layer forms second medium layer 208.In the present embodiment, described second medium material layer is the stacked structure of silica and silicon nitride layer, and described silicon oxide layer is positioned on described silicon nitride layer.In second medium material layer etching process, first using described silicon nitride layer as etching stop layer, silicon oxide layer described in employing dry etch process etching, change again etching parameters, as adopt wet etching remove as described in silicon nitride layer, can reduce in second medium material layer etching process the damage to described annular electrode 204.
Please continue to refer to Fig. 9, existence due to described barrier layer 207, make by the annular electrode 204 of described barrier layer 207 coverings isolated with described barrier layer 208, therefore, after forming described second medium layer 208, the top surface of the sidewall of described second medium layer 208 and described annular electrode 204 has unique contact wire (with reference to figure 8).The follow-up sidewall surfaces at described second medium layer 208 forms after phase change layer, and the contact-making surface of described phase change layer and described annular electrode 204 is also unique.Follow-up in phase transition storage operating process, the phase change layer region that produces phase transformation is only positioned at unique contact-making surface region of described phase change layer and described annular electrode, can not produce a plurality of phase change region and cause phase transition storage to lose efficacy.
In addition, in the present embodiment, the thickness of described second medium layer 208 is greater than the thickness on described barrier layer 207.Phase change layer described in subsequent technique forms by side wall etching (Spacer Etch) technique; because phase-change material layers not only can cover the sidewall of described second medium layer 208; also can cover the sidewall on described barrier layer 207; the thickness of described second medium layer 208 is greater than the thickness on described barrier layer 207; can guarantee back after etching technics that only the sidewall surfaces at described second medium layer 208 forms phase change layer, the phase-change material layers of barrier layer 207 sidewall surfaces can be removed clean.In the present embodiment, the thickness of described second medium layer 208 is greater than three times of described barrier layer 207 thickness.
Please refer to Figure 11, Figure 11 continues to form phase transition storage on the basis of Figure 10, form phase-change material layers 209, described phase-change material layers 209 covers top surface and the sidewall of described first medium layer 206, described annular electrode 204 and described second medium layer 208.
The technique that forms phase-change material layers 209 can be physical vapour deposition (PVD) or chemical vapour deposition (CVD), and the material of described phase-change material layers 209 is Ge
isb
jte
k, or doped with the Ge of nitrogen, oxygen or carbon
isb
jte
ki wherein, j, k is atomic percent, be that i is the percentage of germanium atom in germanium-antimony-tellurium compound, j is the percentage of antimony atoms in germanium-antimony-tellurium compound, and k is the percentage of tellurium atom in germanium-antimony-tellurium compound, and 0≤i < 1,0≤j < 1,0≤k < 1, i+j+k=1.For example the material of described phase-change material layers 209 is Ge
2sb
2te
5, corresponding i=2/9, j=2/9, k=5/9.
In the present embodiment, after forming phase-change material layers 209, on described phase-change material layers 209, form contact metal layer 210.The technique that forms described contact metal layer 210 can be physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process, and the material of described contact metal layer 210 is titanium nitride.Described contact metal layer 210 can reduce phase change layer and the diffusion of the atom between top electrode and the 5th dielectric layer of follow-up formation, improve the reliability of phase transition storage, described contact metal layer 210 can also reduce heat conduction and the contact resistance between phase change layer and the top electrode of follow-up formation.
Please refer to Figure 12, return described in etching phase-change material layers 209(with reference to Figure 11) until expose the top surface of described annular electrode 204, the phase-change material layers 209 that is positioned at described second medium layer 208 sidewall surfaces forms phase change layers 211.
Concrete, adopt anisotropic dry etch process to return phase-change material layers 209 described in etching, in the present embodiment, described dry etch process is reactive ion etching.Because reactive ion etching has good directivity, without forming mask, return phase-change material layers 209 described in etching, remove the phase-change material layers 209 in described second medium layer 208 top surface and other regions, until expose the top surface of described annular electrode 204, the phase-change material layers 209 that is only positioned at described second medium layer 208 sidewall surfaces retains, and forms phase change layer 211.Because described second medium layer 208 sidewall and described annular electrode 204 have unique contact wire, therefore described phase change layer 211 also has unique contact-making surface with described annular electrode 204.In addition, because the thickness of the layer of second medium described in the present embodiment 208 is greater than the thickness on described barrier layer 207, the height of the phase-change material layers 209 of described second medium layer 208 sidewall surfaces is greater than the height of the phase-change material layers 209 of described barrier layer 207 sidewall surfaces, return in etching process, the phase-change material layers 209 of described barrier layer 207 sidewall surfaces can be completely removed.
In this enforcement, on described phase-change material layers 209, be formed with contact metal layer 210, in phase-change material layers 209 described in returning etching, return contact metal layer 210 described in etching, after returning etching technics, between described contact metal layer 210 and described annular electrode 204, by phase change layer 211, isolate.
Because phase change layer described in the present embodiment 211 forms by side wall etching technics, the width of described phase change layer 211 can regulate by thickness and the etching technics of phase-change material layers 209.And the thickness of described phase-change material layers 209 can regulate by controlling deposition process parameters and sedimentation time, can be relatively easy to acquisition and be less than the minimum dimension that existing photoetching process can reach.And as previously mentioned, the side width of described annular electrode 204 also can be less than the minimum dimension that existing photoetching process can reach, the contact area of described annular electrode 204 and described phase change layer 211 will reduce greatly.In the operating process of phase transition storage, operating current is by the bottom electrode annular electrode of flowing through, heating phase-change material on the contact-making surface of described annular electrode 204 and described phase change layer 211, phase-change material is changed between crystalline state and amorphous state, because described phase change layer 211 and the contact area of described annular electrode 204 reduce, thereby reduced the volume of the phase-change material that undergoes phase transition in phase transition process, reached the object that reduces operation power consumption.
Please refer to Figure 13, form the 5th layer of dielectric material (not shown) that covers described first medium layer 206, annular electrode 204, barrier layer 207, phase change layer 211 and second medium layer 208; The 5th layer of dielectric material described in chemico-mechanical polishing is until expose the top surface of described phase change layer 211, formation the 5th dielectric layer 212.
The technique that forms described the 5th layer of dielectric material can be physical vapour deposition (PVD) or chemical vapour deposition (CVD), and the material of described the 5th layer of dielectric material can be silicon nitride, silica, silicon oxynitride or low-K material.By the 5th layer of dielectric material described in chemico-mechanical polishing, until expose the top surface of described phase change layer 211, form the 5th dielectric layer 212.Described the 5th dielectric layer 212 and described second medium layer 208 are as isolation structure, jointly by described phase change layer 211 and peripheral devices electric isolation.
Please refer to Figure 14, on described the 5th dielectric layer 212, form top electrode 213, described top electrode 213 is connected with described phase change layer 211 electricity.
Adopt chemical vapour deposition (CVD) or physical gas-phase deposition to form upper electrode material layer (not shown), described upper electrode material layer covers described phase change layer 211, the 5th dielectric layer 212 and second medium layer 208, and the material of described upper electrode material layer can be copper, aluminium, tungsten or titanium.Then, on described upper electrode material layer, form the 4th photoetching offset plate figure, described the 4th photoetching offset plate figure is corresponding with the position of described phase change layer 211, take described the 4th photoetching offset plate figure as upper electrode material layer described in mask etching, until expose described the 5th dielectric layer 212 surfaces, remove described the 4th photoetching offset plate figure, residue upper electrode material layer forms top electrode 213.In the present embodiment, the top surface of the 5th dielectric layer 212 surfaces and described second medium layer 208 described in described top electrode 213 cover parts, described top electrode 213 also covers the top surface of described phase change layer 211, and described top electrode 213 is connected with described phase change layer 211 electricity.
Corresponding, please continue to refer to Figure 14, the embodiment of the present invention also provides a kind of phase transition storage, comprising: Semiconductor substrate 200, and described Semiconductor substrate 200 surfaces have first medium layer 206; Be positioned at the annular electrode 204 of described Semiconductor substrate 200 surfaces, first medium layer 206, described annular electrode 204 upper surfaces and described first medium layer 206 flush, and described first medium layer 206 is filled described annular electrode 204 inside; Be positioned on described first medium layer 206, and the barrier layer (not shown) of annular electrode 204 described in cover part; Be positioned on described first medium layer 206, and the second medium layer 208 of the described annular electrode 204 of barrier layer and part described in cover part, the thickness of described second medium layer 208 is greater than the thickness on described barrier layer, and the top surface of the sidewall of described second medium layer 208 and described annular electrode 204 has unique contact wire; Be positioned at the phase change layer 211 of described second medium layer 208 sidewall surfaces, described phase change layer 211 contacts with described annular electrode 204.
In the present embodiment, also comprise the contact metal layer 210 that is positioned at described phase change layer 211 sidewall surfaces, the material of described contact metal layer 210 is titanium nitride.
In the present embodiment, also comprise the bottom electrode 201 that is positioned at described Semiconductor substrate 200, described bottom electrode 201 is connected with described annular electrode 204 electricity.
In the present embodiment, also comprise the 5th dielectric layer 212 being positioned on described first medium layer 206, annular electrode 204, barrier layer 207 and phase change layer 211, the top surface of described the 5th dielectric layer 212 flushes with the top surface of described phase change layer 211.
In the present embodiment, also comprise the top electrode 213 being positioned on described the 5th dielectric layer 212, described top electrode 213 is connected with described phase change layer 211 electricity.In the present embodiment, the material of described phase change layer 211 is Ge
isb
jte
k, or doped with the Ge of nitrogen, oxygen or carbon
isb
jte
k, i wherein, j, k is atomic percent, and 0≤i < 1,0≤j < 1,0≤k < 1, i+j+k=1.
The phase transition storage of the embodiment of the present invention adopts the formation method of above-mentioned phase transition storage to form, specifically can be with reference to the description of the formation method of above-mentioned phase transition storage, and described phase transition storage also has advantages of low-power consumption.
Corresponding, please refer to Figure 15, the present invention also provides a kind of phase change memory array, comprise: some above-mentioned phase transition storages 215, the structure of described phase transition storage 215 please refer to Figure 14 and associated description, described phase transition storage is ranks and distributes, and wherein the phase transition storage 215 of every adjacent two row shares same barrier layer 207, and the phase transition storage of every adjacent two row shares same second medium layer 208 and same top electrode 213.It should be noted that, it is example that Figure 15 be take the vertical view of phase change memory array of two row two row, for the purpose of knowing for simplicity, only show annular electrode 204, barrier layer 207, second medium layer 208, the perspective position relation of phase change layer 211 and top electrode 213, and the phase transition storage 215 that the phase change memory array of two row two row in Figure 15 only shows every adjacent two row shares same barrier layer 207, the phase transition storage of every adjacent two row shares the situation of same top electrode 213, in having the phase change memory array of multiple row more, the phase transition storages of every adjacent two row also share same second medium layer 208.
Because adopting aforementioned phase transition storage, described phase change memory array forms, described phase change memory array has advantages of low-power consumption, and in described phase change memory array, the phase transition storage of every adjacent two row shares same barrier layer 207, described barrier layer 207 covers the part annular electrode 204 of adjacent two row simultaneously, can reduce the process complexity that forms described barrier layer 207.In like manner, the phase transition storage of every adjacent two row shares same second medium layer 208 and same top electrode 213, also can reduce the process complexity that forms described second medium layer 208 and top electrode 213.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (17)
1. a formation method for phase transition storage, is characterized in that, comprising:
Semiconductor substrate is provided, be positioned at the first medium layer of described semiconductor substrate surface, be positioned at the annular electrode of described semiconductor substrate surface, first medium layer, described annular electrode upper surface and described first medium layer flush, and described first medium layer is filled described annular electrode inside;
The barrier layer of annular electrode described in formation cover part;
The second medium layer that forms barrier layer and the described annular electrode of part described in cover part, the thickness of described second medium layer is greater than the thickness on described barrier layer, and the sidewall of described second medium layer and the top surface of described annular electrode have unique contact wire;
Form phase-change material layers, described phase-change material layers covers top surface and the sidewall of described first medium layer, described annular electrode and described second medium layer;
Return phase-change material layers described in etching until expose the top surface of described annular electrode, the phase-change material layers that is positioned at described second medium layer sidewall surfaces forms phase change layer.
2. the formation method of phase transition storage as claimed in claim 1, it is characterized in that, be also included in and form after phase-change material layers, on described phase-change material layers, form contact metal layer, and in phase-change material layers described in returning etching, return contact metal layer described in etching.
3. the formation method of phase transition storage as claimed in claim 2, is characterized in that, the material of described contact metal layer is titanium nitride.
4. the formation method of phase transition storage as claimed in claim 1, is characterized in that, is also included in described Semiconductor substrate and forms bottom electrode, and described bottom electrode is connected with described annular electrode electricity.
5. the formation method of phase transition storage as claimed in claim 4, is characterized in that, the formation method of described annular electrode comprises:
At described semiconductor substrate surface, form the 3rd dielectric layer;
The 3rd dielectric layer described in etching, forms the first opening, and described the first opening exposes the top surface of described bottom electrode;
Form annular electrode material layer, the bottom of the first opening and the top surface of sidewall and described the 3rd dielectric layer described in described annular electrode layer of material covers;
Form the 4th dielectric layer that covers described annular electrode material layer, described the 4th dielectric layer is filled full the first opening;
The 4th dielectric layer and described annular electrode material layer described in chemico-mechanical polishing, until expose the top surface of described the 3rd dielectric layer, described the first open bottom and the remaining annular electrode material layer of sidewall surfaces looping electrode, described the 3rd dielectric layer and residue the 4th dielectric layer form first medium layer.
6. the formation method of phase transition storage as claimed in claim 1, it is characterized in that, also comprise: described in time etching, after phase-change material layers, form the 5th layer of dielectric material that covers described first medium layer, annular electrode, barrier layer, phase change layer and second medium layer; The 5th layer of dielectric material described in chemico-mechanical polishing is until expose the top surface of described phase change layer, formation the 5th dielectric layer.
7. the formation method of phase transition storage as claimed in claim 6, is characterized in that, is also included in and forms after the 5th dielectric layer, on described the 5th dielectric layer, forms top electrode, and described top electrode is connected with described phase change layer electricity.
8. the formation method of phase transition storage as claimed in claim 1, is characterized in that, described second medium layer is the stacked structure of silicon oxide layer and silicon nitride layer, and described silicon oxide layer is positioned on described silicon nitride layer.
9. the formation method of phase transition storage as claimed in claim 1, is characterized in that, the technique that forms described phase-change material layers is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
10. the formation method of phase transition storage as claimed in claim 1, is characterized in that, described phase-change material layers is Ge
isb
jte
k, or doped with the Ge of nitrogen, oxygen or carbon
isb
jte
k, i wherein, j, k is atomic percent, and 0≤i < 1,0≤j < 1,0≤k < 1, i+j+k=1.
11. 1 kinds of phase transition storages, is characterized in that, comprising:
Semiconductor substrate, described semiconductor substrate surface has first medium layer;
Be positioned at the annular electrode of described semiconductor substrate surface, first medium layer, described annular electrode upper surface and described first medium layer flush, and described first medium layer is filled described annular electrode inside;
Be positioned on described first medium layer, and the barrier layer of annular electrode described in cover part;
Be positioned on described first medium layer, and the second medium layer of barrier layer and the described annular electrode of part described in cover part, the thickness of described second medium layer is greater than the thickness on described barrier layer, and the sidewall of described second medium layer and the top surface of described annular electrode have unique contact wire;
Be positioned at the phase change layer of described second medium layer sidewall surfaces, described phase change layer contacts with described annular electrode.
12. phase transition storages as claimed in claim 11, is characterized in that, also comprise the contact metal layer that is positioned at described phase change layer sidewall surfaces, and the material of described contact metal layer is titanium nitride.
13. phase transition storages as claimed in claim 11, is characterized in that, also comprise the bottom electrode that is positioned at described Semiconductor substrate, and described bottom electrode is connected with described annular electrode electricity.
14. phase transition storages as claimed in claim 11, is characterized in that, also comprise the 5th dielectric layer being positioned on described first medium layer, annular electrode, barrier layer and phase change layer, and described the 5th top surface of dielectric layer and the top surface of described phase change layer flush.
15. phase transition storages as claimed in claim 14, is characterized in that, also comprise the top electrode being positioned on described the 5th dielectric layer, and described top electrode is connected with described phase change layer electricity.
16. phase transition storages as claimed in claim 11, is characterized in that, the material of described phase change layer is Ge
isb
jte
k, or doped with the Ge of nitrogen, oxygen or carbon
isb
jte
k, i wherein, j, k is atomic percent, and 0≤i < 1,0≤j < 1,0≤k < 1, i+j+k=1.
17. 1 kinds of phase change memory arrays, it is characterized in that, comprise: some phase transition storages as described in any one in claim 11 to 16, described phase transition storage is ranks and distributes, wherein the phase transition storage of every adjacent two row shares same barrier layer, and the phase transition storage of every adjacent two row shares same second medium layer and same top electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310105912.0A CN104078563A (en) | 2013-03-28 | 2013-03-28 | Phase change memory, forming method of phase change memory and phase change memory array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310105912.0A CN104078563A (en) | 2013-03-28 | 2013-03-28 | Phase change memory, forming method of phase change memory and phase change memory array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104078563A true CN104078563A (en) | 2014-10-01 |
Family
ID=51599715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310105912.0A Pending CN104078563A (en) | 2013-03-28 | 2013-03-28 | Phase change memory, forming method of phase change memory and phase change memory array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104078563A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716260A (en) * | 2015-03-24 | 2015-06-17 | 中国科学院上海微系统与信息技术研究所 | Sb-Te-Cr phase-change material, phase-change storage unit and manufacturing method thereof |
| CN110335941A (en) * | 2019-07-03 | 2019-10-15 | 芯盟科技有限公司 | Structure of phase transition storage and forming method thereof |
| CN112599667A (en) * | 2020-12-15 | 2021-04-02 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN115312454A (en) * | 2022-10-11 | 2022-11-08 | 合肥新晶集成电路有限公司 | Semiconductor structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6501111B1 (en) * | 2000-06-30 | 2002-12-31 | Intel Corporation | Three-dimensional (3D) programmable device |
| CN1992326A (en) * | 2005-12-30 | 2007-07-04 | 财团法人工业技术研究院 | Semiconductor storage element, phase-change storage element and method for fabrication thereof |
| US20080164454A1 (en) * | 2007-01-10 | 2008-07-10 | Winbond Electronics Corp. | Phase change memory device and method for fabricating the same |
| CN101226989A (en) * | 2008-01-22 | 2008-07-23 | 中国科学院上海微系统与信息技术研究所 | Transition layer for phase-change memory |
| CN102403454A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Method for making phase change memory component |
-
2013
- 2013-03-28 CN CN201310105912.0A patent/CN104078563A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6501111B1 (en) * | 2000-06-30 | 2002-12-31 | Intel Corporation | Three-dimensional (3D) programmable device |
| CN1992326A (en) * | 2005-12-30 | 2007-07-04 | 财团法人工业技术研究院 | Semiconductor storage element, phase-change storage element and method for fabrication thereof |
| US20080164454A1 (en) * | 2007-01-10 | 2008-07-10 | Winbond Electronics Corp. | Phase change memory device and method for fabricating the same |
| CN101226989A (en) * | 2008-01-22 | 2008-07-23 | 中国科学院上海微系统与信息技术研究所 | Transition layer for phase-change memory |
| CN102403454A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Method for making phase change memory component |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716260A (en) * | 2015-03-24 | 2015-06-17 | 中国科学院上海微系统与信息技术研究所 | Sb-Te-Cr phase-change material, phase-change storage unit and manufacturing method thereof |
| CN110335941A (en) * | 2019-07-03 | 2019-10-15 | 芯盟科技有限公司 | Structure of phase transition storage and forming method thereof |
| CN110335941B (en) * | 2019-07-03 | 2023-08-18 | 芯盟科技有限公司 | Phase change memory structure and forming method thereof |
| CN112599667A (en) * | 2020-12-15 | 2021-04-02 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN112599667B (en) * | 2020-12-15 | 2024-06-18 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN115312454A (en) * | 2022-10-11 | 2022-11-08 | 合肥新晶集成电路有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100639206B1 (en) | Phase-change memory device and method for manufacturing the same | |
| JP6059349B2 (en) | 3D memory array architecture | |
| CN101461071B (en) | A vertical phase change memory cell and methods for manufacturing thereof | |
| CN102237390B (en) | Semiconductor device and method of manufacturing same | |
| CN108417236B (en) | Vertical semiconductor device, method of manufacturing the same, and method of operating the same | |
| US7151300B2 (en) | Phase-change memory device and method for manufacturing the same | |
| CN103165662B (en) | Resistive memory device and method of manufacturing the same | |
| CN103855300A (en) | Phase change storage and forming method thereof | |
| KR20140077499A (en) | Variable Resistance Memory Device and Method of Manufacturing The Same | |
| CN104078563A (en) | Phase change memory, forming method of phase change memory and phase change memory array | |
| JP2015072977A (en) | Nonvolatile semiconductor storage device and manufacturing method of the same | |
| CN101882627A (en) | Phase change memory device and manufacturing method thereof | |
| KR20090088523A (en) | Phase-change memory device and fabrication method thereof | |
| US8084759B2 (en) | Integrated circuit including doped semiconductor line having conductive cladding | |
| KR20130087196A (en) | Method for manufacturing phase-change random access memory device and method of manufacturing the same | |
| CN106298481A (en) | Phase transition storage and forming method thereof | |
| US7755074B2 (en) | Low area contact phase-change memory | |
| KR101052860B1 (en) | Phase change memory device and its manufacturing method | |
| US20230209836A1 (en) | Memory device and method for fabricating the same | |
| US20100061140A1 (en) | Integrated circuit including doped semiconductor line having conductive cladding | |
| CN102956819A (en) | Forming method of phase change memory | |
| US20080315171A1 (en) | Integrated circuit including vertical diode | |
| CN106997924B (en) | Phase transition storage and its manufacturing method and electronic equipment | |
| US7696510B2 (en) | Integrated circuit including memory having reduced cross talk | |
| CN112585758A (en) | Novel gap fill and cell structure for improved selector thermal reliability for 3D PCM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141001 |