CN117412664A - Semiconductor structure, forming method thereof and memory - Google Patents

Semiconductor structure, forming method thereof and memory Download PDF

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Publication number
CN117412664A
CN117412664A CN202210786445.1A CN202210786445A CN117412664A CN 117412664 A CN117412664 A CN 117412664A CN 202210786445 A CN202210786445 A CN 202210786445A CN 117412664 A CN117412664 A CN 117412664A
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Prior art keywords
layer
ion implantation
substrate
phase change
forming
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廖昱程
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210786445.1A priority Critical patent/CN117412664A/en
Priority to PCT/CN2022/108178 priority patent/WO2024007381A1/en
Priority to US18/155,656 priority patent/US20240008376A1/en
Publication of CN117412664A publication Critical patent/CN117412664A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors

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Abstract

The embodiment of the disclosure discloses a semiconductor structure, a forming method thereof and a memory. The semiconductor structure includes: a substrate; a phase change memory cell located on the substrate; the phase change memory cell includes: the heating layer is positioned between the phase change material layer and the substrate; the heating layer includes a first portion composed of a first conductive material and a second portion composed of a second conductive material, the first portion surrounding at least a sidewall of the second portion.

Description

Semiconductor structure, forming method thereof and memory
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a forming method thereof and a memory.
Background
Phase change memories (Phase Change Memory, PCM) are new types of memories that exploit the large resistance differences of phase change materials in crystalline and amorphous states to enable information storage. The phase change material has higher resistance in an amorphous state, and the molecular structure of the phase change material is in a disordered state; the phase change material has lower resistance in the crystalline state, the internal molecular structure is in an ordered state, and the resistance difference between the two states is usually up to 2 orders of magnitude.
By means of the current-induced joule heat, a rapid transition of the phase change material between two resistive states (high resistance and low resistance) can be achieved.
PCM has the advantages of strong stability, low power consumption, high storage density, compatibility with the traditional CMOS process and the like, so that the PCM is paid attention to by more researchers and enterprises. PCM is considered to be one of the most potential next generation non-volatile memories with its great advantages. How to increase the storage density and the storage speed of PCM has become a problem to be solved.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a memory.
In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising:
a substrate;
a phase change memory cell located on the substrate;
the phase change memory cell includes: the heating layer is positioned between the phase change material layer and the substrate;
the heating layer includes a first portion composed of a first conductive material and a second portion composed of a second conductive material, the first portion surrounding at least a sidewall of the second portion.
In some embodiments, the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.
In some embodiments, the sidewalls and at least a portion of the upper surface of the phase change memory cell are also covered with a thermal insulation layer.
In some embodiments, the phase change memory cell further comprises:
and the diode is perpendicular to the substrate, is positioned between the substrate and the heating layer, and is in a conduction direction from the heating layer to the substrate.
In some embodiments, the diode comprises:
a first ion implantation structure located on the substrate;
a second ion implantation structure located on the first ion implantation structure;
the ion type of the first ion implantation structure is opposite to the ion type of the second ion implantation structure.
In some embodiments, the second ion implantation structure comprises:
an upper layer second ion implantation structure and a lower layer second ion implantation structure, wherein the ion concentration of the upper layer second ion implantation structure is different from that of the lower layer second ion implantation structure.
In some embodiments, the substrate comprises:
a back substrate;
an oxygen-buried layer on the backing substrate;
the doping structure is positioned on the oxygen burying layer and is in direct contact with the first ion implantation structure;
And the shallow trench isolation structure is positioned between the adjacent doped structures.
In some embodiments, the doping structure includes:
an N well located on the buried oxide layer;
a P well located on the N well;
and the third ion implantation structure is positioned on the surface of the P well and is in direct contact with the first ion implantation structure.
In some embodiments, the semiconductor structure further comprises:
an interlayer dielectric layer positioned between the phase change memory cells;
and the first conductive structure penetrates through the interlayer dielectric layer and is connected with the third ion implantation structure.
In some embodiments, the semiconductor structure further comprises:
a second conductive structure connected to the phase change memory cell;
wherein the first conductive structure is connected with a first conductive line extending in a first direction parallel to the substrate, and the second conductive structure is connected with a second conductive line extending in a second direction parallel to the substrate, the second direction intersecting the first direction.
In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, including:
providing a substrate;
forming a phase change memory cell on the substrate; the phase change memory cell includes:
The phase change material layer and the heating layer are positioned between the phase change material layer and the substrate, and the heating layer comprises a first part formed by a first conductive material and a second part formed by a second conductive material, and the first part at least surrounds the side wall of the second part.
In some embodiments, the method further comprises:
and forming an insulating layer to cover the side wall and at least part of the upper surface of the phase change memory unit.
In some embodiments, the phase change memory cell further comprises: a diode; forming a phase change memory cell on the substrate includes:
forming a diode on the substrate perpendicular to the substrate;
forming the heating layer on the diode;
the phase change material layer is formed on the heating layer.
In some embodiments, forming a diode on the substrate perpendicular to the substrate includes:
forming a first ion implantation layer on the substrate;
forming a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;
and etching the first ion implantation layer and the second ion implantation layer to form a first ion implantation structure and a second ion implantation structure so as to form the diode.
In some embodiments, forming the second ion implantation layer includes:
forming a lower second ion implantation layer;
forming an upper second ion implantation layer on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from that of the lower second ion implantation layer.
In some embodiments, forming the heating layer on the diode includes:
forming a first conductive layer on the second ion implantation layer;
etching the first conductive layer to form a plurality of groove structures;
filling the second conductive material in the groove structure to form the second part;
the first conductive layer outside the second portion is etched to form the first portion.
In some embodiments, the substrate comprises a back substrate, an oxygen-buried layer on the back substrate, and a top layer of silicon on the oxygen-buried layer; before the step of forming the phase change memory cell on the substrate, the method further comprises:
doping the top silicon layer to form a doped layer; the doped layer comprises an N well layer, a P well layer and a third ion implantation layer;
etching the doped layer to form a plurality of doped structures, wherein the doped structures comprise an N well, a P well and a third ion implantation structure, and the third ion implantation structure is connected with the first ion implantation structure;
And forming shallow trench isolation structures and filling grooves between adjacent doped structures.
In some embodiments, the method further comprises:
forming an interlayer dielectric layer, and filling the interlayer dielectric layer between a plurality of the phase change memory cells;
and forming a first conductive structure which penetrates through the interlayer dielectric layer and is connected with the third ion implantation structure.
In some embodiments, the method further comprises:
forming a second conductive structure connected with the phase change memory unit;
wherein the first conductive structure is connected with a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected with a second conductive line extending along a second direction parallel to the substrate; the second direction intersects the first direction.
In a third aspect, embodiments of the present disclosure further provide a memory including a memory cell array including the semiconductor structure of any one of the above embodiments, and a peripheral circuit structure located above or outside the memory cell array.
In an embodiment of the present disclosure, the heating layer is formed using two conductive materials, and the heating layer has a first portion and a second portion, and the first portion surrounds at least a sidewall of the second portion. Therefore, the heating efficiency can be improved by utilizing the advantages of the conductive material of the first part, and the second part surrounds the first part, so that the heated heat is not easy to dissipate, and the heating efficiency is further improved. After the heating efficiency is improved, the time required for phase transition of the phase change material layer is shorter, so that the phase transition can occur faster, and the data writing speed can be improved.
Drawings
FIG. 1 is a schematic diagram of a phase change memory provided in some embodiments;
fig. 2 through 4 are schematic cross-sectional views of a semiconductor structure provided in embodiments of the present disclosure;
fig. 5-8 are schematic diagrams of top cross-sectional views of heating layers provided by embodiments of the present disclosure;
fig. 9 to 13 are schematic cross-sectional views of a semiconductor structure according to an embodiment of the present disclosure;
fig. 14 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
FIG. 15 is a schematic view of a substrate provided by an embodiment of the present disclosure;
fig. 16 to 38 are schematic cross-sectional views of a semiconductor structure provided in an embodiment of the present disclosure;
fig. 39 is a top view of a semiconductor structure provided by an embodiment of the present disclosure;
FIG. 40 is a simplified circuit diagram of a semiconductor structure provided by embodiments of the present disclosure;
FIG. 41 is a graph of current versus voltage for a memory cell of a semiconductor structure according to an embodiment of the present disclosure;
fig. 42 is a schematic diagram of a memory formed by a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.
It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.
Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In the presently disclosed embodiments, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
Deposition processes described in embodiments of the present disclosure, including but not limited to deposition processes, may include but are not limited to: chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma Enhanced CVD (PECVD), sputtering (Sputtering), metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD), atomic layer deposition (Atomic Layer Deposition, ALD), combinations thereof, and the like.
Growth processes described in embodiments of the present disclosure include, but are not limited to: vapor phase epitaxy (Vapour Phase Epitaxy, VPE), liquid phase epitaxy (Liquid Phase Epitaxy, LPE), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), ion beam epitaxy, solid phase epitaxy, combinations thereof, and the like.
The etching process according to the embodiments of the present disclosure includes, but is not limited to: dry etching, wet etching, and combinations thereof.
Embodiments of the present disclosure relate to semiconductor structures that will be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a three-dimensional PCM memory, or other memory chip or processing chip including PCM memory cells.
The phase change memory is a novel memory for realizing information storage by utilizing the huge resistance difference of the phase change material in a crystalline state and an amorphous state. The phase change material has higher resistance in an amorphous state, and the molecular structure of the phase change material is in a disordered state; the phase change material has lower resistance in the crystalline state, the internal molecular structure is in an ordered state, and the resistance difference between the two states is usually up to 2 orders of magnitude.
By means of the current-induced joule heat, a rapid transition of the phase change material between two resistive states (high resistance and low resistance) can be achieved. PCM has the advantages of strong stability, low power consumption, high storage density, compatibility with the traditional CMOS process and the like, so that the PCM is paid attention to by more researchers and enterprises. PCM is considered to be one of the most potential next generation non-volatile memories with its great advantages.
In some embodiments, as shown in fig. 1, a phase change memory cell 100 in a phase change memory includes a planar MOS transistor 110 and a phase change cell 120. The phase change cell 120 includes a KH (Key Heater) structure. The resistance of the phase change material in the phase change material layer 130 in the phase change cell 120 may be changed by the formation heater, the phase change material having a high resistivity in an amorphous state, which may be used to store data "1", and a low resistivity in a crystalline state, which may be used to store data "0". This makes use of the reversible phase change of the phase change material to store information.
Embodiments of the present disclosure provide a semiconductor structure, as shown in fig. 2, comprising: a substrate 210; a phase change memory cell 300 on the substrate 210; a phase change material layer 310 and a heating layer 320, the heating layer 320 being located between the phase change material layer 310 and the substrate 210; the heating layer 320 includes a first portion 321 composed of a first conductive material and a second portion 322 composed of a second conductive material, the first portion 321 surrounding at least a sidewall of the second portion 322.
The substrate 210 may include a P-type semiconductor material substrate (e.g., a silicon (Si) substrate or a germanium (Ge) substrate, etc.), an N-type semiconductor substrate (e.g., an indium phosphide (InP) substrate), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Embodiments of the present disclosure may prefer a substrate such as silicon-on-insulator or germanium-on-insulator to reduce substrate leakage current.
The substrate 210 may have an array of a plurality of phase change memory cells 300 thereon, where the phase change memory cells are used to perform functions such as data storage, reading and writing.
Each phase change memory cell 300 may include a phase change material layer 310 and a heating layer 320 between the phase change material layer 310 and the substrate 210. The phase change material layer 310 that can be used to store data has at least two distinct solid phase structures, for example, one state may be amorphous, the phase change material layer 310 may have a high resistance when in the amorphous state, and the other state may be crystalline, and the phase change material layer may have a low resistance when in the crystalline state. The stored data "0" and "1" are distinguished by the distinct resistance values of the phase change material layer 310 in both the amorphous and crystalline states. The transition from the metastable amorphous state to the steady state crystalline state may be obtained by heating the amorphous state to a crystallization temperature and for a time sufficient to allow it to crystallize sufficiently. Whereas from a stable crystalline to an amorphous state, the crystalline structure may be heated to melt and allowed to cool rapidly, i.e. undergo a rapid annealing process to condense and obtain the amorphous state. The phase change material layer 310 may be made using glass (Chalcogenide glass) containing one or more chalcogenides including four elements of group VIA of the periodic table, namely oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). The material of the phase change material layer 310 includes, but is not limited to, geSbTe (germanium antimony tellurium) -based alloys, and may include at least one or more of the following alloys: ga/Sb (gallium/antimony), in/Sb (indium/antimony), in/Se (indium/selenium), sb/Te (antimony/tellurium), ge/Te (tellurium/tellurium), ge/Sb/Te (germanium/antimony/tellurium), in/Sb/Te (indium/antimony/tellurium), ga/Se/Te (gallium/selenium/tellurium), sn/Sb/Te (tin/antimony/tellurium), in/Sb/Ge (indium/antimony/germanium), ag/In/Sb/Te (silver/indium/antimony/tellurium), ge/Sn/Sb/Te (germanium/tin/antimony/tellurium), ge/Sb/Se/Te (germanium/antimony/selenium/tellurium), te/Ge/Sb/S (tellurium/germanium/antimony/sulfur).
The phase change memory cell 300 further includes a heating layer 320, the heating layer 320 may be located under the phase change material layer 310, and the heating layer 320 is used to heat the phase change material layer 310 to change the phase of the phase change material layer.
The heating layer 320 in the embodiments of the present disclosure includes a first portion 321 composed of a first conductive material and a second portion 322 composed of a second conductive material; the first portion 321 encloses at least the side walls of the second portion 322. By using two conductive materials, the advantages of the two conductive materials can be combined, so that the reset current of the phase change memory is lower, the heating efficiency is higher, the heating efficiency is improved, and the phase change memory unit can be subjected to state switching by using lower working voltage.
In some embodiments, as shown in fig. 2, the second portion 322 extends through the first portion 321 and contacts the substrate 210, and has a contact surface.
In some embodiments, as shown in fig. 3, the bottom of the second portion 322 is connected to the first portion 321 without contacting the substrate.
In some embodiments, as shown in fig. 4, the second portion 322 extends through the first portion 321 and is in partial contact with the substrate 210.
As shown in fig. 5 to 8, a top cross-sectional view of the heating layer 320 is shown, and as shown in fig. 5, a top view of the heating layer 320 may be a quadrangle (including a square), a top view of the second portion 322 may be a quadrangle (including a square), and a top view of the first portion 321 may be a quadrangle with a quadrangle hollowed out in the middle. As shown in fig. 6, the top view of the first portion 321 may be a quadrangle (including a square), the top view of the second portion 322 may be an ellipse (including a circle), and the top view of the first portion 321 may be a quadrangle with an ellipse hollowed out in the middle. As shown in fig. 7, the top view of the first portion 321 may be elliptical (including circular), the top view of the second portion 322 may be elliptical (including circular), and the top view of the first portion 321 may be elliptical with an ellipse hollowed out in the middle. As shown in fig. 8, the top view of the first portion 321 may be elliptical (including circular), the top view of the second portion 322 may be quadrilateral (including square), and the top view of the first portion 321 may be elliptical with a quadrilateral cut out in the middle. The above is only 4 examples of the top cross-sectional view of the heating layer 320, and the top cross-sectional view of the heating layer 320 or the first portion 321 may further include triangles, other polygons, and the like, which are not described herein.
However, in either structure, the first portion 321 surrounds at least the side wall of the second portion 322, so that heat loss after the conductive material used in the second portion is heated can be reduced, and heating efficiency can be improved.
In the embodiment of the present disclosure, the heating layer 320 is formed using two conductive materials, and the heating layer 320 has a first portion 321 and a second portion 322, and the first portion 321 surrounds at least a sidewall of the second portion 322. Therefore, the heating efficiency can be improved by utilizing the advantages of the conductive material used by the second part, and the heated heat is not easy to dissipate by utilizing the structural advantage that the first part surrounds the second part, so that the heating efficiency is further improved. After the heating efficiency is improved, the phase change material layer 310 has shorter phase change conversion time and can generate phase change conversion more quickly, so that the data writing speed can be improved.
In some embodiments, the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.
The first conductive material and the second conductive material may be: tungsten, titanium, copper, and combinations thereof.
In embodiments of the present disclosure, the first conductivity of the first conductive material may be less than the second conductivity of the second conductive material, i.e., when the first conductive material is selected, the first conductivity of the first conductive material is also determined. The second conductive material may be selected from materials having a conductivity greater than the first conductivity, which may ensure that a majority of the current flows to the second portion when the heater is in use.
In some embodiments, when the first electrically conductive material is selected, a first thermal conductivity of the first electrically conductive material is then determined. When the second conductive material is selected, the second conductive material may be selected from conductive materials satisfying the following conditions: the second thermal conductivity of the second electrically conductive material is greater than the first thermal conductivity of the first electrically conductive material. This results in the second portion having a higher thermal conductivity than the first portion, so that heat in the first portion is not readily dissipated.
Illustratively, the first conductive material may be TaN and the second conductive material may be TiN. TaN has good heat radiation prevention effect, is also a conductor, and has good current ratio.
In addition to the increased resistance of the heating layer due to the structure of the first portion surrounding at least the side wall of the second portion, the heating effect is enhanced by adopting the material with the first heat conductivity coefficient smaller than the second heat conductivity coefficient of the second heat conductivity material, and further enabling the heat source to be concentrated in the heater.
In some embodiments, the sidewalls and at least a portion of the upper surface of the phase change memory cell are also covered with a thermal insulating layer. The third coefficient of heat conductivity of the material used for the heat preservation layer can be smaller than the first coefficient of heat conductivity of the first conductive material, so that the heat dissipation effect of the heat preservation layer is worse than that of the first conductive material, namely, the heat source of the heater cannot be easily dissipated, and the heating effect is further increased. And the heating effect can be assisted through the cladding effect of the heat preservation layer.
In some embodiments, the insulating layer may be made of an insulating material, preferably SiN (silicon nitride).
In some embodiments, as shown in FIG. 9, the phase change memory cell 300 further includes: a diode 330 perpendicular to the substrate 210; the diode 330 is located between the substrate 210 and the heating layer 320, and the conducting direction of the diode 320 is directed from the heating layer 320 to the substrate 210.
The diode 330 is located between the substrate 210 and the heating layer 320 and is placed perpendicular to the surface of the substrate 210 such that current may flow from the heating layer 320 to the substrate 210, i.e., the flow of current may be perpendicular to the surface of the substrate 210. The number of the diodes 330 may be one or more, and a plurality of diodes 330 may be connected in series between the substrate 210 and the heating layer 320. When the diode 330 is turned on, a current is generated to drive the phase change memory cell 300 to perform data writing, reading, erasing, etc.
In some embodiments, as shown in fig. 9, diode 330 includes: a first ion implantation structure 331 disposed on the substrate 210; a second ion implantation structure 332 located on the first ion implantation structure 331; the ion type of the first ion implantation structure 331 is opposite to the ion type of the second ion implantation structure 332.
The first ion implantation structure 331 may be formed by doping the substrate 210, or may be formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210. The impurity species of doping can be classified into N-type and P-type. The N-type mainly includes phosphorus (P), arsenic (As), antimony (Sb), and the like. The P-type mainly includes boron (B), indium (In), and the like.
The second ion implantation structure 332 may be formed by doping the substrate 210, or may be formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210. The impurity species of doping can be classified into N-type and P-type. The N-type mainly includes phosphorus (P), arsenic (As), antimony (Sb), and the like. The P-type mainly includes boron (B), indium (In), and the like.
It should be noted here that, because the first ion implantation structure 331 and the second ion implantation structure 332 are used to form the diode 330, the implanted types of the first ion implantation structure 331 and the second ion implantation structure 332 are opposite. In the embodiment of the disclosure, the first ion implantation structure 331 may be an N-type doping, and the second ion implantation structure 332 may be a P-type doping.
In some embodiments, if the first ion implantation structure 331 and the second ion implantation structure 332 are both formed by doping on the substrate, then the first implantation depth at which the first ion implantation structure 331 is formed is deeper than the second implantation depth at which the second ion implantation structure 332 is formed.
In some embodiments, if the first ion implantation structure 331 and the second ion implantation structure 332 are both formed by doping an epitaxial layer formed by epitaxial growth of the substrate 210, the first epitaxial layer may be formed by first epitaxial growth and then doping the first epitaxial layer to form the first ion implantation structure. The first epitaxial layer is then doped to form a first ion implantation structure 331 and the second epitaxial layer is doped to form a second ion implantation structure 332.
In some embodiments, as shown in fig. 10, the second ion implantation structure 332 includes: the upper layer second ion implantation structure 3322 and the lower layer second ion implantation structure 3321, the ion concentration of the upper layer second ion implantation structure 3322 is different from the ion concentration 3321 of the lower layer second ion implantation structure.
The second ion implantation structure 332 may include at least two layers, which when two layers have an upper layer second ion implantation structure 3322 and a lower layer second ion implantation structure 3321. The type of dopant ions of the upper second ion implantation structure 3322 may be the same as the type of dopant ions of the lower second ion implantation structure. For example, the dopant ions of the upper layer of the second ion implantation structure 3322 are P-type dopant ions, and the dopant ions of the lower layer of the second ion implantation structure may also be P-type dopant ions.
In some embodiments, the ion concentration of the upper second ion implantation structure 3322 is different from the ion concentration 3321 of the lower second ion implantation structure. For example, the ion concentration of the upper second ion implantation structure 3322 may be greater than the ion concentration 3321 of the lower second ion implantation structure. Doping the upper second ion implantation structure 3322 with a higher concentration of ions may be used to increase the conductivity of the PN junction in the diode 330. The underlying second ion implantation structure 3321 may utilize its doped ion concentration or its thickness to adjust the threshold voltage of the diode 330. Forming the second ion implantation structure 332 using a multi-layer structure may improve the performance of the diode 330.
In some embodiments, as shown in fig. 11 (fig. 11 is a schematic three-dimensional structure of a substrate), the substrate includes: a back substrate 213; a buried oxide layer 212 on the back substrate 213; the doped structure 350 is located on the buried oxide layer 212, and the doped structure 350 is in direct contact with the first ion implantation structure; shallow trench isolation structures 360 are located between adjacent doped structures 350.
The doping structure 350 is in direct contact with the first ion implantation structure to connect the plurality of phase change memory cells arranged along the first direction. I.e., the contact points or contact surfaces of the plurality of phase change memory cells along the first direction with the doping structure 350 are equipotential. The first direction may be in any direction parallel to the substrate surface, and in some embodiments, the first direction may be the same as a subsequently formed word line or bit line direction.
The doped structure 350 may be formed by doping the top layer of silicon on the buried oxide layer 212 multiple times.
In some embodiments, as shown in fig. 11, the substrate has a doping structure 350; as shown in fig. 12 (fig. 12 is a cross-sectional view of the semiconductor structure along the Y-direction), the semiconductor structure further includes: shallow trench isolation structures 360 located between adjacent doped structures 350; here, shallow trench isolation structures 360 are used to isolate adjacent doped structures 350.
Specifically, the shallow trench isolation structures 360 are used to isolate adjacent doped structures 350 along the Y-direction, so that the phase change memory cells 300 that do not overlap in the Y-direction are electrically isolated from each other. The relationship of the Y direction and the X direction may be perpendicular or intersecting.
The shallow trench isolation structure 360 may be made of an insulating material, such as silicon oxide, nitride, and combinations thereof.
In some embodiments, as shown in fig. 11, the doping structure includes: an N-well 351 located on the buried oxide layer 212; a P-well 352 located on the N-well 351; the third ion implantation structure 353 is located on the surface of the P-well 352 and is in direct contact with the first ion implantation structure.
In some embodiments, the N-well layer, the P-well layer, and the third ion implantation structure layer may be formed by performing ion implantation of the top silicon three times with different depths. The N-well layer is doped with N-type ions, the P-well layer is doped with P-type ions, and the type of the doped ions of the third ion implantation structure layer and the type of the doped ions implanted by the first ion implantation structure can be the same.
The N-well layer, the P-well layer, and the third ion implantation structure layer are etched to form a doped structure 350 composed of an N-well 351, a P-well 352, and a third ion implantation structure 353. Contact between the third ion implantation structure 353 and the first ion implantation structure is made so that a current can flow from the third ion implantation structure 353 into the first ion implantation structure. The third ion implantation layer can be formed by heavy doping, so that the subsequently formed third ion implantation structure is also heavy doping, and has the characteristics of low resistivity, small resistance and enhanced conductivity.
The N-well and P-well are used to form a reverse biased PN junction to isolate the phase change memory cell 300 from the buried oxide layer 212 and the back substrate 213, avoiding leakage.
In some embodiments, as shown in fig. 13, the semiconductor structure further comprises: an interlayer dielectric layer 370 between each phase change memory cell 300; the first conductive structure 380 penetrates through the interlayer dielectric layer 370 and is connected to the third ion implantation structure 353.
An interlayer dielectric layer 370 may be further disposed between each phase change memory cell 300, where the interlayer dielectric layer 370 is used to electrically isolate each phase change memory cell 300 and reduce parasitic capacitance. The interlayer dielectric layer 370 may be made of an insulating material.
Each of the third ion implantation structures 353 may be connected to a first conductive structure 380 penetrating through the interlayer dielectric layer 370.
The first conductive structure 380 includes at least a first Contact structure 382 (CT), which may be one or a plurality of Contact structures stacked on each other.
The first contact structure 382 may further include a first conductive plug 383 thereon, the first conductive plug 383 being used to reduce ohmic contact between adjacent first contact structures 382 or between the first contact structure 382 and other structures.
The first contact structure 382 may be made of metal.
The first conductive plug 383 may be made of metal, such as Ti and/or TiN.
In some embodiments, as shown in fig. 13, the semiconductor structure further comprises: a second conductive structure 390 connected to the phase change memory cell 300; wherein the first conductive structure 380 is connected to a first conductive line 381 extending in a first direction parallel to the substrate and the second conductive structure 390 is connected to a second conductive line 391 extending in a second direction parallel to the substrate, the second direction intersecting the first direction.
In some embodiments, the same second conductive structure 390 may also be shared among a plurality of phase change memory cells overlapping in the first direction (X-direction), and adjacent second conductive structures 390 may be parallel to each other along the second direction (Y-direction).
The second conductive structure includes at least a second contact structure 392, which may be one or a plurality of contact structures stacked on each other. Each second contact structure 392 also includes a second conductive plug 393 thereon, the second conductive plug 393 being configured to reduce ohmic contact between adjacent second contact structures 392 or between the second contact structures 392 and other structures. The material of the second contact structure 392 may be a metal material. The material of the second conductive plugs 393 may be metal, such as Ti and/or TiN.
In some embodiments, the second conductive structure further includes a second conductive line 391 that extends in the Y-th direction. The first conductive structure 380 further includes a first conductive line 381, the first conductive line 381 extending along the X-th direction. The first conductive line 381 may be used to form a word line or a bit line. The second conductive line 391 may also be used to form a word line or a bit line. In some embodiments, the first conductive line 381 and the second conductive line 391 are spatially disjoint. I.e., the first conductive line 381 and the second conductive line 391 may also have an interlayer dielectric layer therebetween. In the disclosed embodiment, the first conductive line 381 may be a word line, and the second conductive line 391 may be a bit line. By applying different voltages to the bit lines and/or word lines, storage and reading of data to the phase change memory cell can be achieved.
The embodiment of the disclosure further provides a method for forming a semiconductor structure, as shown in fig. 14, including:
step S101, providing a substrate;
step S102, forming a phase change memory cell on a substrate; the phase change memory cell includes:
the phase change material layer and the heating layer are arranged between the phase change material layer and the substrate, and the heating layer comprises a first part formed by a first conductive material and a second part formed by a second conductive material, and the second part at least surrounds the side wall of the first part.
First, step S101 is performed to provide a substrate, wherein a surface of the substrate is any one surface perpendicular to a thickness direction of the substrate. The thickness direction of the substrate or the direction perpendicular to the surface of the substrate is defined as the Z direction, any one direction along the surface of the substrate is defined as the X direction, and the direction intersecting the X direction along the surface of the substrate is defined as the Y direction. The substrate used in embodiments of the present disclosure may be an SOI substrate 210 as shown in fig. 16, the substrate 210 including a top layer of silicon 211, a buried oxide layer 212, and a backing bottom 213. Wherein the top silicon 211 may be ultra-thin monocrystalline silicon, the buried oxide layer 212 may be silicon oxide, and the backing bottom 213 may be monocrystalline silicon.
The substrate may also be cleaned to remove surface impurities before performing step S102.
Step S102 is then executed to form a phase change material layer to be treated and a heating layer to be treated through a growth process or a deposition process; the phase change material layer to be treated is positioned on the heating layer to be treated. And then, etching the phase-change material layer to be treated and the heating layer to be treated through an etching process to form a required phase-change material layer and a required heating layer so as to form the phase-change memory cell.
The heating layer in embodiments of the present disclosure includes a first portion composed of a first conductive material and a second portion composed of a second conductive material; the first portion surrounds at least the side wall of the second portion.
By using two conductive materials, the embodiment of the disclosure can combine the advantages of the two conductive materials, so that the reset current of the phase change memory is lower and the heating efficiency is higher. The heater in the embodiment of the disclosure is composed of the side wall of the second part surrounding at least the first part, and the structure is more beneficial to reducing heat dissipation and further improving heating efficiency.
In some embodiments, the method further comprises:
step S201, forming a heat preservation layer to cover the side wall and at least part of the upper surface of the phase change memory unit.
In some embodiments, after step S102 is performed, a thermal insulation layer may be formed on the sidewall and at least a portion of the upper surface of the phase change memory cell through a deposition process.
In some embodiments, step S201 may be performed alternately with step S102, that is, after the heating layer of the phase change memory cell is formed, a first thermal insulation layer is formed on the sidewall of the heating layer, and then after the phase change material layer is formed, a second thermal insulation layer is formed on the sidewall and at least part of the upper surface of the phase change material layer. The first heat preservation layer and the second heat preservation layer jointly form a heat preservation layer which covers the side wall and at least part of the upper surface of the phase change memory unit.
In some embodiments, the phase change memory cell further comprises: a diode; the phase change memory cell formed on a substrate includes:
step S301, forming a diode vertical to a substrate on the substrate;
step S302, forming a heating layer on the diode;
step S303, a phase change material layer is formed on the heating layer.
The phase change memory cell further includes: a diode located between the substrate and the heating layer. Step S102 can be further divided into step S301, step S302 and step S303.
First, step S301 is performed to form a diode perpendicular to a substrate on the substrate. Then, step S302 is performed to form a heating layer on the diode. Finally, step S303 is performed to form a phase change material layer on the heating layer.
In some embodiments, forming a diode perpendicular to the substrate on the substrate in step S301 includes:
step S401, forming a first ion implantation layer on a substrate;
step S402, forming a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to that of the second ion implantation layer;
step S403, etching the first ion implantation layer and the second ion implantation layer to form a first ion implantation structure and a second ion implantation structure, so as to form a diode.
Performing step S301 may include step S401, step S402, and step S403.
In some embodiments, step S401 may be performed first, and the first ion implantation layer is formed through a growth process (e.g., epitaxial growth) and an ion implantation process.
Then, step S402 is continued to form a second ion implantation on the first ion implantation layer through a growth process (e.g., epitaxial growth) and an ion implantation process.
In some embodiments, the epitaxial growth layer may be formed by a growth process, and then subjected to ion implantation twice at different depths to form the first ion implantation layer and the second ion implantation layer.
The ion types of the first ion implantation layer and the second ion implantation layer are opposite because the two ion implantation layers are subsequently used for forming the diode.
After the first ion implantation layer and the second ion implantation layer are formed, step S403 is performed to etch the first ion implantation layer and the second ion implantation layer to form a diode composed of the first ion implantation structure and the second ion implantation structure. Specifically, a photoresist may be coated on the second ion implantation layer, and a reticle (the pattern on the reticle is opaque) is used to align with the photoresist layer, and when the photoresist is positive, the exposed portion of the photoresist is changed from an insoluble substance to a soluble substance. The soluble portion can be removed by a chemical solvent, which leaves an island on the photoresist layer that corresponds to the opaque portion of the reticle. The island is shaped as a diode. The diode includes a first ion implantation structure and a second ion implantation structure.
In some embodiments, forming the second ion implantation layer in step S402 includes:
step S501, forming a lower second ion implantation layer;
step S502, forming an upper second ion implantation layer on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from that of the lower second ion implantation layer.
In some embodiments, step S402 may be replaced with step S501 and step S502.
In some embodiments, after step S401 is performed, step S501 may be performed first: the underlying second ion implantation layer is formed by a growth process (e.g., epitaxial growth) and an ion implantation process. Then execution continues with step S502: the upper second ion implantation layer is formed by a growth process (e.g., epitaxial growth) and an ion implantation process.
In some embodiments, the epitaxial growth layer may be formed by a growth process, and then subjected to three ion implantations of different depths to form a first ion implantation layer, a lower second ion implantation layer, and an upper second ion implantation layer. The type of ions implanted by the upper second ion implantation layer may be the same as the type of ions implanted by the lower ion implantation layer, but the concentrations of the ions implanted by the two may be different.
In some embodiments, the ion concentration of the upper layer second ion implantation structure may be greater than the ion concentration of the lower layer second ion implantation structure. Doping the upper second ion implantation structure with a higher concentration of ions can be used to increase the conductivity of the diode PN junction. The lower layer second ion implantation structure can adjust the threshold voltage of the diode by utilizing the doped ion concentration or the thickness of the lower layer second ion implantation structure.
In some embodiments, the diode forming heating layer in step S302 includes:
step S601, forming a first conductive layer on the second ion implantation layer;
step S602, etching the first conductive layer to form a plurality of groove structures;
step S603, filling a second conductive material in the groove structure to form a second part;
step S604, etching the first conductive layer except the second portion to form the first portion.
In some embodiments, after step S401 and step S402 are performed, step S302 may be continued without performing step S403. Step S302 includes step S601, step S602, step S603, and step S604.
First, step S601 is performed to deposit a first conductive material (e.g., taN) by a deposition process to form a first conductive layer on the second ion implantation layer. Step S602 is then executed to etch the first conductive layer to form a plurality of groove structures; the recess structure may or may not extend through the first conductive layer. Continuing to execute step S603, filling a second conductive material in the groove structure by using a deposition process to form a second portion; in some embodiments, the second conductive material (e.g., tiN) may also cover the surface of the first conductive layer while filling the recess structure with the second conductive material, at which point the second conductive material covering the surface of the first conductive layer may be removed using a CMP process. Step S604 is continued to etch the first conductive layer except the first portion to form the first portion. Specifically, a photoresist may be coated on the first conductive layer formed with the first portion, aligned with the photoresist layer using a reticle (the pattern on the reticle is opaque), and when the photoresist is positive, the exposed portion of the photoresist is changed from an insoluble substance to a soluble substance. The soluble portion can be removed by a chemical solvent, which leaves an island on the photoresist layer that corresponds to the opaque portion of the reticle. The shape of this island is the shape of the heating layer. In the embodiment of the disclosure, a contact sectional area is reduced by utilizing a TiN/TaN structure, and the technology is also beneficial to miniaturization.
In some embodiments, the substrate includes a back substrate, an oxygen-buried layer on the back substrate, and a top-layer silicon on the oxygen-buried layer; before performing step S102 to form the phase change memory cell on the substrate, the method further includes:
step S701, doping the top silicon to form a doped layer; the doped layer comprises an N well layer, a P well layer and a third ion implantation layer.
Step S702, etching the doped layer to form a plurality of doped structures, wherein the doped structures comprise N wells, P wells and third ion implantation structures, and the third ion implantation structures are connected with the first ion implantation structures along a first direction; and forming shallow trench isolation structures and filling grooves between adjacent doped structures.
Before step S102 is performed, step S701 may also be performed to form a doped layer on the buried oxide layer; the doped layer is formed by performing ion implantation and/or thermal diffusion processes on the top silicon multiple times. Then, step S702 is performed, the doped layer may be etched in a first direction parallel to the substrate to form a doped structure composed of a plurality of N-wells, P-wells, and a third ion implantation structure. The third ion implantation structure is connected with the first ion implantation structure along the first direction, i.e. a plurality of third ion implantation structures are parallel to each other along the first direction. The formed third ion implantation structure is connected with the plurality of first ion implantation structures, so that the plurality of phase change memory cells positioned in the same first direction are connected with the same third ion implantation structure.
In some embodiments, the method further comprises:
step S801, filling grooves between adjacent doped structures to form shallow trench isolation structures.
The doping structures extend in a first direction but are also arranged in a second direction, so that adjacent doping structures have grooves in both the first and second directions. Step S801 is performed to fill the recess with oxide, nitride or a combination thereof by a deposition process to form a shallow trench isolation structure, so that adjacent doped structures have shallow trench isolation structures in both the first direction and the second direction. The shallow trench isolation structure is used to electrically isolate the doped structure, and devices (e.g., phase change memory cells) subsequently formed over the doped structure.
In some embodiments, the method further comprises:
step S901, forming an interlayer dielectric layer, and filling the interlayer dielectric layer between a plurality of phase change memory cells;
step S902, a first conductive structure is formed, penetrating through the interlayer dielectric layer and connecting with the third ion implantation structure.
In some embodiments, step S901 may be performed after step S102 is performed. And depositing an insulating material by using a deposition process to form an interlayer dielectric layer between the plurality of phase change memory cells.
In some embodiments, step S102 and step S901 may be alternately performed, for example, after forming the diode and the heating layer, an insulating material may be first deposited between the diode and the heating layer to form a first interlayer dielectric layer. And then after the phase change material layers are formed, depositing an insulating material between the phase change material layers to form a second interlayer dielectric layer. The first interlayer dielectric layer and the second interlayer dielectric layer jointly form an interlayer dielectric layer.
Then, step S902 is performed to etch the interlayer dielectric layer, and the third ion implantation layer may be used as an etching stop layer. After etching, a groove structure penetrating through the interlayer dielectric layer is formed, and can be filled with a conductive material by using a deposition process, so that a first conductive structure penetrating through the interlayer dielectric layer and connected with the third ion implantation structure is formed. The first conductive structure includes at least a first contact structure. In some embodiments, the first conductive structure may further include a first conductive plug over the first contact structure.
In some embodiments, the method further comprises:
step S1001, forming a second conductive structure to connect the phase change memory cell;
wherein the first conductive structure is connected with a first conductive line extending along a first direction parallel to the substrate; the second conductive structure is connected to a second conductive line extending in a second direction parallel to the substrate, the second direction intersecting the first direction.
After step S102 is performed, step S1001 may also be performed to form a second conductive structure connecting the surfaces of the phase change memory cells. The second conductive structure includes at least a second contact structure. In some embodiments, the second conductive structure may further include a second conductive plug over the second contact structure.
In some embodiments, a deposition process may also be used on the first conductive structure to form a first conductive line that extends in a first direction parallel to the substrate. The second conductive structure may also have a second conductive line formed thereon using a deposition process, the second conductive line extending in a second direction parallel to the substrate. In some embodiments, the first conductive line may be a bit line and the second conductive line may be a word line. Alternatively, the first conductive line may be a word line and the second conductive line may be a bit line.
Embodiments of the present disclosure also provide examples of:
first, step S101 is performed to provide a substrate 210 as shown in fig. 15, which may be an SOI substrate. The thickness direction of the substrate or the direction perpendicular to the surface of the substrate is defined as the Z direction, any one direction along the surface of the substrate is defined as the X direction, and the direction intersecting the X direction along the surface of the substrate is defined as the Y direction. After the substrate is provided, the substrate can be cleaned to remove impurities on the surface. The SOI substrate 210 includes: a back substrate 213, a buried oxide layer 212, and top silicon 211.
Then, step S701 is performed, in which ion implantation doping layers with different depths are performed on the top silicon layer three times from the upper surface of the substrate; the doped layer comprises an N well layer, a P well layer and a third ion implantation layer. The ion implantation depth of the N well layer is larger than that of the P well layer and larger than that of the scattered ion implantation layer.
Then, step S702 is performed to etch the doped layer to form a plurality of doped structures, wherein the doped structures include an N-well, a P-well, and a third ion implantation structure, and the third ion implantation structure is connected to the first ion implantation structure along the first direction. The doped layer is etched along the X direction to form a plurality of doped structures. At this time, grooves are formed between adjacent doped structures.
Step S801 is then performed to fill the shallow trench isolation structures formed by the grooves between adjacent doped structures.
In the embodiment of the disclosure, the non-device region of the doped structure in the Y direction may be etched, two grooves on two sides of the device region may be formed in the Y direction after etching, and the phase change memory cell array may be continuously formed on the doped structure of the device region between the two grooves. And then filling grooves on two sides of the device region by using a deposition process to form two shallow trench isolation structures in the Y direction. The numbers in the above embodiments are merely illustrative, and other numbers of groove structures may be formed in the Y direction of the non-device region.
The semiconductor structure after performing the above steps is shown in fig. 16 and 17, wherein fig. 16 is a cross-sectional view of the semiconductor structure along the X-direction, and fig. 17 is a cross-sectional view of the semiconductor structure along the Y-direction.
Fig. 16 shows, in the positive Z-axis direction, the backing substrate 213, the buried oxide layer 212, and the doping structure 350 (including the N-well 351, the P-well 352, and the third ion implantation structure 353). The doped structure 350 also includes two shallow trench isolation structures 360 at both ends. The region between the two shallow trench isolation structures 360 may serve as a device region for subsequent use in forming semiconductor elements, such as phase change memory cells.
Fig. 17 shows, in the positive Z-axis direction, the backing substrate 213, the buried oxide layer 212, the plurality of shallow trench isolation structures 360, and the doped structures 350 between the shallow trench isolation structures 360. The shallow trench isolation structure 360 and the doped structure 350 are located in the same horizontal direction in the Z direction.
Then, step S401 is performed to form a first epitaxially grown silicon layer by continuing epitaxial growth on the semiconductor structure shown in fig. 16 and 17, and then implanting highly doped N-type ions to form a first ion implantation layer 331 shown in fig. 18 and 19. Fig. 18 is a cross-sectional view of the semiconductor structure along the X-direction, and fig. 19 is a cross-sectional view of the semiconductor structure along the Y-direction.
Then, step S501 is performed to implant N-type ions after continuing epitaxial growth on the first ion implantation layer 331 to form a second epitaxially grown silicon layer, so as to form a lower second ion implantation layer 3321 as shown in fig. 18 and 19.
Then, step S502 is performed to continue epitaxial growth on the lower second ion implantation layer 3321 to form a third epitaxially grown silicon layer, and then highly doped P-type ions are implanted to form the upper second ion implantation layer 3332 as shown in fig. 18 and 19.
Then, step S601 is performed to deposit a first conductive material (e.g., taN) using a deposition process (e.g., chemical vapor deposition) to form a first conductive layer on the second ion implantation layer.
Then, step S602 is performed to process the first conductive layer through a photomask, etching, etc. to form a plurality of groove structures penetrating the first conductive layer. The surface of the formed groove structure can be cleaned to remove the native oxide layer on the surface.
Step S603 is then performed to deposit a second conductive material (e.g., tiN) in the recess structure using a deposition process (e.g., atomic layer deposition) to form a second portion 322 as shown in fig. 20 and 21. Fig. 20 is a cross-sectional view of the semiconductor structure along the X-direction, and fig. 21 is a cross-sectional view of the semiconductor structure along the Y-direction. In some embodiments, tiN may also be deposited onto the TaN layer (i.e., the first conductive layer), at which point the TiN deposited on the TaN layer (i.e., the first conductive layer) may be subjected to chemical mechanical polishing until the TaN layer is exposed.
Then, step S604 and step S403 are performed, and the portion of the first conductive layer other than the second portion and the first ion implantation layer and the second ion implantation layer under the portion of the first conductive layer are etched using a photomask and an etching process, where the etching stop layer is a third ion implantation structure, so as to form the heating layer 320 and the diode 330 as shown in fig. 22 and 23. The three-dimensional structure of the heating layer 320 is shown in fig. 24, and includes a second portion 322 and a first portion 321, where the second portion 322 may be a cylindrical structure, and the first portion 321 may be a cuboid with a cylinder cut out in the middle, and it can be seen that the first portion 321 covers all sidewalls of the second portion 322.
Then, step S201 is performed to deposit a thermal insulating material (e.g., siN) to form the first thermal insulating layer 410. As shown in fig. 25, the first insulating layer may cover the sidewalls of the diode 330, the sidewalls of the heating layer 320, the surface of the heating layer 320, and the surface of the third ion implantation structure 353. As shown in fig. 26, the first insulating layer may cover the sidewalls of the diode 330, the sidewalls of the heating layer 320, the surface of the heating layer 320, and the surface of the shallow trench isolation 360.
In some embodiments, before performing step S201, the surface of the recess structure between the first structures (the heating layer and the diode) may be further cleaned to remove the native oxide layer on the surface thereof.
Then, step S901 is performed to deposit an insulating material (e.g., silicon nitride) between the diode and the heating layer to form a first interlayer dielectric layer. The first interlayer dielectric layer 370 may also cover the first insulating layer 410 on the heating layer 330 when the first interlayer dielectric layer is deposited. An etching process (e.g., CMP) may be used at this point to remove the first insulating layer 410 and the first interlayer dielectric layer 370 on the heating layer 330 until the heating layer 330 is exposed. After the step S901 is performed, a semiconductor structure as shown in fig. 27 and 28 may be formed. Fig. 27 is a cross-sectional view of the semiconductor structure along the X-direction, and fig. 28 is a cross-sectional view of the semiconductor structure along the Y-direction.
As shown in fig. 27, the first insulating layer 410 covers the sidewalls of the heating layer 330 and the diode 320 and the upper surface of the third ion implantation layer 353, as viewed in the X direction. A first interlayer dielectric layer 370 is provided between adjacent first structures (heating layer 300 and diode 320).
As shown in fig. 28, the first insulating layer 410 covers the sidewalls of the heating layer 330 and the diode 320 and the upper surface of the shallow trench isolation structure 360. A first interlayer dielectric layer 370 is provided between adjacent first structures (heating layer 300 and diode 320).
Then, step S303 is performed, in which a phase change material (e.g., GST) is first deposited using a deposition process to form a phase change material layer, and then the phase change material layer is processed through a photomask, etching, etc. process to form a phase change material structure 310 on the heating layer 320 as shown in fig. 29 and 30. In some embodiments, the width (in the X-direction) and length (in the Y-direction) of phase change material structure 310 may be greater than heating layer 320, i.e., phase change material structure 310 may completely cover the upper surface of heating layer 330.
The distance between adjacent phase change material structures formed by the method of the embodiment of the disclosure can be reduced to 0.07 mu m, and the space between each phase change memory cell and the stacking layer number of the phase change memory cells are smaller, so that the memory density of the memory cells in unit area is greatly improved.
Then, step S201 is performed again, and a thermal insulation material (SiN) is deposited between the phase change material structures 310 to form a second thermal insulation layer 420 as shown in fig. 31 and 32, where the second thermal insulation layer 420 covers the sidewalls and upper surface of the phase change material structures 310 and also covers the upper surface of the first interlayer dielectric layer 370.
Then, a step S901 is performed again, in which an insulating material (for example, silicon oxide) is deposited on the second insulating layer 420 to form a second interlayer dielectric layer 371 as shown in fig. 33 and 34.
Then, step S902 and step S1001 are performed to form a first conductive structure penetrating the first interlayer dielectric layer and the second interlayer dielectric layer and connecting the third ion implantation structure and a second conductive structure connecting the surface of the phase change memory cell as shown in fig. 35 and 36.
Specifically, a photomask, etching, and other processes are performed along the Y direction between the phase change memory cell array and the shallow trench isolation (two shallow trench isolations may optionally be provided along the X direction), and a third ion implantation structure is used as an etching stop layer to form a plurality of groove structures overlapping in the X direction and parallel in the Y direction, where the groove structures penetrate through the first interlayer dielectric layer and the second interlayer dielectric layer and are connected with the third ion implantation structure.
On the phase change memory cell array, a photomask, etching and other processes are used along the X direction and the Y direction, and the phase change material structure is used as an etching stop layer to form an opening structure on the phase change material structure, wherein the width (along the X direction) of the opening structure is smaller than or equal to the width of the phase change material structure, and the length (along the Y direction) of the opening is also smaller than or equal to the length of the phase change material structure.
A deposition process (e.g., atomic layer deposition) is then used to deposit conductive material into the recess structure and the opening structure to form first contact structure 382 and first conductive plug 383 and second contact structure 392 and second conductive plug 393.
A conductive material is then deposited over the second conductive plugs 393 and a masking and etching process is performed to form second conductive lines 391 that cover the second conductive plugs 393. As shown in fig. 36, the second conductive line 391 extends in the Y direction. As shown in fig. 35, the second conductive lines 391 are parallel to each other in the X direction.
The distance between adjacent second conductive lines 391 formed using the method of the embodiments of the present disclosure may be reduced to 0.07 μm.
On the basis of fig. 35 and 36, an insulating material (for example, silicon oxide) is continuously deposited to form a third interlayer dielectric layer 372 as shown in fig. 37 and 38, and a recess structure penetrating through the third dielectric layer 372 and connecting the first contact plug 383 is formed on the third interlayer dielectric layer 372 by a photomask process, an etching process, or the like.
A further first contact structure 382 and a further first contact plug 383 are formed over the first contact plug 383 using a deposition process (e.g., atomic layer deposition). The upper surface of the first contact plug 383 is flush with the upper surface of the third interlayer dielectric layer 372.
Then, first conductive lines 381 parallel to each other in the X direction are formed on the third interlayer dielectric layer by a photomask process, an etching process, and the like.
The insulating materials used for the first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer in the embodiments of the present disclosure may be the same or different.
A top view of the semiconductor structure of fig. 37 and 38 is shown in fig. 39: the bit lines extend in the Y direction, and adjacent bit lines are parallel to each other in the X direction.
The word lines extend in the X direction and adjacent word lines are parallel to each other in the Y direction.
In summary, the semiconductor structure formed by the method according to the embodiments of the present disclosure has the advantages of SOI (e.g., less latch-up, less leakage current, etc.) in addition to the advantages of SOI due to the simple process and easy formation. The circuit diagrams corresponding to the semiconductor structures of fig. 37 and 38 may be simplified to fig. 40, where memory cell 500 includes a phase change memory cell and a diode. Multiple diodes in the same row may be connected to the same word line, and multiple phase change memory cells in the same column may be connected to the same bit line.
The programming operation of the memory cell 500 includes: applying a programming voltage V to the bit line where the selected memory cell 500 is located pgm (e.g., 0.5V) to the other unselected bit lines. While the word line where the selected memory cell 500 is located is grounded (e.g., 0V), and a certain voltage is applied to the unselected word lines (e.g., 0.5V).
The reading operation of the memory cell includes: a read voltage (V is applied to the bit line where the selected memory cell 500 is located read ) A ground voltage (e.g., 0V) is applied to the other unselected bit lines. At the same time, a ground voltage (e.g., 0V) is applied to the word line where the selected memory cell 500 is located, and a certain voltage (e.g., 0.5V) is applied to the unselected word lines. Wherein V is read Less than V pgm 。
The IV curve of the memory cell is shown in fig. 41:
curve 1 is the current-voltage curve for a read operation of a memory cell.
Curve 2 is the current-voltage curve for a write operation to a memory cell.
The current-voltage curve in fig. 41 shows that: the read voltage must be smaller than the write voltage (the range of write voltages such as the shaded area), so that the phase change memory will not change state due to the excessive voltage during the read voltage. In general, write operations are classified into RESET operations and SET operations, and voltage ranges are approximately in the shadow region. The writing operation is performed by different pulse time, wherein the SET operation can be longer pulse time and the RESET operation can be shorter pulse time.
Finally, the embodiments of the present disclosure also provide a memory, as shown in fig. 42, where the memory 40 includes a memory cell array 20 including the semiconductor structure 10 according to any of the embodiments described above, and a peripheral circuit 30 structure located above or outside the memory cell array 20.
All or part of the semiconductor structure 10 in the above embodiments may be used to construct the memory cell array 20, and the memory cells of the memory cell array 20 include phase change memory cells.
Peripheral circuitry 30 may include any suitable analog, digital, and mixed signal circuitry to perform the associated operations on memory cell array 20. Operations include reading, writing, erasing, and the like.
Memory 40 may be a phase change memory.
The memory is a three-dimensional structure with higher storage density, lower power consumption and easier access operation, the heater of the memory has smaller volume, so that the heating efficiency is higher, the writing speed is faster, and the memory also has other advantages of the semiconductor structure of any of the embodiments of the present disclosure.
The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The present disclosure is not limited to the specific embodiments, and any person skilled in the art, who is within the technical scope of the present disclosure, can easily conceive of changes or substitutions, which are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (20)

1. A semiconductor structure, the semiconductor structure comprising:
a substrate;
a phase change memory cell located on the substrate;
the phase change memory cell includes: the heating layer is positioned between the phase change material layer and the substrate;
the heating layer includes a first portion composed of a first conductive material and a second portion composed of a second conductive material, the first portion surrounding at least a sidewall of the second portion.
2. The semiconductor structure of claim 1, wherein the first conductivity of the first conductive material is less than the second conductivity of the second conductive material.
3. The semiconductor structure of claim 1, wherein the sidewalls and at least a portion of the upper surface of the phase change memory cell are further covered with a thermal insulating layer.
4. The semiconductor structure of claim 1, wherein the phase change memory cell further comprises:
and the diode is perpendicular to the substrate, is positioned between the substrate and the heating layer, and is in a conduction direction from the heating layer to the substrate.
5. The semiconductor structure of claim 4, wherein the diode comprises:
a first ion implantation structure located on the substrate;
a second ion implantation structure located on the first ion implantation structure;
the ion type of the first ion implantation structure is opposite to the ion type of the second ion implantation structure.
6. The semiconductor structure of claim 5, wherein the second ion implantation structure comprises:
an upper layer second ion implantation structure and a lower layer second ion implantation structure, wherein the ion concentration of the upper layer second ion implantation structure is different from that of the lower layer second ion implantation structure.
7. The semiconductor structure of claim 5, wherein the substrate comprises:
a back substrate;
an oxygen-buried layer on the backing substrate;
the doping structure is positioned on the oxygen burying layer and is in direct contact with the first ion implantation structure;
And the shallow trench isolation structure is positioned between the adjacent doped structures.
8. The semiconductor structure of claim 7, wherein the doped structure comprises:
an N well located on the buried oxide layer;
a P well located on the N well;
and the third ion implantation structure is positioned on the surface of the P well and is in direct contact with the first ion implantation structure.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:
an interlayer dielectric layer positioned between the phase change memory cells;
and the first conductive structure penetrates through the interlayer dielectric layer and is connected with the third ion implantation structure.
10. The semiconductor structure of claim 9, wherein the semiconductor structure further comprises:
a second conductive structure connected to the phase change memory cell;
wherein the first conductive structure is connected with a first conductive line extending in a first direction parallel to the substrate, and the second conductive structure is connected with a second conductive line extending in a second direction parallel to the substrate, the second direction intersecting the first direction.
11. A method of forming a semiconductor structure, the method comprising:
Providing a substrate;
forming a phase change memory cell on the substrate; the phase change memory cell includes:
the phase change material layer and the heating layer are positioned between the phase change material layer and the substrate, and the heating layer comprises a first part formed by a first conductive material and a second part formed by a second conductive material, and the first part at least surrounds the side wall of the second part.
12. The method of forming of claim 11, further comprising:
and forming an insulating layer to cover the side wall and at least part of the upper surface of the phase change memory unit.
13. The method of forming of claim 11, wherein the phase change memory cell further comprises: a diode; forming a phase change memory cell on the substrate includes:
forming a diode on the substrate perpendicular to the substrate;
forming the heating layer on the diode;
the phase change material layer is formed on the heating layer.
14. The method of forming of claim 13, wherein forming a diode on the substrate perpendicular to the substrate comprises:
forming a first ion implantation layer on the substrate;
Forming a second ion implantation layer on the first ion implantation layer; the ion type of the first ion implantation layer is opposite to the ion type of the second ion implantation layer;
and etching the first ion implantation layer and the second ion implantation layer to form a first ion implantation structure and a second ion implantation structure so as to form the diode.
15. The method of forming of claim 14, wherein forming the second ion implantation layer comprises:
forming a lower second ion implantation layer;
forming an upper second ion implantation layer on the lower second ion implantation layer; the ion concentration of the upper second ion implantation layer is different from that of the lower second ion implantation layer.
16. The method of forming of claim 14, wherein forming the heating layer on the diode comprises:
forming a first conductive layer on the second ion implantation layer;
etching the first conductive layer to form a plurality of groove structures;
filling the second conductive material in the groove structure to form the second part;
the first conductive layer outside the second portion is etched to form the first portion.
17. The method of forming of claim 14, wherein the substrate comprises a back substrate, an oxygen-buried layer on the back substrate, and a top layer of silicon on the oxygen-buried layer; before the step of forming the phase change memory cell on the substrate, the method further comprises:
doping the top silicon layer to form a doped layer; the doped layer comprises an N well layer, a P well layer and a third ion implantation layer;
etching the doped layer to form a plurality of doped structures, wherein the doped structures comprise an N well, a P well and a third ion implantation structure, and the third ion implantation structure is connected with the first ion implantation structure;
and forming shallow trench isolation structures and filling grooves between adjacent doped structures.
18. The method of forming of claim 17, further comprising:
forming an interlayer dielectric layer, and filling the interlayer dielectric layer between a plurality of the phase change memory cells;
and forming a first conductive structure which penetrates through the interlayer dielectric layer and is connected with the third ion implantation structure.
19. The method of forming of claim 18, further comprising:
forming a second conductive structure connected with the phase change memory unit;
Wherein the first conductive structure is connected with a first conductive line extending in a first direction parallel to the substrate; the second conductive structure is connected with a second conductive line extending along a second direction parallel to the substrate, the second direction intersecting the first direction.
20. A memory comprising a memory cell array comprising the semiconductor structure of any one of claims 1 to 10, and a peripheral circuit structure located above or outside the memory cell array.
CN202210786445.1A 2022-07-04 2022-07-04 Semiconductor structure, forming method thereof and memory Pending CN117412664A (en)

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