CN101339921A - Manufacturing method of bi-polar transistor array isolated by double shallow slots - Google Patents
Manufacturing method of bi-polar transistor array isolated by double shallow slots Download PDFInfo
- Publication number
- CN101339921A CN101339921A CNA2008100415165A CN200810041516A CN101339921A CN 101339921 A CN101339921 A CN 101339921A CN A2008100415165 A CNA2008100415165 A CN A2008100415165A CN 200810041516 A CN200810041516 A CN 200810041516A CN 101339921 A CN101339921 A CN 101339921A
- Authority
- CN
- China
- Prior art keywords
- bit line
- conduction type
- bipolar transistor
- atom
- sti
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a manufacturing method of a two shallow isolation (dual-STI) bipolar transistor array. The method is characterized in that an selective epitaxial method is avoided in the manufacturing method; a deeper STI is made and formed on a first conductive type underlay; an easy diffused second conductive type atomic materials equably deposit and are contained on the side wall and at the bottom of the STI; the easy diffused second conductive type atomic materials which are deposited near a STI notch are removed. Annealing causes that the second conductive type atomics in the materials to be spread to bit lines, so as to form a second conductive type heavy doping of the bit lines; later, the bit lines which are connected with each other by the diffuse of the second conductive type atomics are separated by etching, so as to ensure that the electricity among bit lines is not communicated; separate bipolar transistors are formed above the separate bit lines by ion injection and photoetching. The transistors on the same bit lines are separated by a lighter STI. The method of the invention also comprises the manufacturing method of a gated phase-change memory based on the two shallow isolation (dual-STI) bipolar transistors.
Description
Technical field
The present invention relates to the manufacture method of the bipolar transistor array of dual shallow groove isolation, belong to the manufacturing field of phase transition storage.
Background technology
Phase transition storage (PCRAM) has been acknowledged as the breakthrough of semiconductor memory technologies maximum since nearly 40 years, and it not only has the superior performance of each side, and is a kind of general memory, has vast market prospect.After it realizes industrialization, be expected to part or substitute comprehensively comprise the present multiple memory device that comprises flash (flash memory), DRAM (dynamic random access memory), hard disk, thereby in semiconductor memory market, occupy consequence.
The memory cell of PCRAM partly is the resistance that can programme and regulate by the signal of telecommunication, in actual application, needs logical device that memory cell is carried out gating and operation.At present, the density of PCRAM depends primarily on the transistorized size of driving, so, in highdensity PCRAM storage array, bipolar transistor becomes the main flow direction of each big semiconductor company development at present because of its relative smaller units area, the chip storage capacity of using this technology manufacturing has at present reached 512Mb.In the PCRAM of bipolar transistor selection made, how making bipolar transistor was the key of technology, also is the place of wrestling of each major company.At present, Samsung adopts the selective epitaxial method to make bipolar transistor above heavily doped bit line, but this method has very high requirement to manufacturing process, and manufacturing cost is very high.
Summary of the invention
The object of the present invention is to provide the manufacture method of the bipolar transistor array that dual shallow groove isolates, and based on the manufacture method of the phase transition storage of said structure.
For this reason, the invention provides the manufacture method of the bipolar transistor array of two kinds of dual shallow grooves isolation.The manufacturing step of method A is:
(1) on the substrate of first conduction type (p type or n type), produce mutually independently bit line, separate by darker shallow trench isolation (STI) between the bit line that (darker STI is with respect to the more shallow STI that occurs in the subsequent technique, its feature is to have darker gash depth relatively, the STI degree of depth is between 50 nanometers to 10 micron, the degree of depth is different because of the difference of the semiconductor technology node that adopted, such as 90nm technology or 45nm semiconductor process techniques);
(2) at the sidewall of this dark STI and the material that bottom deposit contains second conduction type (n type or p type) atom;
(3) spin coating one deck photoresist in above-mentioned substrate, the photoresist that will cover bit line top and STI notch by the oxonium ion bombardment is removed, by returning carving technology the material that contains second conduction type (n type or p type) atom of bit line top and STI notch is removed, the atom that reduces by second conduction type is diffused into the probability at bit line top when annealing again;
(4) annealing in process, through the high temperature long term annealing, the atom diffusion that makes second conduction type in the material that contains the second conduction type atom makes bit line by this atom doped by second conduction type in bit line; The condition of annealing in process is different and different with bitline width because of atomic type, the doping content of second conduction type of diffusion, temperature is between 300 ℃ to 1500 ℃, annealing time then between 1 minute to 48 hours, the annealing atmosphere of employing or be inert gas, nitrogen or be vacuum;
(5) adopt etching method, will the bit line of mutual conduction to be separated because of the above-mentioned second conduction type atom diffusion, purpose is to make between the bit line to insulate on electricity, avoids the signal cross-talk that may exist between bit line in the device operation process;
(6) above above-mentioned bit line, form the thin layer of two-layer different conduction-types by photoetching and ion implantation, the bit line that mixes with second conduction type forms bipolar transistor, separate by more shallow STI between each bipolar transistor on same bit line, the degree of depth of more shallow STI is between 10 nanometers and 2 microns;
(7) by filling, silication and the flatening process of dielectric material, form the bipolar transistor array.
The manufacturing step of method B is:
(1) on the substrate of first conduction type, produce mutually independently bit line, to separate by darker STI between the bit line, the STI degree of depth is between 50 nanometers and 10 microns, and this degree of depth is different because of the difference of the semiconductor technology node that adopted;
(2) continue at the sidewall of this dark STI and the material that bottom deposit contains the second conduction type atom;
(3) at the sidewall of this dark STI and the material that bottom deposit contains the second conduction type atom, guarantee that the STI bottom deposit has the material of the second conduction type atom, remove the material of the second conduction type atom of STI top and sidewall by returning carving technology, the material of the second conduction type atom of reservation bottom shallow road part is as diffusion impervious layer;
(4) spin coating one deck photoresist in above-mentioned substrate, the photoresist that will cover bit line top and STI notch by the oxonium ion bombardment is removed, to cover the material removal that contains the second conduction type atom of bit line top and STI notch by returning carving technology, and avoid the atom of second conduction type too much to be diffused into the top of bit line;
(5) annealing in process, through the high temperature long term annealing, the atom diffusion that makes second conduction type in the material that contains the second conduction type atom makes bit line atom doped by this second conduction type in bit line; The condition of annealing in process is different and different with bitline width because of atomic type, the doping content of second conduction type of diffusion, and temperature is between 300 ℃ to 1500 ℃, and annealing time is then between 1 minute to 48 hours;
(6) adopt etching method, the material removal of the second conduction type atom is contained in STI bottom that will be darker;
(7) form bipolar transistor by photoetching and ion implantation above above-mentioned bit line, separate by more shallow STI between each bipolar transistor on same bit line, the STI degree of depth is between 10 nanometers and 2 microns;
(8) by filling, silication and the flatening process of dielectric material, form the bipolar transistor array.
In two kinds of above-mentioned manufacture methods:
1. the described material that contains the second conduction type atom is characterized in that the atom of this second conduction type can be diffused in the material of first conduction type under the condition of high annealing, form the doping to second conduction type of first conductivity type material.
The foreign atom of 2. described second conduction type is arsenic, phosphorus, antimony, bismuth, sulphur, selenium, tellurium, iodine, boron, aluminium, potassium, indium, thallium, lithium, potassium, sodium, beryllium, magnesium, calcium or silver.
3. the method that described deposition contains the material of the second conduction type atom comprises chemical vapour deposition technique, sputtering method, atomic layer deposition method or sol-gel process.
4. the resistivity of described dielectric material is higher than 1 ohm meter; The bipolar transistor array that described dual shallow groove is isolated is as the phase-changing memory unit gating.
The present invention also provides the manufacture method of the bipolar transistor selection phase transition storage of isolating based on the dual shallow groove of any manufacturing in above-mentioned two kinds of methods, comprises the steps:
Deposition of electrode material, phase-change material produce memory cell by photoetching process on the pair transistor array of made;
By deposition, the planarization of dielectric material, and then photoetching process carves hole on dielectric material, thereby the top electrode and the bit line public electrode of phase-change memory cell are drawn, and produces drive circuit, finally after encapsulating forms basic phase change memory array.
The phase transition storage of the bipolar transistor array gating of isolating with dual shallow groove that the present invention makes is characterised in that:
1. utilize the difference of the resistance before and after the reversible transition of phase-change material to realize the storage of data;
But 2. phase-change material have more than two can be under the signal of telecommunication effect state of inverse conversion, have different resistivity between each state; Selectable material comprises material, above-mentioned various mixtures of material and the back materials that obtain that mix such as Ge-Sb-Te alloy, Si-Sb-Te alloy, Ge-Sb, Si-Sb, Ag-In-Sb-Te, Ge-Te, pure Sb and doping Sb on above-mentioned material.
Characteristics of the present invention are the selective epitaxial manufactured bipolar transistor of not only having avoided expensive, and have also solved deep ion and inject the problem that can't inject big concentration.Utilized in the atom diffusion pairs of bit line of STI sidewall and mixed, and each bit line has effectively been separated by follow-up etching.And this invention is applied in the phase transition storage.
Description of drawings
The preparation process of the bipolar transistor array that the dual shallow groove shown in Figure 1A-1P embodiment 1 is isolated.
The PCRAM storage array schematic diagram of the bipolar transistor array that Fig. 2 A isolates based on dual shallow groove,
Fig. 2 B is along the projection of 5-5 direction among the preceding figure.
The preparation process of the bipolar transistor array that the dual shallow groove of Fig. 3 A-3J embodiment 3 is isolated.
Embodiment
Embodiment 1
1. on the p of cleaning type conductive substrates 11, utilize exposure and etching technics to produce the STI groove 14 that the degree of depth is 500 nanometers, the part that photoresist 12 stops is not etched, and forms the lines 15 of separated projection after the etching on silicon chip; The sectional view that forms lines after the above-mentioned processing is shown in Figure 1A, and vertical view is shown in Figure 1B.
2. adopt chemical vapour deposition technique after removing photoresist, at the sidewall of lines 15 tops, STI groove 14 and the As glass film 16 of bottom uniform deposition; Utilize chemico-mechanical polishing to remove and contain As glassy layer 16 on the lines 15.Obtain the cross section of figure and vertical view shown in Fig. 1 C and Fig. 1 D.
3. rotate in above-mentioned substrate with photoresist spinner and coat photoresist, photoresist layer 18 will partly infiltrate STI groove 14, shown in Fig. 1 E.
4. utilize oxonium ion bombardment substrate in the etching machine, the photoresist of substrate surface is removed, the glue of close slot-open-section also is removed, and residual a part of photoresist 19 is in the STI groove, shown in Fig. 1 F.
5. employing etching technics is removed the As glass that contains of STI groove 14 notches, the groove bottom contain As glass because the protection of photoresist is not etched, remove after the residual photoresist, formed the structure shown in Fig. 1 G.
6. carry out annealing in process in a vacuum, annealing temperature be 1000 ℃ 6 hours, make the As atom diffusion that contains in the As glass film 16 in lines 15, after the annealing diffusion was finished, lines 15 became heavily doped n N-type semiconductor N just by As heavy doping, promptly form bit line 19, and had lower resistivity; Shown in Fig. 1 G, because also depositing, the bottom of STI 14 contains As glass, so also diffused into numerous As atoms, make near the silicon materials that contain As glass to have low resistivity, thereby make the whole conductings of adjacent bit lines on every side in the STI bottom.
7. employing ion implantation is just having formed the p+/n-/n+ structure between injection formation n type lightly doped regional 20 and the p type heavily doped regional 21,21,20 and 19 above the bit line 19, shown in Fig. 1 I; Through behind this step process, among Fig. 1 I along the projection of 1-1 direction shown in Fig. 1 J.
8. adopt photoetching process again, the bit line 19 that conducts mutually because of the As atom diffusion is originally separated, form the structure shown in Fig. 1 K.Just separate fully between the bit line 19 like this, the vertical view of this moment shown in Fig. 1 L, among Fig. 1 L along the projection of 2-2 direction shown in Fig. 1 J.
9. above above-mentioned bit line 19, produce each bipolar transistor that is separated from each other (19+20+21) by photoetching process, the vertical view that forms structure is shown in Fig. 1 M, among Fig. 1 M along the projection of 3-3 direction shown in Fig. 1 N, separate by more shallow STI 22 between the transistor, the degree of depth of this STI is 150nm, so compare shallow with the STI of front 500 nanometers.
10. the filling of dielectric material and flatening process, adopting the dielectric material of filling is amorphous silicon, flattening method is chemico-mechanical polishing.
11. and then formation silicide Si
xCo layer 23; Draw bit line with electrode, form the bipolar transistor array of cross section shown in Fig. 1 O, among Fig. 1 O along the vertical view of the projection of 4-4 direction shown in Fig. 1 P.
Embodiment 2
The manufacture method of the PCRAM device of the bipolar transistor selection of making based on said method.
1. make the manufacture method such as the embodiment 1 of bipolar transistor array.
2. deposition of electrode material 24 (TiN 30nm), phase-change material 25 (SiSb material 100nm) and electrode material 24 (TiN 30nm) successively above the above-mentioned bipolar transistor array that obtains produce the memory cell figure by photoetching process.
3. pass through deposition, the chemico-mechanical polishing planarization of dielectric material 29, and then on dielectric material, carry out photoetching, in dielectric material, carve hole, thereby phase-change memory cell top electrode 24 and bit line 19 usefulness metal bolts 27 and 26 are drawn, produce electrode 28, form storage array, shown in Fig. 2 A.Among Fig. 2 A, along the projection of 5-5 direction shown in Fig. 2 B.
Embodiment 3
1. on the silicon substrate 30 of p type conduction, etch the STI groove 32 that the degree of depth is 700nm with photoetching process, and formed separated lines 31, its cross section as shown in Figure 3A.
2. with vapour deposition process cvd silicon oxide 33, shown in Fig. 3 B.
3. adopt back carving technology, make the removal that is etched entirely of remainder except STI trench bottom silica, shown in Fig. 3 C.
4. chemical vapour deposition technique deposits phosphorous glasses 34, adopts the method for 3 to 5 steps among similar and the embodiment 1, removes the phosphorous glasses of STI top and notch, forms the sectional view shown in Fig. 3 D.
5. in argon shield, carry out annealing in process, annealing temperature be 1100 ℃ 5 hours, the phosphorus atoms in the material fully is diffused in the lines 31, formed heavily doped bit line 35, shown in Fig. 3 E.
6. return quarter, remove the phosphorus glass 34 in the STI groove, shown in Fig. 3 F.
7. ion injects, and forms 36 layers and 37 layers of boron-containing impurities containing phosphorus impurities successively, and shown in Fig. 3 G, the injection degree of depth of phosphorus is 150 nanometers; Along the projection of 6-6 direction shown in Fig. 3 H.
8. photoetching process forms independently unit above bit line, with the STI40 of the degree of depth 180 nanometers each unit separation is opened, and Fig. 3 H has just formed the structure shown in Fig. 3 I after through processing.
9. form phase change memory structure by follow-up semiconducter process, shown in Fig. 3 J.Among the figure, 41 and 42 is silicide Si
xCo, 43 is electrode TiN, and 44 is phase-change material GeSbTe, and 46 and 47 is the W metal bolt, and 48 is the Al plain conductor.
In sum, the invention provides bipolar transistor that a kind of dual shallow groove isolates and based on the manufacture method of this kind transistor PCRAM memory device.Although only describe some preferred embodiment in detail, obvious for those skilled in the art, under the situation that does not depart from the scope of the present invention that defines by claims, can carry out some improvement and variation.
Claims (7)
1, the manufacture method of a kind of dual shallow groove bipolar transistor array of isolating is characterized in that adopting in following two kinds of methods any:
Method A:
A) on the substrate of first conduction type, produce mutually independently bit line, separate by darker shallow trench isolation between the bit line;
B) sidewall of the shallow trench isolation that forms at step a and the material that bottom deposit contains the second conduction type atom;
C) near the material that contains the second conduction type atom of notch that covers bit line top and shallow trench isolation is removed;
D) annealing in process makes the second conduction type atom diffusion in the material that contains the second conduction type atom in bit line, and pairs of bit line forms the doping of second conduction type;
E) adopt etching method, the diffusing, doping that steps d is formed and the bit line of mutual conduction is separated makes not conducting of electricity between the bit line;
F) on the bit line of not conducting on the electricity that step e forms, form bipolar transistor by photoetching and ion implantation, separate by more shallow shallow trench isolation between each bipolar transistor of same bit line top;
G) last, by the filling and the flatening process of dielectric material, form the bipolar transistor array;
Method B:
A) on the substrate of first conduction type, produce mutually independently bit line, separate by darker shallow trench isolation between the bit line;
B) sidewall of the darker shallow trench isolation that forms at this step a and the material of the bottom deposit second conduction type atom;
C) pass through back carving technology, covering bit line top and remove, at the material of the trench bottom residual fraction second conduction type atom of shallow trench isolation than the material of the second conduction type atom of the sidewall of depth channel isolation;
D) deposition contains the material of the second conduction type atom, and, avoid the atom of second conduction type in the annealing in process process, too much to be diffused into the top of bit line near the material removal that contains the second conduction type atom the notch that covers bit line top and shallow trench isolation;
E) annealing in process makes the second conduction type atom diffusion in the material that contains the second conduction type atom in bit line, makes bit line by this atom doped by second conduction type;
F) adopt etching method, the material that contains the second conduction type atom in the shallow trench isolation that will be darker is removed;
G) inject by ion and photoetching process forms the thin layer of two-layer different conduction-types above above-mentioned bit line, the bit line that mixes with second conduction type forms bipolar transistor, separates by more shallow STI between each bipolar transistor of same bit line top;
H) by the filling and the planarization of dielectric material, form the bipolar transistor array;
The degree of depth of described darker STI is between 50 nanometers to 10 micron;
The degree of depth of described more shallow STI is between 10 nanometers to 2 micron;
Described first conduction type is p type or n type, and second conduction type is n type or p type.
2, the manufacture method of the bipolar transistor array of the isolation of the dual shallow groove described in claim 1, the atom that it is characterized in that described second conduction type is arsenic, phosphorus, antimony, bismuth, sulphur, selenium, tellurium, iodine, boron, aluminium, potassium, indium, thallium, lithium, potassium, sodium, beryllium, magnesium, calcium or silver.
3, the manufacture method of the bipolar transistor array of the isolation of the dual shallow groove described in claim 1, it is characterized in that the annealing in process condition is that temperature is between 300 ℃ to 1500 ℃, annealing time is between 1 minute to 48 hours, and atmosphere is inert atmosphere, nitrogen or vacuum.
4, the manufacture method of the bipolar transistor array of the isolation of the dual shallow groove described in claim 1, the method that it is characterized in that depositing the material that contains the second conduction type atom is chemical vapour deposition technique, sputtering method, atomic layer deposition method or sol-gel process.
5, the manufacture method of the bipolar transistor array of the isolation of the dual shallow groove described in claim 1, the resistivity that it is characterized in that dielectric material is greater than 1 ohm meter.
6, the manufacture method of the phase transition storage of a kind of dual shallow groove by each manufacturing in the claim 1 to 5 bipolar transistor array gating of isolating is characterized in that:
1. deposition of electrode material, phase-change material on the array of the bipolar transistor that method A or method B make produce memory cell by photoetching process;
2. deposition, the planarization by dielectric material, and then on dielectric material, carve hole with photoetching process, thus the top electrode and the bit line public electrode of phase-change memory cell are drawn, produce drive circuit, form basic phase change memory array.
7, as the manufacture method of phase-change material memory as described in the claim 6, but it is characterized in that phase-change material have more than two can be under the signal of telecommunication effect state of inverse conversion, have different resistivity between each state; Described phase-change material comprises and mixing on Ge-Sb-Te alloy, Si-Sb-Te alloy, Ge-Sb, Si-Sb, Ag-In-Sb-Te, Ge-Te, pure Sb or doping Sb material and the above-mentioned material or the back material that obtains that mixes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100415165A CN101339921B (en) | 2008-08-08 | 2008-08-08 | Manufacturing method of bi-polar transistor array isolated by double shallow slots |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100415165A CN101339921B (en) | 2008-08-08 | 2008-08-08 | Manufacturing method of bi-polar transistor array isolated by double shallow slots |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101339921A true CN101339921A (en) | 2009-01-07 |
| CN101339921B CN101339921B (en) | 2010-04-07 |
Family
ID=40213946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100415165A Active CN101339921B (en) | 2008-08-08 | 2008-08-08 | Manufacturing method of bi-polar transistor array isolated by double shallow slots |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101339921B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254853A (en) * | 2011-08-01 | 2011-11-23 | 上海宏力半导体制造有限公司 | Dual-shallow trench isolation structure forming method |
| WO2012037829A1 (en) * | 2010-09-21 | 2012-03-29 | 中国科学院上海微系统与信息技术研究所 | Manufacturing method of epitaxial diode array with dual shallow trench isolations |
| CN102446806A (en) * | 2010-10-13 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for trench isolation structure of phase change memory |
| CN102956818A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of phase change random access memory |
| CN113517313A (en) * | 2021-04-26 | 2021-10-19 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional memory and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6579760B1 (en) * | 2002-03-28 | 2003-06-17 | Macronix International Co., Ltd. | Self-aligned, programmable phase change memory |
| CN1294639C (en) * | 2002-12-05 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Process for making shallow slot and deep slot isolation arrangement |
-
2008
- 2008-08-08 CN CN2008100415165A patent/CN101339921B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012037829A1 (en) * | 2010-09-21 | 2012-03-29 | 中国科学院上海微系统与信息技术研究所 | Manufacturing method of epitaxial diode array with dual shallow trench isolations |
| CN102412179A (en) * | 2010-09-21 | 2012-04-11 | 中国科学院上海微系统与信息技术研究所 | Preparation method for epitaxial diode array isolated by double shallow trenches |
| US8476085B1 (en) | 2010-09-21 | 2013-07-02 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Method of fabricating dual trench isolated epitaxial diode array |
| CN102412179B (en) * | 2010-09-21 | 2013-07-17 | 中国科学院上海微系统与信息技术研究所 | Preparation method for epitaxial diode array isolated by double shallow trenches |
| CN102446806A (en) * | 2010-10-13 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for trench isolation structure of phase change memory |
| CN102446806B (en) * | 2010-10-13 | 2014-07-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for trench isolation structure of phase change memory |
| CN102254853A (en) * | 2011-08-01 | 2011-11-23 | 上海宏力半导体制造有限公司 | Dual-shallow trench isolation structure forming method |
| CN102254853B (en) * | 2011-08-01 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | The formation method of two groove isolation constructions |
| CN102956818A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of phase change random access memory |
| CN113517313A (en) * | 2021-04-26 | 2021-10-19 | 长江先进存储产业创新中心有限责任公司 | Three-dimensional memory and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101339921B (en) | 2010-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8067761B2 (en) | Self-aligned memory cells and method for forming | |
| US8350316B2 (en) | Phase change memory cells having vertical channel access transistor and memory plane | |
| US10714684B2 (en) | Phase change memory with doped silicon germanium alloy-containing electrodes and air gap-containing spacer | |
| US8288750B2 (en) | Phase change memory device with air gap | |
| CN102667946B (en) | Phase change memory element and method for manufacturing phase change memory element | |
| KR101779274B1 (en) | Arrays of memory cells and methods of forming an array of memory cells | |
| US20080315359A1 (en) | Integrated circuit including vertical diode | |
| US20100308296A1 (en) | Phase change memory cell with self-aligned vertical heater | |
| US20110001114A1 (en) | Phase change memory cell with self-aligned vertical heater and low resistivity interface | |
| US20100181649A1 (en) | Polysilicon pillar bipolar transistor with self-aligned memory element | |
| CN1574410A (en) | Semiconductor memory device and method of fabricating the same | |
| US8012789B2 (en) | Nonvolatile memory device and method of manufacturing the same | |
| CN101339921B (en) | Manufacturing method of bi-polar transistor array isolated by double shallow slots | |
| US20090230375A1 (en) | Phase Change Memory Device | |
| US20080099814A1 (en) | Integrated circuit and method for production | |
| CN109686755A (en) | High-density phase-change memory and preparation method thereof | |
| KR101675322B1 (en) | Phase change memory device having nanowire network single elemental phase change layer in porous dielectric layer and method for manufacturing same | |
| TW201117367A (en) | Semiconductor memory device and manufacturing method thereof | |
| US20080135825A1 (en) | Phase-change memory device and method of fabricating the same | |
| US20120009731A1 (en) | Method of manufacturing phase-change random access memory | |
| CN105428528A (en) | Preparation method of memory cells of three-dimensional phase change memorizer | |
| CN113451205A (en) | Low resistance via contacts in memory devices | |
| KR102578801B1 (en) | Variable resistance memory device | |
| CN101752312B (en) | Manufacturing method of high-density diode array with double shallow trench isolation channels | |
| CN101882617B (en) | Schottky diode, semiconductor memory and manufacturing technology thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |