CN101339921A - Method for manufacturing bipolar transistor array with double shallow trench isolation - Google Patents

Abstract

The invention relates to a method for manufacturing a double shallow trench isolation (dual-STI) bipolar transistor array, which is characterized in that in the manufacturing method, a selective epitaxy method is avoided, and a deep transistor is formed on a substrate of the first conductivity type. The STI, uniformly deposited on the side walls and bottom of the STI containing the material of the second conductive type atoms that are easily diffused; removed the materials containing the second conductive type atoms that were deposited near the STI slot; annealing made the second conductive type of the above materials Atoms of the conductivity type diffuse into the bit lines to form heavy doping of the second conductivity type on the bit lines; then, the bit lines connected to each other due to the diffusion of the atoms of the second conductivity type are separated by etching, so that the bit lines are not electrically separated. conduction; an independent bipolar transistor is formed above the independent bit line by ion implantation and photolithography, and the transistors on the same bit line are separated by a shallower STI. The present invention also includes a manufacturing method of the phase change memory based on the double shallow trench isolation bipolar transistor gate.

Description

Method for manufacturing bipolar transistor array with double shallow trench isolation

technical field

The invention relates to a method for manufacturing a double-shallow trench isolation bipolar transistor array, and belongs to the field of phase-change memory manufacturing.

Background technique

Phase-change memory (PCRAM) is recognized as the biggest breakthrough in semiconductor memory technology in the past 40 years. It not only has superior performance in all aspects, but also is a general-purpose memory with broad market prospects. After its industrialization, it is expected to partially or completely replace various storage devices including flash (flash memory), DRAM (dynamic random access memory), and hard disk, thereby occupying an important position in the semiconductor memory market.

The storage unit part of the PCRAM is a resistor that can be programmed and adjusted by an electrical signal. In the actual application process, a logic device is required to gate and operate the storage unit. At present, the density of PCRAM mainly depends on the size of the driven transistors. Therefore, in high-density PCRAM storage arrays, bipolar transistors have become the mainstream development direction of major semiconductor companies because of their relatively small cell area. The storage capacity of chips manufactured by applying this technology has reached 512Mb. In the manufacture of bipolar transistor-gated PCRAM, how to manufacture bipolar transistors is the key to the technology, and it is also where major companies struggle. At present, Samsung uses the selective epitaxy method to manufacture bipolar transistors above heavily doped bit lines, but this method has high requirements on the manufacturing process and the manufacturing cost is very high.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a bipolar transistor array with double shallow trench isolation, and a method for manufacturing a phase-change memory based on the above structure.

To this end, the present invention provides two methods for manufacturing bipolar transistor arrays with double shallow trench isolation. The manufacturing steps of method A are:

(1) On a substrate of the first conductivity type (p-type or n-type), mutually independent bit lines are fabricated, and the bit lines are separated by deeper shallow trench isolation (STI) (deeper STI is relatively shallow compared to the STI that appears in the subsequent process. It is characterized by a relatively deep trench depth. The STI depth is between 50 nanometers and 10 microns, and the depth varies depending on the semiconductor technology node used. , such as 90nm process or 45nm semiconductor process technology);

(2) Depositing a material containing atoms of the second conductivity type (n-type or p-type) on the sidewall and bottom of the deeper STI;

(3) Spin-coat a layer of photoresist on the above substrate, remove the photoresist covering the top of the bit line and the STI notch by oxygen ion bombardment, and then remove the photoresist above the bit line and the STI notch by an etching back process. Material removal of atoms of the second conductivity type (n-type or p-type), reducing the probability of atoms of the second conductivity type diffusing to the top of the bit line during annealing;

(4) Annealing treatment, after high temperature and long-term annealing, the atoms of the second conductivity type in the material containing the atoms of the second conductivity type are diffused into the bit line, so that the bit line is doped by the atoms of the second conductivity type; annealing The treatment conditions vary depending on the diffused second conductivity type atom type, doping concentration and bit line width, the temperature is between 300°C and 1500°C, and the annealing time is between 1 minute and 48 hours. The annealing atmosphere is either inert gas, nitrogen or vacuum;

(5) Etching is used to separate the bit lines that are connected to each other due to the diffusion of atoms of the second conductivity type above. Possible signal crosstalk;

(6) Two layers of thin layers of different conductivity types are formed above the bit line by photolithography and ion implantation, and a bipolar transistor is formed with the bit line doped with the second conductivity type, and each bipolar transistor on the same bit line Type transistors are separated by a shallower STI with a depth between 10nm and 2μm;

(7) A bipolar transistor array is formed through filling, silicide and planarization processes of dielectric materials.

The manufacturing steps of Method B are:

(1) On the substrate of the first conductivity type, mutually independent bit lines are manufactured, and the bit lines are separated by a deep STI. The depth of the STI is between 50 nanometers and 10 microns. Varies with differences in semiconductor technology nodes;

(2) Continue to deposit materials containing atoms of the second conductivity type on the sidewall and bottom of this deeper STI;

(3) Deposit materials containing atoms of the second conductivity type on the sidewalls and bottom of the deeper STI to ensure that materials with atoms of the second conductivity type are deposited on the bottom of the STI, and remove the second conductivity on the top and sidewalls of the STI by etching back The material of the type atom, the material of the second conductivity type atom that retains the bottom shallow channel part is used as a diffusion barrier layer;

(4) Spin-coat a layer of photoresist on the above substrate, remove the photoresist covering the top of the bit line and the STI notch by oxygen ion bombardment, and remove the photoresist covering the top of the bit line and the STI notch by an etching-back process Removal of material containing atoms of the second conductivity type to avoid excessive diffusion of atoms of the second conductivity type to the top of the bit line;

(5) Annealing treatment, after high temperature and long-term annealing, the atoms of the second conductivity type in the material containing the atoms of the second conductivity type are diffused into the bit line, so that the bit line is doped by the atoms of the second conductivity type; annealing treatment The conditions vary with the diffused second conductivity type atom type, doping concentration and bit line width, the temperature is between 300°C and 1500°C, and the annealing time is between 1 minute and 48 hours;

(6) Etching is used to remove the material containing atoms of the second conductivity type at the bottom of the deeper STI;

(7) Bipolar transistors are formed above the above-mentioned bit lines by photolithography and ion implantation, and the bipolar transistors on the same bit line are separated by shallow STIs, and the depth of the STIs is between 10 nanometers and 2 Between microns;

(8) A bipolar transistor array is formed through filling, silicide and planarization processes of dielectric materials.

In the above two manufacturing methods:

① The material containing atoms of the second conductivity type is characterized in that the atoms of the second conductivity type can diffuse into the material of the first conductivity type under high-temperature annealing conditions to form a second Doping of conductivity type.

② The doping atoms of the second conductivity type are arsenic, phosphorus, antimony, bismuth, sulfur, selenium, tellurium, iodine, boron, aluminum, potassium, indium, thallium, lithium, potassium, sodium, beryllium, magnesium, calcium or silver.

③ The method for depositing the material containing atoms of the second conductivity type includes chemical vapor deposition, sputtering, atomic layer deposition or sol-gel method.

④ The resistivity of the dielectric material is higher than 1 ohm·meter; the double shallow trench isolation bipolar transistor array is used as phase change memory cell gate.

The present invention also provides a method for manufacturing a double shallow trench isolation bipolar transistor gate phase-change memory based on any one of the above two methods, including the following steps:

Deposit electrode materials and phase-change materials on the fabricated double-transistor array, and manufacture memory cells by photolithography;

Through the deposition and planarization of the dielectric material, and then photolithography, holes are carved on the dielectric material, so that the upper electrode of the phase change memory unit and the common electrode of the bit line are drawn out, and the driving circuit is manufactured. After packaging, the basic Phase change memory array.

The characteristics of the phase-change memory gated by the double shallow trench isolation bipolar transistor array made by the present invention are:

① Utilize the difference in resistance before and after the reversible phase change of the phase change material to realize data storage;

②Phase change materials have more than two states that can be reversibly switched under the action of electrical signals, and each state has different resistivity; optional materials include Ge-Sb-Te alloy, Si-Sb-Te alloy, Ge- Materials such as Sb, Si-Sb, Ag-In-Sb-Te, Ge-Te, pure Sb and doped Sb, mixtures of the above materials, and materials obtained by doping the above materials.

The feature of the invention is that it not only avoids the expensive selective epitaxial method to manufacture bipolar transistors, but also solves the problem that deep ion implantation cannot implant high concentration. The bit lines are doped by atomic diffusion on the sidewall of the STI, and each bit line is effectively separated by subsequent etching. And apply this invention to phase change memory.

Description of drawings

The manufacturing steps of the double shallow trench isolation bipolar transistor array shown in the embodiment 1 of FIGS. 1A-1P .

Figure 2A is a schematic diagram of a PCRAM memory array based on a double shallow trench isolation bipolar transistor array,

Figure 2B is a projection along the 5-5 direction of the previous figure.

3A-3J are the manufacturing steps of the double shallow trench isolation bipolar transistor array of embodiment 3.

Detailed ways

Example 1

1. On a clean p-type conductive substrate 11, an STI groove 14 with a depth of 500 nanometers is manufactured by exposure and etching processes. The part blocked by the photoresist 12 is not etched, and after etching, it is on the silicon wafer Protruding lines 15 separated from each other are formed; the cross-sectional view of the formed lines after the above processing is shown in FIG. 1A , and the top view is shown in FIG. 1B .

2. After removing the glue, use chemical vapor deposition to uniformly deposit the As glass film 16 on the top of the line 15, the side wall and the bottom of the STI groove 14; use chemical mechanical polishing to remove the As-containing glass layer 16 on the line 15. The cross-sectional and top views of the obtained graphics are shown in Figure 1C and Figure 1D.

3. Spin and coat photoresist on the substrate with a spinner, and the photoresist layer 18 will partially penetrate into the STI groove 14, as shown in FIG. 1E.

4. Bombard the substrate with oxygen ions in an etching machine to remove the photoresist on the surface of the substrate, the glue near the notch is also removed, and a part of the photoresist 19 remains in the STI groove, as shown in FIG. 1F .

5. Using an etching process, remove the As-containing glass at the notch of the STI slot 14, and the As-containing glass at the bottom of the slot is not etched because of the protection of the photoresist. After removing the residual photoresist, the As-containing glass is formed as shown in Figure 1G Structure.

6. Perform annealing treatment in vacuum, the annealing temperature is 1000°C for 6 hours, so that the As atoms in the As-containing glass film 16 diffuse into the lines 15, after the annealing and diffusion are completed, the lines 15 are heavily doped with As, becoming heavily doped Mixed n-type semiconductor, which forms the bit line 19, and has a lower resistivity; as shown in Figure 1G, because the bottom of the STI 14 is also deposited with As-containing glass, so many As atoms are also diffused into the bottom of the STI , so that the silicon material close to the As-containing glass has a lower resistivity, so that all the surrounding adjacent bit lines are turned on.

7. Using the ion implantation method, the n-type lightly doped region 20 and the p-type heavily doped region 21 are implanted above the bit line 19, and a p+/n-/n+ structure is formed between 21, 20 and 19 , as shown in Figure 1I; after this process, the projection along the 1-1 direction in Figure 1I is shown in Figure 1J.

8. The photolithography method is used again to separate the bit lines 19 that are originally electrically connected to each other due to the diffusion of As atoms, forming a structure as shown in FIG. 1K . In this way, the bit lines 19 are completely separated. The top view at this time is shown in FIG. 1L , and the projection along the direction 2 - 2 in FIG. 1L is shown in FIG. 1J .

9. Fabricate bipolar transistors (19+20+21) separated from each other above the above-mentioned bit line 19 by photolithography, and the top view of the formed structure is shown in Figure 1M. As shown in the projection in Figure 1N, the transistors are separated by a shallower STI 22. The depth of this STI is 150nm, so it is shallower than the previous STI of 500nm.

10. The filling and planarization process of the dielectric material, the dielectric material to be filled is amorphous silicon, and the planarization method is chemical mechanical polishing.

11. Further form the silicide _Six Co layer 23; use the electrodes to lead out the bit lines to form a bipolar transistor array with a cross section as shown in Figure 1O, and the top view of the projection along the direction 4-4 in Figure 1O is shown in Figure 1P .

Example 2

A method for manufacturing a bipolar transistor-gated PCRAM device based on the method described above.

1. The manufacturing method of manufacturing bipolar transistor array is as embodiment 1.

2. Deposit electrode material 24 (TiN 30nm), phase change material 25 (SiSb material 100nm) and electrode material 24 (TiN 30nm) sequentially above the bipolar transistor array obtained above, and manufacture memory cell patterns by photolithography.

3. Through the deposition of the dielectric material 29, chemical mechanical polishing and planarization, and then photolithography on the dielectric material, holes are carved in the dielectric material, so that the upper electrode 24 of the phase change memory unit and the bit line 19 are connected by metal plugs 27 and 26 is drawn out to manufacture electrodes 28 to form a memory array, as shown in FIG. 2A. In FIG. 2A, the projection along the 5-5 direction is shown in FIG. 2B.

Example 3

1. On the p-type conductive silicon substrate 30, use a photolithography process to etch an STI groove 32 with a depth of 700 nm, and form separate lines 31, the cross section of which is shown in FIG. 3A.

2. Deposit silicon oxide 33 by vapor deposition, as shown in FIG. 3B.

3. Using an etch-back process, the rest of the silicon oxide at the bottom of the STI trench is etched away, as shown in FIG. 3C .

4. Phosphorus-containing glass 34 is deposited by chemical vapor deposition, and the phosphorous-containing glass at the top and notch of the STI is removed by a method similar to steps 3 to 5 in Example 1 to form a cross-sectional view as shown in FIG. 3D .

5. Perform annealing treatment in argon protection, the annealing temperature is 1100°C for 5 hours, so that the phosphorus atoms in the material are fully diffused into the line 31, forming a heavily doped bit line 35, as shown in Figure 3E.

6. Etching back, removing the phosphorous glass 34 in the STI groove, as shown in FIG. 3F .

7. Ion implantation, sequentially forming 36 layers containing phosphorus impurities and 37 layers containing boron impurities, as shown in Figure 3G, the implantation depth of phosphorus is 150 nanometers; the projection along the 6-6 direction is shown in Figure 3H.

8. Photolithography, forming independent units above the bit line, and separating each unit with STI40 with a depth of 180 nanometers. After processing in Figure 3H, the structure shown in Figure 3I is formed.

9. Form a phase change memory structure through subsequent semiconductor processing technology, as shown in FIG. 3J . In the figure, 41 and 42 are Si _x Co silicides, 43 is electrode TiN, 44 is phase change material GeSbTe, 46 and 47 are W metal plugs, 48 is Al metal wire.

In summary, the present invention provides a bipolar transistor with double shallow trench isolation and a method for manufacturing a PCRAM storage device based on the transistor. Although only certain preferred embodiments have been described in detail, it will be apparent to those skilled in the art that certain modifications and changes can be made without departing from the scope of the present invention as defined in the appended claims.

Claims (7)

1, a kind of manufacturing method of the bipolar transistor array of double shallow trench isolation, it is characterized in that adopting any one in following two methods: Method A: a) On the substrate of the first conductivity type, mutually independent bit lines are manufactured, and the bit lines are separated by deep shallow trench isolation; b) depositing a material containing atoms of the second conductivity type on the sidewall and bottom of the shallow trench isolation formed in step a; c) removal of material containing atoms of the second conductivity type overlying the bit line and adjacent to the notch of the shallow trench isolation; d) annealing to diffuse the atoms of the second conductivity type in the material containing the atoms of the second conductivity type into the bit line, and form doping of the second conductivity type on the bit line; e) using an etching method to separate the diffusion-doped and mutually conductive bit lines formed in step d, so that the bit lines are electrically non-conductive; f) Form bipolar transistors on the electrically non-conductive bit lines formed in step e by photolithography and ion implantation, and separate bipolar transistors above the same bit line by relatively shallow shallow trenches separated; g) Finally, a bipolar transistor array is formed by filling and planarizing the dielectric material; Method B: a) On the substrate of the first conductivity type, mutually independent bit lines are manufactured, and the bit lines are separated by deep shallow trench isolation; b) depositing a material of the second conductivity type atoms on the sidewall and bottom of the deeper shallow trench isolation formed in step a; c) removing the material of the second conductivity type atoms covering above the bit line and the sidewall of the deeper shallow trench isolation through an etching-back process, and leaving part of the material of the second conductivity type atoms at the bottom of the groove of the shallow trench isolation; d) Deposit a material containing atoms of the second conductivity type, and remove the material containing atoms of the second conductivity type covering the bit line and near the notch of the shallow trench isolation, so as to prevent the atoms of the second conductivity type from being annealed during the annealing process Excessive diffusion to the top of the bitline in e) an annealing treatment to diffuse atoms of the second conductivity type in the material containing atoms of the second conductivity type into the bit line, so that the bit line is thereby doped with atoms of the second conductivity type; f) using an etching method to remove the material containing the atoms of the second conductivity type in the deeper shallow trench isolation; g) Two thin layers of different conductivity types are formed above the bit line by ion implantation and photolithography, and a bipolar transistor is formed with the bit line doped with the second conductivity type, and each bipolar transistor above the same bit line Transistors are separated by shallower STIs; h) forming a bipolar transistor array by filling and planarizing a dielectric material; The depth of the deeper STI is between 50 nanometers and 10 microns; The shallower STI has a depth between 10 nanometers and 2 micrometers; The first conductivity type is p-type or n-type, and the second conductivity type is n-type or p-type. 2. The method for manufacturing a bipolar transistor array with double shallow trench isolation as claimed in claim 1, characterized in that the atoms of the second conductivity type are arsenic, phosphorus, antimony, bismuth, sulfur, selenium, Tellurium, iodine, boron, aluminum, potassium, indium, thallium, lithium, potassium, sodium, beryllium, magnesium, calcium, or silver. 3. The manufacturing method of double shallow trench isolation bipolar transistor array as claimed in claim 1, characterized in that the annealing treatment condition is that the temperature is between 300°C and 1500°C, and the annealing time is between 1 minute and 48 hours Between, the atmosphere is an inert atmosphere, nitrogen or vacuum. 4. The manufacturing method of double shallow trench isolation bipolar transistor array as claimed in claim 1, characterized in that the method of depositing the material containing atoms of the second conductivity type is chemical vapor deposition, sputtering, atomic layer deposition method or sol-gel method. 5. The method for manufacturing a double shallow trench isolation bipolar transistor array as claimed in claim 1, characterized in that the resistivity of the dielectric material is greater than 1 ohm·meter. 6. A method for manufacturing a double shallow trench isolated bipolar transistor array-gated phase-change memory manufactured by any one of claims 1 to 5, characterized in that: ① Deposit electrode materials and phase change materials on the array of bipolar transistors produced by method A or method B, and manufacture memory cells by photolithography; ②Through the deposition and planarization of the dielectric material, and then use photolithography to carve holes in the dielectric material, so as to lead out the upper electrode of the phase change memory unit and the common electrode of the bit line, and manufacture a driving circuit to form a basic phase change memory array. 7. The method for manufacturing a phase-change material memory according to claim 6, wherein the phase-change material has more than two states that can be reversibly switched under the action of an electric signal, and each state has a different resistivity; said Phase change materials include Ge-Sb-Te alloys, Si-Sb-Te alloys, Ge-Sb, Si-Sb, Ag-In-Sb-Te, Ge-Te, pure Sb or doped Sb materials and mixtures of the above materials Or materials obtained after doping.

Images