CN113517313A - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN113517313A CN113517313A CN202110454675.3A CN202110454675A CN113517313A CN 113517313 A CN113517313 A CN 113517313A CN 202110454675 A CN202110454675 A CN 202110454675A CN 113517313 A CN113517313 A CN 113517313A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application discloses a three-dimensional memory and a manufacturing method thereof, wherein the method comprises the following steps: providing a plurality of memory cells, wherein grooves are formed among the memory cells; the depth-to-width ratio of the groove is greater than a preset value; depositing a first insulating material in the groove to form a first insulating layer; performing first etching on the first insulating layer to enable the size of the top opening of the groove formed with the first insulating layer to be larger than the size of the bottom opening; and depositing a second insulating material in the groove with the first insulating layer to form a second insulating layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a three-dimensional memory and a method for manufacturing the same.
Background
Three-dimensional cross-point memories, such as Phase Change Memories (PCMs), are a Memory technology that uses chalcogenides as the storage medium to store data by using the difference in resistance of materials in different states. PCM has the advantages of bit-addressable, no data loss after power-off, high storage density, fast read-write speed, etc., and is considered as the most promising next-generation memory.
However, in the related art, three-dimensional cross-point memories also present various challenges.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present application provide a three-dimensional memory and a method for manufacturing the same.
The embodiment of the application provides a manufacturing method of a three-dimensional memory, which comprises the following steps: providing a plurality of memory cells, wherein grooves are formed among the memory cells; the depth-to-width ratio of the groove is greater than a preset value;
depositing a first insulating material in the groove to form a first insulating layer;
performing first etching on the first insulating layer to enable the size of the top opening of the groove formed with the first insulating layer to be larger than the size of the bottom opening;
and depositing a second insulating material in the groove with the first insulating layer to form a second insulating layer.
In the above scheme, the method further comprises:
performing second etching on the second insulating layer to enable the size of the top opening of the groove formed with the first insulating layer and the second insulating layer to be larger than or equal to the size of the bottom opening;
and depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer to form a third insulating layer.
In the above scheme, the three-dimensional memory comprises a phase change memory, and the memory cell comprises a stacked phase change memory PCM element, a gating element and a plurality of electrodes;
the first insulating material comprises silicon oxide, the second insulating material comprises silicon nitride, and the third insulating material comprises carbon-doped silicon oxide.
In the above scheme, the depositing the first insulating material in the trench includes: depositing a first insulating material in the trench by utilizing an atomic layer deposition process;
the depositing of the second insulating material in the groove formed with the first insulating layer comprises: depositing a second insulating material in the groove with the first insulating layer by using a chemical vapor deposition process;
depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer, wherein the third insulating material comprises: and depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer by using a spin coating process.
In the above-mentioned scheme, the first step of the method,
depositing a first insulating material in the groove and performing first etching on the first insulating layer are both performed in a first reaction chamber;
and/or the presence of a gas in the gas,
and depositing a second insulating material in the groove with the first insulating layer and performing second etching on the second insulating layer in a second reaction chamber.
In the above-mentioned scheme, the first step of the method,
depositing a first insulating material in the groove to form a first insulating layer, wherein the first insulating layer comprises:
performing multiple depositions of a first insulating material in the groove by utilizing an atomic layer deposition method process, wherein each deposition forms a corresponding sub-insulating layer, and the multiple sub-insulating layers form the first insulating layer;
performing a first etch on the first insulating layer, including:
after depositing a first insulating material in the groove at least once, forming a first sub-insulating layer, and performing first etching on the formed first sub-insulating layer for the first time;
after the first etching is carried out for the first time, after the first insulating material is deposited in the groove for at least one time, a second sub insulating layer is formed, and the first etching is carried out for the second time on the formed second sub insulating layer;
and repeating the deposition and the first etching process for multiple times to enable the size of the top opening of the groove formed with the first insulating layer to be larger than that of the bottom opening.
In the above scheme, the depositing the first insulating material in the trench includes: depositing a first insulating material on top of the memory cell;
the first etching of the first insulating layer includes: and carrying out first etching on the first insulating material deposited on the top of the memory cell.
An embodiment of the present application further provides a three-dimensional memory, including: a plurality of memory cells, a first insulating layer, and a second insulating layer covering the first insulating layer; wherein the content of the first and second substances,
the first insulating layer is arranged in the grooves among the memory units, the size of the top opening of the groove formed with the first insulating layer is larger than that of the bottom opening, and the depth-to-width ratio of the groove is larger than a preset value.
In the above scheme, the three-dimensional memory further includes a third insulating layer covering the second insulating layer; wherein the content of the first and second substances,
the size of the top opening of the trench formed with the first insulating layer and the second insulating layer is larger than or equal to the size of the bottom opening.
In the above scheme, the three-dimensional memory comprises a phase change memory, and the memory cell comprises a stacked phase change memory PCM element, a gating element and a plurality of electrodes;
the first insulating layer is made of silicon oxide, the second insulating layer is made of silicon nitride, and the third insulating layer is made of carbon-doped silicon oxide.
The embodiment of the application provides a three-dimensional memory and a manufacturing method thereof, wherein the method comprises the following steps: providing a plurality of memory cells, wherein grooves are formed among the memory cells; the depth-to-width ratio of the groove is greater than a preset value; depositing a first insulating material in the groove to form a first insulating layer; performing first etching on the first insulating layer to enable the size of the top opening of the groove formed with the first insulating layer to be larger than the size of the bottom opening; and depositing a second insulating material in the groove with the first insulating layer to form a second insulating layer. In the embodiment of the application, a first insulating layer is formed in the trenches between the memory cells, the first insulating layer is subjected to first etching, so that the size of the top opening of the trench formed with the first insulating layer is larger than that of the bottom opening of the trench, and then a second insulating layer is formed in the trench formed with the first insulating layer. The size of the top opening of the groove is larger than that of the bottom opening, so that a reaction gas source for forming the second insulating layer can enter the groove more easily, the second insulating material can be deposited in the groove better, and the problem of poor filling effect of the second insulating material in the groove is solved.
Drawings
FIGS. 1a to 1c are schematic structural diagrams illustrating a method for fabricating a three-dimensional memory according to the related art;
fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 4a to fig. 4c are schematic structural diagrams illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a three-dimensional memory according to the related art;
fig. 6 is a schematic structural diagram of a method for manufacturing a three-dimensional memory according to another embodiment of the present application.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
The three-dimensional Memory according to the embodiment of the present application may include a three-dimensional Memory including a bit line, a word line, and a Memory cell, which are staggered horizontally and vertically, and includes but is not limited to a PCM, a Ferroelectric Memory (FeRAM), a magnetic Memory (MRAM), a Resistive Random Access Memory (RRAM), and a Resistive Random Access Memory (RRAM). Hereinafter, only PCM will be described as an example.
In the phase change memory, it is necessary to seal and protect the memory cells of the phase change memory, in the related art, a trench between the phase change memory cells is filled with silicon oxide, and a trench filled with silicon oxide is sequentially filled with silicon nitride (PPSiN) and spin-on dielectric (SOD) for encapsulation, and a process of filling a trench between the phase change memory cells with silicon oxide in the related art is shown in fig. 1a to 1 c. As can be seen from the figure, when depositing silicon oxide into the trench by using an atomic layer deposition process, silicon oxide is usually formed on the sidewall and the bottom of the trench and on the top of the phase change memory cell, which easily causes a top seal of the encapsulated silicon nitride in the subsequent process during filling, so that the encapsulated silicon nitride and the spin-on dielectric in the subsequent process have poor filling effect in the trench.
Therefore, the following technical scheme of the embodiment of the application is provided.
Fig. 2 is a schematic flow chart illustrating an implementation of the method for manufacturing a three-dimensional memory according to the embodiment of the present application. As shown in fig. 2, the method comprises the steps of:
step 201: providing a plurality of memory cells, wherein grooves are formed among the memory cells; the depth-to-width ratio of the groove is greater than a preset value;
step 202: depositing a first insulating material in the groove to form a first insulating layer;
step 203: performing first etching on the first insulating layer to enable the size of the top opening of the groove formed with the first insulating layer to be larger than the size of the bottom opening;
step 204: and depositing a second insulating material in the groove with the first insulating layer to form a second insulating layer.
In step 201, each of the plurality of memory cells is located on the same plane and has a pillar shape, and trenches are formed between the plurality of memory cells. In practical applications, after the memory cells are formed, some insulating materials need to be filled into the trenches to protect the memory cells and isolate the memory cells. In practical applications, the method for forming the pillar-shaped memory cell may include an etching process, including but not limited to dry etching.
Here, the aspect ratio of the trench is greater than the predetermined value, which means that the thickness of the memory cell is relatively thick, the depth of the trench formed between the memory cells is relatively deep, and in order to meet the requirement of miniaturization of the memory, the density of the memory cell arrangement is relatively high, and the width of the trench formed between the memory cells is relatively narrow, so that the ratio of the depth to the width of the trench, i.e., the aspect ratio, is relatively large. For the trench with a large aspect ratio, the problem of poor filling effect is easy to occur during filling. In the embodiment of the present application, the trench is a trench with a large aspect ratio. Here, the preset value of the aspect ratio of the groove may be 5: 1.
In some embodiments, as shown in fig. 3, the three-dimensional memory comprises a phase change memory, the memory cell comprising a phase change memory PCM element, a gating element and a plurality of electrodes arranged in a stack. The three-dimensional memory further includes a substrate, peripheral circuitry on the substrate, and an interconnect layer on the peripheral circuitry.
In practical applications, taking the phase change memory as an example, the depth of the trench between the memory cells is about 2200nm, the width of the trench is about 150nm, and the aspect ratio of the trench is about 15: 1.
In practical application, the electrode is heated or quenched by the conduction of the gating element to realize the switching between the crystalline state and the amorphous state of the PCM element; the storage of data is achieved by switching between the crystalline and amorphous states of the PCM element. In practice, the material of the PCM element comprises a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the material of the gating element may comprise any suitable OTS material, such as ZnxTey、GexTey、NbxOy、SixAsyTezEtc.; the material of the electrode may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes comprises carbon, such as amorphous carbon.
In practical applications, as shown in fig. 4a, the three-dimensional memory further includes a substrate, on which the plurality of memory cells are disposed, and the substrate may be a simple substance semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
In step 202, a first insulating material is deposited in the trench, forming a first insulating layer, as shown in fig. 4 b.
In some embodiments, the first insulating material comprises silicon oxide.
In some embodiments, the depositing a first insulating material within the trench includes: depositing a first insulating material within the trench using an atomic layer deposition process.
In some embodiments, the depositing a first insulating material within the trench includes: a first insulating material is deposited on top of the memory cell.
In step 203, as shown in fig. 4c, a first etching is performed on the first insulating layer to make the top opening size of the trench formed with the first insulating layer larger than the bottom opening size.
In practical applications, the first etching may include dry etching, wherein, when the first insulating material includes silicon oxide, an etching gas containing a fluorine source may be used in the step of dry etching. In some embodiments, the dry etching may be plasma etching, and the etching gas may be NF3、CF4Or CHF3Or other etching gases known in the art that may be used to etch silicon oxide. It should be noted that the first etching is performed under a low power condition, so that the first etching process has less influence on the first insulating material at the middle and bottom of the trench during the process of removing the first insulating material at the top of the trench.
In some embodiments, the first etching the first insulating layer includes: and carrying out first etching on the first insulating material deposited on the top of the memory cell.
It will be appreciated that, at the same time as the first insulating material is deposited in the trenches, a portion of the first insulating material is also deposited on top of the memory cells, during the etching of the first insulating material in the trench, a portion of the first insulating material deposited on top of the memory cell is also etched, after depositing the first insulating material on the top of the memory cell, if the first insulating material deposited on the top of the memory cell is not etched, since the first insulating material deposited on top of the memory cell has a certain thickness, such that the depth of the trench becomes relatively deeper when the second insulating material is deposited, the deeper the trench is, the less conducive to filling with the second insulating material, in the embodiment of the application, the first insulating material on the top of the storage unit is etched, so that the depth of the groove is relatively shallow when the second insulating material is deposited, and the filling effect of the second insulating material is better.
In some embodiments, the depositing a first insulating material within the trench, forming a first insulating layer, includes:
performing multiple depositions of a first insulating material in the groove by utilizing an atomic layer deposition method process, wherein each deposition forms a corresponding sub-insulating layer, and the multiple sub-insulating layers form the first insulating layer;
performing a first etch on the first insulating layer, including:
after depositing a first insulating material in the groove at least once, forming a first sub-insulating layer, and performing first etching on the formed first sub-insulating layer for the first time;
after the first etching is carried out for the first time, after the first insulating material is deposited in the groove for at least one time, a second sub insulating layer is formed, and the first etching is carried out for the second time on the formed second sub insulating layer;
and repeating the deposition and the first etching process for multiple times to enable the size of the top opening of the groove formed with the first insulating layer to be larger than that of the bottom opening.
Here, after performing deposition of a first insulating material at least once in the trench, forming a first sub-insulating layer; performing first etching on the formed first sub-insulating layer for the first time; it is to be understood that the first insulating material may be deposited once in the trench and then the first etching may be performed, or the first insulating material may be deposited multiple times in the trench and then the first etching may be performed. Forming a second sub-insulating layer after depositing the first insulating material in the groove at least once; performing second etching on the formed second sub-insulating layer; it is understood that the first insulating material may be deposited once in the trench and then the first etching may be performed a second time, or the first insulating material may be deposited multiple times in the trench and then the first etching may be performed a second time.
Here, repeatedly performing the above-described deposition and etching processes a plurality of times may be understood as that the deposition and etching process for the first insulating material includes a plurality of cycle processes, each cycle process includes deposition and etching for the first insulating material, and the size of the top opening of the trench formed with the first insulating layer is made larger than the size of the bottom opening through the plurality of deposition and etching processes, which may achieve a better effect of filling the second insulating material.
In step 204, a second insulating material is deposited in the trench formed with the first insulating layer to form a second insulating layer.
In some embodiments, the depositing a second insulating material in the trench formed with the first insulating layer includes:
and depositing a second insulating material in the groove with the first insulating layer by using a chemical vapor deposition process.
It can be understood that, since the upper sealing phenomenon is very likely to occur during the process of forming the second insulating layer, the top opening size of the trench formed with the first insulating layer is larger than the bottom opening size by performing the first etching on the deposited first insulating layer in the embodiment of the present application, so that a space with a large top and a small bottom is reserved for the second insulating layer, and the second insulating material can be better filled into the trench.
In practical applications, as shown in fig. 5, since the second insulating layer has poor uniformity during filling, and needs to be made thicker during the manufacturing process of the three-dimensional memory in order to provide better protection for the elements in the phase change memory, this results in a high aspect ratio of the trench during deposition of the second insulating layer, which is detrimental to the deposition of the second insulating material, typically resulting in the second insulating material approaching the seal at the top of the trench, the top of the trench is of a small size so that the subsequent third insulating material cannot completely fill the trench, thereby forming a void in the trench, and failing to form stable dielectric isolation between the phase change memory cell and the phase change memory cell conductor, meanwhile, the void formed in the trench is also prone to cause instability of subsequent processes, thereby affecting product yield and reliability.
In some embodiments, the method further comprises:
performing second etching on the second insulating layer to enable the size of the top opening of the groove formed with the first insulating layer and the second insulating layer to be larger than or equal to the size of the bottom opening;
and depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer to form a third insulating layer.
In some embodiments, the second insulating material comprises silicon nitride and the third insulating material comprises carbon-doped silicon oxide.
In practical applications, the second etching may include dry etching, wherein, when the second insulating material includes silicon nitride, an etching gas containing a fluorine source may be used in the step of dry etching. In some embodiments, the dry etching may be plasma etching, and the etching gas may include CF4、CHF3、Ar、NF3、O2、H2Or other etching gases known in the art that may be used to etch silicon nitride.
Here, the first insulating material, the second insulating material, and the third insulating material function to protect the element seal in the phase change memory cell.
In some embodiments, the depositing of the first insulating material within the trench and the first etching of the first insulating layer are both performed in a first reaction chamber;
and/or the presence of a gas in the gas,
and depositing a second insulating material in the groove with the first insulating layer and performing second etching on the second insulating layer in a second reaction chamber.
Here, the depositing of the first insulating material in the trench and the first etching of the first insulating layer are performed in a first reaction chamber, and it is understood that the depositing of the first insulating material and the etching of the first insulating layer are performed in the same reaction chamber, and specifically, the depositing of the first insulating material and the etching of the first insulating layer may be performed in the following reaction chambers: introducing a reaction gas source into the first reaction chamber, depositing a first insulating material on the side wall and the bottom of the groove, introducing etching gas into the first reaction chamber to etch the first insulating material, and removing part of the first insulating material deposited on the top of the groove.
The depositing of the second insulating material in the trench formed with the first insulating layer and the second etching of the second insulating layer are performed in the second reaction chamber, which may be understood as that the depositing of the second insulating material and the etching of the second insulating layer are performed in the same reaction chamber, and specifically may be that: and introducing a reaction gas source into the second reaction chamber, depositing a second insulating material on the side wall and the bottom of the groove formed with the first insulating material, introducing etching gas into the second reaction chamber to etch the second insulating material, and removing part of the second insulating material deposited on the top of the groove.
It can be understood that, since the deposition and etching of the first insulating material can be performed in the same reaction chamber, and the deposition and etching of the second insulating material can be performed in the same reaction chamber, the overall processing time of the process can be reduced, and meanwhile, the pollution caused by the deposition and etching in and out of different reaction chambers can be avoided, and the product yield can be improved.
As shown in fig. 6, in the embodiment of the present application, the deposited second insulating layer is subjected to a second etching process, so that the size of the top opening of the trench in which the second insulating layer is formed is greater than or equal to the size of the bottom opening, and thus the third insulating material can be better filled into the trench.
Here, it is understood that, when the second insulating layer is formed, the top opening of the trench formed with the first insulating layer and the second insulating layer is close to the bottom opening, that is, the top opening of the trench is smaller than the bottom opening, so that the top opening of the trench needs to be widened to be equal to or larger than the bottom opening, so that the trench can be better filled with the third insulating material in the subsequent process.
In practical application, when the second insulating material is deposited in the trench in which the first insulating layer is formed, a part of the second insulating material is deposited on the top of the phase change memory cell, and in the process of etching the second insulating material in the trench, a part of the second insulating material deposited on the top of the phase change memory cell is also etched. And depositing a part of the third insulating material on the top of the phase change memory cell at the same time of depositing the third insulating material in the groove formed with the first insulating layer and the second insulating layer.
In practical applications, after the third insulating layer is formed, the third insulating material deposited on the top of the phase change memory cell, the portion of the first insulating material deposited on the top of the phase change memory cell that is not removed by the first etching, and the portion of the second insulating material deposited on the top of the phase change memory cell that is not removed by the second etching are also removed, and methods for removing the third insulating material deposited on the top of the phase change memory cell, the portion of the first insulating material deposited on the top of the phase change memory cell, and the portion of the second insulating material deposited on the top of the phase change memory cell include, but are not limited to, a chemical mechanical polishing process.
It can be understood that, since a portion of the first insulating material and the second insulating material deposited on the top of the phase change memory cell has been removed in the first etching and the second etching, the time required in the subsequent process of removing the third insulating material deposited on the top of the phase change memory cell, the portion of the first insulating material deposited on the top of the phase change memory cell, and the portion of the second insulating material deposited on the top of the phase change memory cell by using the chemical mechanical polishing process is shortened, so that the time for manufacturing the whole three-dimensional memory is not increased by increasing the first etching and the second etching, and the polishing slurry required by the chemical mechanical polishing can be saved, so that a three-dimensional memory with higher performance can be manufactured, and the manufacturing cost can be saved.
It should be noted that, in the process of forming the second insulating layer, there is a process of performing surface treatment on the deposited second insulating layer, and the surface treatment process can make the deposited second insulating layer denser, so that the protection effect on the phase change memory cell is better, the second etching process in the embodiment of the present application cannot be introduced in the deposition step, and since the process of introducing the second etching in the deposition step can damage the PCM element and the gate element in the phase change memory cell, the second etching process in the embodiment of the present application can be introduced in the process of surface treatment, and the surface treatment process and the second etching process are performed simultaneously, so that the time of the manufacturing process can be saved, and under the effect of the bias electric field, the introduced etching particles bombard the second insulating layer on the top of the phase change memory cell, and remove the second insulating material on the top of the trench, which can cause sealing, so that the size of the top opening of the trench formed with the first insulating layer and the second insulating layer is larger than or equal to the size of the bottom opening, and the third insulating material can be better filled into the trench.
In some embodiments, the depositing a third insulating material in the trench formed with the first insulating layer and the second insulating layer includes: and depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer by using a spin coating process.
It is understood that the atomic layer deposition process is a deposition method for depositing a very thin film through a plurality of deposition cycles, and the deposited film has good uniformity and high denseness. The first insulating layer is used for preventing water vapor, oxygen and the like from entering the PCM element and the gating element in the phase change memory unit so as to avoid influencing the performance of the phase change memory. The formation of the dense first insulating layer on the sidewalls and bottom of the trench by the atomic layer deposition process can provide better protection for the PCM element and the gate element in the phase change memory cell.
The compactness of the film obtained by the chemical vapor deposition process is relatively poorer than that of the film obtained by the atomic layer deposition process, but the deposition rate of the chemical vapor deposition process is higher than that of the atomic layer deposition process. The uniformity of the second insulating layer deposited by the chemical vapor deposition method is poor, and the upper sealing condition is easy to occur during deposition, so that the effect of filling the second insulating material in the groove is poor, a cavity is formed, stable dielectric isolation cannot be formed between the memory unit and the memory unit conductor, meanwhile, the formed cavity is easy to cause instability of subsequent processes, the yield and the reliability of products are affected, although the size of the top opening of the formed groove can be larger than that of the bottom opening by carrying out first etching on the first insulating layer, the upper sealing phenomenon which is easy to occur during deposition of the second insulating material can be improved, and the sealing phenomenon cannot be avoided.
And because the material source used by the spin coating process is an organic solvent, a thin film is formed by using liquid glue drops under certain centrifugal acceleration, and compared with a chemical vapor deposition method, the thin film can fill a gap with a smaller opening size.
The embodiment of the application provides a manufacturing method of a three-dimensional memory, which comprises the following steps: providing a plurality of memory cells, wherein grooves are formed among the memory cells; the depth-to-width ratio of the groove is greater than a preset value; depositing a first insulating material in the groove to form a first insulating layer; performing first etching on the first insulating layer to enable the size of the top opening of the groove formed with the first insulating layer to be larger than the size of the bottom opening; and depositing a second insulating material in the groove with the first insulating layer to form a second insulating layer. In the embodiment of the application, a first insulating layer is formed in the trenches between the memory cells, the first insulating layer is subjected to first etching, so that the size of the top opening of the trench formed with the first insulating layer is larger than that of the bottom opening of the trench, and then a second insulating layer is formed in the trench formed with the first insulating layer. The size of the top opening of the groove is larger than that of the bottom opening, so that a reaction gas source for forming the second insulating layer can enter the groove more easily, the second insulating material can be deposited in the groove better, and the problem of poor filling effect of the second insulating material in the groove is solved.
Based on the manufacturing method of the three-dimensional memory, an embodiment of the present application further provides a three-dimensional memory, including: a plurality of memory cells, a first insulating layer, and a second insulating layer covering the first insulating layer;
the first insulating layer is arranged in the grooves among the memory units, the size of the top opening of the groove formed with the first insulating layer is larger than that of the bottom opening, and the aspect ratio of the groove is larger than a preset value.
In some embodiments, the three-dimensional memory further comprises a third insulating layer covering the second insulating layer; wherein the content of the first and second substances,
the size of the top opening of the trench formed with the first insulating layer and the second insulating layer is larger than or equal to the size of the bottom opening.
In some embodiments, the three-dimensional memory comprises a phase change memory, the memory cell comprising a Phase Change Memory (PCM) element, a gating element, and a plurality of electrodes arranged in a stack;
the material of the first insulating layer comprises silicon oxide, the material of the second insulating layer comprises silicon nitride, and the material of the third insulating layer comprises carbon-doped silicon oxide.
The details of the three-dimensional memory described above are described in detail in the corresponding manufacturing method, and are not described herein again.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of fabricating a three-dimensional memory, the method comprising:
providing a plurality of memory cells, wherein grooves are formed among the memory cells; the depth-to-width ratio of the groove is greater than a preset value;
depositing a first insulating material in the groove to form a first insulating layer;
performing first etching on the first insulating layer to enable the size of the top opening of the groove formed with the first insulating layer to be larger than the size of the bottom opening;
and depositing a second insulating material in the groove with the first insulating layer to form a second insulating layer.
2. The method of manufacturing a three-dimensional memory according to claim 1, further comprising:
performing second etching on the second insulating layer to enable the size of the top opening of the groove formed with the first insulating layer and the second insulating layer to be larger than or equal to the size of the bottom opening;
and depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer to form a third insulating layer.
3. The method of manufacturing a three-dimensional memory according to claim 2, wherein the three-dimensional memory comprises a phase change memory, and the memory cell comprises a stacked Phase Change Memory (PCM) element, a gate element, and a plurality of electrodes;
the first insulating material comprises silicon oxide, the second insulating material comprises silicon nitride, and the third insulating material comprises carbon-doped silicon oxide.
4. The method of manufacturing a three-dimensional memory according to claim 3,
the depositing a first insulating material within the trench includes:
depositing a first insulating material in the groove by utilizing an atomic layer deposition process;
the depositing of the second insulating material in the groove formed with the first insulating layer comprises:
depositing a second insulating material in the groove with the first insulating layer by using a chemical vapor deposition process;
depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer, wherein the third insulating material comprises:
and depositing a third insulating material in the groove formed with the first insulating layer and the second insulating layer by using a spin coating process.
5. The method of manufacturing a three-dimensional memory according to claim 4,
depositing a first insulating material in the groove and performing first etching on the first insulating layer are both performed in a first reaction chamber;
and/or the presence of a gas in the gas,
and depositing a second insulating material in the groove with the first insulating layer and performing second etching on the second insulating layer in a second reaction chamber.
6. The method of manufacturing a three-dimensional memory according to claim 1,
depositing a first insulating material in the groove to form a first insulating layer, wherein the first insulating layer comprises:
performing multiple depositions of a first insulating material in the groove by utilizing an atomic layer deposition method process, wherein each deposition forms a corresponding sub-insulating layer, and the multiple sub-insulating layers form the first insulating layer;
performing a first etch on the first insulating layer, including:
after depositing a first insulating material in the groove at least once, forming a first sub-insulating layer, and performing first etching on the formed first sub-insulating layer for the first time;
after the first etching is carried out for the first time, after the first insulating material is deposited in the groove for at least one time, a second sub insulating layer is formed, and the first etching is carried out for the second time on the formed second sub insulating layer;
and repeating the deposition and the first etching process for multiple times to enable the size of the top opening of the groove formed with the first insulating layer to be larger than that of the bottom opening.
7. The method of claim 1, wherein depositing a first insulating material within the trench comprises: depositing a first insulating material on top of the memory cell;
the first etching of the first insulating layer includes:
and carrying out first etching on the first insulating material deposited on the top of the memory cell.
8. A three-dimensional memory, comprising: a plurality of memory cells, a first insulating layer, and a second insulating layer covering the first insulating layer; wherein the content of the first and second substances,
the first insulating layer is arranged in the grooves among the memory units, the size of the top opening of the groove formed with the first insulating layer is larger than that of the bottom opening, and the depth-to-width ratio of the groove is larger than a preset value.
9. The three-dimensional memory according to claim 8, further comprising a third insulating layer covering the second insulating layer; wherein the content of the first and second substances,
the size of the top opening of the trench formed with the first insulating layer and the second insulating layer is larger than or equal to the size of the bottom opening.
10. The three-dimensional memory according to claim 9, wherein the three-dimensional memory comprises a phase change memory, the memory cell comprising a Phase Change Memory (PCM) element, a gating element, and a plurality of electrodes arranged in a stack;
the first insulating layer is made of silicon oxide, the second insulating layer is made of silicon nitride, and the third insulating layer is made of carbon-doped silicon oxide.
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