CN112435957A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN112435957A
CN112435957A CN202011301184.7A CN202011301184A CN112435957A CN 112435957 A CN112435957 A CN 112435957A CN 202011301184 A CN202011301184 A CN 202011301184A CN 112435957 A CN112435957 A CN 112435957A
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groove
semiconductor structure
etching
plasma
material layer
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涂飞飞
罗兴安
王新胜
王雄禹
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202011301184.7A priority Critical patent/CN112435957A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32568—Relative arrangement or disposition of electrodes; moving means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention relates to a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a dielectric layer, and a groove is formed in the dielectric layer; forming a first material layer conformally on the dielectric layer, wherein the first material layer forms a first groove in the groove; adjusting an incident angle when the semiconductor structure is etched, and etching according to the incident angle to enlarge the opening of the first groove and form a second groove; and forming a second material layer filling the second groove.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to a manufacturing method of a semiconductor device, and the semiconductor device formed by the manufacturing method is provided with a compact filling part.
Background
Semiconductor integrated circuits have since their birth, undergone a phase of development from small-scale, medium-scale to large-scale and very large-scale integration, and are increasingly becoming one of the most active technical fields in modern scientific technology.
A memory is a widely used semiconductor device. To overcome the limitation of the storage capacity of the conventional two-dimensional memory, modern technologies often adopt a stacked memory chip manner to achieve higher integration. For example, chips or structures with different functions can be processed by micro-machining technology such as stacking or hole interconnection to form a three-dimensional (3D) device with three-dimensional integration and signal communication in the vertical direction. The three-dimensional memory is formed by three-dimensionally arranging memory cells on a substrate by using the technology, so that the aim of improving the performance and the storage density of the memory is fulfilled.
In the fabrication of semiconductor devices, such as three-dimensional memories, semiconductor structures having high aspect ratio trenches are often formed. In the subsequent process, the deep trench needs to be filled.
For example, the large-size trench filling can be achieved by depositing silicon oxide using a Plasma-enhanced tetraethylorthosilicate (PETEOS) source.
However, this filling method is only suitable for shallow (height <3um) trenches. For deeper trenches, filling voids are generated due to the Deposition growth method of Plasma Enhanced Chemical Vapor Deposition (PECVD) and the Step Coverage (Step Coverage) characteristics, which seriously affect the subsequent process. Therefore, with the development of the stacking process, higher requirements are put on the filling of deep trenches (height >9 um).
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, and the semiconductor device formed by the manufacturing method has a compact filling part.
The present invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a dielectric layer, and a groove is formed in the dielectric layer; forming a first material layer conformally on the dielectric layer, wherein the first material layer forms a first groove in the groove; adjusting an incident angle when the semiconductor structure is etched, and etching according to the incident angle to enlarge the opening of the first groove and form a second groove; and forming a second material layer filling the second groove.
In an embodiment of the present invention, the etching is plasma etching, the plasma is emitted from an upper electrode located above the semiconductor structure to a lower electrode located below the semiconductor structure, an incident angle when the semiconductor structure is etched is adjusted, and the etching is performed according to the incident angle to enlarge the opening of the first groove, including: adjusting the inclination angle of the lower electrode relative to the horizontal direction so that the incident angle of the plasma incident on the semiconductor structure between the upper electrode and the lower electrode is the incident angle; and etching the semiconductor structure according to the incident angle so as to enlarge the opening of the first groove.
In an embodiment of the present invention, the etching is plasma etching, the plasma is emitted from an upper electrode located above the semiconductor structure to a lower electrode located below the semiconductor structure, an incident angle when the semiconductor structure is etched is adjusted, and the etching is performed according to the incident angle to enlarge the opening of the first groove, including: adjusting an inclination angle of the semiconductor structure relative to a horizontal direction so that an angle of the plasma when the plasma is incident on the semiconductor structure between the upper electrode and the lower electrode is the incident angle; and etching the semiconductor structure according to the incident angle so as to enlarge the opening of the first groove.
In an embodiment of the present invention, the step of etching the semiconductor structure to enlarge the opening of the first groove according to the incident angle includes: and the plasma is incident according to the incident angle, and the semiconductor structure is rotated by taking a straight line positioned in the vertical direction as an axis and/or the lower electrode is rotated by taking a straight line positioned in the vertical direction as an axis so as to etch the semiconductor structure.
In an embodiment of the invention, an opening width of at least a part of an opening of the second groove is larger than an opening width of the first groove.
In an embodiment of the invention, a material of the first material layer and/or the second material layer includes silicon oxide.
In an embodiment of the invention, an aspect ratio of the trench is 1 to 4.
In an embodiment of the invention, after forming the second material layer filling the second groove, the planarizing the semiconductor device is further included.
In an embodiment of the present invention, the semiconductor device is a three-dimensional memory.
Another aspect of the present invention provides an etching apparatus of a semiconductor device, including: an upper electrode; a lower electrode oppositely arranged below the upper electrode; the bearing table is arranged between the upper electrode and the lower electrode and is used for bearing the semiconductor device; wherein the lower electrode is adapted to change the tilt angle relative to the horizontal direction and/or the carrier table is adapted to change the tilt angle relative to the horizontal direction.
In an embodiment of the invention, the susceptor and/or the lower electrode are further adapted to rotate about a straight line in a vertical direction.
Another aspect of the present invention provides a semiconductor device including: the dielectric layer is provided with a groove; a first material layer covering the dielectric layer, wherein the first material layer is provided with a groove in the groove; and a second material layer filling the recess; wherein the second material layer is obtained by the manufacturing method of the semiconductor device.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following remarkable advantages:
the manufacturing method of the semiconductor device of the invention conformally forms the first material layer on the dielectric layer with the groove, and correspondingly forms the first groove in the groove. And then, removing at least one part of the first material layer by utilizing plasma etching to enlarge the opening of the first groove so as to form a second groove. In the etching process, the plasma concentration of the top and/or the side wall of the first groove is greater than that of the bottom of the first groove, so that a denser filling part can be formed after the second material layer is filled in the second groove.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 to 3 are schematic process steps of a method for manufacturing a semiconductor device;
fig. 4 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 5 to 10 are schematic process steps of a method for manufacturing a semiconductor device according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
Fig. 1 to 3 are schematic process steps of a method for manufacturing a semiconductor device. Referring to fig. 1-3, one method is to etch the top of the trench to enlarge the opening by High Density Plasma Integrated Profile Modulation (HDP IPM) during PETEOS deposition. For example, semiconductor structure 100 of fig. 1 is formed after a preliminary Tetraethylorthosilicate (TEOS) source deposition has been performed on trench 101 in dielectric layer 110. A recess 102 corresponding to the trench 101 is formed in the first filling-up layer 120 thereof. Next, referring to fig. 2, the upper portion and the sidewall of the groove 102 may be etched to enlarge the opening degree of the groove 102. However, since the Bias Power (Bias Power) applied to the lower electrode by the high-density plasma is vertical and fixed, the silicon oxide at the bottom of the recess 102 is etched more during the flaring process, so that the opening degree of the upper portion of the etched recess 103 is enlarged and the depth thereof is also increased, which fails to achieve the purpose of reducing the aspect ratio of the recess 102, and in the subsequent Capping deposition process, after the second step of TEOS source filling, the second filling layer 130 thereof generates a gap 301 in the semiconductor structure 300 due to the high aspect ratio of the recess 103.
In view of the above problems, the following embodiments of the present invention provide a method for manufacturing a semiconductor device, which has a dense filling portion.
The manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a dielectric layer, and a groove is formed in the dielectric layer; forming a first material layer conformally on the dielectric layer, wherein the first material layer forms a first groove in the groove; adjusting an incident angle when the semiconductor structure is etched, and etching according to the incident angle to enlarge the opening of the first groove and form a second groove; and forming a second material layer filling the second groove.
Fig. 4 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. Fig. 5 to 10 are schematic process steps of a method for manufacturing a semiconductor device according to an embodiment of the invention. The manufacturing method will be described with reference to fig. 4 to 10.
It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
In step S10, a semiconductor structure 500 is provided, the semiconductor structure 500 includes a dielectric layer 510, and the dielectric layer 510 has a trench 501.
In an embodiment of the present invention, the semiconductor device may be a three-dimensional memory. Correspondingly, the manufacturing method of the semiconductor device is a manufacturing method of a three-dimensional memory (for example, 3D NAND).
Preferably, the semiconductor device of the present invention may also be referred to as a wafer.
In some embodiments, dielectric layer 510 may be deposited on a substrate (not shown). The material of the substrate may be, for example, silicon (Si). The substrate may also be made of other suitable materials including, but not limited to, polysilicon, silicon germanium, silicon-on-insulator (SOI), and the like.
Referring to fig. 5, the material of the dielectric layer 510 includes, but is not limited to, silicon oxide, silicon nitride, or a combination thereof. Taking dielectric layer 510 of silicon oxide as an example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods may be used to deposit silicon oxide on the substrate to form dielectric layer 510.
In some embodiments, the dielectric layer 510 may include an insulating layer (not shown) and a sacrificial layer (not shown) stacked on each other. The material of the insulating layer includes, but is not limited to, silicon oxide, and the material of the sacrificial layer includes, but is not limited to, silicon nitride. For example, the dielectric layer 510 having a multi-layer structure of SiOx-SiOxNx-SiOx stack (ONO stack) may be formed by alternately stacking insulating layers and sacrificial layers.
For example, for the semiconductor structure 500 having the dielectric layer 510, the trench 501 may be formed on the dielectric layer 510 by forming a patterned hard mask layer (not shown) on the dielectric layer 510 and then etching the semiconductor structure using the hard mask layer as a mask. The trench 501 may correspond to an opening in a patterned hard mask layer.
In some examples, the trench 501 of the semiconductor structure 500 may have a step structure therein, but the invention is not limited thereto.
In other examples, the Trench 501 may refer to a Trench in a Shallow Trench Isolation (STI) structure, or a Trench structure in a Top Select Gate (TSG) layer and a Bottom Select Gate (BSG) layer, and the like.
It is understood that the trench of the present invention is not limited to the trench 501 on the dielectric layer 510 shown in fig. 5, and any deep trench structure with high aspect ratio is within the spirit and scope of the present invention.
In an embodiment of the invention, the aspect ratio of the trench 501 may be 1 to 4, but the invention is not limited thereto.
In step S20, a first material layer 520 is conformally formed on the dielectric layer 510, and the first material layer 520 forms a first recess 502 in the trench 501.
Referring to fig. 5 and 6, a semiconductor structure 600 is formed overlying a semiconductor structure 500 overlying a first material layer 520.
In an embodiment of the present invention, the material of the first material layer 520 includes silicon oxide.
Illustratively, the first material layer 520 of silicon oxide material may be deposited on the dielectric layer 510 by Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDP-CVD), Atomic Layer Deposition (ALD), or any combination thereof.
In some examples, a process of depositing silicon oxide by a tetraethyl orthosilicate (TEOS) source or a plasma enhanced tetraethyl orthosilicate (PETEOS) source may be performed on the dielectric layer 510 directly by CVD, PECVD, LPCVD, or the like to form the first material layer 520.
Step S30, adjusting an incident angle when the semiconductor structure is etched, and etching according to the incident angle to enlarge the opening of the first groove 502, so as to form the second groove 503.
In an embodiment of the present invention, at least a portion of the upper portion of the second recess 503 has a width greater than a width of a corresponding portion of the first recess 502. The upper portion may refer to an opening of the groove.
Referring to fig. 6 and 9, the semiconductor structure 600 is expanded in width at the upper portion of the first groove 502 to form a second groove 503.
Illustratively, the semiconductor structure 600 may be dry etched to remove at least a portion of the first material layer 520. It is understood that dry etching mainly utilizes reactive gases and plasma to etch the etched material.
In an embodiment of the invention, the etching is plasma etching. The step of removing at least a portion of the first material layer 520 to enlarge the opening of the first recess 502 includes etching the first recess 502 using plasma, and the plasma concentration at the top and/or the sidewall of the first recess 502 is greater than the plasma concentration at the bottom of the first recess 502 during the etching.
In an embodiment of the present invention, the plasma may be emitted from the upper electrode above the semiconductor structure 600 to the lower electrode below the semiconductor structure, and the plasma concentration at the top and/or the sidewall of the first groove 502 may be made greater than the plasma concentration at the bottom of the first groove 502 by adjusting the angle at which the plasma is incident on the first groove 502.
The concentration of the plasma directly affects the rate of etching. Higher plasma concentrations have higher etch rates.
Preferably, in the following embodiments of the present invention, the plasma may be a high density plasma.
In some embodiments, the step of etching to enlarge the opening of the first groove 502 according to the incident angle includes: adjusting the inclination angle of the lower electrode relative to the horizontal direction so that the incident angle of the plasma incident on the semiconductor structure (e.g., semiconductor structure 600) between the upper electrode and the lower electrode is an incident angle; and etching the semiconductor structure (e.g., semiconductor structure 600) to enlarge the opening of the first recess 502 according to the angle of incidence.
In some embodiments, the step of etching to enlarge the opening of the first groove 502 according to the incident angle includes: adjusting an inclination angle of the semiconductor structure (e.g., semiconductor structure 600) with respect to a horizontal direction such that an angle at which the plasma is incident on the semiconductor structure (e.g., semiconductor structure 600) between the upper electrode and the lower electrode is an incident angle; and etching the semiconductor structure (e.g., semiconductor structure 600) to enlarge the opening of the first recess 502 according to the angle of incidence.
In some embodiments, the method of adjusting the angle at which the plasma is incident on the first recess 502 further comprises rotating the semiconductor structure (e.g., semiconductor structure 600) about a line in the vertical direction and/or rotating the lower electrode about a line in the vertical direction.
Preferably, the rotation axis of the semiconductor structure (e.g., semiconductor structure 600) and/or the lower electrode in the vertical direction may pass through the geometric center of the semiconductor structure and/or the lower electrode, respectively.
It should be noted that the incident direction of the plasma is affected by the action of the electric field between the upper electrode and the lower electrode, and is therefore always perpendicular to the extending direction of the lower electrode pad. In this way, by adjusting the tilt angle of the lower electrode with respect to the horizontal direction, the angle at which plasma is incident on the semiconductor structure (e.g., semiconductor structure 600) can be changed.
Since the first groove 502 is a three-dimensional structure, 360 degrees of etching is required to completely enlarge the opening degree of the first groove.
Illustratively, referring to fig. 7 and 8, the method of adjusting the angle of the plasma incident on the semiconductor structure 600 to achieve 360 degree etching of the top and/or sidewalls of the first recess 502 includes, but is not limited to, any of the following:
a. the lower electrode can rotate by taking two orthogonal straight lines positioned in the horizontal direction as an axis;
b. the lower electrode can rotate with a straight line in the horizontal direction as an axis, and the semiconductor structure (e.g., semiconductor structure 600) can rotate with a straight line in the vertical direction as an axis;
c. the lower electrode can rotate by taking a straight line in the horizontal direction as an axis, and can rotate by taking a straight line in the vertical direction as an axis;
d. the lower electrode and the semiconductor structure (e.g., semiconductor structure 600) can rotate about two orthogonal straight lines in the horizontal direction, respectively;
e. the lower electrode is fixed in the horizontal direction, the semiconductor structure (e.g., semiconductor structure 600) can rotate around a straight line in the horizontal direction, and the semiconductor structure (e.g., semiconductor structure 600) can rotate around a straight line in the vertical direction;
f. the lower electrode is fixed in the horizontal direction, and the semiconductor structure (for example, semiconductor structure 600) can rotate about two orthogonal straight lines located in the horizontal direction.
In the embodiment of the application, during the rotation of the semiconductor along the axis, plasma can be incident on the side wall at the opening of the first groove 502, so that the peripheral side wall (360 degrees) at the opening of the first groove 502 is etched, and the opening of the first groove is enlarged.
In some examples, the inclination angle of the semiconductor structure (e.g., the semiconductor structure 600) with respect to the horizontal direction and the angle of rotation of the semiconductor structure (e.g., the semiconductor structure 600) or the lower electrode about a straight line in the vertical direction may be achieved by adjusting a stage for carrying the semiconductor structure (e.g., the semiconductor structure 600). For example, the platform may have a function of adjusting its inclination angle with respect to the horizontal direction and its rotation.
For example, referring to fig. 7, when the lower electrode can rotate around a line in the horizontal direction, 360 degree etching of the top and/or the sidewall of the first groove 502 can be achieved by rotating the semiconductor structure (e.g., semiconductor structure 600) around a line in the vertical direction and/or rotating the lower electrode around a line in the vertical direction. And during the etching process, the plasma concentration at the top and/or the side wall of the first groove 502 is greater than that at the bottom of the first groove 502, so that the etching damage to the bottom of the first groove 502 is reduced.
Similarly, referring to fig. 8, when the lower electrode is fixed in the horizontal direction and the semiconductor structure (e.g., semiconductor structure 600) can be rotated about a line in the horizontal direction, 360 degree etching of the top and/or sidewalls of the first recess 502 can be achieved by rotating the semiconductor structure (e.g., semiconductor structure 600) about a line in the vertical direction. And during the etching process, the plasma concentration at the top and/or the side wall of the first groove 502 is greater than that at the bottom of the first groove 502, so that the etching damage to the bottom of the first groove 502 is reduced.
It can be understood that, in the actual manufacturing process of the semiconductor device, the incidence angle of the plasma can be obtained according to the semiconductor structure to be etched before etching is started, and the inclination angle of the lower electrode and/or the semiconductor structure relative to the horizontal direction can be adjusted according to the incidence angle. Specifically, when the etching machine is connected to the monitoring and adjusting device, the monitoring and adjusting device may select an inclination angle of the lower electrode pad and/or the susceptor with respect to the horizontal direction according to the currently placed semiconductor structure (e.g., the semiconductor structure 600), and instruct the etching machine to perform etching according to the angle. For example, the etching may be performed for 15 seconds after the lower electrode pad is rotated by an angle of 45 degrees about a straight line in the horizontal direction, and then the etching may be continued for 5 seconds by adjusting the angle to 30 degrees.
Preferably, the inclination angle of the lower electrode and/or the semiconductor structure with respect to the horizontal direction and the angle of the semiconductor structure and/or the lower electrode rotating around a straight line in the vertical direction as an axis may be adjusted according to the real-time etching condition while monitoring the etching condition during the etching process, but the invention is not limited thereto.
By providing a suitable tilt angle and/or corner, plasma may be focused primarily on the top and/or sidewalls of first recess 502 without significantly etching the bottom of first recess 502 during the process of removing at least a portion of first material layer 520 to enlarge the opening of first recess 502.
Preferably, in an ideal situation, the distance from the bottom of the second recess 503 to the bottom of the trench 501 should be equal to the distance from the bottom of the first recess 502 to the bottom of the trench 501. That is, the bottom of the first groove 502 is not significantly etched during the flaring process. The non-obvious etching may mean that the depth of the bottom of the first groove 502 etched in the flaring process is less than a set threshold, or that the ratio of the depth of the bottom of the first groove 502 etched in the flaring process to the depth before being etched is less than the set threshold.
Thus, through step S30, the second groove 503 is formed with an increased (average) width without a change in depth. The aspect ratio of the second groove 503 becomes smaller compared to the first groove 502. A smaller aspect ratio will facilitate the formation of dense void-free fills during subsequent filling.
Referring to fig. 7-9, in other embodiments of the present invention, the process of expanding the top opening of the first recess 502 may also make the depth of the second recess 503 shallower relative to the depth of the first recess 502. Thus, not only the depth of the second groove 503 is smaller than the depth of the first groove 502, but also the (average) width of the second groove 503 is larger than the width of the first groove 502. Therefore, the aspect ratio of the second groove 503 is significantly reduced compared to the first groove 502. A smaller aspect ratio will facilitate the formation of dense void-free fills during subsequent filling.
In step S40, a second material layer 530 filling the second recess 503 is formed.
Referring to fig. 10, a second material layer 530 is formed to fill the second recess 503 to form a semiconductor structure 1000.
In an embodiment of the present invention, the material of the second material layer 530 includes silicon oxide.
For example, the second material layer 530 of silicon oxide material filling the second groove 503 may be formed by Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDP-CVD), Atomic Layer Deposition (ALD), or any combination thereof.
Preferably, a process of depositing silicon oxide by using a tetraethyl orthosilicate (TEOS) source or a plasma enhanced tetraethyl orthosilicate (PETEOS) source is performed on the semiconductor structure 900 by CVD, PECVD, LPCVD, or the like to form the second material layer 530 filling the second recess 503. In some examples, the material of the first material layer 520 may be the same as the material of the second material layer 530.
Through the above steps, the second groove 503 with a smaller aspect ratio may be formed, such that the second material layer 530 completely conforms to/contacts the sidewall of the second groove 503 during the filling process using the second material layer 530. That is, the formed filled portion is dense without occurrence of a residual void.
The method for manufacturing a semiconductor device of the present invention separates the whole filling process into the first filling (i.e. forming the first material layer 520) of step S20 and the second filling (i.e. forming the second material layer 530) of step S40, and flares the groove (i.e. the first groove 502) formed after the first filling between the two fillings. By adjusting the incident angle of plasma in etching, the plasma concentration at the top and/or the side wall of the first groove 502 is increased, and the plasma concentration at the bottom of the first groove 502 is reduced by using the groove shadow effect, so that the plasma concentration at the top and/or the side wall of the first groove 502 is greater than the plasma concentration at the bottom of the first groove 502, and the purpose of adjusting the etching rate of the first groove 502 at different positions is achieved.
It should be understood that the method for fabricating the semiconductor structure of the present invention is not limited to the plasma etching described in fig. 4 to 10, and any process and method capable of achieving the enlarged opening are within the spirit and scope of the present invention, and those skilled in the art can make corresponding adjustments to the specific etching method according to actual needs, and the present invention is not limited thereto.
Thus, while the opening of the first groove 502 is enlarged or widened, the depth of the second groove 503 is not further increased, and the aspect ratio of the second groove 503 after flaring is effectively reduced, thereby avoiding the problem that a residual gap still exists in the filled part after filling, which is easily caused when the trench is directly filled once. Meanwhile, the etching uniformity in the manufacturing process of the semiconductor device is improved.
In an embodiment of the invention, after forming the second material layer 530 filling the second recess 503, the planarization of the semiconductor device (e.g., the semiconductor structure 1000) is further included.
The planarization may use a Chemical Mechanical Polishing (CMP) process. Chemical mechanical polishing is a technique combining chemical action and mechanical action, and can obtain a surface which is flat and free from scratches and contamination by impurities.
The planarized semiconductor device may be further processed to form a new semiconductor layer or a new semiconductor structure thereon, which is not developed.
It should be noted that the flowchart shown in fig. 4 is used herein to illustrate the steps/operations performed by the fabrication method according to the embodiments of the present application. It should be understood that these steps/operations are not necessarily performed in the exact order in which they are performed. Rather, various steps/operations may be processed in reverse order or concurrently. Meanwhile, other steps/operations may be added to or removed from these processes.
The priority of the specific operation steps of the manufacturing method can be appropriately adjusted according to the actual needs by those skilled in the art, and the present invention is not limited thereto.
The above embodiments of the present invention propose a method for manufacturing a semiconductor device, by which a semiconductor device having a dense filling portion is formed.
Another aspect of the present invention provides an etching apparatus for a semiconductor device, wherein the semiconductor device manufactured by the etching apparatus has a denser filling portion.
Referring to fig. 8, an etching apparatus for a semiconductor device according to the present invention includes an upper electrode (not shown), a lower electrode oppositely disposed below the upper electrode, and a susceptor disposed between the upper electrode and the lower electrode. Wherein, the bearing table is suitable for bearing the semiconductor device.
In an embodiment of the invention, the lower electrode is adapted to change the tilt angle with respect to the horizontal direction. The carrier is adapted to change the angle of inclination with respect to the horizontal.
In an embodiment of the invention, the susceptor and/or the lower electrode are further adapted to rotate about a vertical line.
In some examples, the tilt angle of the semiconductor structure (e.g., the semiconductor structure 600) with respect to the horizontal direction and the angle of rotation of the semiconductor structure (e.g., the semiconductor structure 600) or the lower electrode about a straight line in the vertical direction may be achieved by adjusting a stage for carrying the semiconductor structure (e.g., the semiconductor structure 600). For example, the platform may have a function of adjusting its inclination angle with respect to the horizontal direction and its rotation.
For example, referring to fig. 7 and 8, when the lower electrode can rotate around a line in the horizontal direction, 360 degrees of etching of the top and/or the sidewalls of the first recess 502 can be achieved by rotating the semiconductor structure (e.g., semiconductor structure 600) around a line in the vertical direction and/or rotating the lower electrode around a line in the vertical direction. And in the etching process, the plasma concentration at the top and/or the side wall of the first groove 502 is greater than that at the bottom of the first groove 502, so that the etching damage to the bottom of the first groove 502 is avoided. By adjusting the plate of the lower electrode, for example, rotating it around one or two axes in the horizontal direction, the tilt angle of the lower electrode with respect to the horizontal direction can be changed, and thus the angle at which the plasma is incident on the first grooves 502 can be changed, so that the plasma concentration at the tops and/or the sidewalls of the first grooves 502 is greater than the plasma concentration at the bottoms of the first grooves 502.
Similarly, referring to fig. 8, when the lower electrode is fixed in the horizontal direction and the semiconductor structure (e.g., semiconductor structure 600) can be rotated about a line in the horizontal direction, 360 degree etching of the top and/or sidewalls of the first recess 502 can be achieved by rotating the semiconductor structure (e.g., semiconductor structure 600) about a line in the vertical direction. And in the etching process, the plasma concentration at the top and/or the side wall of the first groove 502 is greater than that at the bottom of the first groove 502, so that the etching damage to the bottom of the first groove 502 is avoided being reduced.
By providing a suitable tilt angle and/or corner, plasma may be focused primarily on the top and/or sidewalls of first recess 502 without significantly etching the bottom of first recess 502 during the process of removing at least a portion of first material layer 520 to enlarge the opening of first recess 502.
Further implementation details of the etching apparatus for a semiconductor device of the present embodiment may refer to the embodiments described in fig. 4 to 10, and are not expanded herein.
The above embodiments of the present invention provide an etching apparatus for a semiconductor device, and the semiconductor device manufactured by the etching apparatus has a denser filling portion.
Another aspect of the present invention is to provide a semiconductor device having a denser filling portion.
Referring to fig. 10, a semiconductor device 1000 includes a dielectric layer 510, a first material layer 520 covering the dielectric layer 510, and a second material layer 530.
The dielectric layer 510 has a trench 501 thereon. A first material layer 520 overlies the dielectric layer 510, the first material layer 520 having a recess 503 in a corresponding trench 501. The second material layer 530 fills the recess 503. Wherein the second material layer 530 completely conforms to/contacts the sidewalls of the recess 503. That is, the filling portion is dense without occurrence of a residual void. In an embodiment of the present invention, the width of the top of the groove 503 may be greater than the width of the bottom of the groove 503.
In some examples, the trench 501 may further have a step region (step structure) therein, but the invention is not limited thereto.
In an embodiment of the present invention, the depth-to-width ratio of the trench 501 is 1 to 4.
In an embodiment of the present invention, the material of the first material layer 520 and/or the second material layer 530 includes silicon oxide.
For example, a process of depositing silicon oxide by using a Tetraethylorthosilicate (TEOS) source or a Plasma Enhanced Tetraethylorthosilicate (PETEOS) source may be performed on the dielectric layer 510 by CVD, PECVD, LPCVD, or the like to form the first material layer 520 covering the dielectric layer 510.
Similarly, a process of depositing silicon oxide by using a tetraethyl orthosilicate (TEOS) source or a plasma enhanced tetraethyl orthosilicate (PETEOS) source may be performed on the first material layer 520 by CVD, PECVD, LPCVD, or the like to form the second material layer 530 filling the recess 503 of the first material layer 520.
Preferably, the material of the first material layer 520 may be the same as the material of the second material layer 530.
In an embodiment of the present invention, the semiconductor device 1000 may be a three-dimensional memory (e.g., 3D NAND).
It should be noted that the semiconductor device 1000 shown in fig. 10 can be implemented according to, for example, the method for manufacturing the semiconductor device shown in fig. 4, but the invention is not limited thereto.
Further implementation details of the semiconductor device of the present embodiment may refer to the embodiments described in fig. 4 to 10, and are not expanded herein.
The above embodiments of the present invention propose a semiconductor device having a denser filling portion.
It should be noted that the number and size of the components are not limited in the present invention, and as in another embodiment of the present invention, the parallel mechanism of the present invention comprises more than two sets of the first connecting member, the second connecting member and the telescopic rod, any selection and adjustment of the number and size of the components to achieve the effect of free rotation and meet the actual production requirement is within the spirit and scope of the present invention.
It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims (12)

1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a dielectric layer, and a groove is formed in the dielectric layer;
forming a first material layer conformally on the dielectric layer, wherein the first material layer forms a first groove in the groove;
adjusting an incident angle when the semiconductor structure is etched, and etching according to the incident angle to enlarge the opening of the first groove and form a second groove; and
and forming a second material layer filling the second groove.
2. The method according to claim 1, wherein the etching is plasma etching, the plasma is emitted from an upper electrode above the semiconductor structure to a lower electrode below the semiconductor structure, an incident angle of the plasma during etching of the semiconductor structure is adjusted, and the etching is performed according to the incident angle to enlarge the opening of the first groove, and the step includes:
adjusting the inclination angle of the lower electrode relative to the horizontal direction so that the incident angle of the plasma incident on the semiconductor structure between the upper electrode and the lower electrode is the incident angle; and
and etching the semiconductor structure according to the incident angle so as to enlarge the opening of the first groove.
3. The method according to claim 1, wherein the etching is plasma etching, the plasma is emitted from an upper electrode above the semiconductor structure to a lower electrode below the semiconductor structure, an incident angle of the plasma during etching of the semiconductor structure is adjusted, and the etching is performed according to the incident angle to enlarge the opening of the first groove, and the step includes:
adjusting an inclination angle of the semiconductor structure relative to a horizontal direction so that an angle of the plasma when the plasma is incident on the semiconductor structure between the upper electrode and the lower electrode is the incident angle; and
and etching the semiconductor structure according to the incident angle so as to enlarge the opening of the first groove.
4. A manufacturing method according to claim 2 or 3, wherein the step of etching the semiconductor structure to enlarge the opening of the first groove according to the incident angle comprises:
and the plasma is incident according to the incident angle, and the semiconductor structure is rotated by taking a straight line positioned in the vertical direction as an axis and/or the lower electrode is rotated by taking a straight line positioned in the vertical direction as an axis so as to etch the semiconductor structure.
5. The production method according to any one of claims 1 to 3, wherein at least a part of an opening width at which the second groove opens is larger than an opening width of the first groove.
6. Method of manufacturing according to any of claims 1 to 3, characterized in that the material of the first material layer and/or the second material layer comprises silicon oxide.
7. The method of any one of claims 1 to 3, wherein the trench has an aspect ratio of 1 to 4.
8. The method of any one of claims 1 to 3, further comprising planarizing the semiconductor device after forming the second material layer filling the second recess.
9. The method of manufacturing according to any one of claims 1 to 3, wherein the semiconductor device is a three-dimensional memory.
10. An etching apparatus for a semiconductor device, comprising:
an upper electrode;
a lower electrode oppositely arranged below the upper electrode; and
the bearing table is arranged between the upper electrode and the lower electrode and is used for bearing the semiconductor device;
wherein the lower electrode is adapted to change the angle of inclination with respect to the horizontal direction, and/or,
the carrier is adapted to change the angle of inclination with respect to the horizontal.
11. Etching apparatus according to claim 10, wherein the susceptor and/or the lower electrode are further adapted to rotate about a line in a vertical direction.
12. A semiconductor device, comprising:
the dielectric layer is provided with a groove;
a first material layer covering the dielectric layer, wherein the first material layer is provided with a groove in the groove; and
a second material layer filling the groove;
wherein the semiconductor device is obtained by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.
CN202011301184.7A 2020-11-19 2020-11-19 Semiconductor device and method for manufacturing the same Pending CN112435957A (en)

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