WO2024006439A1 - Substrat radiofréquence à faible permittivité, son assemblage et son procédé de fabrication - Google Patents

Substrat radiofréquence à faible permittivité, son assemblage et son procédé de fabrication Download PDF

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Publication number
WO2024006439A1
WO2024006439A1 PCT/US2023/026579 US2023026579W WO2024006439A1 WO 2024006439 A1 WO2024006439 A1 WO 2024006439A1 US 2023026579 W US2023026579 W US 2023026579W WO 2024006439 A1 WO2024006439 A1 WO 2024006439A1
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WIPO (PCT)
Prior art keywords
substrate
coordinate system
dielectric material
monolithic structure
axis
Prior art date
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PCT/US2023/026579
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English (en)
Inventor
Trevor POLIDORE
Karl Edward Sprentall
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Rogers Corporation
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Publication of WO2024006439A1 publication Critical patent/WO2024006439A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/0287—Unidirectional or parallel fibers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072—Anchoring, i.e. one structure gripping into another
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/209—Auto-mechanical connection between a component and a PCB or between two PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the present disclosure relates generally to a low permittivity radio frequency substrate, an assembly of the same, and a method of making the same.
  • Substrates having a low permittivity, or low Dk (dielectric constant), are often preferred to be used in certain RF (radio frequency) radiating elements like patch antennas.
  • RF radio frequency
  • these antenna constructions as the Dk of the substrate decreases, a smaller portion of the electric field is confined and less energy is stored within the substrate, enabling higher radiation efficiency, wider bandwidth, and increased gain antennas.
  • foam materials cannot be metalized and/or imaged directly on the surface since they are porous, so other circuit materials must be laminated to the foam surface causing additional processing complications.
  • end users either have to overcome the challenges of constructing a low Dk substrate system or use a higher Dk laminate.
  • An embodiment includes a substrate, an assembly, and a method, as defined by the appended independent claims. Further advantageous modifications of the substrate, assembly, and method, are defined by the appended dependent claims.
  • An embodiment includes a substrate having: a monolithic structure formed from a dielectric material having a first side, a second side, and an intermediate region between the first side and the second side; wherein the intermediate region has a lattice structure of the dielectric material having a plurality of interstitial spaces between the dielectric material of the lattice structure; wherein the lattice structure extends between and monolithically connects with the first side and the second side; wherein at least one of the first side and the second side has a substantially solid surface suitably configured to support one or more of: electronic circuit imaging; electroplating; metal deposition; or, vias between the first side and the second side.
  • An embodiment includes a multi-layer assembly having two or more of the aforementioned substrate, wherein each of the substrate is mechanically attached, adhesively bonded, or fusion bonded, to an adjacent one of the substrate.
  • An embodiment includes a method of making the aforementioned substrate having the aforementioned monolithic structure wherein the method includes: in a continuous process, forming the first side of the substrate; via the continuous process, forming the intermediate region of the substrate on and monolithic with the first side, the intermediate region having the lattice stmcture of the dielectric material comprising the plurality of interstitial spaces between the dielectric material of the lattice structure; and via the continuous process, forming the second side of the substrate on and monolithic with the intermediate region.
  • FIG. 1 A depicts a rotated isometric view of a substrate, in accordance with an embodiment
  • FIG. IB depicts a plan view of example generic electronic circuitry representative of being suitable for use with the substrate of FIG. 1, in accordance with an embodiment
  • FIG. 2A depicts a cross section view of the substrate of FIG. 1A, in accordance with an embodiment
  • FIG. 2B depicts an alternative cross section view to that of FIG. 2A, in accordance with an embodiment
  • FIG. 3 A depicts a rotated isometric view of an enlarged portion of the substrate of FIG. 1A depicting a surface-based lattice structure, in accordance with an embodiment
  • FIG. 3B depicts the rotated isometric view of FIG. 3A depicting ceramic fibers, in accordance with an embodiment
  • FIG. 4A depicts a cross section view of a disassembled multi-layer assembly of the substrate of FIG. 1 A, in accordance with an embodiment
  • FIG. 4B depicts a cross section view of a multi-layer assembly having mechanically attached adjacent substrates, and an enlarged portion thereof, in accordance with an embodiment
  • FIG. 4C depicts a cross section view similar to that of FIG. 4B but with adhesively bonded adjacent substrates, in accordance with an embodiment
  • FIG. 4D depicts a cross section view similar to that of FIG. 4B but with fusion bonded adjacent substrates, in accordance with an embodiment.
  • An embodiment as shown and described by the various figures and accompanying text, provides a 3D-printable, or other additive manufacturing processes, substrate that uses a lattice structure to impart a low permittivity dielectric while also being configured to provide one or more substantially solid surfaces on either or both sides of the substrate for electrical circuit imaging, and to provide for inclusion of one or more vias in- situ. While an embodiment described and illustrated herein depicts a gyroid lattice structure as an example structure for the substrate disclosed herein, it will be appreciated that an invention disclosed herein and in accordance with the appended claims is not so limited, as other lattice structures as described herein may also be applicable for a purpose disclosed herein.
  • monolithic means a structure integrally formed from a single material composition and/or process absent material discontinuities from one region of the structure to another, such as a structure produced from a plastic molding process, a 3D printing process, a deposition process, or a machined process, for example.
  • an embodiment includes a 3D printable substrate that uses a lattice structure to impart low permittivity while designed to have solid surfaces for circuit imaging and the ability to create vias in-situ.
  • the substrate may comprise a 3D lattice of printed dielectric material with a solid printed film on one or both sides.
  • vias can be printed directly within the substrate by creating a solid cylindrical wall within the lattice that opens on both ends of the substrate. Printing a solid film on both sides may be employed when using ground planes or capacitively coupled patch elements within one part, but single (or double-sided) parts can be incorporated into other structures.
  • the printed lattice may operate as a single dielectric medium since the features are much smaller than a fraction of the operating wavelength and can typically be lower than a few hundred microns.
  • the lattice structure may be a gyroid lattice, with good mechanical stability and even density distribution within a cell.
  • Some advantages of an embodiment disclosed herein may include one or more of the following: a mechanically robust, low permittivity substrate, with solid, non-porous surfaces; integrally formed via structures to connect elements on either side of the substrate; a single monolithic structure, with better alignment, and lower Dk; no additional lamination processes needed; and, lower permittivity than other copper-clad laminates.
  • FIGS. 1 A, IB, 2A, 2B, 3A, and 3B in combination.
  • a substrate 100 includes a monolithic structure 102 formed from a dielectric material having a first side 200, a second side 300, and an intermediate region 400 between the first side 200 and the second side 300.
  • the intermediate region 400 has a lattice structure 403 of the dielectric material that has a plurality of interstitial spaces 402 (best seen with reference to FIG. 3A) between the dielectric material of the lattice structure 403, wherein the lattice structure 403 extends between and monolithically connects with the first side 200 and the second side 300.
  • At least one of the first side 200 and the second side 300 includes a substantially solid surface 202, 302 suitably configured to support one or more of: electronic circuit imaging; electroplating; metal deposition (collectively herein referred to by reference numeral 250); or, vias 140 between the first side 200 and the second side 300.
  • the interstitial spaces 402 are fully or at least partially formed of air.
  • the monolithic structure 102 is not formed of a foam and/or is not a laminate structure.
  • laminate structure means a structure having separate and discrete layers that are fixed together to form a hard, flat, or flexible material.
  • the lattice structure 403 is a gyroid lattice structure, but may be any other surface-based lattice structure, as opposed to a strut-based lattice structure.
  • the lattice structure 403 of the intermediate region 400 has a uniform distribution of the dielectric material and the interstitial spaces 402.
  • both the first side 200 and the second side 300 have substantially solid surfaces 202, 302 (best seen with reference to FIG. 2A) suitably configured to support one or more of: electronic circuit imaging; electroplating; metal deposition 250 (best seen with reference to FIG. IB); or, vias 104 (best seen with reference to FIG. 3A) between the first side 200 and the second side 300.
  • the monolithic structure 102 of the substrate 100 includes one or more vias 104 that extend between the first side 200 and the second side 300 (best seen with reference to FIG. 3).
  • the one or more vias 104 have an electrically conductive (interior) surface that extends between the first side 200 and the second side 300 of the monolithic structure 102 that serves to provide at least one electrical conduction path between the first side 200 and the second side 300.
  • the first side 200, the second side 300, or both the first side 200 and the second side 300, of the monolithic structure 102 has a metallized surface to which the electrically conductive vias 104 are in electrical contact with.
  • the electrically conductive vias 104 and the metallized surfaces of the first and second sides 200, 300 are metallized together with the same metallizing process, such as metal vapor deposition for example.
  • the dielectric material of the monolithic structure 102 of the substrate 100 has a relative dielectric constant equal to or greater than 1.01 and equal to or less than 5, or alternatively has a relative dielectric constant equal to or greater than 1. 1 and equal to or less than 4.5.
  • the monolithic structure 102 of the substrate 100 is formed relative to an orthogonal x-y-z coordinate system where the z-axis is perpendicular to both the first side 200 and the second side 300
  • the dielectric material includes: ceramic fibers 150 that are substantially aligned with an x-y plane of the x-y-z coordinate system; ceramic fibers 160 substantially aligned with a z-axis of the x-y-z coordinate system; or, both ceramic fibers 150 substantially aligned with an x-y plane of the x-y-z coordinate system, and ceramic fibers 160 substantially aligned with a z-axis of the x-y-z coordinate system (best seen with reference to FIG. 3B). While FIG.
  • the first side 200 of the substrate 100 is planar
  • the second side 300 of the substrate 100 is planar
  • the second side 300 is parallel with the first side 200 (best seen with reference to FIGS. 1 and 2 A).
  • first side 200 of the substrate 100 is disposed equidistant at a distance “T” with respect to the second side 300 of the substrate 100, and in an embodiment, the first side 200 of the substrate 100 and the second side 300 of the substrate 100 are curved (best seen with reference to FIG. 2B).
  • the monolithic structure 102 of the substrate 100 is formed relative to an orthogonal x-y-z coordinate system where the z-axis is perpendicular to both the first side 200 and the second side 300, and the substrate 100 is operational at a defined center frequency f having an operational wavelength X, and the overall thickness of the substrate 100 in the z-direction is equal to or less than X/2, or alternatively equal to or less than X/4.
  • the defined center frequency is 4.9GHz
  • the z- directional thickness of the substrate is 4.0mm.
  • FIGS. 4 A, 4B, 4C, and 4D in combination with FIGS. 1, 2A, 2B, 3 A, and 3B.
  • a multi-layer assembly 500 includes two or more of the substrate 100 described herein above and illustrated in FIGS. 1, 2A, 2B, 3A, and 3B (individually referred to by reference numerals 100.1, 100.2, etc., in FIGS. 4A 4B, 4C, and 4D), with multiple (i.e., two or more) substrates 100 being denoted by ellipses 502 in FIG. 4A.
  • one substrate 100.1 is mechanically attached to another adjacent substrate 100.2 via a mechanical attachment construct 504, such as interlocking elastically deformable projections 510 on each substrate, 100.1, 100.2, that are arranged in a one-to-one registration with corresponding elastically deformable recesses 515 on an adjacent one of each substrate, 100.1, 100.2, for example.
  • each substrate 100.1, 100.2 has one or more mechanical registration features 510, 515 that mechanically attach and interlock with corresponding ones of mechanical registration features 515, 510 of an adjacent one of the substrate 100.1, 100.2.
  • the one or more mechanical registration features 510, 515 and corresponding ones of the mechanical registration features 515, 510 have an elastically deformable interference fit therebetween.
  • the elastically deformable projections 510 are completely or at least partially insertable within a corresponding one of the elastically deformable recesses 515.
  • one substrate 100. 1 is fusion bonded to another adjacent substrate 100.2 via a fusion bond interface 508.
  • the multi-layer assembly 500 is configured such that each monolithic structure 102 is formed relative to an orthogonal x-y-z coordinate system where the z-axis is perpendicular to both the first side 200 and the second side 300, wherein the multi-layer assembly 500 is operational at a defined frequency f having an operational wavelength , and wherein the overall thickness of the multi-layer assembly 500 in the z- direction is equal to or less than k/2, or alternatively is equal to or less than k/4.
  • a method of making the substrate 100 having the monolithic structure 102 as disclosed and illustrated herein includes: in a continuous process, forming the first side 200 of the substrate 100; via the continuous process, forming the intermediate region 400 of the substrate 100 on and monolithic with the first side 100, the intermediate region 400 having the lattice structure 403 of the dielectric material having the plurality of interstitial spaces 402 between the dielectric material of the lattice structure 403; and, via the continuous process, forming the second side 300 of the substrate 100 on and monolithic with the intermediate region 400.
  • the continuous process further includes forming one or more vias 104 that extend from the first side 200, through the intermediate region 400, to the second side 300.
  • the method further includes imaging or metallizing electronic circuitry 250 on at least one of the first side 200 and the second side 300 to provide the electronic circuit imaging.
  • FIG. IB depicts a portion of generic electronic circuitry 250 having a plurality of electrically conductive trace lines 252, and a plurality of electrically conductive vias 104 (same reference numeral used for vias 104 depicted in FIG. 3 A, as they would be electrically connected with each other), which may be employed in a manner disclosed herein.
  • the method of making the substrate 100 includes forming the monolithic structure 102 relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side 200 and the second side 300, wherein via the continuous process the method further includes forming within the dielectric material ceramic fibers 150 that are: substantially aligned with an x-y plane of the x-y-z coordinate system; substantially aligned with a z-axis of the x-y-z coordinate system; or, substantially aligned with an x-y plane of the x-y-z coordinate system, and substantially aligned with a z-axis of the x-y-z coordinate system.
  • the continuous process involved in the method of making the substrate 100 includes any one of: 3D printing; stereolithography; light-based additive manufacturing; or, digital light processing with crosslinking of the dielectric material.
  • a substrate comprising: a monolithic structure formed from a dielectric material having a first side, a second side, and an intermediate region between the first side and the second side; wherein the intermediate region comprises a lattice structure of the dielectric material comprising a plurality of interstitial spaces between the dielectric material of the lattice structure; wherein the lattice structure extends between and monolithically connects with the first side and the second side; wherein at least one of the first side and the second side comprises a substantially solid surface suitably configured to support one or more of: electronic circuit imaging; electroplating; metal deposition; or, vias between the first side and the second side.
  • Aspect 2 The substrate of Aspect 1, wherein: the interstitial spaces comprise air.
  • Aspect 3 The substrate of any one of Aspects 1 to 2, wherein: the monolithic structure is not a foam material.
  • Aspect 4 The substrate of any one of Aspects 1 to 3, wherein: the monolithic structure is not a laminate structure.
  • Aspect 5 The substrate of any one of Aspects 1 to 4, wherein: both the first side and the second side comprise substantially solid surfaces suitably configured to support one or more of: electronic circuit imaging; electroplating; metal deposition; or, vias between the first side and the second side.
  • Aspect 6 The substrate of any one of Aspects 1 to 5, wherein: the dielectric material of the monolithic structure has a relative dielectric constant equal to or greater than 1.01 and equal to or less than 5.
  • Aspect 7 The substrate of Aspect 6, wherein: the dielectric material of the monolithic structure has a relative dielectric constant equal to or greater than 1.1 and equal to or less than 4.5.
  • Aspect 8 The substrate of any one of Aspects 1 to 7, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side; and, the dielectric material comprises ceramic fibers substantially aligned with an x-y plane of the x-y-z coordinate system.
  • Aspect 9 The substrate of any one of Aspects 1 to 7, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side; and, the dielectric material comprises ceramic fibers substantially aligned with a z-axis of the x-y-z coordinate system.
  • Aspect 10 The substrate of any one of Aspects 1 to 7, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side; the dielectric material comprises ceramic fibers substantially aligned with an x-y plane of the x-y-z coordinate system; and, the dielectric material comprises ceramic fibers substantially aligned with a z- axis of the x-y-z coordinate system.
  • Aspect 11 The substrate of any one of Aspects 1 to 10, wherein: the monolithic structure comprises one or more vias that extend between the first side and the second side.
  • Aspect 12 The substrate of Aspect 11, wherein: the one or more vias comprise an electrically conductive surface between the first side and the second side of the monolithic structure.
  • Aspect 13 The substrate of any one of Aspects 1 to 12, wherein: the lattice structure comprises a gyroid lattice structure.
  • Aspect 14 The substrate of any one of Aspects 1 to 13, further comprising: a metallized layer on the first side, the second side, or both the first side and the second side of the monolithic structure.
  • Aspect 15 The substrate of Aspect 14, further comprising the vias, wherein: the vias comprise an electrically conductive surface between the first side and the second side of the monolithic structure that are in electrical connection with the metallized layer of the first side, the second side, or both the first side and the second side.
  • Aspect 16 The substrate of any one of Aspects 1 to 15, wherein: the lattice structure is a surface-based lattice structure and not a strut-based lattice structure.
  • Aspect 17 The substrate of any one of Aspects 1 to 16, wherein: the lattice structure of the intermediate region has a uniform distribution of the dielectric material and the interstitial spaces.
  • Aspect 18 The substrate of any one of Aspects 1 to 17, wherein: the first side is planar, the second side is planar, and the second side is parallel with the first side.
  • Aspect 19 The substrate of any one of Aspects 1 to 17, wherein: the first side is disposed equidistant with respect to the second side.
  • Aspect 20 The substrate of Aspect 19, wherein: the first side and the second side are curved.
  • Aspect 21 The substrate of any one of Aspects 1 to 20, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side; and, the substrate is operational at a defined frequency f having an operational wavelength X, and the overall thickness of the substrate in the z-direction is equal to or less than X/2.
  • Aspect 22 The substrate of Aspect 21, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z-axis is perpendicular to both the first side and the second side; and, the substrate is operational at a defined frequency f having an operational wavelength I, and the overall thickness of the substrate in the z-direction is equal to or less than X/4.
  • Aspect 23 A multi-layer assembly, comprising: two or more of the substrate of any one of Aspects 1 to 22; wherein each of the substrate is mechanically attached, adhesively bonded, or fusion bonded, to an adjacent one of the substrate.
  • Aspect 24 The assembly of Aspect 23, wherein: each of the substrate comprises one or more mechanical registration features to mechanically attach and interlock with corresponding ones of mechanical registration features of an adjacent one of the substrate.
  • Aspect 25 The assembly of Aspect 24, wherein: the one or more mechanical registration features and the corresponding ones of mechanical registration features comprise an elastically deformable interference fit therebetween.
  • Aspect 26 The assembly of any one of Aspects 23 to 25, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side; and, the assembly is operational at a defined frequency f having an operational wavelength X, and the overall thickness of the assembly in the z-direction is equal to or less than X/2.
  • Aspect 27 The assembly of any one of Aspects 23 to 25, wherein: the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side; and, the assembly is operational at a defined frequency f having an operational wavelength X, and the overall thickness of the assembly in the z-direction is equal to or less than X/4.
  • Aspect 28 A method of making the substrate having the monolithic structure of any one of Aspects 1 to 22, the method comprising: in a continuous process, forming the first side of the substrate; via the continuous process, forming the intermediate region of the substrate on and monolithic with the first side, the intermediate region having the lattice structure of the dielectric material comprising the plurality of interstitial spaces between the dielectric material of the lattice structure; and, via the continuous process, forming the second side of the substrate on and monolithic with the intermediate region.
  • Aspect 29 The method of Aspect 28, wherein: the continuous process further includes forming one or more vias that extend from the first side, through the intermediate region, to the second side.
  • Aspect 30 The method of any one of Aspects 28 to 29, further comprising: imaging electronic circuitry on at least one of the first side and the second side to provide the electronic circuit imaging.
  • Aspect 31 The method of any one of Aspects 28 to 29, further comprising: metallizing electronic circuitry on at least one of the first side and the second side to provide the electronic circuit imaging.
  • Aspect 32 The method of any one of Aspects 28 to 31, wherein the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side, the method further comprising: via the continuous process, forming within the dielectric material ceramic fibers that are substantially aligned with an x-y plane of the x-y-z coordinate system.
  • Aspect 33 The method of any one of Aspects 28 to 31, wherein the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side, the method further comprising: via the continuous process, forming within the dielectric material ceramic fibers that are substantially aligned with a z-axis of the x-y-z coordinate system.
  • Aspect 34 The method of any one of Aspects 28 to 31, wherein the monolithic structure is formed relative to an orthogonal x-y-z coordinate system where the z- axis is perpendicular to both the first side and the second side, the method further comprising: via the continuous process, forming within the dielectric material ceramic fibers that are substantially aligned with an x-y plane of the x-y-z coordinate system; and, via the continuous process, forming within the dielectric material ceramic fibers that are substantially aligned with a z-axis of the x-y-z coordinate system.
  • Aspect 35 The method of any one of Aspects 28 to 34, wherein: the continuous process comprises any one of: 3D printing; stereolithography; light-based additive manufacturing; or, digital light processing with crosslinking of the dielectric material.

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Abstract

La présente invention concerne un substrat qui comprend une structure monolithique constituée d'un matériau diélectrique ayant une première face, une seconde face et une région intermédiaire située entre la première face et la seconde face, et la région intermédiaire ayant une structure en treillis séparée du matériau diélectrique par une pluralité d'espaces interstitiels. La structure en treillis s'étend entre la première face et la seconde face et les relie de manière monolithique, la première face et/ou la seconde face ayant une surface sensiblement solide conçue de manière à supporter un ou plusieurs procédés tels que l'imagerie de circuits électroniques, le dépôt électrolytique, le dépôt de métal ou encore des trous d'interconnexion entre la première face et la seconde face.
PCT/US2023/026579 2022-06-30 2023-06-29 Substrat radiofréquence à faible permittivité, son assemblage et son procédé de fabrication WO2024006439A1 (fr)

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US202263357386P 2022-06-30 2022-06-30
US63/357,386 2022-06-30
US202318215570A 2023-06-28 2023-06-28
US18/215,570 2023-06-28

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020655A1 (en) * 2001-07-26 2003-01-30 Mckinzie William E. Reduced weight artificial dielectric antennas and method for providing the same
US20040257279A1 (en) * 2003-06-19 2004-12-23 Dennis Tebbe Dielectric substrate with selectively controlled effective permittivity and loss tangent
US20080052904A1 (en) * 2004-07-28 2008-03-06 Reinhard Schneider Method Of Manufacturing An Electronic Circuit Assembly
US20090072930A1 (en) * 2004-03-04 2009-03-19 Achyut Kumar Dutta High speed electronics interconnect and method of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020655A1 (en) * 2001-07-26 2003-01-30 Mckinzie William E. Reduced weight artificial dielectric antennas and method for providing the same
US20040257279A1 (en) * 2003-06-19 2004-12-23 Dennis Tebbe Dielectric substrate with selectively controlled effective permittivity and loss tangent
US20090072930A1 (en) * 2004-03-04 2009-03-19 Achyut Kumar Dutta High speed electronics interconnect and method of manufacture
US20080052904A1 (en) * 2004-07-28 2008-03-06 Reinhard Schneider Method Of Manufacturing An Electronic Circuit Assembly

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