WO2024000794A1 - 显示面板及显示终端 - Google Patents

显示面板及显示终端 Download PDF

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Publication number
WO2024000794A1
WO2024000794A1 PCT/CN2022/116194 CN2022116194W WO2024000794A1 WO 2024000794 A1 WO2024000794 A1 WO 2024000794A1 CN 2022116194 W CN2022116194 W CN 2022116194W WO 2024000794 A1 WO2024000794 A1 WO 2024000794A1
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WO
WIPO (PCT)
Prior art keywords
signal
trace
metal layer
fan
out area
Prior art date
Application number
PCT/CN2022/116194
Other languages
English (en)
French (fr)
Inventor
郑颖
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2024000794A1 publication Critical patent/WO2024000794A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display terminal.
  • Embodiments of the present application provide a display panel and a display terminal, which are used to reduce the lower frame of the display panel and increase the screen-to-body ratio of the display area.
  • An embodiment of the present application discloses a display panel.
  • the display panel includes a display area, a fan-out area and a bending area.
  • the fan-out area is located between the display area and the bending area.
  • the display panel includes:
  • a plurality of data lines are provided on the substrate, and the data lines are located in the display area;
  • a plurality of first signal traces are located in the fan-out area, and one first signal trace is connected to one of the data lines;
  • a plurality of second signal traces are located in the fan-out area, and one second signal trace is connected to one of the data lines;
  • a plurality of third signal traces are located in the fan-out area, and one third signal trace is connected to one of the data lines;
  • a plurality of fourth signal traces are located in the fan-out area, and one fourth signal trace is connected to one of the data lines;
  • the first signal trace, the second signal trace, the third signal trace and the fourth signal trace are arranged in different layers.
  • the fan-out area includes a first fan-out area and a second fan-out area, and the first fan-out area is located on both sides of the second fan-out area.
  • a plurality of the first signal traces and a plurality of the second signal traces extend from the first fan-out area to the second fan-out area;
  • the plurality of third signal traces and the plurality of fourth signal traces are located in the second fan-out area and are arranged along the first direction.
  • a first signal trace includes a first trace segment and a second trace segment, and part of the first trace segment is located in the first fan-out area, The second wiring segment is located in the second fan-out area, and the second wiring segment extends along the first direction.
  • a second signal trace includes a third trace segment and a fourth trace segment, and part of the third trace segment is located in the first fan-out area, The fourth wiring segment is located in the second fan-out area, and the fourth wiring segment extends along the first direction.
  • the second wiring segments and the fourth wiring segments are arranged in sequence.
  • the second wiring segment is provided between a plurality of the third signal wiring lines and the fourth signal wiring lines, and between two adjacent third signal wiring lines and the fourth signal wiring lines. , one of the fourth wiring segments.
  • the display area includes a first side, a second side and a third side, and the first side and the second side pass through the A third side is connected, the third side is arc-shaped, and the data line of the display area corresponding to the third side is connected to the first signal trace and the second signal trace;
  • the extending direction of the first wiring segment and the third wiring segment is the same as the extending direction of the third side.
  • the plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines, and the plurality of first-type data lines are located on multiple On both sides of the second type data line, a plurality of the first type data lines correspond to the third side, a part of the first type data line is connected to the first signal line, and the other part of the first type data line is connected to the first signal line. A type of data line is connected to the second signal line.
  • the first signal line and the second signal line are alternately connected to the first type of data line.
  • the third signal line and the fourth signal line are alternately connected to the second type of data line.
  • the display panel further includes:
  • a shielding metal layer is provided on the substrate, and the first signal trace is located on the shielding metal layer;
  • a first metal layer is provided on the side of the shielding metal layer away from the substrate and is insulated from the shielding metal layer, and the third signal trace is located on the first metal layer;
  • a second metal layer is provided on the side of the first metal layer away from the substrate and is insulated from the first metal layer, and the fourth signal wiring is located on the second metal layer;
  • a third metal layer is provided on a side of the second metal layer away from the first metal layer and is insulated from the second metal layer.
  • the second signal wiring is located on the third metal layer.
  • the fan-out area includes a first fan-out area and a second fan-out area, and the first fan-out area is located on both sides of the second fan-out area.
  • a plurality of the first signal traces, a plurality of the second signal traces and a plurality of the third signal traces extend from the first fan-out area to the second fan-out area;
  • a plurality of fourth signal traces are located in the second fan-out area and arranged along the first direction.
  • a first signal line, a second signal line and a third signal line are alternately arranged.
  • a first signal trace includes a connected first trace segment and a second trace segment, and a said second signal trace includes a connected third trace segment. and a fourth trace segment, the third signal trace includes a connected fifth trace segment and a sixth trace segment;
  • the first trace segment, the third trace segment and the fifth trace segment extend from the first fan-out area to the second fan-out area, the second trace segment, the fourth trace segment and The sixth trace segment is located in the second fan-out area, and the second trace segment, the fourth trace segment, and the sixth trace segment extend along the first direction.
  • the second trace segment, the fourth trace segment and the third trace segment are Six trace segments are arranged in sequence between the plurality of fourth signal traces, and the second trace segment, the fourth trace segment and all the second trace segments are arranged between two adjacent fourth signal traces.
  • One of the sixth routing segments are Six trace segments.
  • the display panel further includes:
  • a shielding metal layer is provided on the substrate, and the fourth signal trace is located on the shielding metal layer;
  • a first metal layer is provided on the side of the shielding metal layer away from the substrate and is insulated from the shielding metal layer, and the second signal wiring is located on the first metal layer;
  • a second metal layer is provided on the side of the first metal layer away from the substrate and is insulated from the first metal layer, and the third signal wiring is located on the second metal layer;
  • a third metal layer is provided on a side of the second metal layer away from the first metal layer and is insulated from the second metal layer.
  • the first signal wiring is located on the third metal layer.
  • the display panel further includes a first active layer and a second active layer, and the first active layer is disposed on the shielding metal layer away from the substrate.
  • the second active layer is provided on one side of the second metal layer away from the first metal layer and is insulated from the second metal layer;
  • the first active layer is a low-temperature polysilicon active layer
  • the second active layer is a metal oxide active layer.
  • the shielding metal layer further includes shielding metal lines, and the shielding metal lines are located in the display area.
  • the display panel further includes a fourth metal layer, which is disposed on a side of the third metal layer away from the second metal layer, and the data line is located on the side of the third metal layer away from the second metal layer.
  • the fourth metal layer is disposed on a side of the third metal layer away from the second metal layer, and the data line is located on the side of the third metal layer away from the second metal layer.
  • the height of the second fan-out area in the first direction is less than or equal to 600 microns.
  • an embodiment of the present application also provides a display terminal, which includes the above-mentioned display panel and a casing, and the display panel is disposed in the casing.
  • Embodiments of the present application provide a display panel and a display terminal.
  • the display panel includes a display area, a fan-out area and a bending area.
  • the fan-out area is located between the display area and the bend area.
  • the display panel includes a substrate, a plurality of data lines, a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines and a plurality of fourth signal lines located in the fan-out area.
  • a plurality of data lines are arranged on the substrate, and the data lines are located in the display area.
  • a first signal line is connected to a data line.
  • a second signal line is connected to a data line.
  • a third signal line is connected to a data line.
  • a fourth signal line is connected to a data line.
  • the first signal trace, the second signal trace, the third signal trace and the fourth signal trace are arranged in different layers.
  • the number of signal traces provided in the same film layer can be reduced.
  • the display panel of this embodiment can be reduced in size.
  • the area occupied by the fan-out area can reduce the lower border of the display panel and increase the screen-to-body ratio of the display area.
  • Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a first schematic plan view of a display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic cross-sectional structural view of the fan-out area taken along the A-A direction of Figure 2;
  • Figure 4 is a schematic cross-sectional structural view of the display area taken along the B-B direction of Figure 2;
  • Figure 5 is a second schematic plan view of a display panel provided by an embodiment of the present application.
  • Figure 6 is a schematic cross-sectional structural diagram of the fan-out area taken along the C-C direction of Figure 5;
  • FIG. 7 is a schematic plan view of a display terminal provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • An embodiment of the present application provides a splicing display panel. Each is explained in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.
  • FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • the left and right borders and the top border of the display panel in the known technology can be made very narrow (for example, the width is less than 1 mm).
  • the bending radius a of the bending area BA of the lower frame of the display panel and the fit of the backplane during bending The precision and routing of the traces in the fan-out area will cause the bottom bezel to be too wide, which is not conducive to the development of narrow bezels.
  • the inventor found through research that the reason for the above problem is that the lower frame of the display panel is usually designed with relatively dense wiring, making the structure of the lower frame more complex than other frames.
  • Known routing methods usually use diagonal wiring.
  • connection lines drawn from the bending area BA are diagonally routed in the fan-out area FA to connect the data lines of the display area AA.
  • the display area AA there are usually many data lines.
  • the number of data lines also increases rapidly. For example, at 1080*2340 resolution, there are 2160 data lines.
  • the width of the lower frame needs to be enlarged, that is, the b value will be very large (more than 1 mm), which is not conducive to achieving a narrow lower frame.
  • An embodiment of the present application provides a display panel, which includes a display area, a fan-out area, and a bending area.
  • the fan-out area is located between the display area and the bend area.
  • the display panel includes a substrate, a plurality of data lines, a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines and a plurality of fourth signal lines located in the fan-out area.
  • a plurality of data lines are arranged on the substrate, and the data lines are located in the display area.
  • a first signal line is connected to a data line.
  • a second signal line is connected to a data line.
  • a plurality of third signal lines are connected to a data line.
  • a fourth signal line is connected to a data line.
  • the first signal trace, the second signal trace, the third signal trace and the fourth signal trace are arranged in different layers.
  • the number of signal traces provided in the same film layer can be reduced.
  • the display panel of this embodiment The area occupied by the fan-out area can be reduced, thereby reducing the lower frame of the display panel and increasing the screen-to-body ratio of the display area.
  • FIG. 2 is a first plan view of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structural view of the fan-out area taken along the A-A direction of FIG. 2 .
  • FIG. 4 is a schematic cross-sectional structural view of the display area taken along the B-B direction of FIG. 2 .
  • An embodiment of the present application provides a display panel.
  • the display panel 100 includes a display area AA, a fan-out area FA and a bending area BA.
  • the fan-out area FA is located between the display area AA and the bending area BA.
  • the fan-out area FA includes a third A fan-out area FA1 and a second fan-out area FA2.
  • the first fan-out area FA1 is located on both sides of the second fan-out area FA2.
  • the second fan-out area FA2 is a rectangular area, and one side of the rectangular area is the display On the lower frame of the panel 100, the first fan-out area FA1 is the area in the fan-out area FA except the second fan-out area FA2.
  • the display panel 100 includes a substrate 10 , a plurality of data lines 101 , a plurality of first signal traces 103 , a plurality of second signal traces 104 , a plurality of third signal traces 105 and a plurality of fourth signal traces 106 .
  • the data line 101 is provided on the substrate 10, and the data line 101 is located in the display area AA.
  • the plurality of data lines 101 extend along the first direction X and are arranged along the second direction Y.
  • a first signal line 103 is connected to a data line 101, and the first signal line 103 extends from the first fan-out area FA1 to the second fan-out area FA2.
  • a second signal line 104 is connected to a data line 101, and the second signal line 104 extends from the first fan-out area FA1 to the second fan-out area FA1.
  • a third signal line 105 is connected to a data line 101.
  • the third signal line 105 is located in the second fan-out area FA2, and the third signal line 105 extends along the first direction X.
  • a fourth signal line 106 is connected to a data line, the fourth signal line 106 is located in the second fan-out area FA2, and the fourth signal line 106 extends along the first direction X.
  • the first signal trace 103, the second signal trace 104, the third signal trace 105 and the fourth signal trace 106 are arranged in different layers.
  • the first signal trace 103, the second signal trace 104, the third signal trace 105 and the fourth signal trace 106 are arranged in different layers, that is, the first signal trace located in the first fan-out area FA1
  • the signal trace 103 and the second signal trace 104 are arranged on different film layers, and the third signal trace 105 and the fourth signal trace 106 located in the second fan-out area FA2 are arranged on different film layers, which can reduce the number of same layers. Set the number of signal traces in the film layer. Therefore, compared with the prior art technology of arranging the first signal trace 103 and the second signal trace 104 on the same film layer, and arranging the third signal trace 105 and the fourth signal trace 106 on the same layer.
  • the first signal trace 103, the second signal trace 104, the third signal trace 105 and the fourth signal trace 106 are arranged in different layers. Between the adjacent first signal trace 103 and the second signal trace, the display panel 100 of this embodiment can reduce the area occupied by the first fan-out area FA1. Specifically, the distance along the first direction X of the first fan-out area FA1 can be reduced, that is, the distance along the first direction Border design.
  • the display area AA is used to realize the display function of the display panel 100 , and a pixel circuit composed of thin film transistors is provided in the display area AA for driving the light-emitting elements on the substrate 10 to emit light.
  • a plurality of data lines 101 extending along the first direction X in the display area AA are used to transmit data voltages to the pixel circuit.
  • the plurality of data lines 101 include a plurality of first-type data lines 101a and a plurality of second-type data lines 101b.
  • the plurality of first-type data lines 101a are located on both sides of the plurality of second-type data lines 101b; wherein, the first-type data lines 101a are located on both sides of the second-type data lines 101b.
  • the data line 101a extends along the first direction X to the corner frame between two sides of the display panel 100
  • the second type data line 101b extends along the first direction X to the lower frame of the display panel 100.
  • a part of the first type data line 101a is connected to the first signal line 103, and another part of the first type data line 101a is connected to the second signal line 104.
  • a part of the second type data line 101b is connected to the third signal line 105, and another part of the second type data line 101b is connected to the fourth signal line 106.
  • the first signal wiring 103 and the second signal wiring 104 are alternately connected to the first type of data line 101a.
  • the third signal trace 105 and the fourth signal trace 106 are alternately connected to the second type data line 101b.
  • Parts of the first signal trace 103 and the second signal trace 104 are disposed between a plurality of third signal traces 105 and fourth signal traces 106 .
  • the first signal traces 103 and the second signal traces 104 are arranged alternately.
  • the third signal trace 105 and the fourth signal trace 106 are arranged alternately.
  • the vertical routing space for signal traces in the fan-out area FA is reduced.
  • a first signal trace 103 includes a connected first trace segment 1031 and a second trace segment 1032. Part of the first trace segment 1031 is located in the first fan-out area FA1. The second wiring segment 1032 is located in the second fan-out area FA2, and the second wiring segment 1032 extends along the first direction X.
  • a second signal trace 104 includes a third trace segment 1041 and a fourth trace segment 1042. Part of the third wiring segment 1041 is located in the first fan-out area FA1. The fourth wiring segment 1042 is located in the second fan-out area FA2, and the fourth wiring segment 1042 extends along the first direction X.
  • the second wiring segment 1032 and the fourth wiring segment 1042 are wirings parallel to the third signal wiring 105 and the fourth signal wiring 106, and the first wiring segment 1031 is the A signal trace 103 is a line segment other than the second trace segment 1032, and the third trace segment 1041 is a line segment of the second signal trace 104 except the fourth trace segment 1042.
  • the second trace segments 1032 and the fourth trace segments 1042 are arranged in sequence between the plurality of third signal traces 105 and the fourth signal traces 106 , and one of the second wiring segment 1032 and the fourth wiring segment 1042 is provided between the two adjacent third signal wiring lines 105 and the fourth signal wiring line 106 .
  • two adjacent third signal traces 105 and fourth signal traces 106 are provided with only one trace segment, and the second trace segments 1032 and the fourth trace segments 1042 are arranged in sequence to prevent The distance between the adjacent second wiring segment 1032 and the fourth wiring segment 1042 along the second direction Y is too narrow and is short-circuited, which improves the stability of the display panel 100 .
  • the display area AA includes a first side a1, a second side a2, and a third side a3.
  • the first side a1 and the second side a2 are connected by the third side a3.
  • the third side Side a3 is arc-shaped.
  • the data line 101 of the display area AA corresponding to the third side a3 is connected to the first signal wiring 103 and the second signal wiring 104 .
  • the plurality of first type data lines 101a correspond to the third side a3.
  • the extending direction of the first wiring segment 1031 and the third wiring segment 1041 is the same as the extending direction of the third side a3.
  • the second trace segments 1032 and the fourth trace segments 1042 are alternately provided between the third signal trace 105 and the fourth signal trace 106 .
  • the first wiring segment 1031 and the third wiring segment 1041 extend into the first sector area FA1 along the third side a3, and the second wiring segment 1032 and the fourth wiring segment 1042 are alternately provided in the first sector area FA1.
  • the distance of the first fan-out area FA1 along the first direction X is further reduced, and the second trace segment 1032 and the fourth trace segment 1042 are alternately interspersed
  • the space between the third signal trace 105 and the fourth signal trace 106 is fully utilized to prevent the second trace segment 1032 and the fourth trace segment 1042 from accumulating.
  • the first fan-out area FA1 there is a risk of short circuit.
  • the height of the second fan-out area FA2 in the first direction X is less than or equal to 600 microns.
  • the height of the second fan-out area FA2 in the first direction X may be any one of 600 microns, 500 microns, 400 microns, 300 microns, 200 microns, 100 microns, or 50 microns.
  • the display panel 100 of this embodiment can reduce the area occupied by the first fan-out area FA1. Specifically, the distance along the first direction X of the first fan-out area FA1 can be reduced, that is, the distance along the first direction Border design.
  • the display panel also includes a shielding metal layer BSM, a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4.
  • the shielding metal layer BSM is disposed on the substrate 10, and the first signal trace 103 is located on the shielding metal layer BSM.
  • the first metal layer M1 is provided on a side of the shielding metal layer BSM away from the substrate 10 and is insulated from the shielding metal layer BSM.
  • the third signal trace 105 is located on the first metal layer M1.
  • the second metal layer M2 is disposed on a side of the first metal layer M1 away from the substrate 10 and is insulated from the first metal layer M1.
  • the fourth signal trace 106 is located on the second metal layer M2.
  • the third metal layer M3 is disposed on a side of the second metal layer M2 away from the first metal layer M1 and is insulated from the second metal layer M2.
  • the second signal trace 104 is located on the third metal layer M3.
  • the shielding metal layer BSM further includes a shielding metal line 1033 located in the display area AA.
  • the shielding metal layer BSM since the shielding metal layer BSM includes the first signal wiring and the shielding metal line 1033, that is, the shielding metal layer BSM including the first signal wiring and the shielding metal line 1033 can be formed through the same process. Therefore, this application does not need to add another film layer to set the first signal trace, nor does it need to add a mask.
  • the original manufacturing process of the display panel is used to realize the layout of multi-layer signal traces, so that the first fan-out area FA1 is arranged along the The distance in the first direction X is reduced, which reduces the distance of the lower frame along the first direction X, and increases the screen-to-body ratio of the display area of the display panel.
  • the display panel 100 also includes a barrier layer 11, a buffer layer 12, a first active layer AL1, a first gate insulating layer 13, a second gate insulating layer 14, a first interlayer dielectric layer 15, and a second active layer AL2. , the third gate insulating layer 16, the second interlayer dielectric layer 17, the first planarization layer 18, and the second planarization layer 19.
  • the barrier layer 11 covers the shielding metal layer BSM.
  • the buffer layer 12 is disposed on the side of the barrier layer 11 away from the substrate 10 .
  • the material of the buffer layer 12 includes but is not limited to silicon-containing oxide, nitride or oxynitride.
  • the first active layer AL1 is disposed on a side of the shielding metal layer BSM away from the substrate 10 and is insulated from the shielding metal layer BSM. Specifically, the first active layer AL1 is disposed on the side of the buffer layer 12 away from the substrate 10 .
  • the first active layer AL1 is a low-temperature polysilicon active layer.
  • the first gate insulating layer 13 is provided on a side of the first active layer AL1 away from the substrate 10 .
  • the first metal layer M1 is disposed on the first gate insulating layer 13 away from the first active layer AL1, and the first metal layer M1 includes the first gate GE1 and the third signal trace 105.
  • the second gate insulating layer 14 is disposed on the side of the first gate insulating layer 13 away from the buffer layer 12 , and the second gate insulating layer 14 covers the first metal layer M1 .
  • the second metal layer M2 is disposed on the second gate insulating layer 14 , and the second metal layer M2 includes the second gate GE2 and the second four signal traces 1042 .
  • the second gate insulating layer 14 provided on the first interlayer dielectric layer 15 is on a side away from the first gate insulating layer 13 and covers the second metal layer M2.
  • the second active layer AL2 is disposed on a side of the second metal layer M2 away from the first metal layer M1 and is insulated from the second metal layer M2. Specifically, the second active layer AL2 is disposed on a side of the first interlayer dielectric layer 15 away from the second gate insulating layer 14 .
  • the second active layer AL2 is a metal oxide active layer.
  • the third gate insulating layer 16 is disposed on a side of the first interlayer dielectric layer 15 away from the second gate insulating layer 14 .
  • the third metal layer M3 is disposed on a side of the third gate insulating layer 16 away from the second gate insulating layer 14 .
  • the third metal layer M3 includes the second signal trace 104 and the third gate GE3 .
  • the second interlayer dielectric layer 17 is disposed on the side of the third gate insulating layer 16 away from the first interlayer insulating layer.
  • the fourth metal layer M4 is disposed on the side of the second interlayer dielectric layer 17 away from the third gate insulating layer 16 .
  • the fourth metal layer M4 includes a first source electrode S1, a first drain electrode D1, a contact electrode TE, a second source electrode S2, a second drain electrode D2 and a data line 101.
  • the first source electrode and the first drain electrode are respectively connected to the first active layer AL1 through via holes.
  • the second source electrode S2 and the second drain electrode D2 are respectively connected to the second active layer AL2 through via holes.
  • the first active layer AL1 and the second source electrode S2 are connected through the contact electrode TE.
  • the display panel 100 further includes a fifth metal layer M5 disposed on a side of the first planarization layer 18 away from the second interlayer dielectric layer 17 .
  • the data line may also be located on the fifth metal layer M5.
  • the fifth metal layer M5 also includes a connection electrode NE, which is used to connect the first drain electrode D1 and the light-emitting functional layer of the display panel 100 to drive the display panel to emit light.
  • FIG. 5 is a second schematic plan view of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structural diagram of the fan-out area taken along the C-C direction of FIG. 5.
  • the difference between the display panel 100 provided by the embodiment of the present application and the display panel 100 provided in FIG. 2 is that a plurality of first signal traces 103 , the plurality of second signal traces 104 and the plurality of third signal traces 105 extend from the first fan-out area FA1 to the second fan-out area FA2, and the plurality of fourth signal traces 106 are located in the second fan-out area FA2, and arranged along the first direction X.
  • a first signal trace 103, a second signal trace 104 and a third signal trace 105 are arranged alternately.
  • the first signal trace 103 includes a connected first trace segment 1031 and a second trace segment 1032.
  • the second signal trace 104 includes connected third trace segments 1041 and fourth trace segments 1042 .
  • the third signal trace 105 includes connected fifth trace segments 1051 and sixth trace segments 1052 .
  • the first wiring segment 1031, the third wiring segment 1041 and the fifth wiring segment 1051 extend from the first fan-out area FA1 to the second fan-out area FA2.
  • the second trace segments 1032 , the fourth trace segments 1042 and the sixth trace segments 1052 are alternately arranged between the fourth signal traces 106 , and the second trace segments 1032 , the fourth trace segments 1042 and the sixth trace segments 1052 are arranged along the first Extend in direction X.
  • the second wiring segment 1032, the fourth wiring segment 1042 and the sixth wiring segment 1052 are wiring parallel to the fourth signal wiring 106, and the first wiring segment 1031 is the first wiring segment.
  • the signal trace 103 is a line segment other than the second trace segment 1032.
  • the third trace segment 1041 is a line segment of the second signal trace 104 except the fourth trace segment 1042.
  • the fifth trace segment 1051 is the third signal trace 105. Line segments other than the sixth trace segment 1052.
  • the second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 are sequentially arranged on multiple fourth signal traces.
  • 106 and between two adjacent fourth signal traces 106, one of the second trace segment 1032, the fourth trace segment 1042 and the sixth trace segment 1052 is provided. That is, in the embodiment of the present application, two adjacent fourth signal traces 106 are provided with only one trace segment, and the second trace segment 1032, the fourth trace segment 1042, and the sixth trace segment 1052 are arranged in sequence to prevent mutual interference.
  • the distance between the adjacent second wiring segment 1032 , the fourth wiring segment 1042 and the sixth wiring segment 1052 along the second direction Y is too narrow and is short-circuited, which improves the stability of the display panel 100 .
  • a part of the first type of data line 101a is connected to the first signal trace 103, a part of the first type of data line 101a is connected to the second signal trace 104, and a part of the first type of data line 101a is connected to the third signal trace.
  • the second type of data line 101b is connected to the fourth signal line 106.
  • a first signal line 103, a second signal line 104 and a third signal line section 105 are alternately connected to the first type of data line 101a.
  • the first signal trace 103 is located in the third metal layer M3.
  • the second signal trace 104 is located on the first metal layer M1.
  • the third signal trace 105 is located on the second metal layer M2.
  • the fourth signal trace 106 is located on the shielding metal layer BSM.
  • the first signal trace 103, the second signal trace 104, the third signal trace 105 and the fourth signal trace 106 are arranged in different layers, that is, the first signal trace located in the first fan-out area FA1
  • the signal trace 103, the second signal trace 104 and the third signal trace are provided in different film layers, which can reduce the number of signal traces provided in the same film layer.
  • the display panel 100 of this embodiment can further reduce the area occupied by the first fan-out area FA1. Specifically, the distance along the first direction X of the first fan-out area FA1 can be reduced, that is, the distance along the first direction Border design.
  • FIG. 7 is a schematic plan view of a display terminal provided by an embodiment of the present application.
  • An embodiment of the present application also provides a display terminal 1000.
  • the display terminal 1000 includes a display panel 100 and a casing 200.
  • the display panel 100 is disposed in the casing 200.
  • the display panel 100 is the above-mentioned display panel 100 .
  • the display terminal 1000 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, Vehicle-mounted displays, medical equipment, industrial control equipment, touch interactive terminals, etc. are not specifically limited in the embodiments of this application.

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Abstract

一种显示面板（100）及显示终端（1000），显示面板（100）包括显示区（AA）、扇出区（FA）和弯折区（BA）。显示面板（100）包括位于显示区（AA）的多条数据线（101）、位于扇出区（FA）的多条第一信号走线（103）、多条第二信号走线（104）、多条第三信号走线（105）和多条第四信号走线（106）。第一信号走线（103）、第二信号走线（104）、第三信号走线（105）和第四信号走线（106）异层设置。

Description

显示面板及显示终端 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示终端。
 背景技术
随着极致全面屏的发展趋势，显示面板的边框越来越窄，屏占比也越来越高，给消费者带来更加极致的体验。
但随着屏幕分别率的增高，显示面板所包含的数据走线数目急剧增加，显示面板的下边框部分所需要留给走线的空间增加，使得有效显示区AA域变小。
 技术问题
本申请实施例提供一种显示面板及显示终端，用于减小显示面板的下边框，提高显示区的屏占比。
 技术解决方案
本申请实施例公开一种显示面板，显示面板包括显示区、扇出区和弯折区，所述扇出区位于所述显示区和所述弯折区之间，所述显示面板包括：
基板；
多条数据线，设置在所述基板上，且所述数据线位于所述显示区；
多条第一信号走线，位于所述扇出区，一所述第一信号走线与一所述数据线连接；
多条第二信号走线，位于所述扇出区，一所述第二信号走线与一所述数据线连接；
多条第三信号走线，位于所述扇出区，一所述第三信号走线与一所述数据线连接；
多条第四信号走线，位于所述扇出区，一所述第四信号走线与一所述数据线连接；其中
所述第一信号走线、所述第二信号走线、所述第三信号走线和所述第四信号走线异层设置。
可选的，在本申请提供的一些实施例中，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区位于所述第二扇出区的两侧；其中
多条所述第一信号走线和多条所述第二信号走线由所述第一扇出区延伸至所述第二扇出区；
多条所述第三信号走线和多条所述第四信号走线位于所述第二扇出区，且沿第一方向排列。
可选的，在本申请提供的一些实施例中，一所述第一信号走线包括第一走线段和第二走线段，所述第一走线段的部分位于所述第一扇出区，所述第二走线段位于所述第二扇出区，且所述第二走线段沿所述第一方向延伸。
可选的，在本申请提供的一些实施例中，一所述第二信号走线包括第三走线段和第四走线段，所述第三走线段的部分位于所述第一扇出区，所述第四走线段位于所述第二扇出区，且所述第四走线段沿所述第一方向延伸。
可选的，在本申请提供的一些实施例中，沿所述第二扇出区指向所述第一扇出区的方向，所述第二走线段、所述第四走线段依次排布在多条所述第三信号走线和所述第四信号走线之间，且相邻两条所述第三信号走线和所述第四信号走线之间设置有所述第二走线段、所述第四走线段中的一者。
可选的，在本申请提供的一些实施例中，所述显示区包括第一侧边、第二侧边和第三侧边，所述第一侧边和所述第二侧边通过所述第三侧边连接，所述第三侧边为弧形，与所述第三侧边对应的所述显示区的所述数据线与所述第一信号走线以及第二信号走线连接；
所述第一走线段和所述第三走线段的延伸方向与所述第三侧边的延伸方向相同。
可选的，在本申请提供的一些实施例中，多条所述数据线包括多条第一类数据线和多条第二类数据线，多条所述第一类数据线位于多条所述第二类数据线的两侧，多条所述第一类数据线对应所述第三侧边，一部分所述第一类数据线和所述第一信号走线连接，另一部分所述第一类数据线和所述第二信号走线连接。
可选的，在本申请提供的一些实施例中，所述第一信号走线和所述第二信号走线交替与所述第一类数据线连接。
可选的，在本申请提供的一些实施例中，所述第三信号走线和所述第四信号走线交替与所述第二类数据线连接。
可选的，在本申请提供的一些实施例中，所述显示面板还包括：
屏蔽金属层，设置在所述基板上，所述第一信号走线位于屏蔽金属层；
第一金属层，设置在所述屏蔽金属层远离所述基板的一侧，与所述屏蔽金属层绝缘设置，所述第三信号走线位于所述第一金属层；
第二金属层，设置在所述第一金属层远离所述基板的一侧，与第一金属层绝缘设置，所述第四信号走线位于所述第二金属层；
第三金属层，设置在所述第二金属层远离所述第一金属层的一侧，且与所述第二金属层绝缘设置，所述第二信号走线位于所述第三金属层。
可选的，在本申请提供的一些实施例中，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区位于所述第二扇出区的两侧；其中
多条所述第一信号走线、多条所述第二信号走线和多条所述第三信号走线由所述第一扇出区延伸至所述第二扇出区；
多条所述第四信号走线位于所述第二扇出区，且沿第一方向排列。
可选的，在本申请提供的一些实施例中，一所述第一信号走线、一所述第二信号走线和一所述第三信号走线交替设置。
可选的，在本申请提供的一些实施例中，一所述第一信号走线包括连接的第一走线段和第二走线段，一所述第二信号走线包括连接的第三走线段和第四走线段，一所述第三信号走线包括连接的第五走线段和第六走线段；其中
所述第一走线段、所述第三走线段和所述第五走线段由所述第一扇出区延伸至第二扇出区，所述第二走线段、所述第四走线段和所述第六走线段位于所述第二扇出区，且所述第二走线段、所述第四走线段和所述第六走线段沿所述第一方向延伸。
可选的，在本申请提供的一些实施例中，沿所述第二扇出区指向所述第一扇出区的方向，所述第二走线段、所述第四走线段和所述第六走线段依次排布在多条所述第四信号走线之间，且相邻两条所述第四信号走线之间设置有所述第二走线段、所述第四走线段和所述第六走线段中的一者。
可选的，在本申请提供的一些实施例中，所述显示面板还包括：
屏蔽金属层，设置在所述基板上，所述第四信号走线位于屏蔽金属层；
第一金属层，设置在所述屏蔽金属层远离所述基板的一侧，与所述屏蔽金属层绝缘设置，所述第二信号走线位于所述第一金属层；
第二金属层，设置在所述第一金属层远离所述基板的一侧，与第一金属层绝缘设置，所述第三信号走线位于所述第二金属层；
第三金属层，设置在所述第二金属层远离所述第一金属层的一侧，且与所述第二金属层绝缘设置，所述第一信号走线位于所述第三金属层。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第一有源层和第二有源层，所述第一有源层设置在所述屏蔽金属层远离所述基板的一侧，且与所述屏蔽金属层绝缘设置，所述第二有源层设置第二金属层远离所述第一金属层的一侧，且与所述第二金属层绝缘设置；其中
所述第一有源层为低温多晶硅有源层，所述第二有源层为金属氧化物有源层。
可选的，在本申请提供的一些实施例中，所述屏蔽金属层还包括屏蔽金属线，所述屏蔽金属线位于所述显示区。
可选的，在本申请提供的一些实施例中，所述显示面板还包括第四金属层，设置在所述第三金属层远离所述第二金属层的一面，所述数据线位于所述第四金属层。
可选的，在本申请提供的一些实施例中，所述第二扇出区在所述第一方向上的高度小于或等于600微米。
相应的，本申请实施例还提供一种显示终端，所述显示终端包括上述的显示面板及壳体，所述显示面板设置在所述壳体内。
 有益效果
本申请实施例提供一种显示面板及显示终端，显示面板包括显示区、扇出区和弯折区。扇出区位于显示区和弯折区之间。显示面板包括基板、多条数据线、位于扇出区的多条第一信号走线、多条第二信号走线、多条第三信号走线和多条第四信号走线。其中多条数据线设置在基板上，且数据线位于显示区。一第一信号走线与一数据线连接。一第二信号走线与一数据线连接。一第三信号走线与一数据线连接。一第四信号走线与一数据线连接。第一信号走线、第二信号走线、第三信号走线和第四信号走线异层设置。在本申请实施例中，由于第一信号走线、第二信号走线、第三信号走线和第四信号走线异层设置，即可以减少同一膜层中设置信号走线的数量。在相邻的第一信号走线和第二信号走线之间的距离以及第三信号走线和第四信号走线之间的距离不变的情况下，本实施例的显示面板可以减小扇出区所占的面积，从而减小显示面板的下边框，提高显示区的屏占比。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的一种示意图；
图2为本申请实施例提供的显示面板的第一种平面示意图；
图3为沿图2的A-A方向截取的扇出区的一种剖面结构示意图；
图4为沿图2的B-B方向截取的显示区的一种剖面结构示意图；
图5为本申请实施例提供的显示面板的第二种平面示意图；
图6为沿图5的C-C方向截取的扇出区的一种剖面结构示意图；
图7为本申请实施例提供的显示终端的一种平面示意图。
 本发明的实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，请参照附图中的图式，其中相同的组件符号代表相同的组件，以下的说明是基于所示的本申请具体实施例，其不应被视为限制本申请未在此详述的其他具体实施例。本说明书所使用的词语“实施例”意指实例、示例或例证。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请实施例提供一种拼接显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参考图1，图1为本申请实施例提供的显示面板的一种示意图。已知技术中的显示面板的左右边框和上边框都可以做的很窄(例如，宽度小于1mm)，显示面板下边框的弯折区BA的弯折半径a、弯折时背板的贴合精度和扇出区的走线的布线均会导致下边框过宽的现象，不利于实现下窄边框的发展。经发明人研究发现，出现上述问题的原因在于，显示面板的下边框通常会设计有较为密集的走线，使得下边框的结构相比于其他边框更为复杂。已知的走线通常选择斜向布线的方式，将弯折区BA引出的连接线在扇出区FA进行斜向布线，以连接显示区AA的数据线。在显示区AA中，数据线的数量通常有很多根，随着分辨率的提高，数据线的数量也急速增加，例如，1080*2340分辨率下，数据线有2160根。按照现有技术中的斜向布线时，为了防止连接线之间短路，需拉大下边框的宽度，也即b值会很大(大于1mm)，不利于实现下窄边框。
本申请实施例提供一种显示面板，显示面板包括显示区、扇出区和弯折区。扇出区位于显示区和弯折区之间。显示面板包括基板、多条数据线、位于扇出区的多条第一信号走线、多条第二信号走线、多条第三信号走线和多条第四信号走线。其中，多条数据线设置在基板上，且数据线位于显示区。一第一信号走线与一数据线连接。一第二信号走线与一数据线连接。多条一第三信号走线与一数据线连接。一第四信号走线与一数据线连接。第一信号走线、第二信号走线、第三信号走线和第四信号走线异层设置。在本申请实施例中，由于第一信号走线、第二信号走线、第三信号走线和第四信号走线异层设置，即可以减少同一膜层中设置信号走线的数量。在相邻的第一信号走线和第二信号走线之间的距离以及相邻的第三信号走线和第四信号走线之间的距离不变的情况下，本实施例的显示面板可以减小扇出区所占的面积，从而减小显示面板的下边框，提高显示区的屏占比。
下面通过具体实施例对本申请提供的显示面板进行详细的阐述。
请结合图2、图3和图4，图2为本申请实施例提供的显示面板的第一种平面示意图。图3为沿图2的A-A方向截取的扇出区的一种剖面结构示意图。图4为沿图2的B-B方向截取的显示区的一种剖面结构示意图。本申请实施例提供一种显示面板，显示面板100包括显示区AA、扇出区FA和弯折区BA，扇出区FA位于显示区AA和弯折区BA之间，扇出区FA包括第一扇出区FA1和第二扇出区FA2，第一扇出区FA1位于第二扇出区FA2的两侧；其中，第二扇出区FA2为一矩形区域，该矩形区域的一边为显示面板100的下边框，第一扇出区FA1为扇出区FA中除第二扇出区FA2之外的区域。显示面板100包括基板10、多条数据线101、多条第一信号走线103、多条第二信号走线104、多条第三信号走线105和多条第四信号走线106。其中，数据线101设置在基板10上，且数据线101位于显示区AA。多条数据线101沿第一方向X延伸且沿第二方向Y排列。一第一信号走线103和一数据线101连接，第一信号走线103由第一扇出区FA1延伸至第二扇出区FA2。一第二信号走线104与一数据线101连接，第二信号走线104由第一扇出区FA1延伸至第二扇出区FA1。一第三信号走线105一数据线101连接，第三信号走线105位于第二扇出区FA2，且第三信号走线105沿第一方向X延伸。一第四信号走线106一数据线连接，第四信号走线106位于第二扇出区FA2，且第四信号走线106沿第一方向X延伸。其中，第一信号走线103、第二信号走线104、第三信号走线105和第四信号走线106异层设置。
在本申请中，由于第一信号走线103、第二信号走线104、第三信号走线105和第四信号走线106异层设置，即，将位于第一扇出区FA1的第一信号走线103和第二信号走线104设置于不同的膜层，将位于第二扇出区FA2的第三信号走线105和第四信号走线106设置于不同的膜层，可以减少同一膜层中设置信号走线的数量。因此，与现有技术中将第一信号走线103和第二信号走线104设置于同一膜层，并将第三信号走线105和第四信号走线106设置于同层的技术相比，本实施例将第一信号走线103、第二信号走线104、第三信号走线105和第四信号走线106异层设置，在相邻的第一信号走线103和第二信号走线104之间的距离的不变的情况下，本实施例的显示面板100可以减小第一扇出区FA1所占的面积。具体地，上述第一扇出区FA1沿第一方向X的距离可以减小，即可以缩小第一扇出区FA1所在的下边框沿第一方向X的距离，从而使得显示面板100可以实现窄边框设计。
具体地，显示区AA用于实现显示面板100的显示功能，在显示区AA内设置有薄膜晶体管构成的像素电路，用于驱动基板10上的发光元件发光。显示区AA内多条沿第一方向X延伸的数据线101用于向像素电路传输数据电压。
多条数据线101包括多条第一类数据线101a和多条第二类数据线101b，多条第一类数据线101a位于多条第二类数据线101b的两侧；其中，第一类数据线101a沿第一方向X延伸至显示面板100两侧边之间的角部边框，第二类数据线101b沿第一方向X延伸至显示面板100的下边框。一部分第一类数据线101a和第一信号走线连接103，另一部分第一类数据线101a和第二信号走线104连接。一部分第二类数据线101b和第三信号走线连接105，另一部分第二类数据线101b和第四信号走线106连接。
其中，第一信号走线103和第二信号走线104交替与第一类数据线101a连接。第三信号走线105和第四信号走线106交替与第二类数据线101b连接。
其中，第一信号走线103和第二信号走线104的部分设置在多条第三信号走线105和第四信号走线106之间。
第一信号走线103和第二信号走线104交替设置。第三信号走线105和第四信号走线106交替设置。减小了扇出区FA的信号走线在垂直方向的布线空间。
具体的，一第一信号走线103包括连接的第一走线段1031和第二走线段1032。第一走线段1031的部分位于第一扇出区FA1。第二走线段1032位于第二扇出区FA2，且第二走线段1032沿第一方向X延伸。一第二信号走线104包括第三走线段1041和第四走线段1042。第三走线段1041的部分位于第一扇出区FA1。第四走线段1042位于第二扇出区FA2，且第四走线段1042沿第一方向X延伸。
需要说明的是，在本申请实施例中，第二走线段1032和第四走线段1042为与第三信号走线105和第四信号走线106平行的走线，第一走线段1031为第一信号走线103除了第二走线段1032之外的线段，第三走线段1041为第二信号走线104除了第四走线段1042之外的线段。
沿第二扇出区FA2指向第一扇出区FA1的方向，第二走线段1032、第四走线1042段依次排布在多条第三信号走线105和第四信号走线106之间，且相邻两条第三信号走线105和第四信号走线106之间设置有第二走线段1032、第四走线段1042中的一者。即，在本申请实施例中，相邻两条第三信号走线105和第四信号走线106仅设置有一条走线段，且第二走线段1032和第四走线段1042依次排布，防止相邻的第二走线段1032和第四走线段1042之间沿第二方向Y的距离过窄而短接，提高了显示面板100的稳定性。
在一些实施例中，显示区AA包括第一侧边a1、第二侧边a2和第三侧边a3，第一侧边a1和第二侧边a2通过第三侧边a3连接，第三侧边a3为弧形。与第三侧边a3对应的显示区AA的数据线101与第一信号走线103以及第二信号走线104连接。多条第一类数据线101a对应第三侧边a3。第一走线段1031和第三走线段1041的延伸方向与第三侧边a3的延伸方向相同。且第二走线段1032和第四走线段1042交替设置在第三信号走线105和第四信号走线106之间。
在本申请实施例中，第一走线段1031和第三走线段1041沿着第三侧边a3延伸至第一扇形区FA1内，且第二走线段1032和第四走线段1042交替设置在第三信号走线105和第四信号走线106之间，因此，进一步减小了第一扇出区FA1沿第一方向X的距离，并且，第二走线段1032和第四走线段1042交替穿插在第三信号走线105和第四信号走线106，充分利用的第三信号走线105和第四信号走线106之间的空间，防止了第二走线段1032和第四走线段1042堆积在第一扇出区FA1内，造成短接的风险。
在一些实施例中，第二扇出区FA2在第一方向X上的高度小于或等于600微米。例如，第二扇出区FA2在第一方向X上的高度可以是600微米、500微米、400微米、300微米、200微米、100微米或50微米中的任意一者。
在本申请实施例中，通过将连接数据线101的信号走线设置于不同的四个膜层上，可以减少同一膜层中设置信号走线的数量。因此，与现有技术中将第一信号走线103和第二信号走线104设置于同一膜层，并将第三信号走线105和第四信号走线106设置于同层相比，本实施例将第一信号走线103、第二信号走线104、第三信号走线105和第四信号走线106异层设置，在相邻的第一信号走线103和第二信号走线104之间的距离的不变的情况下，本实施例的显示面板100可以减小第一扇出区FA1所占的面积。具体地，上述第一扇出区FA1沿第一方向X的距离可以减小，即可以缩小第一扇出区FA1所在的下边框沿第一方向X的距离，从而使得显示面板100可以实现窄边框设计。
请继续参考图2和图3，显示面板还包括屏蔽金属层BSM、第一金属层M1，第二金属层M2、第三金属层M3和第四金属层M4。屏蔽金属层BSM设置在基板10上，第一信号走线103位于屏蔽金属层BSM。第一金属层M1设置在屏蔽金属层BSM远离基板10的一面，且与屏蔽金属层BSM绝缘设置，第三信号走线105位于第一金属层M1。第二金属层M2设置在第一金属层M1远离基板10的一面，且与第一金属层M1绝缘设置。第四信号走线106位于第二金属层M2。第三金属层M3设置在第二金属层M2远离第一金属层M1的一面，且与第二金属层M2绝缘设置。第二信号走线104位于第三金属层M3。
在一些实施例中，屏蔽金属层BSM还包括屏蔽金属线1033，屏蔽金属线1033位于显示区AA。在本申请实施例中，由于屏蔽金属层BSM包括第一信号走线和屏蔽金属线1033，即屏蔽金属层BSM包括第一信号走线和屏蔽金属线1033可以通过同一道制程形成。因此，本申请无需增加另外的膜层以设置第一信号走线，也不需要增加掩模板，即利用显示面板原来的制程实现多层信号走线的布置，从而使得第一扇出区FA1沿第一方向X的距离减小，减小了下边框沿第一方向X的距离，提高了显示面板的显示区的屏占比。
显示面板100还包括阻挡层11、缓冲层12、第一有源层AL1、第一栅极绝缘层13、第二栅极绝缘层14、第一层间介质层15、第二有源层AL2、第三栅极绝缘层16、第二层间介质层17、第一平坦化层18、第二平坦化层19。
其中，阻挡层11覆盖屏蔽金属层BSM。
缓冲层12设置在阻挡层11远离基板10的一面。缓冲层12的材质包括但不限于含硅的氧化物、氮化物或氮氧化物。
第一有源层AL1设置在屏蔽金属层BSM远离基板10的一侧，且与屏蔽金属层BSM绝缘设置。具体的，第一有源层AL1设置缓冲层12远离基板10的一侧。第一有源层AL1为低温多晶硅有源层。
第一栅极绝缘层13设置在第一有源层AL1远离基板10的一面。第一金属层M1设置在第一栅极绝缘层13远离第一有源层AL1上，第一金属层M1包括第一栅极GE1和第三信号走线105。
第二栅极绝缘层14设置在第一栅极绝缘层13远离缓冲层12的一面，第二栅极绝缘层14覆盖第一金属层M1。第二金属层M2设置在第二栅极绝缘层14上，第二金属层M2包括第二栅极GE2和第二四信号走线1042。
第一层间介质层15设置的第二栅极绝缘层14远离第一栅极绝缘层13的一面，并覆盖第二金属层M2。
第二有源层AL2设置第二金属层M2远离第一金属层M1的一侧，且与第二金属层M2绝缘设置。具体的，第二有源层AL2设置在第一层间介质层15远离第二栅极绝缘层14的一面。第二有源层AL2为金属氧化物有源层。
第三栅极绝缘层16设置在第一层间介质层15远离第二栅极绝缘层14的一面。第三金属层M3设置在第三栅极绝缘层16远离第二栅极绝缘层14的一面，第三金属层M3包括第二信号走线104和第三栅极GE3。
第二层间介质层17设置在第三栅极绝缘层16远离第一层间绝缘层的一侧。第四金属层M4设置在第二层间介质层17远离第三栅极绝缘层16的一侧。其中，第四金属层M4包括第一源极S1、第一漏极D1、接触电极TE、第二源极S2、第二漏极D2和数据线101。其中，第一源极和第一漏极分别通过过孔与第一有源层AL1连接。第二源极S2和第二漏极D2分别通过过孔与第二有源层AL2连接。且第一有源层AL1和第二源极S2通过接触电极TE连接。
在一些实施例中，显示面板100还包括第五金属层M5，第五金属层M5设置在第一平坦化层18远离第二层间介质层17的一面。数据线还可以位于第五金属层M5上。第五金属层M5还包括连接电极NE，连接电极NE用于连接第一漏极D1和显示面板100的发光功能层，以驱动显示面板发光。
请结合图5和图6，图5为本申请实施例提供的显示面板的第二种平面示意图。图6为沿图5的C-C方向截取的扇出区的一种剖面结构示意图，本申请实施例提供的显示面板100与图2提供的显示面板100的区别在于，多条第一信号走线103、多条第二信号走线104和多条第三信号走线105由第一扇出区FA1延伸至第二扇出区FA2，多条第四信号走线106位于第二扇出区FA2，且沿第一方向X排列。
一第一信号走线103、一第二信号走线104和一第三信号走线105交替设置。
其中，第一信号走线103包括连接的第一走线段1031和第二走线段1032。第二信号走线104包括连接的第三走线段1041和第四走线段1042。第三信号走线105包括连接的第五走线段1051和第六走线段1052。其中，第一走线段1031、第三走线段1041和第五走线段1051由第一扇出区FA1延伸至第二扇出区FA2。第二走线段1032、第四走线段1042和第六走线段1052交替设置在第四信号走线106之间，且第二走线段1032、第四走线段1042和第六走线段1052沿第一方向X延伸。
需要说明的是，在本申请实施例中，第二走线段1032、第四走线段1042和第六走线段1052为与第四信号走线106平行的走线，第一走线段1031为第一信号走线103除了第二走线段1032之外的线段，第三走线段1041为第二信号走线104除了第四走线段1042之外的线段，第五走线段1051为第三信号走线105除了第六走线段1052之外的线段。
在一些实施中，沿第二扇出区FA2指向第一扇出区FA1的方向，第二走线段1032、第四走线段1042和第六走线段1052依次排布在多条第四信号走线106之间，且相邻两条第四信号走线106之间设置有第二走线段1032、第四走线段1042和第六走线段1052中的一者。即，在本申请实施例中，相邻两条第四信号走线106仅设置有一条走线段，且第二走线段1032、第四走线段1042以及第六走线段1052依次排布，防止相邻的第二走线段1032、第四走线段1042以及第六走线段1052之间沿第二方向Y的距离过窄而短接，提高了显示面板100的稳定性。
在一些实施例中，一部分第一类数据线101a和第一信号走线连接103，一部分第一类数据线101a和第二信号走线104连接，一部分第一类数据线101a和第三信号走线105连接。第二类数据线101b和第四信号走线106连接。
其中，一第一信号走线103、一第二信号走线104和一第三信号走线段105交替与第一类数据线101a连接。
在本申请实施例中，第一信号走线103位于第三金属层M3。第二信号走线104位于第一金属层M1。第三信号走线105位于第二金属层M2。第四信号走线106位于屏蔽金属层BSM。
在本申请中，由于第一信号走线103、第二信号走线104、第三信号走线105和第四信号走线106异层设置，即，将位于第一扇出区FA1的第一信号走线103、第二信号走线104和第三信号走线设置于不同的膜层，可以减少同一膜层中设置信号走线的数量。因此，与现有技术中将第一信号走线103和第二信号走线104设置于同一膜层，并将第三信号走线105和第四信号走线106设置于同层相比，本实施例将第一信号走线103、第二信号走线104、第三信号走线105和第四信号走线106异层设置，在相邻的第一信号走线103、第二信号走线104和第三信号走线105之间的距离的不变的情况下，本实施例的显示面板100可以进一步减小第一扇出区FA1所占的面积。具体地，上述第一扇出区FA1沿第一方向X的距离可以减小，即可以缩小第一扇出区FA1所在的下边框沿第一方向X的距离，从而使得显示面板100可以实现窄边框设计。
相应的，请参考图7，图7为本申请实施例提供的显示终端的一种平面示意图。本申请实施例还提供一种显示终端1000，显示终端1000包括显示面板100及壳体200，显示面板100设置在壳体200内。
其中，显示面板100为上述的显示面板100。
该显示终端1000可以是手机，也可以为任何具有显示功能的电子产品，包括但不限于以下类别：电视机、笔记本电脑、桌上型显示器、平板电脑、数码相机、智能手环、智能眼镜、车载显示器、医疗设备、工控设备、触摸交互终端等，本申请实施例对此不作特殊限定。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，包括显示区、扇出区和弯折区，所述扇出区位于所述显示区和所述弯折区之间，所述显示面板包括：
    基板；
    多条数据线，设置在所述基板上，且所述数据线位于所述显示区；
    多条第一信号走线，位于所述扇出区，一所述第一信号走线与一所述数据线连接；
    多条第二信号走线，位于所述扇出区，一所述第二信号走线与一所述数据线连接；
    多条第三信号走线，位于所述扇出区，一所述第三信号走线与一所述数据线连接；
    多条第四信号走线，位于所述扇出区，一所述第四信号走线与一所述数据线连接；其中
    所述第一信号走线、所述第二信号走线、所述第三信号走线和所述第四信号走线异层设置。
  2. 根据权利要求1所述的显示面板，其中，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区位于所述第二扇出区的两侧；其中
    多条所述第一信号走线和多条所述第二信号走线由所述第一扇出区延伸至所述第二扇出区；
    多条所述第三信号走线和多条所述第四信号走线位于所述第二扇出区，且沿第一方向排列。
  3. 根据权利要求2所述的显示面板，其中，一所述第一信号走线包括第一走线段和第二走线段，所述第一走线段的部分位于所述第一扇出区，所述第二走线段位于所述第二扇出区，且所述第二走线段沿所述第一方向延伸。
  4. 根据权利要求3所述的显示面板，其中，一所述第二信号走线包括第三走线段和第四走线段，所述第三走线段的部分位于所述第一扇出区，所述第四走线段位于所述第二扇出区，且所述第四走线段沿所述第一方向延伸。
  5. 根据权利要求4所述的显示面板，其中，沿所述第二扇出区指向所述第一扇出区的方向，所述第二走线段、所述第四走线段依次排布在多条所述第三信号走线和所述第四信号走线之间，且相邻两条所述第三信号走线和所述第四信号走线之间设置有所述第二走线段、所述第四走线段中的一者。
  6. 根据权利要求4所述的显示面板，其中，所述显示区包括第一侧边、第二侧边和第三侧边，所述第一侧边和所述第二侧边通过所述第三侧边连接，所述第三侧边为弧形，与所述第三侧边对应的所述显示区的所述数据线与所述第一信号走线以及第二信号走线连接；
    所述第一走线段和所述第三走线段的延伸方向与所述第三侧边的延伸方向相同。
  7. 根据权利要求6所述的显示面板，其中，多条所述数据线包括多条第一类数据线和多条第二类数据线，多条所述第一类数据线位于多条所述第二类数据线的两侧，多条所述第一类数据线对应所述第三侧边，一部分所述第一类数据线和所述第一信号走线连接，另一部分所述第一类数据线和所述第二信号走线连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一信号走线和所述第二信号走线交替与所述第一类数据线连接。
  9. 根据权利要求7所述的显示面板，其中，所述第三信号走线和所述第四信号走线交替与所述第二类数据线连接。
  10. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    屏蔽金属层，设置在所述基板上，所述第一信号走线位于屏蔽金属层；
    第一金属层，设置在所述屏蔽金属层远离所述基板的一侧，与所述屏蔽金属层绝缘设置，所述第三信号走线位于所述第一金属层；
    第二金属层，设置在所述第一金属层远离所述基板的一侧，与第一金属层绝缘设置，所述第四信号走线位于所述第二金属层；
    第三金属层，设置在所述第二金属层远离所述第一金属层的一侧，且与所述第二金属层绝缘设置，所述第二信号走线位于所述第三金属层。
  11. 根据权利要求1所述的显示面板，其中，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区位于所述第二扇出区的两侧；其中
    多条所述第一信号走线、多条所述第二信号走线和多条所述第三信号走线由所述第一扇出区延伸至所述第二扇出区；
    多条所述第四信号走线位于所述第二扇出区，且沿第一方向排列。
  12. 根据权利要求11所述的显示面板，其中，一所述第一信号走线、一所述第二信号走线和一所述第三信号走线交替设置。
  13. 根据权利要求12所述的显示面板，其中，一所述第一信号走线包括连接的第一走线段和第二走线段，一所述第二信号走线包括连接的第三走线段和第四走线段，一所述第三信号走线包括连接的第五走线段和第六走线段；其中
    所述第一走线段、所述第三走线段和所述第五走线段由所述第一扇出区延伸至第二扇出区，所述第二走线段、所述第四走线段和所述第六走线段位于所述第二扇出区，且所述第二走线段、所述第四走线段和所述第六走线段沿所述第一方向延伸。
  14. 根据权利要求13所述的显示面板，其中，沿所述第二扇出区指向所述第一扇出区的方向，所述第二走线段、所述第四走线段和所述第六走线段依次排布在多条所述第四信号走线之间，且相邻两条所述第四信号走线之间设置有所述第二走线段、所述第四走线段和所述第六走线段中的一者。
  15. 根据权利要求11所述的显示面板，其中，所述显示面板还包括：
    屏蔽金属层，设置在所述基板上，所述第四信号走线位于屏蔽金属层；
    第一金属层，设置在所述屏蔽金属层远离所述基板的一侧，与所述屏蔽金属层绝缘设置，所述第二信号走线位于所述第一金属层；
    第二金属层，设置在所述第一金属层远离所述基板的一侧，与第一金属层绝缘设置，所述第三信号走线位于所述第二金属层；
    第三金属层，设置在所述第二金属层远离所述第一金属层的一侧，且与所述第二金属层绝缘设置，所述第一信号走线位于所述第三金属层。
  16. 根据权利要求10所述的显示面板，其中，所述显示面板还包括第一有源层和第二有源层，所述第一有源层设置在所述屏蔽金属层远离所述基板的一侧，且与所述屏蔽金属层绝缘设置，所述第二有源层设置第二金属层远离所述第一金属层的一侧，且与所述第二金属层绝缘设置；其中
    所述第一有源层为低温多晶硅有源层，所述第二有源层为金属氧化物有源层。
  17. 根据权利要求16所述的显示面板，其中，所述屏蔽金属层还包括屏蔽金属线，所述屏蔽金属线位于所述显示区。
  18. 根据权利要求16所述的显示面板，其中，所述显示面板还包括第四金属层，设置在所述第三金属层远离所述第二金属层的一面，所述数据线位于所述第四金属层。
  19. 根据权利要求2所述的显示面板，其中，所述第二扇出区在所述第一方向上的高度小于或等于600微米。
  20. 一种显示终端，其中，所述显示终端包括如权利要求1所述的显示面板及壳体，所述显示面板设置在所述壳体内。
PCT/CN2022/116194 2022-06-30 2022-08-31 显示面板及显示终端 WO2024000794A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107065336A (zh) * 2017-06-13 2017-08-18 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN108878484A (zh) * 2018-06-26 2018-11-23 武汉天马微电子有限公司 显示面板及显示装置
KR20200023569A (ko) * 2018-08-23 2020-03-05 삼성디스플레이 주식회사 플렉시블 디스플레이 장치 및 그 제조방법
CN113410277A (zh) * 2021-06-18 2021-09-17 京东方科技集团股份有限公司 显示基板、显示面板及显示装置
CN113629039A (zh) * 2021-07-20 2021-11-09 武汉华星光电半导体显示技术有限公司 柔性显示面板及显示装置
CN113964142A (zh) * 2021-11-19 2022-01-21 昆山国显光电有限公司 显示面板和显示装置
CN114003143A (zh) * 2021-10-28 2022-02-01 成都京东方光电科技有限公司 触控显示面板和触控显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107065336A (zh) * 2017-06-13 2017-08-18 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN108878484A (zh) * 2018-06-26 2018-11-23 武汉天马微电子有限公司 显示面板及显示装置
KR20200023569A (ko) * 2018-08-23 2020-03-05 삼성디스플레이 주식회사 플렉시블 디스플레이 장치 및 그 제조방법
CN113410277A (zh) * 2021-06-18 2021-09-17 京东方科技集团股份有限公司 显示基板、显示面板及显示装置
CN113629039A (zh) * 2021-07-20 2021-11-09 武汉华星光电半导体显示技术有限公司 柔性显示面板及显示装置
CN114003143A (zh) * 2021-10-28 2022-02-01 成都京东方光电科技有限公司 触控显示面板和触控显示装置
CN113964142A (zh) * 2021-11-19 2022-01-21 昆山国显光电有限公司 显示面板和显示装置

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