WO2024000634A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024000634A1
WO2024000634A1 PCT/CN2022/104874 CN2022104874W WO2024000634A1 WO 2024000634 A1 WO2024000634 A1 WO 2024000634A1 CN 2022104874 W CN2022104874 W CN 2022104874W WO 2024000634 A1 WO2024000634 A1 WO 2024000634A1
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Prior art keywords
bit line
layer
line contact
isolation
isolation layer
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PCT/CN2022/104874
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English (en)
French (fr)
Inventor
于有权
孙明祥
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长鑫存储技术有限公司
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Priority to US18/155,061 priority Critical patent/US20240008267A1/en
Publication of WO2024000634A1 publication Critical patent/WO2024000634A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • Embodiments of the present disclosure relate to the technical field of semiconductor integrated circuit manufacturing, and in particular to semiconductor structures and manufacturing methods thereof.
  • DRAM Dynamic Random Access Memory
  • a semiconductor structure and a method of manufacturing the same are provided.
  • embodiments of the present disclosure provide a method for preparing a semiconductor structure, including:
  • bit line contact holes in the substrate
  • bit line contact isolation layer Forming a bit line contact isolation layer; the bit line contact isolation layer at least covers the sidewall of the bit line contact hole;
  • bit line contact layer Forming a bit line contact layer; the bit line contact layer fills the bit line contact hole; the bit line contact layer and the bit line contact isolation layer together form a bit line contact structure;
  • bitline stack is formed; the bitline stack is located on an upper surface of the bitline contact structure.
  • bit line contact layer includes:
  • bit line contact material layer Forming a bit line contact material layer; the bit line contact material layer fills the bit line contact hole and covers the surface of the substrate on which the bit line contact hole is formed;
  • bit line contact material layer located on the substrate surface is removed; the remaining bit line contact material layer is the bit line contact layer.
  • the bit line stack includes a first conductive layer, a second conductive layer and an insulating dielectric layer sequentially stacked from bottom to top.
  • forming a bitline stack includes:
  • first conductive material layer Forming a first conductive material layer, a second conductive material layer and an insulating dielectric material layer sequentially stacked from bottom to top on the surface of the bit line contact structure and the surface of the substrate on which the bit line contact hole is formed;
  • Etch the first conductive material layer, the second conductive material layer and the insulating dielectric material layer, and the remaining first conductive material layer, the second conductive material layer and the insulating dielectric material layer are respectively The first conductive layer, the second conductive layer and the insulating dielectric layer form the bit line stack.
  • the width of the bitline stack is the same as the width of the top of the bitline contact structure.
  • the width of the bitline stack is less than the width of the top of the bitline contact structure and not less than the width of the top of the bitline contact layer.
  • bit line contact isolation layer includes:
  • the first isolation layer covers at least the sidewalls of the bit line contact holes
  • the second isolation layer covers the exposed side of the first isolation layer
  • the first isolation layer, the second isolation layer and the third isolation layer constitute the bit line contact isolation layer.
  • forming the first isolation layer includes:
  • the first isolation material layer covers the surface of the substrate on which the bit line contact hole is formed, the side walls of the bit line contact hole, and the bottom of the bit line contact hole;
  • the remaining first isolation material layer is the first isolation layer
  • the forming the second isolation layer includes:
  • the second isolation material layer covers the surface of the substrate on which the bit line contact hole is formed, the surface of the first isolation layer and the bottom of the bit line contact hole;
  • the remaining second isolation material layer is the second isolation layer ;
  • the forming of the third isolation layer includes:
  • the third isolation material layer covers the surface of the substrate on which the bit line contact hole is formed, the surface of the second isolation layer and the bottom of the bit line contact hole;
  • the isolation material layer is the third isolation layer.
  • the first isolation layer and the third isolation layer each include a silicon nitride layer; the second isolation layer includes a silicon oxide layer; and the bit line contact layer includes a polysilicon layer.
  • a polysilicon layer is further formed on the upper surface of the substrate;
  • the first conductive material layer, the second conductive material layer and the insulating dielectric material layer are etched using a reactive gas with a selectivity ratio of greater than or equal to 10:1 for the polysilicon layer.
  • embodiments of the present disclosure further provide a semiconductor structure, including:
  • bit line contact structure includes a bit line contact isolation layer and a bit line contact layer; the bit line contact isolation layer at least covers the sidewall of the bit line contact hole; the bit line contact layer fills the bit line contact hole;
  • Bit line stack the bit line stack is located on the upper surface of the bit line contact structure.
  • the bit line stack includes a first conductive layer, a second conductive layer and an insulating dielectric layer sequentially stacked from bottom to top.
  • the width of the bitline stack is the same as the width of the top of the bitline contact structure.
  • the width of the bitline stack is less than the width of the top of the bitline contact structure and not less than the width of the top of the bitline contact layer.
  • the bit line contact isolation layer includes:
  • the first isolation layer covers at least the sidewalls of the bit line contact holes
  • the second isolation layer covers the exposed side of the first isolation layer
  • a third isolation layer covers the exposed side of the second isolation layer.
  • the first isolation layer and the third isolation layer each include a silicon nitride layer; the second isolation layer includes a silicon oxide layer; and the bit line contact layer includes a polysilicon layer.
  • the thickness of the first isolation layer is 3 nm ⁇ 5 nm; the thickness of the second isolation layer is 0.5 nm ⁇ 1.5 nm; and the thickness of the third isolation layer is 8 nm ⁇ 10 nm.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the method for preparing a semiconductor structure can reduce the impact of coupling by forming a bit line contact isolation layer covering the side walls of the bit line contact hole; by forming the bit line contact isolation layer in the bit line contact hole before forming the bit line stack Fill the bit line contact layer so that the bit line stack can be effectively protected in the bit line contact isolation layer during its preparation process, preventing the middle and bottom of the bit line stack from being eroded by condensation generated during its preparation process, thereby Improve the yield and performance of preparation methods.
  • the semiconductor structure provided by the embodiment of the present disclosure has a bit line contact structure; the bit line contact isolation layer in the bit line contact structure can reduce the impact of coupling due to covering the side walls of the bit line contact hole; in the bit line contact structure
  • the bit line contact layer fills the bit line contact holes so that the bit line stack located on the upper surface of the bit line contact structure can be effectively protected in the bit line contact isolation layer, thus avoiding the middle and bottom parts of the bit line stack Due to the generation of condensation and erosion, the semiconductor structure provided by the embodiments of the present disclosure has better yield and performance.
  • Figures 1 to 2 are schematic cross-sectional structural diagrams of structures obtained during some traditional preparation methods
  • Figure 3 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figures 10 to 21 are schematic cross-sectional structural diagrams of the structures obtained in each step of the method for preparing a semiconductor structure provided by different embodiments of the present disclosure.
  • a mask layer 6' can be formed on the upper surface of the bit line material stack 40', and then dried The etching process transfers the pattern defined by the mask layer 6' to the bit line material stack 40' to form the bit line structure 40'.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure according to some embodiments.
  • the method for preparing a semiconductor structure may include the following steps:
  • S200 Form bit line contact holes in the substrate.
  • bit line contact isolation layer Form a bit line contact isolation layer; the bit line contact isolation layer at least covers the sidewall of the bit line contact hole.
  • bit line contact layer Forms a bit line contact layer; the bit line contact layer fills the bit line contact hole; the bit line contact layer and the bit line contact isolation layer together form a bit line contact structure.
  • S500 Form a bit line stack; the bit line stack is located on the upper surface of the bit line contact structure.
  • the manufacturing method of the semiconductor structure provided by the above embodiment can reduce the influence of parasitic coupling between the bit line contact layer and the bit line stack by forming a bit line contact isolation layer covering the side wall of the bit line contact hole.
  • the method for manufacturing a semiconductor structure provided by the above embodiment also fills the bit line contact hole with a bit line contact layer before forming the bit line stack, so that the bit line stack can be effectively protected during its preparation process.
  • the middle and bottom of the bit line stack are prevented from being corroded by defects such as condensation generated during the preparation process, thereby improving the yield and performance of the preparation method.
  • forming the bit line contact layer in step S400 may include the following steps:
  • bit line contact material layer Forms a bit line contact material layer; the bit line contact material layer fills the bit line contact holes and covers the surface of the substrate on which the bit line contact holes are formed.
  • the bit line stack may include a first conductive layer, a second conductive layer and an insulating dielectric layer sequentially stacked from bottom to top.
  • forming a bit line stack in step S500 may include the following steps:
  • S510 Form a first conductive material layer, a second conductive material layer and an insulating dielectric material layer sequentially stacked from bottom to top on the surface of the bit line contact structure and the surface of the substrate where the bit line contact holes are formed.
  • S520 Etch the first conductive material layer, the second conductive material layer and the insulating dielectric material layer, and the remaining first conductive material layer, the second conductive material layer and the insulating dielectric material layer serve as the first conductive layer and the second conductive layer respectively. and an insulating dielectric layer to form a bit line stack.
  • the width of the bitline stack is the same as the width of the top of the bitline contact structure.
  • the width of the bit line stack is less than the width of the top of the bit line contact structure and not less than the width of the top of the bit line contact layer.
  • the preparation method of the semiconductor structure provided in the above embodiment can protect the bit line contact isolation layer by forming a first conductive layer with a cross-section similar to a trapezoid.
  • the bit line stack obtained by the preparation method of the semiconductor structure provided in the above embodiment has a smaller line width, which can make room for a larger storage node contact hole, further improving the yield and performance of the resulting semiconductor structure. .
  • step S300 forms a bit line contact isolation layer, which may include the following steps:
  • S310 Form a first isolation layer; the first isolation layer at least covers the sidewalls of the bit line contact holes.
  • S320 Form a second isolation layer; the second isolation layer covers the exposed side of the first isolation layer.
  • S330 Form a third isolation layer, and the third isolation layer covers the exposed side of the second isolation layer.
  • the first isolation layer, the second isolation layer and the third isolation layer constitute a bit line contact isolation layer.
  • step S310 forms the first isolation layer, which may include the following steps:
  • S311 Form a first isolation material layer; the first isolation material layer covers the surface of the substrate where the bit line contact hole is formed, the sidewalls of the bit line contact hole, and the bottom of the bit line contact hole.
  • S312 Remove the first isolation material layer located on the substrate surface and the bottom of the bit line contact hole; the remaining first isolation material layer is the first isolation layer.
  • Step S320 forms a second isolation layer, which may include the following steps:
  • S321 Form a second isolation material layer; the second isolation material layer covers the surface of the substrate where the bit line contact hole is formed, the surface of the first isolation layer and the bottom of the bit line contact hole.
  • S322 Remove the second isolation material layer located on the substrate surface, the upper surface of the first isolation layer and the bottom of the bit line contact hole; the remaining second isolation material layer is the second isolation layer.
  • Step S330 forms the third isolation layer, which may include the following steps:
  • S331 Form a third isolation material layer; the third isolation material layer covers the surface of the substrate where the bit line contact hole is formed, the surface of the second isolation layer and the bottom of the bit line contact hole.
  • S332 Remove the third isolation material layer located on the substrate surface, the upper surface of the first isolation layer, the upper surface of the second isolation layer and the bottom of the bit line contact hole; the remaining third isolation material layer is the third isolation layer.
  • a polysilicon layer is further formed on the upper surface of the substrate.
  • the first conductive material layer, the second conductive material layer and the insulating dielectric material layer may be etched using a reactive gas with a selectivity ratio of greater than or equal to 10:1 for the polysilicon layer.
  • step S100 referring to FIG. 10, a substrate 1 is provided.
  • the substrate 1 may include, but is not limited to, a silicon (Si) substrate, a sapphire substrate, a glass substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate. Any one or more of the bottom or silicon-on-insulator (SOI) substrates, etc.
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • GaAs gallium arsenide
  • a shallow trench isolation structure 11 can be formed in the substrate 1 , and the shallow trench isolation structure 11 can isolate a plurality of spaced-apart active components in the substrate 1 . District 12.
  • the shallow trench isolation structure 11 may include a single layer or multiple layers of insulating materials, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon nitride carbide or other suitable insulating materials.
  • step S200 please continue to refer to FIG. 10 to form a bit line contact hole 2 in the substrate 1 .
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the method of forming the bit line contact hole 2 .
  • the bit line contact hole 2 may be formed in the substrate 1 by, but is not limited to, dry etching.
  • the following steps can be used to form the bit line contact hole 2 in the substrate 1, such as: forming a patterned mask layer 5.
  • the patterned mask layer 103 should cover the substrate 1. surface, and has an opening for defining the shape and position of the bit line contact hole 2; after forming the patterned mask layer 5, the substrate 1 is etched based on the patterned mask layer 5 to form a bit line in the substrate 1 Line contact hole 2.
  • bit line contact hole 2 should be located on the active area 12 so that the bit line contact structure 3 formed in the subsequent process can be in contact with the active area 12 contact.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the material of the patterned mask layer 103.
  • the patterned mask layer 103 may include, but is not limited to, a carbon layer, a silicon nitride layer, an amorphous carbon layer (ACL), a silicon oxynitride layer, and a spin-on hard mask ( Spin-On Hard-Mask (SOH for short) layer and so on.
  • bit line contact isolation layer 31 is formed. Specifically, the bit line contact isolation layer 31 should at least cover the side walls of the bit line contact hole 2 .
  • the manufacturing method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the structure of the bit line contact isolation layer 31 .
  • the bit line contact isolation layer 31 may include, but is not limited to, a first isolation layer 311 , a second isolation layer 312 and a third isolation layer 313 .
  • step S300 may specifically include the following steps:
  • S310 Form a first isolation layer 311; the first isolation layer 311 should at least cover the sidewalls of the bit line contact hole 2.
  • S320 Form a second isolation layer 312; the second isolation layer 312 should cover the exposed side of the first isolation layer 311;
  • S330 Form a third isolation layer 313, which should cover the exposed side of the second isolation layer 312.
  • the first isolation layer 311 is formed in step S310, which may include the following steps:
  • S311 Form a first isolation material layer 3110; the first isolation material layer 3110 covers the surface of the substrate 1 where the bit line contact hole 2 is formed, the sidewalls of the bit line contact hole 2 and the bottom of the bit line contact hole 2.
  • S312 Remove the first isolation material layer 3110 located on the surface of the substrate 1 and the bottom of the bit line contact hole 2; the remaining first isolation material layer 3110 is the first isolation layer 311.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the method of removing the first isolation material layer 3110 located on the surface of the substrate 1 and the bottom of the bit line contact hole 2 .
  • a dry etching process may be used to remove the first isolation material layer 3110 located on the surface of the substrate 1 and the bottom of the bit line contact hole 2 .
  • forming the second isolation layer 312 in step S320 may include the following steps:
  • S321 Form a second isolation material layer 3120; the second isolation material layer 3120 covers the surface of the substrate 1 on which the bit line contact hole 2 is formed, the surface of the first isolation layer 311 and the bottom of the bit line contact hole 2.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the method of removing the second isolation material layer 3120 located on the surface of the substrate 1 , the upper surface of the first isolation layer 311 and the bottom of the bit line contact hole 2 .
  • a dry etching process may be used, but is not limited to, to remove the second isolation material layer 3120 located on the surface of the substrate 1 , the upper surface of the first isolation layer 311 and the bottom of the bit line contact hole 2 .
  • the third isolation layer 313 is formed in step S330, which may include the following steps:
  • S331 Form a third isolation material layer 3130; the third isolation material layer 3130 covers the surface of the substrate 1 on which the bit line contact hole 2 is formed, the surface of the second isolation layer 312 and the bottom of the bit line contact hole 2.
  • S332 Remove the third isolation material layer 3130 located on the surface of the substrate 1, the upper surface of the first isolation layer 311, the upper surface of the second isolation layer 312 and the bottom of the bit line contact hole 2; the remaining third isolation material layer 3130 is The third isolation layer 313.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure is to remove the third isolation material layer 3130 located on the surface of the substrate 1 , the upper surface of the first isolation layer 311 , the upper surface of the second isolation layer 312 and the bottom of the bit line contact hole 2
  • the method is not specifically limited.
  • a dry etching process may be used, but is not limited to, to remove the third isolation material layer located on the surface of the substrate 1 , the upper surface of the first isolation layer 311 , the upper surface of the second isolation layer 312 and the bottom of the bit line contact hole 2 3130.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the materials of the first isolation layer 311, the second isolation layer 312, and the third isolation layer 313.
  • the first isolation layer 311 and the third isolation layer 313 may each include a nitride layer; the second isolation layer 312 may include an oxide layer. In this way, the first isolation layer 311 , the second isolation layer 312 and the third isolation layer 313 can form the bit line contact isolation layer 31 of the N-O-N structure.
  • the materials of the first isolation layer 311 and the third isolation layer 313 may include but are not limited to silicon nitride, silicon oxynitride, and the like.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the materials of the first isolation material layer 3110, the second isolation material layer 3120, and the third isolation material layer 3130. It can be understood that the materials of the first isolation material layer 3110, the second isolation material layer 3120 and the third isolation material layer 3130 should be adapted according to the materials of the first isolation layer 311, the second isolation layer 312 and the third isolation layer 313 respectively. choose.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the method of forming the first isolation material layer 3110, the second isolation material layer 3120, and the third isolation material layer 3130.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • PCVD high-density plasma deposition
  • plasma can be used, but are not limited to
  • the enhanced deposition process Pasma Enhanced Chemical Vapor Deposition, referred to as PECVD
  • Atomic layer deposition referred to as ALD
  • a first isolation material layer 3110 is formed at the bottom of the line contact hole 2 .
  • the second isolation material layer 3120 and the third isolation material layer 3130 can also be deposited and formed using the aforementioned process.
  • the method for preparing the semiconductor structure in the embodiment of the present disclosure does not specifically limit the thickness of the first isolation layer 311, the second isolation layer 312, and the third isolation layer 313.
  • the thickness of the first isolation layer 311 may be 3 nm to 5 nm; for example, the thickness of the first isolation layer 311 may be 3 nm, 4 nm, or 5 nm, and so on.
  • the thickness of the second isolation layer 312 may be 0.5 nm to 1.5 nm; for example, the thickness of the second isolation layer 312 may be 0.5 nm, 1 nm, or 1.5 nm, and so on.
  • the thickness of the third isolation layer 313 may be 8 nm to 10 nm; for example, the thickness of the third isolation layer 313 may be 8 nm, 9 nm, or 10 nm, and so on.
  • the thickness of the first isolation layer 311 is 4 nm
  • the thickness of the second isolation layer 312 is 1 nm
  • the thickness of the third isolation layer 313 is 9 nm.
  • step S400 referring to FIGS. 17 and 18 , the bit line contact layer 32 is formed. Specifically, the bit line contact layer 32 should fill the bit line contact hole 2 .
  • bit line contact layer 32 and the bit line contact isolation layer 31 together constitute the bit line contact structure 3 .
  • the manufacturing method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the material of the bit line contact layer 32 in step S400.
  • the material of the bit line contact layer 32 may include any one or more of polysilicon (Poly), titanium nitride (TiN), and/or tungsten (W).
  • the material of the bit line contact layer 32 is polysilicon; the deposition material of the bit line contact layer 32 may include but is not limited to silane (Silane) or disilane (disilane), and may be doped with boron ( B), any one or more of arsenic (As), phosphorus (P) or germanium (Ge) elements, etc.
  • bit line contact layer 32 in step S400 may include the following steps:
  • bit line contact material layer 320 Form the bit line contact material layer 320; specifically, the bit line contact material layer 320 should fill the bit line contact hole 2 and cover the surface of the substrate 1 on which the bit line contact hole 2 is formed.
  • the manufacturing method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the material of the bit line contact material layer 320 in step S410. It can be understood that the material of the bit line contact material layer 320 should be adaptively selected according to the material of the bit line contact layer 32 .
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the method of removing the bit line contact material layer 320 on the surface of the substrate 1 in step S420.
  • a dry etching process or a chemical mechanical polishing (CMP) process can be used to remove the bit line contact material layer 320 located on the surface of the substrate 1 .
  • bit line stack 4 is formed. Specifically, the bit line stack 4 is located on the upper surface of the bit line contact structure 3 .
  • the manufacturing method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the structure of the bit line stack 4 .
  • the bit line stack 4 may include a first conductive layer 41, a second conductive layer 42 and an insulating dielectric layer 43 stacked in sequence from bottom to top.
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the materials of the first conductive layer 41, the second conductive layer 42 and the insulating dielectric layer 43 in step S500.
  • the material of the first conductive layer 41 may include but is not limited to titanium (Ti) or titanium nitride.
  • the material of the second conductive layer 42 may include but is not limited to tungsten.
  • the material of the insulating dielectric layer 43 may include but is not limited to silicon nitride, silicon oxynitride, spin-on carbon (SOC) or other carbon-containing organic materials.
  • the material of the second conductive layer 42 is tungsten, and the second conductive layer 42 can be used as a metal conductive layer; on this basis, the material of the first conductive layer 41 is titanium nitride, and the first conductive layer 42 can be made of titanium nitride.
  • the conductive layer 41 acts as a metal barrier layer to prevent tungsten diffusion of the second conductive layer 42 .
  • step S500 may specifically include the following steps:
  • S510 Form a first conductive material layer 410, a second conductive material layer 420 and an insulating dielectric material layer 430 sequentially stacked from bottom to top on the surface of the bit line contact structure 3 and the surface of the substrate 1 on which the bit line contact hole 2 is formed. .
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the materials of the first conductive material layer 410, the second conductive material layer 420 and the insulating dielectric material layer 430 formed in step S510. It can be understood that the materials of the first conductive material layer 410 , the second conductive material layer 420 and the insulating dielectric material layer 430 should be adaptively selected according to the materials of the first conductive layer 41 , the second conductive layer 42 and the insulating dielectric layer 43 .
  • step S520 the first conductive material layer 410, the second conductive material layer 420 and the insulating dielectric material layer 430 are etched to form the first conductive layer 41, the second conductive layer 42 and
  • the form of the insulating dielectric layer 43 is not specifically limited.
  • the following steps can be used to form the first conductive layer 41 , the second conductive layer 42 and the insulating dielectric layer 43 , such as: forming a mask pattern 6 on the upper surface of the insulating dielectric material layer 430 ; after forming the mask pattern 6 , perform a pattern transfer process to etch the insulating dielectric material layer 430, the second conductive material layer 420 and the first conductive material layer 410 based on the mask pattern 6, so as to transfer the mask pattern 6 to the first conductive material layer 410, the second conductive material layer 410 and the first conductive material layer 410. on the conductive material layer 420 and the insulating dielectric material layer 430, thereby forming the first conductive layer 41, the second conductive layer 42 and the insulating dielectric layer 43.
  • the embodiment of the present disclosure also does not specifically limit the method of forming the mask pattern 6 .
  • the following methods can be used to form the mask pattern 6, such as: using a coating-curing method, an inkjet printing method, or a deposition method to form a photoresist layer covering the upper surface of the resulting structure; and exposing the aforementioned photoresist layer. , development, etching and other patterning processing methods to obtain the mask pattern 6.
  • Mask pattern 6 may define the shape of bit line stack 4 .
  • the preparation method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the method of forming the first conductive layer 41 with a cross-section similar to a trapezoid.
  • a polysilicon layer 7 is also formed on the upper surface of the substrate 1 .
  • the first conductive layer 41 with a cross-section similar to a trapezoid can be formed in the following manner, for example: etching the insulating dielectric material layer 430, the second conductive material layer 420 and the first conductive layer 41 based on the mask pattern 6.
  • a reactive gas with a selectivity ratio of polysilicon/nitrogen (oxygen) material greater than or equal to 10:1 can be used to continue etching in the subsequent etching process; for example, a combination of hydrobromic acid and oxygen (HBr- O2) can achieve a selection ratio greater than 100:1.
  • HBr- O2 hydrobromic acid and oxygen
  • the manufacturing method of the semiconductor structure in the embodiment of the present disclosure does not specifically limit the size of the bit line stack 4 .
  • the width of the bitline stack 4 may be the same as the width of the top of the bitline contact structure 3 .
  • the width of the bit line stack 4 may be smaller than the width of the top of the bit line contact structure 3 , but should not be smaller than the width of the top of the bit line contact layer 32 .
  • Embodiments of the present disclosure also provide a semiconductor structure according to some embodiments.
  • the semiconductor structure may include a substrate 1 , a bit line contact structure 3 and a bit line stack 4 .
  • the substrate 1 may have a bit line contact hole 2 in the substrate 1 .
  • the bit line contact structure 3 may include a bit line contact isolation layer 31 and a bit line contact layer 32; wherein, the bit line contact isolation layer 31 should at least cover the side walls of the bit line contact hole 2, and the bit line contact layer 32 should fill the bit line contact hole 2.
  • the bit line stack 4 may be located on the upper surface of the bit line contact structure 3 .
  • the semiconductor structure provided by the above embodiment has a bit line contact structure 3; since the bit line contact isolation layer 31 in the bit line contact structure 3 covers the side walls of the bit line contact hole 2, it can reduce the overlap between the bit line contact structure 3 and the bit line. Effect of parasitic coupling between layers 4.
  • the bit line contact layer 32 in the bit line contact structure 3 fills the bit line contact hole 2 so that the bit line stack 4 located on the upper surface of the bit line contact structure 3 can be effectively protected.
  • this can prevent the middle and bottom of the bit line stack 4 from being eroded due to defects such as condensation. Therefore, the semiconductor structure provided by the embodiment of the present disclosure has better yield and performance.
  • the substrate 1 may include, but is not limited to, any of a silicon substrate, a sapphire substrate, a glass substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon-clad insulating substrate, and the like. One or several.
  • the substrate 1 may have a shallow trench isolation structure 11 , and the shallow trench isolation structure 11 may isolate a plurality of spaced-apart active areas in the substrate 1 12.
  • the bit line contact hole 2 should be located on the active area 12 so that the bit line contact structure 3 can be in contact with the active area 12 .
  • the shallow trench isolation structure 11 may include a single layer or multiple layers of insulating materials, such as silicon nitride, silicon oxynitride, silicon nitride carbide or other suitable insulating materials.
  • the material of the bit line contact layer 32 of the semiconductor structure in the embodiment of the present disclosure is not specifically limited.
  • the material of the bit line contact layer 32 may include any one or more of polysilicon, titanium nitride, and/or tungsten.
  • the bit line stack 4 may include a first conductive layer 41 , a second conductive layer 42 and an insulating dielectric layer 43 sequentially stacked from bottom to top.
  • the semiconductor structure in the embodiment of the present disclosure has no specific limitations on the materials of the first conductive layer 41 , the second conductive layer 42 and the insulating dielectric layer 43 .
  • the material of the first conductive layer 41 may include but is not limited to titanium or titanium nitride.
  • the material of the second conductive layer 42 may include but is not limited to tungsten.
  • the material of the insulating dielectric layer 43 may include but is not limited to silicon nitride.
  • the semiconductor structure in the embodiment of the present disclosure does not specifically limit the size of the bit line stack 4.
  • the width of the bitline stack 4 may be the same as the width of the top of the bitline contact structure 3 .
  • the width of the bit line stack 4 is smaller than the width of the top of the bit line contact structure 3 and not smaller than the width of the top of the bit line contact layer 32 .
  • the semiconductor structure provided by the above embodiment has a first conductive layer 41 with a cross-section similar to a trapezoid, which can protect the bit line contact isolation layer 31 .
  • the semiconductor structure provided by the above embodiments has a bit line stack 4 with a smaller line width, thereby making room for a larger storage node contact hole, further improving the yield and performance of the resulting semiconductor structure.
  • the semiconductor structure in the embodiment of the present disclosure does not specifically limit the structure of the bit line contact isolation layer 31 .
  • the bit line contact isolation layer 31 may include, but is not limited to, a first isolation layer 311 , a second isolation layer 312 , and a third isolation layer 313 .
  • the first isolation layer 311 at least covers the side walls of the bit line contact hole 2; the second isolation layer 312 covers the exposed side of the first isolation layer 311; and the third isolation layer 313 covers the exposed side of the second isolation layer 312.
  • the semiconductor structure in the embodiment of the present disclosure has no specific limitations on the materials of the first isolation layer 311, the second isolation layer 312, and the third isolation layer 313.
  • the first isolation layer 311 and the third isolation layer 313 may each include a nitride layer; the second isolation layer 312 may include an oxide layer. In this way, the first isolation layer 311 , the second isolation layer 312 and the third isolation layer 313 can form the bit line contact isolation layer 31 of the N-O-N structure.
  • the materials of the first isolation layer 311 and the third isolation layer 313 may include but are not limited to silicon nitride, silicon oxynitride, and the like.
  • the semiconductor structure in the embodiment of the present disclosure does not specifically limit the thickness of the first isolation layer 311, the second isolation layer 312, and the third isolation layer 313.
  • the thickness of the first isolation layer 311 may be 3 nm to 5 nm; for example, the thickness of the first isolation layer 311 may be 3 nm, 4 nm, or 5 nm, and so on.
  • the thickness of the second isolation layer 312 may be 0.5 nm to 1.5 nm; for example, the thickness of the second isolation layer 312 may be 0.5 nm, 1 nm, or 1.5 nm, and so on.
  • the thickness of the third isolation layer 313 may be 8 nm to 10 nm; for example, the thickness of the third isolation layer 313 may be 8 nm, 9 nm, or 10 nm, and so on.
  • the thickness of the first isolation layer 311 is 4 nm
  • the thickness of the second isolation layer 312 is 1 nm
  • the thickness of the third isolation layer 313 is 9 nm.
  • the execution of the steps is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least part of the steps described may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The order of execution is not necessarily sequential, but may be performed in turn or alternately with other steps or sub-steps of other steps or at least part of the stages.

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Abstract

本公开实施例涉及一种半导体结构及其制备方法。本公开实施例提供的制备方法包括：提供衬底；于衬底内形成位线接触孔；形成位线接触隔离层；位线接触隔离层至少覆盖位线接触孔的侧壁；形成位线接触层；位线接触层填满位线接触孔；位线接触层与位线接触隔离层共同构成位线接触结构；形成位线叠层；位线叠层位于位线接触结构的上表面。本公开实施例提供的制备方法，能够减少耦合作用产生的影响；使得位线叠层在其制备过程中能够被有效地保护在位线接触隔离层中，并能够避免位线叠层的中部和底部被其制备过程中生成的凝结侵蚀，从而提升制备方法的良率和性能。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开实施例要求于2022年6月29日提交中国专利局、申请号为202210753396.1的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开实施例中。
技术领域
本公开实施例涉及半导体集成电路制造技术领域，特别是涉及半导体结构及其制备方法。
背景技术
在动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)制造过程中，器件结构尺寸正在逐渐减小，关键尺寸已经达到20nm以下。这导致相邻金属之间寄生的耦合效应越来越明显，并且密集程度越高，耦合效应则越明显，其必然会影响电路的开启速度甚至电路的良率和可靠性。
同时，在先进制程中，尤其在20nm以下线宽的位元线制程中，由于关键尺寸(Critical Dimension，CD)太小，使用的干法蚀刻或湿法清洗工艺中产生的副产物和反应化学品残留会容易生成凝结(Condense)等缺陷，从而对于已经形成的位元线的中部和底部进行侵蚀，最终导致位元线无法正常工作，降低器件的良率和性能。
发明内容
根据本公开实施例的各种实施例，提供一种半导体结构及其制备方法。
根据一些实施例，本公开实施例一方面提供一种半导体结构的制备方法，包括：
提供衬底；
于所述衬底内形成位线接触孔；
形成位线接触隔离层；所述位线接触隔离层至少覆盖所述位线接触孔的侧壁；
形成位线接触层；所述位线接触层填满所述位线接触孔；所述位线接触层与所述位线接触隔离层共同构成位线接触结构；
形成位线叠层；所述位线叠层位于所述位线接触结构的上表面。
根据一些实施例，所述形成位线接触层，包括：
形成位线接触材料层；所述位线接触材料层填满所述位线接触孔，并覆盖所述衬底形成有所述位线接触孔的表面；
去除位于所述衬底表面的所述位线接触材料层；保留的所述位线接触材料层为所述位线接触层。
根据一些实施例，所述位线叠层包括由下至上依次叠置的第一导电层、第二导电层及绝缘介质层。
根据一些实施例，所述形成位线叠层，包括：
于所述位线接触结构的表面及所述衬底形成有所述位线接触孔的表面形成由下至上依次叠置的第一导电材料层、第二导电材料层及绝缘介质材料层；
刻蚀所述第一导电材料层、所述第二导电材料层及所述绝缘介质材料层，保留的所述第一导电材料层、所述第二导电材料层及所述绝缘介质材料层分别作为所述第一导电层、所述第二导电层及所述绝缘介质层以构成所述位线叠层。
根据一些实施例，所述位线叠层的宽度与所述位线接触结构的顶部的宽度相同。
根据一些实施例，所述位线叠层的宽度小于所述位线接触结构的顶部的宽度且不小于所述位线接触层的顶部的宽度。
根据一些实施例，所述形成位线接触隔离层，包括：
形成第一隔离层；所述第一隔离层至少覆盖所述位线接触孔的侧壁；
形成第二隔离层；所述第二隔离层覆盖所述第一隔离层裸露的侧面；
形成第三隔离层，所述第三隔离层覆盖所述第二隔离层裸露的侧面；
所述第一隔离层、所述第二隔离层及所述第三隔离层构成所述位线接触隔离层。
根据一些实施例，所述形成第一隔离层，包括：
形成第一隔离材料层；所述第一隔离材料层覆盖所述衬底形成有所述位线接触孔的表面、所述位线接触孔的侧壁及所述位线接触孔的底部；
去除位于所述衬底表面及所述位线接触孔底部的所述第一隔离材料层；保留的所述第一隔离材料层为所述第一隔离层；
所述形成第二隔离层，包括：
形成第二隔离材料层；所述第二隔离材料层覆盖所述衬底形成有所述位线接触孔的表面、所述第一隔离层的表面及所述位线接触孔的底部；
去除位于所述衬底表面、所述第一隔离层的上表面及所述位线接触孔底部的所述第二隔离材料层；保留的所述第二隔离材料层为所述第二隔离层；
所述形成第三隔离层，包括：
形成第三隔离材料层；所述第三隔离材料层覆盖所述衬底形成有所述位线接触孔的表面、所述第二隔离层的表面及所述位线接触孔的底部；
去除位于所述衬底表面、所述第一隔离层的上表面、所述第二隔离层的上表面及所述位线接触孔底部的所述第三隔离材料层；保留的所述第三隔离材料层为所述第三隔离层。
根据一些实施例，所述第一隔离层及所述第三隔离层均包括氮化硅层；所述第二隔离层包括氧化硅层；所述位线接触层包括多晶硅层。
根据一些实施例，所述衬底的上表面还形成有多晶硅层；
采用对所述多晶硅层具有大于或等于10∶1的选择比的反应气体刻蚀所述第一导电材料层、所述第二导电材料层及所述绝缘介质材料层。
根据一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：
衬底；所述衬底内具有位线接触孔；
位线接触结构，所述位线接触结构包括位线接触隔离层及位线接触层；所述位线接触 隔离层至少覆盖所述位线接触孔的侧壁；所述位线接触层填满所述位线接触孔；
位线叠层；所述位线叠层位于所述位线接触结构的上表面。
根据一些实施例，所述位线叠层包括由下至上依次叠置的第一导电层、第二导电层及绝缘介质层。
根据一些实施例，所述位线叠层的宽度与所述位线接触结构的顶部的宽度相同。
根据一些实施例，所述位线叠层的宽度小于所述位线接触结构的顶部的宽度且不小于所述位线接触层的顶部的宽度。
根据一些实施例，所述位线接触隔离层包括：
第一隔离层；所述第一隔离层至少覆盖所述位线接触孔的侧壁；
第二隔离层；所述第二隔离层覆盖所述第一隔离层裸露的侧面；
第三隔离层，所述第三隔离层覆盖所述第二隔离层裸露的侧面。
根据一些实施例，所述第一隔离层及所述第三隔离层均包括氮化硅层；所述第二隔离层包括氧化硅层；所述位线接触层包括多晶硅层。
根据一些实施例，所述第一隔离层的厚度为3nm～5nm；所述第二隔离层的厚度为0.5nm～1.5nm；所述第三隔离层的厚度为8nm～10nm。
本公开实施例可以/至少具有以下优点：
本公开实施例提供的半导体结构的制备方法，通过形成覆盖位线接触孔侧壁的位线接触隔离层，能够减少耦合作用产生的影响；通过在形成位线叠层之前在位线接触孔内填满位线接触层，使得位线叠层在其制备过程中能够被有效地保护在位线接触隔离层中，避免位线叠层的中部和底部被其制备过程中生成的凝结侵蚀，从而提升制备方法的良率和性能。
本公开实施例提供的半导体结构，具有位线接触结构；位线接触结构中的位线接触隔离层，由于覆盖位线接触孔的侧壁，能够减少耦合作用产生的影响；位线接触结构中的位线接触层，填满位线接触孔，使得位于位线接触结构上表面的位线叠层能够被有效地保护在位线接触隔离层中，这样能够避免位线叠层的中部和底部因生成凝结而被侵蚀，故本公开实施例提供的半导体结构具有较好的良率和性能。
本公开实施例的一个或多个实施例的细节在下面的附图和描述中提出。本公开实施例的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1至图2为一些传统制备方法过程中所得结构的截面结构示意图；
图3为本公开一实施例提供的半导体结构的制备方法的流程图；
图4至图9为本公开不同实施例提供的半导体结构的制备方法中，各步骤的流程图；
图10至图21为本公开不同实施例提供的半导体结构的制备方法中，各步骤所得结构 的截面结构示意图。
具体实施方式
为了便于理解本公开，下面将参考相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
请参阅图1至图21。需要说明的是，本实施例中所提供的图示仅以示意方式说明本公开的基本构想，虽图示中仅显示与本公开中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
在先进制程中，例如在20nm以下线宽的位元线制程中，如图1至图2所示，可以在位元线材料叠层40'的上表面形成掩膜层6'，然后通过干法刻蚀工艺将掩膜层6'定义出的 图案转移至位元线材料叠层40'，以形成位元线结构40'。
由于关键尺寸太小，使用的干法蚀刻或湿法清洗工艺中产生的副产物和反应化学品残留会容易生成凝结等缺陷，从而对于已经形成的位元线的中部和底部进行侵蚀，最终导致位元线无法正常工作，降低器件的良率和性能。
基于此，本公开实施例根据一些实施例，提供一种半导体结构的制备方法。
请参阅图3，在其中一个实施例中，所述半导体结构的制备方法可以包括如下步骤：
S100：提供衬底。
S200：于衬底内形成位线接触孔。
S300：形成位线接触隔离层；位线接触隔离层至少覆盖位线接触孔的侧壁。
S400：形成位线接触层；位线接触层填满位线接触孔；位线接触层与位线接触隔离层共同构成位线接触结构。
S500：形成位线叠层；位线叠层位于位线接触结构的上表面。
上述实施例提供的半导体结构的制备方法，通过形成覆盖位线接触孔侧壁的位线接触隔离层，能够减少位线接触层与位线叠层之间寄生耦合作用产生的影响。
并且，上述实施例提供的半导体结构的制备方法，还通过在形成位线叠层之前在位线接触孔内填满位线接触层，使得位线叠层在其制备过程中能够被有效地保护在位线接触隔离层中，避免位线叠层的中部和底部被其制备过程中生成的凝结等缺陷的侵蚀，从而提升制备方法的良率和性能。
请参阅图4，在其中一个实施例中，步骤S400中形成位线接触层，可以包括如下步骤：
S410：形成位线接触材料层；位线接触材料层填满位线接触孔，并覆盖衬底形成有位线接触孔的表面。
S420：去除位于衬底表面的位线接触材料层；保留的位线接触材料层为位线接触层。
在其中一个实施例中，位线叠层可以包括由下至上依次叠置的第一导电层、第二导电层及绝缘介质层。
请参阅图5，在其中一个实施例中，步骤S500中形成位线叠层，可以包括如下步骤：
S510：于位线接触结构的表面及衬底形成有位线接触孔的表面形成由下至上依次叠置的第一导电材料层、第二导电材料层及绝缘介质材料层。
S520：刻蚀第一导电材料层、第二导电材料层及绝缘介质材料层，保留的第一导电材料层、第二导电材料层及绝缘介质材料层分别作为第一导电层、第二导电层及绝缘介质层以构成位线叠层。
在一些可能的实施例中，位线叠层的宽度与位线接触结构的顶部的宽度相同。
在另一些可能的实施例中，位线叠层的宽度小于位线接触结构的顶部的宽度且不小于位线接触层的顶部的宽度。
上述实施例提供的半导体结构的制备方法，通过形成截面类似于梯形的第一导电层，可以对位线接触隔离层起到保护作用。同时，上述实施例提供的半导体结构的制备方法得到的位线叠层具有更小的线宽，从而能够让出空间以得到更大的存储节点接触孔，进一步 提升所得半导体结构的良率和性能。
请参阅图6，在其中一个实施例中，步骤S300形成位线接触隔离层，可以包括如下步骤：
S310：形成第一隔离层；第一隔离层至少覆盖位线接触孔的侧壁。
S320：形成第二隔离层；第二隔离层覆盖第一隔离层裸露的侧面。
S330：形成第三隔离层，第三隔离层覆盖第二隔离层裸露的侧面。
第一隔离层、第二隔离层及第三隔离层构成位线接触隔离层。
请参阅图7至图9，在其中一个实施例中，步骤S310形成第一隔离层，可以包括如下步骤：
S311：形成第一隔离材料层；第一隔离材料层覆盖衬底形成有位线接触孔的表面、位线接触孔的侧壁及位线接触孔的底部。
S312：去除位于衬底表面及位线接触孔底部的第一隔离材料层；保留的第一隔离材料层为第一隔离层。
步骤S320形成第二隔离层，可以包括如下步骤：
S321：形成第二隔离材料层；第二隔离材料层覆盖衬底形成有位线接触孔的表面、第一隔离层的表面及位线接触孔的底部。
S322：去除位于衬底表面、第一隔离层的上表面及位线接触孔底部的第二隔离材料层；保留的第二隔离材料层为第二隔离层。
步骤S330形成第三隔离层，可以包括如下步骤：
S331：形成第三隔离材料层；第三隔离材料层覆盖衬底形成有位线接触孔的表面、第二隔离层的表面及位线接触孔的底部。
S332：去除位于衬底表面、第一隔离层的上表面、第二隔离层的上表面及位线接触孔底部的第三隔离材料层；保留的第三隔离材料层为第三隔离层。
在其中一个实施例中，衬底的上表面还形成有多晶硅层。在步骤S520中，可以采用对多晶硅层具有大于或等于10∶1的选择比的反应气体刻蚀第一导电材料层、第二导电材料层及绝缘介质材料层。
为了更清楚的说明上述一些实施例中的制备方法，以下请结合图10至图理解本公开实施例提供的一些实施例。
在步骤S100中，请参阅图10，提供衬底1。
本公开实施例中半导体结构的制备方法对于衬底1的材质并不做具体限定。作为示例，衬底1可以包括但不限于硅(Si)衬底、蓝宝石衬底、玻璃衬底、碳化硅(SiC)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底或硅覆绝缘(silicon-on-insulator，简称SOI)衬底等等中的任意一种或几种。
在一些可能的实施例中，如图10所示，衬底1内可以形成有浅沟槽隔离结构11，浅沟槽隔离结构11可以在衬底1内隔离出多个间隔排布的有源区12。作为示例，浅沟槽隔离结构11可以包括单层或多层的绝缘材料，例如氮化硅(SiN)、氮氧化硅(SiON)、氮碳化硅或其他适合的绝缘材料。
在步骤S200中，请继续参阅图10，于衬底1内形成位线接触孔2。
本公开实施例中半导体结构的制备方法对于形成位线接触孔2的方式并不做具体限定。作为示例，可以采用但不仅限于干法刻蚀的方式在衬底1内形成位线接触孔2。
请继续参阅图10，作为示例，可以采用如下的步骤在衬底1内形成位线接触孔2，比如：形成图形化掩模层5，图形化掩模层103应当覆盖于衬底1的上表面，且具有用于定义位线接触孔2的形状及位置的开口；在形成图形化掩模层5之后，基于图形化掩模层5刻蚀衬底1，以于衬底1内形成位线接触孔2。
需要说明的是，如图10所示，在一些可能的实施例中，位线接触孔2应当位于有源区12上，以使得后续制程中形成的位线接触结构3能够与有源区12相接触。
本公开实施例中半导体结构的制备方法对于图形化掩模层103的材质并不做具体限定。作为示例，图形化掩模层103可以包括但不限于碳(Carbon)层、氮化硅层、非晶碳层(Armorphous Carbon Layer，简称ACL)、氮氧化硅层及旋涂式硬掩模(Spin-On Hard-Mask，简称SOH)层等等。
在步骤S300中，请参阅图11至图16，形成位线接触隔离层31。具体的，位线接触隔离层31应当至少覆盖位线接触孔2的侧壁。
本公开实施例中半导体结构的制备方法对于位线接触隔离层31的结构并不做具体限定。作为示例，位线接触隔离层31可以包括但不限于由第一隔离层311、第二隔离层312及第三隔离层313构成。
在其中一个实施例中，步骤S300具体可以包括如下的步骤：
S310：形成第一隔离层311；第一隔离层311应当至少覆盖位线接触孔2的侧壁。
S320：形成第二隔离层312；第二隔离层312应当覆盖第一隔离层311裸露的侧面；
S330：形成第三隔离层313，第三隔离层313应当覆盖第二隔离层312裸露的侧面。
作为示例，请参阅图11至图12，步骤S310中形成第一隔离层311，具体可以包括如下的步骤：
S311：形成第一隔离材料层3110；第一隔离材料层3110覆盖衬底1形成有位线接触孔2的表面、位线接触孔2的侧壁及位线接触孔2的底部。
S312：去除位于衬底1表面及位线接触孔2底部的第一隔离材料层3110；保留的第一隔离材料层3110为第一隔离层311。
本公开实施例中半导体结构的制备方法对于去除位于衬底1表面及位线接触孔2底部的第一隔离材料层3110的方式并不做具体限定。作为示例，可以采用但不仅限于干法刻蚀工艺去除位于衬底1表面及位线接触孔2底部的第一隔离材料层3110。
作为示例，请参阅图13至图14，步骤S320中形成第二隔离层312，具体可以包括如下的步骤：
S321：形成第二隔离材料层3120；第二隔离材料层3120覆盖衬底1形成有位线接触孔2的表面、第一隔离层311的表面及位线接触孔2的底部。
S322：去除位于衬底1表面、第一隔离层311的上表面及位线接触孔2底部的第二隔离材料层3120；保留的第二隔离材料层3120为第二隔离层312。
本公开实施例中半导体结构的制备方法对于去除位于衬底1表面、第一隔离层311的上表面及位线接触孔2底部的第二隔离材料层3120的方式并不做具体限定。作为示例，可以采用但不仅限于干法刻蚀工艺去除位于衬底1表面、第一隔离层311的上表面及位线接触孔2底部的第二隔离材料层3120。
作为示例，请参阅图15至图16，步骤S330中形成第三隔离层313，具体可以包括如下的步骤：
S331：形成第三隔离材料层3130；第三隔离材料层3130覆盖衬底1形成有位线接触孔2的表面、第二隔离层312的表面及位线接触孔2的底部。
S332：去除位于衬底1表面、第一隔离层311的上表面、第二隔离层312的上表面及位线接触孔2底部的第三隔离材料层3130；保留的第三隔离材料层3130为第三隔离层313。
本公开实施例中半导体结构的制备方法对于去除位于衬底1表面、第一隔离层311的上表面、第二隔离层312的上表面及位线接触孔2底部的第三隔离材料层3130的方式并不做具体限定。作为示例，可以采用但不仅限于干法刻蚀工艺去除位于衬底1表面、第一隔离层311的上表面、第二隔离层312的上表面及位线接触孔2底部的第三隔离材料层3130。
本公开实施例中半导体结构的制备方法对于第一隔离层311、第二隔离层312及第三隔离层313的材质均不做具体限定。在其中一个实施例中，第一隔离层311及第三隔离层313可以均包括氮化物层；第二隔离层312可以包括氧化物层。如此，第一隔离层311、第二隔离层312及第三隔离层313可以构成N-O-N结构的位线接触隔离层31。
作为示例，第一隔离层311及第三隔离层313的材质可以包括但不仅限于氮化硅或氮氧化硅等等。
本公开实施例中半导体结构的制备方法对于第一隔离材料层3110、第二隔离材料层3120及第三隔离材料层3130的材质亦不做具体限定。可以理解，第一隔离材料层3110、第二隔离材料层3120及第三隔离材料层3130的材质应当分别根据第一隔离层311、第二隔离层312及第三隔离层313的材质进行适应性选择。
本公开实施例中半导体结构的制备方法对于形成第一隔离材料层3110、第二隔离材料层3120及第三隔离材料层3130的方式亦不做具体限定。作为示例，可以采用但不限于化学气相沉积工艺(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)、高密度等离子沉积工艺(plasma chemical vapor deposition，简称PCVD)、等离子体增强沉积工艺(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)或原子层沉积(Atomic layer deposition，简称ALD)工艺在衬底1的表面位线接触孔2的表面、位线接触孔2的侧壁及位线接触孔2的底部形成第一隔离材料层3110。类似的，第二隔离材料层3120及第三隔离材料层3130也可以采用前述工艺沉积形成。
本公开实施例中半导体结构的制备方法对于第一隔离层311、第二隔离层312及第三隔离层313的厚度并不做具体限定。作为示例，第一隔离层311的厚度可以为3nm～5nm；譬如，第一隔离层311的厚度可以为3nm、4nm或5nm等等。作为示例，第二隔离层312 的厚度可以为0.5nm～1.5nm；譬如，第二隔离层312的厚度可以为0.5nm、1nm或1.5nm等等。作为示例，第三隔离层313的厚度可以为8nm～10nm；譬如，第三隔离层313的厚度可以为8nm、9nm或10nm等等。
在其中一个实施例中，第一隔离层311的厚度为4nm，第二隔离层312的厚度为1nm，第三隔离层313的厚度为9nm。
在步骤S400中，请参阅图17至图18，形成位线接触层32。具体的，位线接触层32应当填满位线接触孔2。
可以理解，在本公开实施例提供的半导体结构的制备方法中，位线接触层32与位线接触隔离层31共同构成位线接触结构3。
本公开实施例中半导体结构的制备方法对于步骤S400中位线接触层32的材质并不做具体限定。作为限定，位线接触层32的材质可以包括多晶硅(Poly)、氮化钛(TiN)和/或钨(W)中的任意一种或几种。
在一些可能的实施例中，位线接触层32的材质为多晶硅；位线接触层32的沉积原料可以包括但不限于硅烷(Silane)或乙硅烷(disilane)，且可以同时掺杂有硼(B)，砷(As)，磷(P)或者锗(Ge)元素等等中的任意一种或几种。
作为示例，请继续参阅图17至图18，步骤S400中形成位线接触层32，具体可以包括如下步骤：
S410：形成位线接触材料层320；具体的，位线接触材料层320应当填满位线接触孔2，并覆盖衬底1形成有位线接触孔2的表面。
S420：去除位于衬底1表面的位线接触材料层320；保留的位线接触材料层320为位线接触层32。
本公开实施例中半导体结构的制备方法对于步骤S410中位线接触材料层320的材质并不做具体限定。可以理解，位线接触材料层320的材质应当根据位线接触层32的材质进行适应性选择。
本公开实施例中半导体结构的制备方法对于步骤S420中去除位于衬底1表面的位线接触材料层320的方式并不做具体限定。作为示例，可以采用采用干法刻蚀工艺或化学机械抛光(Chemical Mechanical Polishing，简称CMP)工艺去除位于衬底1表面的位线接触材料层320。
在步骤S500中，请参阅图19至图20，形成位线叠层4。具体的，位线叠层4位于位线接触结构3的上表面。
本公开实施例中半导体结构的制备方法对于位线叠层4的结构并不做具体限定。作为示例，位线叠层4可以包括由下至上依次叠置的第一导电层41、第二导电层42及绝缘介质层43。
本公开实施例中半导体结构的制备方法对于步骤S500中第一导电层41、第二导电层42及绝缘介质层43的材质均不做具体限定。作为示例，第一导电层41的材质可以包括但不仅限于钛(Ti)或氮化钛。作为示例，第二导电层42的材质可以包括但不仅限于钨。作为示例，绝缘介质层43的材质可以包括但不仅限于氮化硅、氮氧化硅、旋涂有机碳(Spin  On Carbon，简称SOC)或其他含碳有机材料。
在其中一个实施例中，第二导电层42的材质为钨，可以将第二导电层42作为金属导电层；在此基础上，第一导电层41的材质为氮化钛，可以将第一导电层41作为金属阻挡层，以防止第二导电层42的钨扩散。
请继续参阅图19至图20，在其中一个实施例中，步骤S500具体可以包括如下的步骤：
S510：于位线接触结构3的表面及衬底1形成有位线接触孔2的表面形成由下至上依次叠置的第一导电材料层410、第二导电材料层420及绝缘介质材料层430。
S520：刻蚀第一导电材料层410、第二导电材料层420及绝缘介质材料层430，保留的第一导电材料层410、第二导电材料层420及绝缘介质材料层430分别作为第一导电层41、第二导电层42及绝缘介质层43以构成位线叠层4。
本公开实施例中半导体结构的制备方法对于步骤S510中形成的第一导电材料层410、第二导电材料层420及绝缘介质材料层430的材质均不做具体限定。可以理解，第一导电材料层410、第二导电材料层420及绝缘介质材料层430的材质应当根据第一导电层41、第二导电层42及绝缘介质层43的材质进行适应性选择。
本公开实施例中半导体结构的制备方法对于步骤S520中刻蚀第一导电材料层410、第二导电材料层420及绝缘介质材料层430，以形成第一导电层41、第二导电层42及绝缘介质层43的方式并不做具体限定。作为示例，可以采用如下的步骤形成第一导电层41、第二导电层42及绝缘介质层43，比如：在绝缘介质材料层430的上表面形成掩膜图案6；在形成掩膜图案6之后，执行图案转移工艺，基于掩膜图案6刻蚀绝缘介质材料层430、第二导电材料层420及第一导电材料层410，以将掩膜图案6转移至第一导电材料层410、第二导电材料层420及绝缘介质材料层430上，从而形成第一导电层41、第二导电层42及绝缘介质层43。
本公开实施例对于形成掩膜图案6的方式亦不做具体限定。作为示例，可以采用如下的方法形成掩膜图案6，比如：采用涂布-固化法、喷墨打印法或沉积法形成覆盖所得结构上表面的光刻胶层；对前述光刻胶层进行曝光、显影、刻蚀等图形化处理方式，以得到掩膜图案6。掩膜图案6可以定义出位线叠层4的形状。
本公开实施例中半导体结构的制备方法对于形成截面类似于梯形的第一导电层41的方式并不做具体限定。
在一些可能的实施例中，如图19所示，衬底1的上表面还形成有多晶硅层7。在此基础上，作为示例，可以采用如下的方式形成截面类似于梯形的第一导电层41，比如：基于掩膜图案6刻蚀绝缘介质材料层430、第二导电材料层420及第一导电材料层410；刻蚀到多晶硅层7时，使用对多晶硅/氮(氧)材料具有高选择比的反应气体继续后续的刻蚀工艺进行蚀刻，并去除多晶硅层7，这样可以对位线接触隔离层31起到有效保护。最终的刻蚀停止在第一隔离层311上，保留和形成了具有中部和底部位线接触隔离层31的位线叠层4。
作为示例，可以但不仅限于使用对多晶硅/氮(氧)材料具有大于或等于10∶1的选择 比的反应气体继续后续的刻蚀工艺进行蚀刻；譬如，氢溴酸和氧气的组合(HBr-O2)能达到大于100∶1的选择比。
本公开实施例中半导体结构的制备方法对于位线叠层4的尺寸并不做具体限定。
在一些可能的实施例中，如图20所示，位线叠层4的宽度可以与位线接触结构3的顶部的宽度相同。
在另一些可能的实施例中，如图21所示，位线叠层4的宽度可以小于位线接触结构3的顶部的宽度，但不应小于位线接触层32的顶部的宽度。
本公开实施例还根据一些实施例，提供一种半导体结构。
请继续参阅图20，在其中一个实施例中，所述半导体结构可以包括衬底1、位线接触结构3及位线叠层4。
如图20所示，衬底1内可以具有位线接触孔2。位线接触结构3可以包括位线接触隔离层31及位线接触层32；其中，位线接触隔离层31应当至少覆盖位线接触孔2的侧壁，位线接触层32则应当填满位线接触孔2。位线叠层4可以位于位线接触结构3的上表面。
上述实施例提供的半导体结构，具有位线接触结构3；由于位线接触结构3中的位线接触隔离层31覆盖位线接触孔2的侧壁，能够减少位线接触结构3与位线叠层4之间寄生耦合作用产生的影响。
并且，上述实施例提供的半导体结构，位线接触结构3中的位线接触层32填满位线接触孔2，使得位于位线接触结构3上表面的位线叠层4能够被有效地保护在位线接触隔离层31中，这样能够避免位线叠层4的中部和底部因生成凝结等缺陷而被侵蚀，故本公开实施例提供的半导体结构具有较好的良率和性能。
本公开实施例中的半导体结构对于衬底1的材质并不做具体限定。作为示例，衬底1可以包括但不限于硅衬底、蓝宝石衬底、玻璃衬底、碳化硅衬底、氮化镓衬底、砷化镓衬底或硅覆绝缘衬底等等中的任意一种或几种。
在一些可能的实施例中，如图20所示，衬底1内可以具有浅沟槽隔离结构11，浅沟槽隔离结构11可以在衬底1内隔离出多个间隔排布的有源区12。此时，位线接触孔2应当位于有源区12上，以使得位线接触结构3能够与有源区12相接触。作为示例，浅沟槽隔离结构11可以包括单层或多层的绝缘材料，例如氮化硅、氮氧化硅、氮碳化硅或其他适合的绝缘材料。
本公开实施例中的半导体结构位线接触层32的材质并不做具体限定。作为限定，位线接触层32的材质可以包括多晶硅、氮化钛和/或钨中的任意一种或几种。
请继续参阅图20，在其中一个实施例中，位线叠层4可以包括由下至上依次叠置的第一导电层41、第二导电层42及绝缘介质层43。
本公开实施例中的半导体结构对于第一导电层41、第二导电层42及绝缘介质层43的材质均不做具体限定。作为示例，第一导电层41的材质可以包括但不仅限于钛或氮化钛。作为示例，第二导电层42的材质可以包括但不仅限于钨。作为示例，绝缘介质层43的材质可以包括但不仅限于氮化硅。
本公开实施例中的半导体结构对于位线叠层4的尺寸并不做具体限定。
在一些可能的实施例中，如图20所示，位线叠层4的宽度可以与位线接触结构3的顶部的宽度相同。
在另一些可能的实施例中，如图21所示，位线叠层4的宽度小于位线接触结构3的顶部的宽度且不小于位线接触层32的顶部的宽度。
上述实施例提供的半导体结构，具有截面类似于梯形的第一导电层41，这可以对位线接触隔离层31起到保护作用。同时，上述实施例提供的半导体结构具有更小线宽的位线叠层4，从而能够让出空间以得到更大的存储节点接触孔，进一步提升所得半导体结构的良率和性能。
本公开实施例中的半导体结构对于位线接触隔离层31的结构并不做具体限定。作为示例，如图20所示，位线接触隔离层31可以包括但不限于由第一隔离层311、第二隔离层312及第三隔离层313构成。
具体的，第一隔离层311至少覆盖位线接触孔2的侧壁；第二隔离层312覆盖第一隔离层311裸露的侧面；第三隔离层313覆盖第二隔离层312裸露的侧面。
本公开实施例中的半导体结构对于第一隔离层311、第二隔离层312及第三隔离层313的材质均不做具体限定。在其中一个实施例中，第一隔离层311及第三隔离层313可以均包括氮化物层；第二隔离层312可以包括氧化物层。如此，第一隔离层311、第二隔离层312及第三隔离层313可以构成N-O-N结构的位线接触隔离层31。
作为示例，第一隔离层311及第三隔离层313的材质可以包括但不仅限于氮化硅或氮氧化硅等等。
本公开实施例中的半导体结构对于第一隔离层311、第二隔离层312及第三隔离层313的厚度并不做具体限定。作为示例，第一隔离层311的厚度可以为3nm～5nm；譬如，第一隔离层311的厚度可以为3nm、4nm或5nm等等。作为示例，第二隔离层312的厚度可以为0.5nm～1.5nm；譬如，第二隔离层312的厚度可以为0.5nm、1nm或1.5nm等等。作为示例，第三隔离层313的厚度可以为8nm～10nm；譬如，第三隔离层313的厚度可以为8nm、9nm或10nm等等。
在其中一个实施例中，第一隔离层311的厚度为4nm，第二隔离层312的厚度为1nm，第三隔离层313的厚度为9nm。
需要注意的是，本公开实施例中半导体结构的制备方法均可用于制备对应的半导体结构，故而方法实施例与结构实施例之间的技术特征，在不产生冲突的前提下可以相互替换及补充，以使得本领域技术人员能够获悉本发明的技术内容。
应该理解的是，除非本文中有明确的说明，所述的步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，所述的步骤的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他 实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开实施例构思的前提下，还可以做出若干变形和改进，这些都属于本公开实施例的保护范围。因此，本公开实施例专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种半导体结构的制备方法，包括：
    提供衬底；
    于所述衬底内形成位线接触孔；
    形成位线接触隔离层；所述位线接触隔离层至少覆盖所述位线接触孔的侧壁；
    形成位线接触层；所述位线接触层填满所述位线接触孔；所述位线接触层与所述位线接触隔离层共同构成位线接触结构；
    形成位线叠层；所述位线叠层位于所述位线接触结构的上表面。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述形成位线接触层，包括：
    形成位线接触材料层；所述位线接触材料层填满所述位线接触孔，并覆盖所述衬底形成有所述位线接触孔的表面；
    去除位于所述衬底表面的所述位线接触材料层；保留的所述位线接触材料层为所述位线接触层。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，所述位线叠层包括由下至上依次叠置的第一导电层、第二导电层及绝缘介质层。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，所述形成位线叠层，包括：
    于所述位线接触结构的表面及所述衬底形成有所述位线接触孔的表面形成由下至上依次叠置的第一导电材料层、第二导电材料层及绝缘介质材料层；
    刻蚀所述第一导电材料层、所述第二导电材料层及所述绝缘介质材料层，保留的所述第一导电材料层、所述第二导电材料层及所述绝缘介质材料层分别作为所述第一导电层、所述第二导电层及所述绝缘介质层以构成所述位线叠层。
  5. 根据权利要求3所述的半导体结构的制备方法，其中，所述位线叠层的宽度与所述位线接触结构的顶部的宽度相同。
  6. 根据权利要求3所述的半导体结构的制备方法，其中，所述位线叠层的宽度小于所述位线接触结构的顶部的宽度且不小于所述位线接触层的顶部的宽度。
  7. 根据权利要求1至6中任一项所述的半导体结构的制备方法，其中，所述形成位线接触隔离层，包括：
    形成第一隔离层；所述第一隔离层至少覆盖所述位线接触孔的侧壁；
    形成第二隔离层；所述第二隔离层覆盖所述第一隔离层裸露的侧面；
    形成第三隔离层，所述第三隔离层覆盖所述第二隔离层裸露的侧面；
    所述第一隔离层、所述第二隔离层及所述第三隔离层构成所述位线接触隔离层。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，
    所述形成第一隔离层，包括：
    形成第一隔离材料层；所述第一隔离材料层覆盖所述衬底形成有所述位线接触孔的表面、所述位线接触孔的侧壁及所述位线接触孔的底部；
    去除位于所述衬底表面及所述位线接触孔底部的所述第一隔离材料层；保留的所述第一隔离材料层为所述第一隔离层；
    所述形成第二隔离层，包括：
    形成第二隔离材料层；所述第二隔离材料层覆盖所述衬底形成有所述位线接触孔的表面、所述第一隔离层的表面及所述位线接触孔的底部；
    去除位于所述衬底表面、所述第一隔离层的上表面及所述位线接触孔底部的所述第二隔离材料层；保留的所述第二隔离材料层为所述第二隔离层；
    所述形成第三隔离层，包括：
    形成第三隔离材料层；所述第三隔离材料层覆盖所述衬底形成有所述位线接触孔的表面、所述第二隔离层的表面及所述位线接触孔的底部；
    去除位于所述衬底表面、所述第一隔离层的上表面、所述第二隔离层的上表面及所述位线接触孔底部的所述第三隔离材料层；保留的所述第三隔离材料层为所述第三隔离层。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述第一隔离层及所述第三隔离层均包括氮化硅层；所述第二隔离层包括氧化硅层；所述位线接触层包括多晶硅层。
  10. 根据权利要求6所述的半导体结构的制备方法，其中，所述衬底的上表面还形成有多晶硅层；
    采用对所述多晶硅层具有大于或等于10∶1的选择比的反应气体刻蚀所述第一导电材料层、所述第二导电材料层及所述绝缘介质材料层。
  11. 一种半导体结构，包括：
    衬底；所述衬底内具有位线接触孔；
    位线接触结构，所述位线接触结构包括位线接触隔离层及位线接触层；所述位线接触隔离层至少覆盖所述位线接触孔的侧壁；所述位线接触层填满所述位线接触孔；
    位线叠层；所述位线叠层位于所述位线接触结构的上表面。
  12. 根据权利要求11所述的半导体结构，其中，所述位线叠层包括由下至上依次叠置的第一导电层、第二导电层及介质层。
  13. 根据权利要求12所述的半导体结构，其中，所述位线叠层的宽度与所述位线接触结构的顶部的宽度相同。
  14. 根据权利要求12所述的半导体结构，其中，所述位线叠层的宽度小于所述位线接触结构的顶部的宽度且不小于所述位线接触层的顶部的宽度。
  15. 根据权利要求11至14中任一项所述的半导体结构，其中，所述位线接触隔离层包括：
    第一隔离层；所述第一隔离层至少覆盖所述位线接触孔的侧壁；
    第二隔离层；所述第二隔离层覆盖所述第一隔离层裸露的侧面；
    第三隔离层，所述第三隔离层覆盖所述第二隔离层裸露的侧面。
  16. 根据权利要求15所述的半导体结构，其中，所述第一隔离层及所述第三隔离层均包括氮化硅层；所述第二隔离层包括氧化硅层；所述位线接触层包括多晶硅层。
  17. 根据权利要求16所述的半导体结构，其中，所述第一隔离层的厚度为3nm～5nm；所述第二隔离层的厚度为0.5nm～1.5nm；所述第三隔离层的厚度为8nm～10nm。
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KR20110029672A (ko) * 2009-09-16 2011-03-23 주식회사 하이닉스반도체 반도체 소자 및 그 형성방법
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US20140353744A1 (en) * 2013-05-31 2014-12-04 SK Hynix Inc. Semiconductor device
CN107492550A (zh) * 2017-08-08 2017-12-19 睿力集成电路有限公司 存储器、其制造方法及半导体器件
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US20120326214A1 (en) * 2011-06-22 2012-12-27 Hyun-Shik Cho Semiconductor device and method for fabricating the same
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