WO2024000467A1 - 显示基板、显示装置和应用于显示基板的负载补偿方法 - Google Patents

显示基板、显示装置和应用于显示基板的负载补偿方法 Download PDF

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Publication number
WO2024000467A1
WO2024000467A1 PCT/CN2022/102972 CN2022102972W WO2024000467A1 WO 2024000467 A1 WO2024000467 A1 WO 2024000467A1 CN 2022102972 W CN2022102972 W CN 2022102972W WO 2024000467 A1 WO2024000467 A1 WO 2024000467A1
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Prior art keywords
pixel units
compensation
row
conductive layer
compensation capacitor
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PCT/CN2022/102972
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English (en)
French (fr)
Inventor
邓银
吴博
李豪豪
赵泽
廖政
杨永菊
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/102972 priority Critical patent/WO2024000467A1/zh
Publication of WO2024000467A1 publication Critical patent/WO2024000467A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a display device, and a load compensation method applied to the display substrate.
  • a display substrate which includes: a substrate including a display area and a frame area located on at least one side of the display area; a plurality of A pixel unit, the plurality of pixel units are arranged in an array on the base substrate along the row direction and the column direction, and each row of pixel units includes a plurality of sub-pixels; a plurality of scanning signal lines provided on the base substrate, so The plurality of scanning signal lines are used to provide scanning signals to multiple rows of pixel units respectively; a plurality of load compensation units are provided on the substrate and located in the frame area, and the plurality of load compensation units are respectively connected to the At least some of the plurality of scanning signal lines are electrically connected; and a common electrode is provided on the substrate, at least a part of the common electrode is located in the display area, and the common electrode is connected to a common electrode.
  • the display substrate includes N rows of pixel units, and n rows of pixel units in the N rows of pixel units include sub-pixels.
  • the numbers are inconsistent with each other, where N is a positive integer greater than or equal to 2, n is a positive integer greater than or equal to 2 and less than or equal to N; and for the n rows of pixel units, the scanning signal lines of each row of pixel units are electrically connected to their respective Load compensation unit, the load compensation value of the load compensation unit of each row of pixel units is negatively related to the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.
  • the compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode is electrically connected to the scan signal line, and the second compensation capacitor electrode is connected to The common voltage signal, the orthographic projection of the first compensation capacitor electrode on the substrate substrate and the orthographic projection of the second compensation capacitor electrode on the substrate substrate at least partially overlap.
  • a plurality of scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to respective compensation capacitors, and the first compensation capacitor of the compensation capacitor of each row of pixel units
  • the overlapping area between the electrode and the second compensation capacitor electrode is negatively related to the number of sub-pixels included in the row of pixel units.
  • At least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units has a size in the row direction equal to that of the row of pixel units.
  • the number of subpixels included is inversely related.
  • the compensation resistor includes a compensation conductive trace; and for the n rows of pixel units, a plurality of scan signal leads that provide scan signals to each row of pixel units are electrically connected to respective compensation conductive traces. line, the resistance value of the compensation conductive trace of each row of pixel units is negatively related to the number of sub-pixels included in the row of pixel units.
  • the length of the compensation conductive trace of each row of pixel units is inversely related to the number of sub-pixels included in the row of pixel units, and/or, each row of pixel units
  • the diameter of the compensation conductive trace is positively related to the number of sub-pixels included in the row of pixel units.
  • the display substrate further includes: a gate drive circuit disposed on the base substrate and located in the frame area, the gate drive circuit being used to output a scan signal; and A plurality of scanning signal leads on the base substrate and located in the frame area, the plurality of scanning signal leads are electrically connected to the plurality of scanning signal lines respectively, wherein the display substrate includes: located on the a first conductive layer on the base substrate; a second conductive layer located on the side of the first conductive layer away from the base substrate; and a third conductive layer located on the side of the second conductive layer away from the base substrate.
  • the first compensation capacitor electrode and the scan signal lead are connected to each other, and the first compensation capacitor electrode and the scan signal lead are located on the first
  • the conductive layer and one of the second conductive layers are the same conductive layer.
  • the first compensation capacitor electrode and the scan signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer. in three conductive layers; or, wherein the first compensation capacitor electrode and the scan signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the in the third conductive layer.
  • the compensation capacitor includes a first sub-compensation capacitor and a second sub-compensation capacitor
  • the second compensation capacitor electrode includes a first sub-compensation capacitor electrode and a second sub-compensation capacitor electrode
  • the third sub-compensation capacitor electrode includes A sub-compensation capacitor electrode and a second sub-compensation capacitor electrode are both connected to the common voltage signal
  • the first compensation capacitor electrode is located in the second conductive layer
  • the first sub-compensation capacitor electrode is located in the first In the conductive layer
  • the second sub-compensation capacitor electrode is located in the third conductive layer
  • the orthographic projection of the first compensation capacitor electrode on the substrate substrate and the first sub-compensation capacitor electrode are on the The orthographic projections on the base substrate at least partially overlap to form the first sub-compensation capacitor electrode
  • the orthographic projection of the first compensation capacitor electrode on the base substrate and the second sub-compensation capacitor electrode are on Orthographic projections on the base substrate at least partially overlap to form the second sub-compensation capacitor electrode.
  • the display substrate further includes: a driver chip disposed on the substrate substrate and located in the frame area, the driver chip being used to output scanning signals; and a driver chip disposed on the substrate.
  • a base substrate and multiple scanning signal leads located in the frame area; the multiple scanning signal leads are electrically connected to the multiple scanning signal lines respectively
  • the display substrate includes: located on the base substrate a first conductive layer; a second conductive layer located on the side of the first conductive layer away from the base substrate; and a third conductive layer located on the side of the second conductive layer away from the base substrate, wherein , for the same row of pixel units, the first compensation capacitor electrode and the scan signal lead are connected to each other, and the first compensation capacitor electrode and the scan signal lead are located on the first conductive layer and the a same conductive layer in the second conductive layer.
  • the first compensation capacitor electrode and the scanning signal lead are located in the first conductive layer; for pixel units in even-numbered rows, the first compensation capacitor electrode and the scanning signal lead are located in the first conductive layer; The first compensation capacitor electrode and the scanning signal lead are located in the second conductive layer; for all n rows of pixel units, the second compensation capacitor electrode is located in the third conductive layer; or, Wherein, for the pixel units of odd-numbered rows, the first compensation capacitor electrode and the scanning signal lead are located in the second conductive layer; for the pixel units of even-numbered rows, the first compensation capacitor electrode and the scanning signal leads are located in the first conductive layer; for all n rows of pixel units, the second compensation capacitor electrodes are located in the third conductive layer.
  • the first compensation capacitor electrode and the scan signal lead are located in the first conductive layer, and the second compensation capacitor electrode is located in the in the second conductive layer or the third conductive layer; and for even-numbered rows of pixel units, the first compensation capacitor electrode and the scan signal lead are both located in the second conductive layer, and the second The compensation capacitor electrode is located in the first conductive layer or the third conductive layer; or, for pixel units in odd rows, the first compensation capacitor electrode and the scan signal lead are both located in the third conductive layer.
  • the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer; and for the pixel units of even rows, the first compensation capacitor electrode and the scan signal
  • the leads are all located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer.
  • the first compensation capacitor electrode includes a plurality of curved traces extending from the scan signal lead; or, the first compensation capacitor electrode includes a first conductive line extending from the scan signal lead. part, and the first conductive part has a hollow structure.
  • the scanning signal leads of two adjacent rows of pixel units extend along the row direction
  • the first compensation capacitor electrode is located between the scanning signal leads of the two adjacent rows of pixel units in the column direction.
  • the display substrate includes an electrostatic protection ring connected to a common voltage signal; and the second compensation capacitance electrode includes a second conductive portion extending from the electrostatic protection ring.
  • the second conductive portion of the compensation capacitor of the n rows of pixel units is a continuously extending integrated structure; or, for the n rows of pixel units, n
  • the second conductive portions of the compensation capacitors of the row pixel units respectively extend from the electrostatic protection ring toward the display area.
  • the display substrate further includes an electrostatic protection circuit, one end of the electrostatic protection circuit is electrically connected to both the scanning signal lead and the scanning signal line, and the other end of the electrostatic protection circuit is connected to
  • the electrostatic protection ring is electrically connected and used to discharge static electricity on the scanning signal lead and the scanning signal line to the electrostatic protection ring.
  • the display substrate further includes a first conductive transfer part located in the third conductive layer; one end of the scanning signal lead close to the display area is connected to the through hole through a first via hole.
  • the first part of the first conductive transfer part is electrically connected, and one end of the scanning signal line away from the display area is electrically connected to the second part of the first conductive transfer part through a second via hole.
  • the first conductive transfer part The third part of the transfer part is electrically connected to one end of the electrostatic protection circuit through a third via hole.
  • the display substrate further includes a second conductive transition portion located in the third conductive layer; a portion of the scanning signal lead is connected to the second conductive transition portion through a fourth via hole.
  • a part of the second conductive transfer part is electrically connected to one end of the first compensation capacitor electrode through a fifth via hole; and/or the display substrate further includes a A third conductive transfer part in the conductive layer; another part of the scanning signal lead is electrically connected to a part of the third conductive transfer part through a sixth via hole, and another part of the third conductive transfer part passes through
  • the seventh via hole is electrically connected to the other end of the first compensation capacitor electrode.
  • a portion of the scan signal lead forms the compensation resistor.
  • At least a portion of the scan signal lead that provides a scan signal to at least one row of pixel units includes a plurality of segments of bent traces, and the compensation resistor includes the multiple segments of bent traces.
  • the difference in the total load on the scanning signal lines of any two adjacent rows of pixel units is within a prescribed threshold, wherein the total load includes the capacitive load and the resistive load on the scanning signal line. product.
  • the display substrate includes a common voltage signal bus that provides the common voltage signal; and for a load compensation unit of at least one row of pixel units, the compensation capacitor is located at the common voltage in the row direction.
  • the signal bus is located on a side close to the display area
  • the compensation resistor is located on a side of the compensation capacitor close to the display area in the row direction
  • the electrostatic protection circuit is located on a side of the compensation resistor close to the display area.
  • a display device including the display substrate as described above.
  • a load compensation method applied to a display substrate includes: a substrate substrate including a display area and a frame area located on at least one side of the display area; A plurality of pixel units in the display area, the plurality of pixel units are arranged in an array on the base substrate along the row direction and the column direction, and each row of pixel units includes a plurality of sub-pixels; A plurality of scanning signal lines, the plurality of scanning signal lines are used to provide scanning signals to multiple rows of pixel units respectively; a plurality of load compensation units provided on the substrate and located in the frame area, the plurality of A load compensation unit is electrically connected to at least some of the plurality of scanning signal lines respectively; and a common electrode is provided on the substrate, at least a part of the common electrode is located in the display area, The common electrode is connected to a common voltage signal, wherein the display substrate includes N rows of pixel units, where N is a positive integer greater than or equal to 2.
  • the method includes: driving the display substrate to display a white picture; obtaining the pth The charging voltage of the row pixel unit and the q-th row pixel unit, wherein the p-th row pixel unit is the row of pixel units with the smallest number of sub-pixels among the N-row pixel units, and the q-th row pixel unit is the N-row pixel unit.
  • the row of pixel units with the largest number of sub-pixels in the row of pixel units calculate the difference in charging voltage between the p-th row pixel unit and the q-th row pixel unit; compare the difference in charging voltage with the prescribed voltage threshold; respond to If the difference between the charging voltages is greater than the specified voltage threshold, it is determined that load compensation is required; in response to the load compensation, n rows of pixel units that need to be loaded compensated are determined, n is a positive integer greater than or equal to 2 and less than or equal to N, where, The difference between the charging voltage of each row of pixel units in the n rows of pixel units and the charging voltage of the qth row of pixel units is greater than a prescribed threshold; according to the number of sub-pixels in each row of pixel units in the n rows of pixel units and The number of sub-pixels in the q-th row pixel unit determines the load compensation value of the load compensation unit, wherein multiple scanning signal lines that provide scanning signals to the n-th row pixel unit
  • a load compensation method applied to a display substrate includes: a substrate substrate, the substrate substrate includes a display area and a frame area located on at least one side of the display area; A plurality of pixel units located in the display area, the plurality of pixel units are arranged in an array on the substrate along the row direction and the column direction, and each row of pixel units includes a plurality of sub-pixels; arranged on the substrate A plurality of scanning signal lines of the substrate, the plurality of scanning signal lines are used to provide scanning signals to multiple rows of pixel units respectively; a plurality of load compensation units arranged on the substrate and located in the frame area, so The plurality of load compensation units are respectively electrically connected to at least some of the plurality of scanning signal lines; and a common electrode is provided on the substrate, at least a part of the common electrode is located in the display area , the common electrode is connected to a common voltage signal, wherein the display substrate includes N rows of pixel units, where N is a positive integer greater than
  • FIG. 1A is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure.
  • FIGS. 1B to 1D schematically illustrate examples of several special shapes of the display substrate.
  • FIG. 2A is a schematic diagram schematically showing a pixel layout of the display device shown in FIG. 1A.
  • FIG. 2B is a partial enlarged view of part I shown in FIG. 1A.
  • FIG. 2C is a partial enlarged view of part II shown in FIG. 1A.
  • FIG. 3A is a schematic structural diagram schematically showing a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure.
  • 3B schematically shows a cross-sectional view of a thin film transistor in an embodiment of the present disclosure.
  • FIG. 4A is a schematic diagram of a fan-out area of a display substrate according to some exemplary embodiments of the present disclosure.
  • 4B to 4D are partial enlarged views of area III, area IV, and area V in FIG. 4A respectively.
  • FIG. 6 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating load compensation units of partial rows of pixel units.
  • FIG. 7 is a partial enlarged view of the display substrate shown in FIG. 6 , which schematically shows the load compensation unit of the pixel unit of the i-th row.
  • FIG. 8 is a partial enlarged view of the display substrate shown in FIG. 6 , which schematically shows the load compensation unit of the i+1th row pixel unit.
  • FIG. 10 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a plan view of a compensation capacitor, an electrostatic protection circuit, and an electrostatic protection structure of a certain row of pixel units.
  • FIG. 11 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing a plan view of compensation capacitances and compensation resistors of certain rows of pixel units.
  • 12A to 12D respectively schematically illustrate a schematic cross-sectional view of a compensation capacitor of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 13A is a partial enlarged view of the display substrate at area VI in FIG. 10 according to some exemplary embodiments of the present disclosure.
  • Fig. 13B is a cross-sectional view taken along line BB' in Fig. 13A.
  • FIG. 14A is a partial enlarged view of the display substrate at area VI in FIG. 10 according to other exemplary embodiments of the present disclosure.
  • FIG. 15A is a partial enlarged view of the display substrate at area VI in FIG. 10 according to some exemplary embodiments of the present disclosure.
  • 17B is a flowchart of a load compensation method applied to a display substrate according to other exemplary embodiments of the present disclosure.
  • Figure 18 is an equivalent circuit diagram of an electrostatic protection circuit according to some exemplary embodiments of the present disclosure.
  • connection may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection.
  • the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader meaning.
  • the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • first”, “second”, etc. may be used herein to describe various components, components, elements, regions, layers and/or sections, these components, components, elements, regions, layers and/or parts shall not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer and/or section from another.
  • a first component, first component, first element, first region, first layer and/or first section discussed below could be termed a second component, second component, second element, second region , second layer and/or second portion without departing from the teachings of the present disclosure.
  • spatially relative terms such as “upper,” “lower,” “left,” “right,” etc. may be used herein to describe one element or feature in relation to another element or feature as illustrated in the figures. relation. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “above” the other elements or features.
  • the terms “substantially,” “approximately,” “approximately,” “approximately,” and other similar terms are used as terms of approximation rather than as terms of degree, and their intended interpretation would be recognized by one of ordinary skill in the art.
  • the inherent deviation in measured or calculated values Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes the stated value and means that for this purpose Specific values are within acceptable deviations as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ⁇ 30%, ⁇ 20%, ⁇ 10%, ⁇ 5% of the stated value.
  • the same layer refers to using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • layer structure Depending on the specific pattern, a patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located on the "same layer” are made of the same material and formed through the same patterning process. Generally, multiple elements, components, structures and/or portions located on the "same layer” are made of the same material and formed through the same patterning process. or parts having approximately the same thickness.
  • the expression “negative correlation” means that the two quantities change in opposite directions. For example, when one of them becomes larger, the other becomes smaller; when one becomes smaller, the other becomes larger.
  • the expression “positive correlation” means that two quantities change in the same direction, for example, when one becomes larger, the other becomes larger; when one becomes smaller, the other becomes smaller.
  • Embodiments of the present disclosure provide at least a display substrate and a display device.
  • the display substrate includes: a base substrate, the base substrate includes a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the multiple pixel units are located along Arranged in an array on the base substrate in the row direction and column direction, each row of pixel units includes a plurality of sub-pixels; a plurality of scanning signal lines provided on the base substrate, the plurality of scanning signal lines are used to respectively provide Multiple rows of pixel units provide scan signals; multiple load compensation units are disposed on the base substrate and located in the frame area, and the multiple load compensation units are respectively connected to at least some of the multiple scan signal lines.
  • the compensation unit includes at least one of a compensation capacitor and a compensation resistor; the display substrate includes N rows of pixel units, and the number of sub-pixels included in the n rows of pixel units in the N rows of pixel units is inconsistent with each other, where N is greater than or equal to A positive integer of 2, n is a positive integer greater than or equal to 2 and less than or equal to N; and for the n rows of pixel units, the scanning signal lines of each row of pixel units are electrically connected to their respective load compensation units, and the load compensation units of each row of pixel units are The load compensation value of the unit is negatively related to the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.
  • load compensation can be performed on rows of pixel units with inconsistent loads.
  • the load compensation unit is electrically connected to the scanning signal lines of each row of pixel units that require load compensation, so that the scanning signal lines of each row of pixel units need to be compensated.
  • the load on the display is basically the same, so that bad phenomena such as uneven display in each sub-display area can be at least improved or even eliminated.
  • FIG. 1A is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure.
  • FIG. 2A is a schematic diagram schematically showing a pixel layout of the display device shown in FIG. 1A.
  • FIG. 2B is a partial enlarged view of part I shown in FIG. 1A.
  • FIG. 2C is a partial enlarged view of part II shown in FIG. 1A.
  • the display device 1000 may include a display substrate.
  • the display substrate may include a base substrate 100, and the base substrate 100 may include a display area AA and a frame area NA located on at least one side of the display area.
  • the frame area NA surrounds the display area AA.
  • the frame area NA may be located in the display area AA. At least one side, but does not surround the display area AA.
  • the display substrate may include a plurality of pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit used to display an image.
  • the pixel unit P may include a light emitting device that emits white light and/or colored light.
  • the pixel units P may be provided in plurality, arranged in a matrix form along rows extending in a first direction (eg, row direction) X and columns extending in a second direction (eg, column direction) Y.
  • first direction eg, row direction
  • second direction eg, column direction
  • embodiments of the present disclosure do not specifically limit the arrangement form of the pixel unit P, and the pixel unit P may be arranged in various forms.
  • the pixel unit P may be arranged such that a direction inclined with respect to the first direction X and the second direction Y becomes the column direction, and such that the direction crossing the column direction becomes the row direction.
  • One pixel unit P may include multiple sub-pixels.
  • one pixel unit P may include three sub-pixels, namely a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3.
  • one pixel unit P may include 4 sub-pixels, namely a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel.
  • the first subpixel SP1 may be a red subpixel
  • the second subpixel SP2 may be a green subpixel
  • the third subpixel SP3 may be a blue subpixel
  • the fourth subpixel may be a white subpixel.
  • the display substrate may be a liquid crystal display substrate, for example, an array substrate of a liquid crystal display panel.
  • FIG. 3A is a schematic structural diagram schematically showing a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure.
  • the display substrate may include: a first electrode E1 , a second electrode E2 , a data signal line DL and a scanning signal line GL provided on the base substrate 100 . It should be understood that when the display panel is a liquid crystal display panel, the display panel may include a liquid crystal layer located between the array substrate and the color filter substrate.
  • the specific structures of the array substrate, color filter substrate and liquid crystal layer can refer to the structure of the existing liquid crystal display panel, and will not be described again here.
  • the first electrode E1 and the second electrode E2 can generate corresponding liquid crystal electric fields driven by the driving signal.
  • the liquid crystal in the liquid crystal layer can be deflected under the action of the liquid crystal electric field to achieve corresponding display functions.
  • the liquid crystal layer may be disposed between the first electrode E1 and the second electrode E2.
  • One of the first electrode E1 and the second electrode E2 may be a pixel electrode, and the other may be a common electrode.
  • the first electrode E1 is a common electrode
  • the second electrode E2 is a pixel electrode.
  • At least one sub-pixel further includes a thin film transistor T electrically connected to the data signal line DL.
  • the thin film transistor T may have a top gate structure or a bottom gate structure. The details may be determined according to actual needs and are not limited here. The following describes the thin film transistor T according to the embodiment of the present disclosure, taking the thin film transistor T adopting a top gate structure as an example.
  • FIG. 16 is a cross-sectional view of a display substrate taken along line AA' in FIG. 2B according to some exemplary embodiments of the present disclosure.
  • the display substrate may include: a semiconductor layer ACT located on the base substrate 100; a first conductive layer located on a side of the semiconductor layer ACT away from the base substrate 100. layer 10; a second conductive layer 20 located on the side of the first conductive layer 10 away from the base substrate 100; and a third conductive layer located on the side of the second conductive layer 20 away from the base substrate 100 30.
  • the thin film transistor T may include an active layer CH, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1.
  • the active layer CH of the thin film transistor T may be located in the semiconductor layer ACT
  • the gate electrode GE1 of the thin film transistor T may be located in the first conductive layer 10
  • the source electrode SE1 and the drain electrode DE1 of the thin film transistor T may be located in the first conductive layer 10. in the second conductive layer 20 .
  • the first electrode E1 eg, the common electrode
  • the third conductive layer 30 may be located in the third conductive layer 30 .
  • the display substrate can adopt a two-image two-domain (2Pixel2Domain, 2P2D) sub-pixel structure design.
  • Each sub-pixel may include a plurality of strip-shaped pixel electrodes E2, and the plurality of strip-shaped pixel electrodes E2 of each sub-pixel are separated by slits.
  • the so-called two images and two domains means that the extension directions of the pixel electrodes E2 of two adjacent rows of sub-pixels are different, and the pixel electrodes E2 of each adjacent two rows of sub-pixels are generally symmetrical with respect to the scanning signal line GL.
  • the pixel electrode E2 and the common electrode E1 of one row of sub-pixels can form the first domain electric field
  • the pixel electrode E2 and the common electrode E1 of the other row of sub-pixels can form the third domain electric field.
  • Two-domain electric field the directions of the first domain electric field and the second domain electric field are different.
  • the directions of the electric fields corresponding to each two adjacent rows of sub-pixels form a certain angle.
  • each two adjacent rows of sub-pixels have a certain angle.
  • the light emission directions can compensate each other, which is beneficial to improving the display effect.
  • the display substrate may have an irregular shape, and the irregular shape may include any special shape.
  • FIGS. 1B to 1D schematically illustrate several examples of special shapes. It should be understood that the embodiments of the present disclosure do not specifically limit the shape of the display substrate. Below, the embodiments of the present disclosure will be described in detail, taking the special shape shown in FIG. 1A as an example.
  • the display substrate includes N rows of pixel units, where N is a positive integer greater than or equal to 2.
  • the display area AA may include a plurality of sub-display areas AA1, AA2, and AA3.
  • the display area AA may include a plurality of sub-display areas AA1, AA2, and AA3.
  • the number of sub-pixels included in each row of pixel units decreases irregularly from bottom to top.
  • the number of sub-pixels included in each row of pixel units located in the sub-display area AA3 is greater than that located in the sub-display area AA3.
  • the number of sub-pixels included in each row of pixel units in area AA2 is greater than the number of sub-pixels included in each row of pixel units located in sub-display area AA1.
  • a scanning signal line GL is provided to provide scanning signals to each sub-pixel of the row of pixel units.
  • the number of sub-pixels included in the n rows of pixel units is inconsistent with each other, where n is a positive integer greater than or equal to 2 and less than or equal to N.
  • the loads electrically connected to the scanning signal lines GL of these n rows of pixel units are inconsistent with each other.
  • the theoretical load of the scanning signal line of each row of pixel units can be calculated based on the design drawing of the display substrate.
  • the load may include a resistive load and a capacitive load.
  • the resistance R on the scanning signal line of the i-th row of pixel units in the N rows of pixel units can be calculated using the following formula:
  • Ri Rs*L/W, where L is the length of the scanning signal line of the i-th row pixel unit, W is the width of the scanning signal line of the i-th row pixel unit, and Rs is the scanning signal line used by the i-th row pixel unit Sheet resistance of metallic materials.
  • the capacitance Ci on the scanning signal line of the i-th row of pixel units in the N rows of pixel units can be calculated using the following formula:
  • Ci Ni*Cpixel, where Ni is the number of sub-pixels included in the i-th row pixel unit, and Cpixel is the capacitive load value of a single sub-pixel, which can be obtained by extracting it through software or calculating the plate capacitance based on the area.
  • the inventor found through research that for each row of pixel units with inconsistent loads, the charging voltages achieved during the same charging time are inconsistent, which may lead to uneven display in each sub-display area and other undesirable phenomena during actual display.
  • load compensation can be performed on rows of pixel units with inconsistent loads.
  • the load compensation unit is electrically connected to the scanning signal lines of each row of pixel units that require load compensation, so that the scanning signal lines of each row of pixel units need to be compensated.
  • the load on the display is basically the same, so that bad phenomena such as uneven display in each sub-display area can be at least improved or even eliminated.
  • a display substrate may include: a substrate substrate 100 that includes a display area AA and a frame area located on at least one side of the display area NA; a plurality of pixel units P located in the display area AA.
  • the plurality of pixel units P are arranged in an array on the substrate 100 along the row direction X and the column direction Y.
  • Each row of pixel units P may include A plurality of sub-pixels; a plurality of scanning signal lines GL provided on the base substrate 100, the plurality of scanning signal lines GL are used to respectively provide scanning signals to multiple rows of pixel units P; provided on the base substrate 100 And a plurality of load compensation units 200 located in the frame area NA, the plurality of load compensation units 200 are respectively electrically connected to at least some of the plurality of scanning signal lines GL; and are provided on the lining
  • the load compensation method may include the following steps S1710 to S1770.
  • step S1710 the display substrate is driven to display a white screen.
  • a white screen requires the largest charging voltage.
  • step S1720 the charging voltages of the p-th row pixel unit and the q-th row pixel unit are obtained, wherein the p-th row pixel unit is the row of pixel units with the smallest number of sub-pixels among the N rows of pixel units, and the p-th row pixel unit is the row of pixel units with the smallest number of sub-pixels.
  • the q-row pixel unit is the row of pixel units with the largest number of sub-pixels among the N-row pixel units.
  • the p-th row of pixel units is a row of pixel units with a smaller load, and the charging voltage on the corresponding scanning signal line is larger, recorded as Vmax; the q-th row of pixel units is a row of pixel units with a larger load. , the corresponding charging voltage on the scanning signal line is smaller, recorded as Vmin.
  • the difference in charging voltage is compared with a prescribed voltage threshold.
  • the prescribed voltage threshold is a critical value between an acceptable range and an unacceptable range.
  • the acceptable range is based on the fact that the user cannot see differences in the display of the entire panel, such as uneven display defects. In other words, when displaying, when the entire panel has the same gray level, if ⁇ V is less than one gray level, it will not be seen by the naked eye. Therefore, the critical value can be calculated.
  • 6-bit data determines that the minimum voltage difference of the signal (ie, the specified voltage threshold) is approximately 30 mV
  • 8-bit data determines that the minimum voltage difference of the signal (ie, the specified voltage threshold) is approximately 8 mV.
  • step S1750 in response to the difference in charging voltage being greater than a prescribed voltage threshold, it is determined that load compensation needs to be performed. For example, when it is determined that the difference between the charging voltage of at least one row of pixel units and Vmin is greater than the prescribed voltage threshold (for example, 8 mV), it is determined that the display substrate needs to perform load compensation.
  • a prescribed voltage threshold for example, 8 mV
  • step S1760 in response to the load compensation, n rows of pixel units that require load compensation are determined, n is a positive integer greater than or equal to 2 and less than or equal to N, where the charge of each row of pixel units in the n rows of pixel units is The difference between the voltage and the charging voltage of the pixel unit in the qth row is greater than a prescribed threshold.
  • the pixel units in these rows are determined as n rows of pixel units that require load compensation. In this way, the n rows of pixel units that require load replenishment can be accurately determined.
  • the load compensation value of the load compensation unit is determined according to the number of sub-pixels of each row of pixel units in the n-th row of pixel units and the number of sub-pixels of the q-th row of pixel units, where:
  • the multiple scanning signal lines that provide scanning signals in n-row pixel units are electrically connected to respective load compensation units.
  • the load compensation value of the n-row pixel units is negatively related to the number of sub-pixels included in the row of pixel units.
  • the load compensation The value includes at least one of a capacitance compensation value and a resistance compensation value.
  • FIG. 5 is a load difference ratio diagram of the signal scanning lines of two adjacent rows of pixel units in the display substrate shown in FIG. 1A before load compensation.
  • FIG. 17B is a diagram applied to the display substrate according to other exemplary embodiments of the present disclosure. Flowchart of the load compensation method. With reference to FIG. 5 and FIG. 17B , the load compensation method may include the following steps S1810 to S1870.
  • step S1810 the load difference of any two adjacent rows of pixel units is calculated.
  • the load difference can be expressed by the load difference percentage Ai of two adjacent rows of pixel units:
  • Ai [(R i *C i -R i+1 *C i+1 )/R i+1 *C i+1 ]*100%, where R i and C i represent the i-th row pixel unit respectively. Resistive load value and capacitive load value, R i+1 and C i+1 respectively represent the resistive load value and capacitive load value of the i+1th row pixel unit.
  • the load difference is compared with a prescribed load difference threshold.
  • the load difference threshold can be determined based on whether the user can visually see the display difference, and the load difference threshold can be about 2% to 5%.
  • step S1830 in response to the load difference being greater than the prescribed load difference threshold, n rows of pixel units that require load compensation are determined, n is a positive integer greater than or equal to 2 and less than or equal to N, wherein, in the n rows of pixel units The load difference between each row of pixel units and its adjacent rows of pixel units is greater than the specified load difference threshold.
  • sub-display area AA2 is also a special-shaped display area, there is no sudden change in Ai value, and the Ai value between two adjacent lines is less than the load difference threshold, so load compensation is not required. In this way, the n rows of pixel units that require load replenishment can be accurately determined.
  • step S1840 determine the load compensation value of the load compensation unit according to the number of sub-pixels of each row of pixel units in the n-th row of pixel units and the number of sub-pixels of the q-th row of pixel units, wherein the The q-row pixel unit is the row of pixel units with the largest number of sub-pixels among the n-row pixel units.
  • Multiple scanning signal lines that provide scanning signals to the n-row pixel units are electrically connected to respective load compensation units.
  • the n-row pixel units The load compensation value of the pixel unit is negatively related to the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.
  • At least one of the load compensation units includes at least one of a compensation capacitor and a compensation resistor.
  • the compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode is electrically connected to the scanning signal line, and the second compensation capacitor electrode is connected to the common voltage signal,
  • An orthographic projection of the first compensation capacitor electrode on the base substrate and an orthographic projection of the second compensation capacitor electrode on the base substrate at least partially overlap.
  • a plurality of scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to respective compensation capacitors, and the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units are The overlapping area is negatively related to the number of sub-pixels included in the row of pixel units.
  • the size of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units in the row direction is negatively related to the number of sub-pixels included in the row of pixel units.
  • the compensation resistor includes a compensation conductive trace.
  • a plurality of scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to respective compensation conductive lines.
  • the resistance value of the compensation conductive lines of each row of pixel units is equal to that of the row of pixel units. is negatively related to the number of sub-pixels.
  • the length of the compensation conductive wiring of each row of pixel units is negatively related to the number of sub-pixels included in the row of pixel units, and/or the line diameter of the compensation conductive wiring of each row of pixel units Positively related to the number of sub-pixels included in the row of pixel units.
  • Load compensation units with different compensation load values are used to compensate scanning signal lines with different numbers of sub-pixels, so that the loads on different scanning signal lines are uniform, avoiding display differences and ensuring display quality.
  • a display substrate may include: a driving chip 110 disposed on the base substrate 100 and located in the frame area NA, and the driving chip 110 is used for outputting scanning signal; and a plurality of scanning signal leads GLY provided on the base substrate 100 and located in the frame area NA, and the plurality of scanning signal leads GLY are electrically connected to the plurality of scanning signal lines GL respectively.
  • the driving chip 110 may be a gate driving chip for providing a gate scanning signal. Accordingly, the scanning signal line GL is a gate line, and the scanning signal lead GLY is a gate lead.
  • the scanning signal lead GLY is electrically connected between the driving chip 110 and the scanning signal line GL, and is used to provide the scanning signal generated by the driving chip 110 to the scanning signal line GL.
  • the scanning signal line GL then transmits the scanning signal to each sub-pixel of a certain row of pixel units that is electrically connected thereto.
  • the scanning signal lead GLY is located in the fan-out area (that is, the fanout area), that is, the scanning signal lead GLY is routed in the fan-out area.
  • FIG. 4A is a schematic diagram of a fan-out area of a display substrate according to some exemplary embodiments of the present disclosure.
  • 4B to 4D are partial enlarged views of area III, area IV, and area V in FIG. 4A respectively.
  • the space of the fan-out area FA of the display substrate is limited, and a larger number of scanning signal leads GLY need to be arranged in the fan-out area FA.
  • a double-layer wiring method is adopted for the scanning signal lead GLY. That is, the scanning signal leads GLY of the pixel units in two adjacent rows can be located in two different conductive layers respectively to facilitate wiring in the fan-out area FA.
  • the scanning signal lead GLY is located in the first conductive layer 10; for even-numbered rows of pixel units, the scanning signal lead GLY is located in the second conductive layer 20.
  • the scanning signal lead GLY is located in the second conductive layer 20; for even-numbered rows of pixel units, the scanning signal lead GLY is located in the first conductive layer 10.
  • a single-layer wiring method may be adopted for the scanning signal lead GLY in the fan-out area FA.
  • all scanning signal leads GLY are located in the first conductive layer 10 .
  • all scanning signal leads GLY are located in the second conductive layer 20 .
  • FIG. 6 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating load compensation units of partial rows of pixel units.
  • FIG. 7 is a partial enlarged view of the display substrate shown in FIG. 6 , which schematically shows the load compensation unit of the pixel unit of the i-th row.
  • FIG. 8 is a partial enlarged view of the display substrate shown in FIG. 6 , which schematically shows the load compensation unit of the i+1th row pixel unit.
  • 9 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a plan view of compensation capacitors and electrostatic protection circuits of certain two rows of pixel units.
  • FIG. 10 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a plan view of a compensation capacitor, an electrostatic protection circuit, and an electrostatic protection structure of a certain row of pixel units.
  • 11 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing a plan view of compensation capacitances and compensation resistors of certain rows of pixel units.
  • 12A to 12D respectively schematically illustrate a schematic cross-sectional view of a compensation capacitor of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 13A is a partial enlarged view of the display substrate at area VI in FIG. 10 according to some exemplary embodiments of the present disclosure.
  • FIG. 13B is a cross-sectional view taken along line BB' in Fig. 13A.
  • FIG. 14A is a partial enlarged view of the display substrate at area VI in FIG. 10 according to other exemplary embodiments of the present disclosure.
  • Fig. 14B is a cross-sectional view taken along line CC' in Fig. 14A.
  • FIG. 15A is a partial enlarged view of the display substrate at area VI in FIG. 10 according to some exemplary embodiments of the present disclosure.
  • Fig. 15B is a cross-sectional view taken along line DD' in Fig. 15A.
  • the scanning signal lead GLY may adopt a double-layer wiring method. As shown in FIG. 7 , the scanning signal lead GLY of the pixel unit in row i is located in the second conductive layer 20 ; as shown in FIG. 8 , the scanning signal lead GLY of the pixel unit in row i+1 is located in the first conductive layer 10 middle.
  • the compensation capacitor 200 may include a first compensation capacitor electrode 210 and a second compensation capacitor electrode 220 .
  • the first compensation capacitor electrode 210 can be connected to a scan signal, for example, a gate scan signal; the second compensation capacitor electrode 220 can be connected to a common voltage signal.
  • the first compensation capacitor electrode 210 includes multiple sections of curved wiring extending from the scanning signal lead GLY.
  • the first compensation capacitor electrode 210 includes a first conductive part extending from the scanning signal lead GLY, and the first conductive part has a hollow structure.
  • the first compensation capacitor electrode is formed as a multi-segment curved line or a conductive part with a hollow structure. While ensuring a large conductive area, static electricity can be prevented from gathering on the first compensation capacitor electrode, which is beneficial to electrostatic protection.
  • the display substrate may further include an electrostatic protection ring 310 connected to a common voltage signal.
  • the second compensation capacitor electrode 220 may be connected to the electrostatic protection ring 310 to access the common voltage signal.
  • the second compensation capacitor electrode 220 includes a second conductive portion 320 extending from the electrostatic protection ring 310 .
  • the second conductive portion 320 of the compensation capacitor of the n-row pixel units is a continuously extending integrated structure.
  • the second conductive portions 320 of the compensation capacitors of the n rows of pixel units respectively extend from the electrostatic protection ring 310 toward the display area AA.
  • the compensation capacitor is connected to the scanning signal lead GLY of the row of pixel units, and the first compensation capacitor electrode and the second compensation capacitor of the compensation capacitor are The capacitor electrodes are respectively located on different conductive layers, the orthographic projections of the first compensation capacitor electrode and the second compensation capacitor electrode on the base substrate 100 at least partially overlap, and there is a gap between the first compensation capacitor electrode and the second compensation capacitor electrode. and at least one insulating layer to form a capacitor structure.
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the first conductive layer 10 , as shown in FIG. 8 , FIG. 9 , and FIG. 12A .
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the second conductive layer 20, as shown in FIG. 7, FIG. 9, FIG. 10, and FIG. 12B.
  • the second compensation capacitor electrode 220 is located in the third conductive layer 30, as shown in FIGS. 7-10, 12A, and 12B.
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the second conductive layer 20, as shown in Figures 7, 9, 10, and As shown in 12B.
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the first conductive layer 10, as shown in Figures 8, 9, and 12A.
  • the second compensation capacitor electrode 220 is located in the third conductive layer 30, as shown in FIGS. 7-10, 12A, and 12B.
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the first conductive layer 10, as shown in Figure 8, Figure 9, and Figure 12A ;
  • the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in FIG. 12C) or the third conductive layer 30.
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are located in the second conductive layer 20, as shown in Figures 7, 9, 10, and 12B;
  • the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in FIG. 12C ) or the third conductive layer 30 .
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the second conductive layer 20, as shown in Figures 7, 9, 10, and As shown in 12B; the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in FIG. 12C) or the third conductive layer 30.
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the first conductive layer 10, as shown in Figures 8, 9, and 12A;
  • the two compensation capacitor electrodes 220 are located in the second conductive layer 20 (as shown in FIG. 12C ) or the third conductive layer 30 .
  • the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the first conductive layer 10
  • the second compensation capacitor electrode 220 is located in the second conductive layer 20 or the in the third conductive layer 30 .
  • the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20
  • the second compensation capacitor electrode 220 is located in the first conductive layer 10 or the in the third conductive layer 30 .
  • the first compensation capacitor electrode 210 and the scan signal lead GLY are connected to each other, and the first compensation capacitor electrode 210 and the scan signal lead GLY are located on the selected One of the first conductive layer 10 and the second conductive layer 20 is the same conductive layer; the second compensation capacitor electrode 220 is located in another conductive layer different from the first compensation capacitor electrode 210 .
  • the display substrate may adopt GOA technology, that is, Gate Driver on Array.
  • GOA technology the driver circuit is directly installed on the array substrate or display substrate to replace the external driver chip.
  • Each GOA unit acts as a first-level shift register, and each level of shift register is connected to a scanning signal line.
  • the shift registers at each level sequentially output the turn-on voltage to achieve line-by-line scanning of pixels.
  • each stage of the shift register may also be connected to multiple scanning signal lines. In this way, it can adapt to the development trend of high resolution and narrow frame of display substrates.
  • the display substrate may include: a gate driving circuit 120 disposed on the base substrate 100 and located in the frame area NA, the gate driving circuit 120 being used to output a scanning signal; and A plurality of scanning signal leads GLY on the base substrate 100 and located in the frame area NA are electrically connected to the plurality of scanning signal lines GL respectively.
  • the scanning signal lead GLY is electrically connected between the gate driving circuit 120 and the scanning signal line GL, and is used to provide the scanning signal generated by the gate driving circuit 120 to the scanning signal line GL.
  • the scanning signal line GL then transmits the scanning signal to each sub-pixel of a certain row of pixel units that is electrically connected thereto.
  • the scanning signal lead GLY does not need to be disposed in the fanout area (ie, fanout area). In this case, the scanning signal lead GLY can adopt a single-layer wiring method.
  • the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10
  • the second compensation capacitor electrode 220 is located in the second conductive layer 20 or the third conductive layer 20 . in the conductive layer 30 .
  • the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20
  • the second compensation capacitor electrode 220 is located in the first conductive layer 10 or the in the third conductive layer 30 .
  • the compensation capacitor 200 may include a first sub-compensation capacitor 200A and a second sub-compensation capacitor 200B, and the second compensation capacitor electrode 220 includes a first sub-compensation capacitor.
  • the first sub-compensation capacitor electrode 221 and the second sub-compensation capacitor electrode 222 are both connected to the common voltage signal.
  • the first compensation capacitor electrode 210 is located in the second conductive layer 20
  • the first sub-compensation capacitor electrode 221 is located in the first conductive layer 10
  • the second sub-compensation capacitor electrode 222 is located in the second conductive layer 20 . in the third conductive layer 30 .
  • the orthographic projection of the first compensation capacitor electrode 210 on the base substrate and the orthographic projection of the first sub-compensation capacitor electrode 221 on the base substrate at least partially overlap to form the first sub-substrate. Compensation capacitor electrode 200A.
  • the orthographic projection of the first compensation capacitor electrode 210 on the base substrate and the orthographic projection of the second sub-compensation capacitor electrode 222 on the base substrate at least partially overlap to form the second sub-substrate. Compensation capacitor electrode 200B.
  • the compensation capacitor includes two capacitors connected in parallel. In this way, it is beneficial to increase the overlapping area between the first compensation capacitor electrode and the second compensation capacitor electrode, thereby being beneficial to increasing the compensation The capacitance value of the capacitor. In this way, the compensation capacitor with the same capacitance value can be realized while reducing the width of the frame area occupied by the compensation capacitor, thereby facilitating the realization of a narrow-frame display device.
  • the load compensation unit may include at least one of a compensation capacitor and a compensation resistor.
  • the load compensation unit may only include the above-mentioned compensation capacitor, and the load compensation unit may only include a compensation resistor.
  • the load compensation unit may include both a compensation capacitor and a compensation resistor.
  • a portion of the scanning signal lead GLY forms the compensation resistor 400 .
  • the scan signal lead GLY that provides a scan signal to at least one row of pixel units includes multiple sections of bent wires, and the compensation resistor 400 includes the multiple sections of bent wires.
  • the length of the scanning signal lead GLY can be increased, thereby increasing its resistance. In this manner, the scan signal leads are resistance compensated.
  • the wire diameter of the scan signal lead GLY can also be changed to perform resistance compensation on the scan signal lead GLY.
  • the scanning signal leads GLY of the pixel units in two adjacent rows extend along the row direction between.
  • the display substrate further includes an electrostatic protection circuit 300 .
  • One end of the electrostatic protection circuit 300 is electrically connected to both the scanning signal lead GLY and the scanning signal line GL.
  • the electrostatic protection circuit 300 The other end is electrically connected to the electrostatic protection ring 310 for discharging the static electricity on the scanning signal lead GLY and the scanning signal line GL to the electrostatic protection ring 310 .
  • FIGS. 7 to 11 and 18 are an equivalent circuit diagram of an electrostatic protection circuit according to some exemplary embodiments of the present disclosure.
  • the electrostatic protection circuit may include four thin film transistors.
  • the thin film transistors of the electrostatic protection circuit may be formed simultaneously with the thin film transistors of the pixel driving circuit.
  • the gate electrode G1 of the thin film transistor T1 and the source electrode S1 of the thin film transistor T1 are electrically connected together to form the first outer lead of the electrostatic protection circuit.
  • the outer lead can be connected with the scanning signal lead GLY and the scanning signal line.
  • GL are all electrically connected.
  • the drain electrode D2 of the thin film transistor T2 may be electrically connected to the source electrode S1 of the thin film transistor T1.
  • the gate electrode G2 of the thin film transistor T2 and the source electrode S2 of the thin film transistor T2 are electrically connected together.
  • the drain electrode D1 of the thin film transistor T1 is electrically connected to the source electrode S2 of the thin film transistor T2.
  • the gate electrode G3 of the thin film transistor T3 and the source electrode S3 of the thin film transistor T3 are electrically connected together, and are electrically connected with the drain electrode D1 of the thin film transistor T1 and the gate electrode G2 of the thin film transistor T2.
  • the drain electrode D4 of the thin film transistor T4 is electrically connected to the source electrode S3 of the thin film transistor T3.
  • the gate electrode G4 of the thin film transistor T4 and the source electrode S4 of the thin film transistor T4 are electrically connected together to form a second outer lead of the electrostatic protection circuit.
  • the outer lead can be electrically connected to the electrostatic protection ring 310 .
  • the drain electrode D3 of the thin film transistor T3 is electrically connected to the source electrode S4 of the thin film transistor T4.
  • the high-voltage static electricity when high-voltage static electricity occurs on a scanning signal lead GLY or a scanning signal line GL, the high-voltage static electricity will be dispersed to the electrostatic protection ring 310 through the electrostatic protection circuit 300, and then pass through the electrostatic protection circuit 300.
  • the electrostatic protection ring 310 is dispersed to the common voltage signal bus, thereby dispersing high-voltage static electricity to the entire display substrate. In this way, damage to a certain scanning signal lead GLY or scanning signal line GL by high-voltage static electricity can be avoided.
  • the display substrate further includes a first conductive transfer portion 330 located in the third conductive layer 30 .
  • One end of the scanning signal lead GLY close to the display area AA is electrically connected to the first part of the first conductive adapter 330 through a first via hole VH1, and one end of the scanning signal line GL is away from the display area AA.
  • the second via hole VH2 is electrically connected to the second part of the first conductive adapter part 330
  • the third part of the first conductive adapter part 330 is electrically connected to the electrostatic protection circuit 300 through the third via hole VH3 One end is electrically connected.
  • the display substrate may further include an electrostatic protection structure for compensating capacitance.
  • the display substrate further includes a second conductive transfer portion 340 located in the third conductive layer 30 .
  • a part of the scanning signal lead GLY is electrically connected to a part of the second conductive adapter part 340 through a fourth via hole VH4, and another part of the second conductive adapter part 340 is electrically connected to the part of the second conductive adapter part 340 through a fifth via hole VH5.
  • One end of the first compensation capacitor electrode 210 is electrically connected.
  • the display substrate further includes a third conductive transfer portion 350 located in the third conductive layer 30 .
  • Another part of the scanning signal lead GLY is electrically connected to a part of the third conductive adapter part 350 through a sixth via hole VH6, and another part of the third conductive adapter part 350 is electrically connected to the third conductive adapter part 350 through a seventh via hole VH7.
  • the other end of the first compensation capacitor electrode 210 is electrically connected.
  • the scan signal lead GLY may be located in the first conductive layer 10
  • the first compensation capacitor electrode 210 may be located in the first conductive layer 10
  • the second conductive transfer part 340 may be located in the third conductive layer. 30 in.
  • At least two insulation layers are provided between the first conductive layer 10 and the third conductive layer 30 .
  • the fourth via hole VH4, the fifth via hole VH5, the sixth via hole VH6, and the seventh via hole VH7 respectively penetrate the at least two insulating layers.
  • the scanning signal lead GLY located in the first conductive layer 10 is electrically connected to the second conductive transfer part 340 located in the third conductive layer 30 through the fourth via hole VH4.
  • the first compensation capacitor electrode located in the first conductive layer 10 210 is electrically connected to the second conductive transfer part 340 located in the third conductive layer 30 through the fifth via VH5.
  • the scanning signal lead GLY and the first compensation capacitor electrode 210 are electrically connected together. .
  • the length of continuous extension of the same type of conductive traces can be reduced, thereby preventing electrostatic burns.
  • the scan signal lead GLY may be located in the first conductive layer 10
  • the first compensation capacitor electrode 210 may be located in the second conductive layer 20
  • the second conductive transfer part 340 may be located in the third conductive layer. 30 in.
  • At least one insulating layer is provided between the first conductive layer 10 and the second conductive layer 20 .
  • At least two insulation layers are provided between the first conductive layer 10 and the third conductive layer 30 .
  • the fourth via hole VH4 and the sixth via hole VH6 respectively penetrate the at least two insulating layers
  • the fifth via hole VH5 and the seventh via hole VH7 respectively penetrate the at least one insulating layer.
  • the scanning signal lead GLY located in the first conductive layer 10 is electrically connected to the second conductive transfer part 340 located in the third conductive layer 30 through the fourth via hole VH4.
  • the first compensation capacitor electrode located in the second conductive layer 20 210 is electrically connected to the second conductive transfer part 340 located in the third conductive layer 30 through the fifth via VH5.
  • the scanning signal lead GLY and the first compensation capacitor electrode 210 are electrically connected together. .
  • the length of continuous extension of the same type of conductive traces can be reduced, thereby preventing electrostatic burns.
  • the scan signal lead GLY may be located in the second conductive layer 20
  • the first compensation capacitor electrode 210 may be located in the second conductive layer 20
  • the second conductive transfer part 340 may be located in the third conductive layer. 30 in.
  • At least one insulating layer is provided between the second conductive layer 20 and the third conductive layer 30 .
  • the fourth via hole VH4, the fifth via hole VH5, the sixth via hole VH6, and the seventh via hole VH7 respectively penetrate the at least one insulating layer.
  • the scanning signal lead GLY located in the second conductive layer 20 is electrically connected to the second conductive transfer part 340 located in the third conductive layer 30 through the fourth via hole VH4.
  • the first compensation capacitor electrode located in the second conductive layer 20 210 is electrically connected to the second conductive transfer part 340 located in the third conductive layer 30 through the fifth via VH5.
  • the scanning signal lead GLY and the first compensation capacitor electrode 210 are electrically connected together. .
  • the length of continuous extension of the same type of conductive traces can be reduced, thereby preventing electrostatic burns.
  • the display substrate includes a common voltage signal bus 360 that provides the common voltage signal.
  • the compensation capacitor 200 is located on the side of the common voltage signal bus 360 close to the display area AA in the row direction X, and the compensation resistor 400 is located in the row direction
  • the compensation capacitor 200 is located on a side close to the display area AA, and the electrostatic protection circuit 300 is located on a side of the compensation resistor 400 close to the display area AA.
  • At least some embodiments of the present disclosure also provide a display panel including the display substrate as described above.
  • the display panel may be a liquid crystal display panel.
  • the display device may include the display substrate as described above.
  • the display device includes a display area AA and a frame area NA.
  • the frame area NA has a smaller width, thereby realizing a display device with a narrow frame.
  • the display device may include any device or product with a display function.
  • the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio Players, mobile medical devices, cameras, wearable devices (such as head-mounted devices, electronic clothing, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smart watches), televisions, etc.
  • the display device according to the embodiment of the present disclosure has all the features and advantages of the above-mentioned display substrate.

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Abstract

提供一种显示基板、显示装置和应用于显示基板的负载补偿方法。该显示基板包括：设置于衬底基板的多根扫描信号线，用于分别给多行像素单元提供扫描信号；设置于衬底基板上且位于边框区域中的多个负载补偿单元，分别与多根扫描信号线中的至少一些扫描信号线电连接。至少一个负载补偿单元包括补偿电容和补偿电阻中的至少一个。显示基板包括N行像素单元，N行像素单元中的n行像素单元包括的子像素的数量彼此不一致，N为大于等于2的正整数，n为大于等于2小于等于N的正整数。对于n行像素单元而言，各行像素单元的扫描信号线分别电连接各自的负载补偿单元，各行像素单元的负载补偿单元的负载补偿值与该行像素单元包括的子像素的数量负相关，负载补偿值包括电容补偿值和电阻补偿值中的至少一个。

Description

显示基板、显示装置和应用于显示基板的负载补偿方法 技术领域
本公开涉及显示技术领域，并且具体地涉及一种显示基板、显示装置和应用于显示基板的负载补偿方法。
背景技术
随着技术的不断发展，对显示屏进行异形定制化设计需求越来越多。在异形显示屏中，显示面板具有异形显示区域，在异形显示区域中每行像素单元的子像素的数量与正常显示区域中每行像素单元的子像素的数量差异较大。各行像素单元的子像素的数量差异较大，会导致正常显示区域和异形显示区域之间的负载差异大，或者导致相邻行的像素单元之间的负载差异大，从而可能会引起显示不良问题。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示基板，所述显示基板包括：衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，其中，至少一个所述负载补偿单元包括补偿电容和补偿电阻中的至少一个；所述显示基板包括N行像素单元，所述N行像素单元中的n行像素单元包括的子像素的数量彼此不一致，其中，N为大于等于2的正整数，n为大于等于2小于等于N的正整数；以及对于所述n行像素单元而言，各行像素单元的扫描信号线分别电连接各自的负载补偿单元， 各行像素单元的负载补偿单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。
根据一些示例性的实施例，所述补偿电容包括第一补偿电容电极和第二补偿电容电极，所述第一补偿电容电极与所述扫描信号线电连接，所述第二补偿电容电极接入所述公共电压信号，所述第一补偿电容电极在所述衬底基板上的正投影和所述第二补偿电容电极在所述衬底基板上的正投影至少部分交叠。
根据一些示例性的实施例，对于所述n行像素单元而言，给各行像素单元提供扫描信号的多根扫描信号引线分别电连接各自的补偿电容，各行像素单元的补偿电容的第一补偿电容电极和第二补偿电容电极之间的交叠面积与该行像素单元包括的子像素的数量负相关。
根据一些示例性的实施例，对于所述至少n行像素单元而言，各行像素单元的补偿电容的第一补偿电容电极和第二补偿电容电极中至少一个在行方向上的尺寸与该行像素单元包括的子像素的数量负相关。
根据一些示例性的实施例，所述补偿电阻包括补偿导电走线；以及对于所述n行像素单元而言，给各行像素单元提供扫描信号的多根扫描信号引线分别电连接各自的补偿导电走线，各行像素单元的补偿导电走线的电阻值与该行像素单元包括的子像素的数量负相关。
根据一些示例性的实施例，对于所述至少n行像素单元而言，各行像素单元的补偿导电走线的长度与该行像素单元包括的子像素的数量负相关，和/或，各行像素单元的补偿导电走线的线径与该行像素单元包括的子像素的数量正相关。
根据一些示例性的实施例，所述显示基板还包括：设置于所述衬底基板上且位于所述边框区域中的栅极驱动电路，所述栅极驱动电路用于输出扫描信号；以及设置于所述衬底基板且位于所述边框区域中的多根扫描信号引线，所述多根扫描信号引线分别与所述多根扫描信号线电连接，其中，所述显示基板包括：位于所述衬底基板上的第一导电层；位于所述第一导电层远离所述衬底基板一侧的第二导电层；以及位于所述第二导电层远离所述衬底基板一侧的第三导电层，其中，对于同一行像素单元而言，所述第一补偿电容电极和所述扫描信号引线彼此连接，所述第一补偿电容电极和所述扫描信号引线均位于选自所述第一导电层和所述第二导电层中的一个同一导电层。
根据一些示例性的实施例，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中，以及所述第二补偿电容电极位于所述第二导电层或所述第三导电层 中；或者，其中，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中，以及所述第二补偿电容电极位于所述第一导电层或所述第三导电层中。
根据一些示例性的实施例，所述补偿电容包括第一子补偿电容和第二子补偿电容，所述第二补偿电容电极包括第一子补偿电容电极和第二子补偿电容电极，所述第一子补偿电容电极和第二子补偿电容电极均接入所述公共电压信号；所述第一补偿电容电极位于所述第二导电层中，所述第一子补偿电容电极位于所述第一导电层中，所述第二子补偿电容电极位于所述第三导电层中；所述第一补偿电容电极在所述衬底基板上的正投影和所述第一子补偿电容电极在所述衬底基板上的正投影至少部分交叠，以形成所述第一子补偿电容电极；所述第一补偿电容电极在所述衬底基板上的正投影和所述第二子补偿电容电极在所述衬底基板上的正投影至少部分交叠，以形成所述第二子补偿电容电极。
根据一些示例性的实施例，所述显示基板还包括：设置于所述衬底基板上且位于所述边框区域中的驱动芯片，所述驱动芯片用于输出扫描信号；以及设置于所述衬底基板且位于所述边框区域中的多根扫描信号引线，所述多根扫描信号引线分别与所述多根扫描信号线电连接，其中，所述显示基板包括：位于所述衬底基板上的第一导电层；位于所述第一导电层远离所述衬底基板一侧的第二导电层；以及位于所述第二导电层远离所述衬底基板一侧的第三导电层，其中，对于同一行像素单元而言，所述第一补偿电容电极和所述扫描信号引线彼此连接，所述第一补偿电容电极和所述扫描信号引线均位于选自所述第一导电层和所述第二导电层中的一个同一导电层。
根据一些示例性的实施例，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中；对于偶数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中；对于全部n行像素单元而言，所述第二补偿电容电极均位于所述第三导电层中；或者，其中，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中；对于偶数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中；对于全部n行像素单元而言，所述第二补偿电容电极均位于所述第三导电层中。
根据一些示例性的实施例，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中，所述第二补偿电容电极位于所述第二导电层或所述第三导电层中；以及对于偶数行的像素单元而言，所述第一补偿电容电 极和所述扫描信号引线均位于所述第二导电层中，所述第二补偿电容电极位于所述第一导电层或所述第三导电层中；或者，其中，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中，所述第二补偿电容电极位于所述第一导电层或所述第三导电层中；以及对于偶数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中，所述第二补偿电容电极位于所述第二导电层或所述第三导电层中。
根据一些示例性的实施例，彼此连接的所述第一补偿电容电极和所述扫描信号引线为连续延伸的一体结构。
根据一些示例性的实施例，所述第一补偿电容电极包括自所述扫描信号引线延伸的多段弯曲走线；或者，所述第一补偿电容电极包括自所述扫描信号引线延伸的第一导电部，所述第一导电部具有镂空结构。
根据一些示例性的实施例，相邻两行的像素单元的扫描信号引线均沿行方向延伸，所述第一补偿电容电极在列方向行位于相邻两行的像素单元的扫描信号引线之间。
根据一些示例性的实施例，所述显示基板包括接入公共电压信号的静电保护环；以及所述第二补偿电容电极包括自静电保护环延伸的第二导电部。
根据一些示例性的实施例，对于所述n行像素单元而言，n行像素单元的补偿电容的第二导电部为连续延伸的一体结构；或者，对于所述n行像素单元而言，n行像素单元的补偿电容的第二导电部分别自所述静电保护环朝向所述显示区域延伸。
根据一些示例性的实施例，所述显示基板还包括静电保护电路，所述静电保护电路的一端与所述扫描信号引线和所述扫描信号线均电连接，所述静电保护电路的另一端与所述静电保护环电连接，用于将所述扫描信号引线和所述扫描信号线上的静电释放至所述静电保护环。
根据一些示例性的实施例，所述显示基板还包括位于所述第三导电层中的第一导电转接部；所述扫描信号引线靠近所述显示区域的一端通过第一过孔与所述第一导电转接部的第一部分电连接，所述扫描信号线远离所述显示区域的一端通过第二过孔与所述第一导电转接部的第二部分电连接，所述第一导电转接部的第三部分通过第三过孔与所述静电保护电路的一端电连接。
根据一些示例性的实施例，所述显示基板还包括位于所述第三导电层中的第二导电转接部；所述扫描信号引线的一部分通过第四过孔与所述第二导电转接部的一部分电连接，所述第二导电转接部的另一部分通过第五过孔与所述第一补偿电容电极的一 端电连接；和/或，所述显示基板还包括位于所述第三导电层中的第三导电转接部；所述扫描信号引线的另一部分通过第六过孔与所述第三导电转接部的一部分电连接，所述第三导电转接部的另一部分通过第七过孔与所述第一补偿电容电极的另一端电连接。
根据一些示例性的实施例，所述扫描信号引线的一部分形成所述补偿电阻。
根据一些示例性的实施例，给至少一行像素单元提供扫描信号的所述扫描信号引线的至少一部分包括多段弯曲走线，所述补偿电阻包括该多段弯曲走线。
根据一些示例性的实施例，任意相邻两行的像素单元的扫描信号线上的总负载的差异在规定的阈值内，其中，所述总负载包括扫描信号线上的电容负载和电阻负载的乘积。
根据一些示例性的实施例，所述显示基板包括提供所述公共电压信号的公共电压信号总线；以及对于至少一行像素单元的负载补偿单元而言，所述补偿电容在行方向上位于所述公共电压信号总线靠近所述显示区域的一侧，所述补偿电阻在行方向上位于所述补偿电容靠近所述显示区域的一侧，所述静电保护电路位于所述补偿电阻靠近所述显示区域的一侧。
在另一方面，提供一种显示装置，包括如上所述的显示基板。
在又一方面，提供一种应用于显示基板的负载补偿方法，所述显示基板包括：衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，其中，所述显示基板包括N行像素单元，其中，N为大于等于2的正整数，所述方法包括：驱动所述显示基板显示白画面；获取第p行像素单元和第q行像素单元的充电电压，其中，所述第p行像素单元为所述N行像素单元中子像素数量最少的一行像素单元，所述第q行像素单元为所述N行像素单元中子像素数量最多的一行像素单元；计算所述第p行像素单元和所述第q行像素单元的充电电压之差；比较所述充电电压之差与规定的电压阈值；响应于所述充电电压之差大于规定的电压阈值，确 定需要进行负载补偿；响应于所述负载补偿，确定需要进行负载补偿的n行像素单元，n为大于等于2小于等于N的正整数，其中，所述n行像素单元中每一行像素单元的充电电压与所述第q行像素单元的充电电压之差大于规定的阈值；根据所述n行像素单元中每一行像素单元的子像素的数量与所述第q行像素单元的子像素的数量，确定负载补偿单元的负载补偿值，其中，给所述n行像素单元提供扫描信号的多根扫描信号线分别电连接各自的负载补偿单元，所述n行像素单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。
在又一方面，提供一种一种应用于显示基板的负载补偿方法，所述显示基板包括：衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，其中，所述显示基板包括N行像素单元，其中，N为大于等于2的正整数，所述方法包括：计算任意相邻两行像素单元的负载差异；比较所述负载差异与规定的负载差异阈值；响应于所述负载差异大于规定的负载差异阈值，确定需要进行负载补偿的n行像素单元，n为大于等于2小于等于N的正整数，其中，所述n行像素单元中每一行像素单元与它相邻行的像素单元的负载差异大于所述规定的负载差异阈值；根据所述n行像素单元中每一行像素单元的子像素的数量与所述第q行像素单元的子像素的数量，确定负载补偿单元的负载补偿值，其中，所述第q行像素单元为所述N行像素单元中子像素数量最多的一行像素单元，给所述n行像素单元提供扫描信号的多根扫描信号线分别电连接各自的负载补偿单元，所述n行像素单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加 明显。
图1A是根据本公开的一些示例性实施例的显示装置的平面示意图。
图1B至图1D示意性示出了显示基板的几种异形形状的示例。
图2A是示意性示出图1A所示的显示装置的像素布局的示意图。
图2B是图1A所示的部分I的局部放大图。
图2C是图1A所示的部分II的局部放大图。
图3A为示意性示出根据本公开的一些示例性实施例的显示基板的一个子像素的结构示意图。
图3B示意性地示出了本公开实施例中薄膜晶体管的截面图。
图4A是根据本公开的一些示例性实施例的显示基板的扇出区的示意图。
图4B至图4D分别是图4A中的区域III、区域IV、区域V的局部放大图。
图5为图1A所示的显示基板中的相邻两行像素单元的信号扫描线在负载补偿之前的负载差异比值图。
图6是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了部分行的像素单元的负载补偿单元。
图7是图6中所示的显示基板的局部放大图，其示意性示出了第i行的像素单元的负载补偿单元。
图8是图6中所示的显示基板的局部放大图，其示意性示出了第i+1行的像素单元的负载补偿单元。
图9是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了某两行的像素单元的补偿电容和静电保护电路的平面图。
图10是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了某一行的像素单元的补偿电容、静电保护电路和静电保护结构的平面图。
图11是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了某些行的像素单元的补偿电容和补偿电阻的平面图。
图12A至图12D分别示意性示出了根据本公开的一些示例性实施例的显示基板的补偿电容的示意截面图。
图13A是根据本公开的一些示例性实施例的显示基板在图10中的区域VI处的局部放大图。
图13B是沿图13A中的线BB’截取的截面图。
图14A是根据本公开的另一些示例性实施例的显示基板在图10中的区域VI处的局部放大图。
图14B是沿图14A中的线CC’截取的截面图。
图15A是根据本公开的一些示例性实施例的显示基板在图10中的区域VI处的局部放大图。
图15B是沿图15A中的线DD’截取的截面图。
图16是根据本公开的一些示例性实施例的显示基板沿图3A中的线AA’截取的截面图。
图17A是根据本公开的一些示例性实施例的应用于显示基板的负载补偿方法的流程图。
图17B是根据本公开的另一些示例性实施例的应用于显示基板的负载补偿方法的流程图。
图18是根据本公开的一些示例性实施例的静电保护电路的等效电路图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在......之间”对“直接在......之间”、“相邻”对“直接相邻”或“在......上”对“直接在......上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于 直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XY、YZ和XZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
在本文中，术语“基本上”、“大约”、“近似”、“大致”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±30％、±20％、±10％、±5％内。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
本领域技术人员应该理解，在本文中，除非另有说明，表述“连续延伸”、“一体结构”、“整体结构”或类似表述表示：多个元件、部件、结构和/或部分是位于同一层的，并且在制造过程中通常通过同一次构图工艺形成的，这些元件、部件、结构和/或部分之间没有间隔或断裂处，而是连续延伸的结构。
需要说明的是，在本文中，表述“负相关”是指两个量的变化方向相反，例如，其中一个变大时，另一个就变小；一个变小时，另一个就变大。表述“正相关”是指两个量的变化方向相同，例如，其中一个变大时，另一个就变大；一个变小时，另一个就变小。
本公开的实施例至少提供一种显示基板和显示装置。所述显示基板包括：衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，其中，至少一个所述负载补偿单元包括补偿电容和补偿电阻中的至少一个；所述显示基板包括N行像素单元，所述N行像素单元中的n行像素单元包括的子像素的数量彼此不一致，其中，N为大于等于2的正整数，n为大于等于2小于等于N的正整数；以及对于所述n行像素单元而言，各行像素单元的扫描信号线分别电连接各自的负载补偿单元，各行像素单元的负载补偿单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。在本公开的实施例中，可以对负载不一致的各行像素单元进行负载补偿，例如，在需要进行负载补偿的各行像素单元的扫描信号线上电连接负载补偿单元，使得各行像素单元的扫描信号线上的负载基本一致，这样，可以至少改善、甚至消除各个子显示区域的显示不均一等不良现象。
图1A是根据本公开的一些示例性实施例的显示装置的平面示意图。图2A是示意性示出图1A所示的显示装置的像素布局的示意图。图2B是图1A所示的部分I的局部放大图。图2C是图1A所示的部分II的局部放大图。
结合参照图1A、图2A至图2C，所述显示装置1000可以包括显示基板。所述显示基板可以包括衬底基板100，所述衬底基板100可以包括显示区域AA和位于所述显示区域至少一侧的边框区域NA。需要说明的是，在图1所示的实施例中，边框区域NA包围显示区域AA，但是，本公开的实施例不局限于此，在其他实施例中，边框区域NA可以位于显示区域AA的至少一侧，但不包围所述显示区域AA。
所述显示基板可以包括位于显示区域AA中的多个像素单元P。需要说明的是，像素单元P是用于显示图像的最小单元。例如，像素单元P可以包括发射白色光和/或彩色光的发光器件。
像素单元P可以设置成多个，以沿着在第一方向(例如行方向)X上延伸的行和在第二方向(例如列方向)Y上延伸的列呈矩阵形式布置。然而，本公开的实施例不具体限制像素单元P的布置形式，并且可以以各种形式布置像素单元P。例如，像素单元P可以布置为使得相对于第一方向X和第二方向Y倾斜的方向成为列方向，并且使得与列方向交叉的方向成为行方向。
一个像素单元P可以包括多个子像素。例如，一个像素单元P可以包括3个子像素，即第一子像素SP1、第二子像素SP2和第三子像素SP3。再例如，一个像素单元P可以包括4个子像素，即第一子像素、第二子像素、第三子像素和第四子像素。例如，第一子像素SP1可以为红色子像素，第二子像素SP2可以为绿色子像素，第三子像素SP3可以为蓝色子像素，第四子像素可以为白色子像素。
在一些示例性的实施例中，所述显示基板可以为液晶显示基板，例如，液晶显示面板的阵列基板。图3A为示意性示出根据本公开的一些示例性实施例的显示基板的一个子像素的结构示意图。结合参照图1A至图3A，所述显示基板可以包括：设置于所述衬底基板100上的第一电极E1、第二电极E2、数据信号线DL和扫描信号线GL。应该理解，在显示面板为液晶显示面板的情况下，所述显示面板可以包括位于阵列基板与彩膜基板之间的液晶层。阵列基板、彩膜基板和液晶层的具体结构可以参照现有的液晶显示面板的结构，在此不再赘述。第一电极E1和第二电极E2能够在驱动信号的驱动下产生相应的液晶电场。液晶层中的液晶能够在液晶电场的作用下偏转，从而实现相应的显示功能。示例性地，液晶层可以设置在第一电极E1和第二电极E2之间。第一电极E1和第二电极E2中的一者可以为像素电极，另一者可以是公共电极，例如，第一电极E1为公共电极，第二电极E2为像素电极。
在一些具体实施例中，至少一个子像素还包括与数据信号线DL电连接的薄膜晶体管T。在本公开实施例中，薄膜晶体管T可以为顶栅结构也可以为底栅结构，具体可以根据实际需要确定，在此不作限制。下面以薄膜晶体管T采用顶栅结构为例，对本公开实施例的薄膜晶体管T进行说明。
图3B示意性地示出了本公开实施例中薄膜晶体管的截面图，图16是根据本公开的一些示例性实施例的显示基板沿图2B中的线AA’截取的截面图。结合参照图3A、图3B和图16，所述显示基板可以包括：位于所述衬底基板100上的半导体层ACT；位于所述半导体层ACT远离所述衬底基板100一侧的第一导电层10；位于所述第一导电层10远离所述衬底基板100一侧的第二导电层20；以及位于所述第二导电层20远离所述衬底基板100一侧的第三导电层30。例如，薄膜晶体管T可以包括有源层CH、栅极GE1、源极SE1和漏极DE1。所述薄膜晶体管T的有源层CH可以位于半导体层ACT中，所述薄膜晶体管T的栅极GE1可以位于第一导电层10中，所述薄膜晶体管T的源极SE1和漏极DE1可以位于第二导电层20中。例如，第一电极E1(例如公共电极)可以位于第三导电层30中。
如图3A所示，所述显示基板可以采用两像两畴(2Pixel2Domain，2P2D)的子像素结构设计。每个子像素可以包括多个条形的像素电极E2，每个子像素的多个条形的像素电极E2被狭缝间隔开。所谓两像两畴是指：相邻的两行子像素的像素电极E2的延伸方向不同，且每相邻的两行子像素的像素电极E2相对于扫描信号线GL大致对称。因此，在显示基板中，对于相邻的两行子像素，其中一行子像素的像素电极E2和公共电极E1能够形成第一畴电场，另一行子像素的像素电极E2和公共电极E1能够形成第二畴电场。其中，第一畴电场和第二畴电场的方向不同，换句话说，每相邻的两行子像素所对应的电场的方向之间呈一定夹角，进而，每相邻的两行子像素的出光方向可以互相补偿，有利于提高显示效果。
返回参照图1A，所述显示基板可以具有不规则形状，所述不规则形状可以包括任何异形形状，例如，图1B至图1D示意性示出了几种异形形状的示例。应该理解，本公开的实施例对所述显示基板的形状不做特别限制，下面，以图1A所示的异形形状为示例，对本公开的实施例进行详细描述。
在本公开的实施例中，所述显示基板包括N行像素单元，其中，N为大于等于2的正整数。示例性地，参照图1A，所述显示区域AA可以包括多个子显示区域AA1、 AA2、AA3。例如，在子显示区域AA1、AA2、AA3中，分别设置有至少一行像素单元。在图1A所示的实施例在，各行像素单元包括的子像素的数量从下向上呈现不规律减小，例如，位于子显示区域AA3中的各行像素单元包括的子像素的数量大于位于子显示区域AA2中的各行像素单元包括的子像素的数量，位于子显示区域AA2中的各行像素单元包括的子像素的数量大于位于子显示区域AA1中的各行像素单元包括的子像素的数量。
对于各行像素单元而言，设置一根扫描信号线GL，给该行像素单元的各个子像素提供扫描信号。在本公开的实施例中，在所述N行像素单元中，存在n行像素单元，该n行像素单元包括的子像素的数量彼此不一致，其中，n为大于等于2小于等于N的正整数。这n行像素单元的扫描信号线GL上电连接的负载彼此不一致。例如，可以根据显示基板的设计图计算每行像素单元的扫描信号线线的理论负载，对于扫描信号线而言，其负载可以包括电阻负载和电容负载。
所述N行像素单元中第i行像素单元的扫描信号线上的电阻R可以用以下公式计算：
Ri＝Rs*L/W，其中L为第i行像素单元的扫描信号线的长度，W为第i行像素单元的扫描信号线的宽度，Rs是第i行像素单元的扫描信号线所使用金属材料的方块电阻。
所述N行像素单元中第i行像素单元的扫描信号线上的电容Ci可以用以下公式计算：
Ci＝Ni*Cpixel，其中Ni是第i行像素单元包括的子像素的个数，Cpixel是单个子像素的电容负载值，它可以通软件提取或根据面积计算平板电容得到。
发明人经研究发现，对于负载不一致的各行像素单元，在相同的充电时间内实现的充电电压不一致，这样，在实际显示时，可能导致各个子显示区域的显示不均一等不良现象。
在本公开的实施例中，可以对负载不一致的各行像素单元进行负载补偿，例如，在需要进行负载补偿的各行像素单元的扫描信号线上电连接负载补偿单元，使得各行像素单元的扫描信号线上的负载基本一致，这样，可以至少改善、甚至消除各个子显示区域的显示不均一等不良现象。
结合参照图1A至图3B，根据本公开的一些示例性实施例的显示基板可以包括： 衬底基板100，所述衬底基板100包括显示区域AA和位于所述显示区域至少一侧的边框区域NA；位于所述显示区域AA中的多个像素单元P，所述多个像素单元P沿行方向X和列方向Y成阵列地设置于所述衬底基板100，每一行像素单元P可以包括多个子像素；设置于所述衬底基板100的多根扫描信号线GL，所述多根扫描信号线GL用于分别给多行像素单元P提供扫描信号；设置于所述衬底基板100上且位于所述边框区域NA中的多个负载补偿单元200，所述多个负载补偿单元200分别与所述多根扫描信号线GL中的至少一些扫描信号线电连接；以及设置于所述衬底基板100上的公共电极E1，所述公共电极E1的至少一部分位于所述显示区域AA中，所述公共电极E1接入公共电压信号。
图17A是根据本公开的一些示例性实施例的应用于显示基板的负载补偿方法的流程图。所述负载补偿方法可以包括以下的步骤S1710～S1770。
在步骤S1710中，驱动所述显示基板显示白画面。例如，对于例如ADS型液晶显示基板的显示基板而言，白画面需要的充电电压最大。
在步骤S1720中，获取第p行像素单元和第q行像素单元的充电电压，其中，所述第p行像素单元为所述N行像素单元中子像素数量最少的一行像素单元，所述第q行像素单元为所述N行像素单元中子像素数量最多的一行像素单元。例如，所述第p行像素单元为负载较小的一行像素单元，其对应的扫描信号线上的充电电压较大，记为Vmax；所述第q行像素单元为负载较大的一行像素单元，其对应的扫描信号线上的充电电压较小，记为Vmin。
在步骤S1730中，计算所述第p行像素单元和所述第q行像素单元的充电电压之差。例如，δV＝Vmax-Vmin，其中，δV为所述充电电压之差。
在步骤S1740中，比较所述充电电压之差与规定的电压阈值。例如，所述规定的电压阈值为一个可以接受的范围和不可接受范围的临界值，可以接受的范围的根据是使用者不能看出整个面板显示差异，例如显示不均等缺陷。换句话说，就是显示时，整个面板同一灰阶时，δV小于一个灰阶就不会被肉眼看出来，因此，所述临界值可以计算出来。根据gamma曲线得到的，6bit的数据确定信号最小电压差(即所述规定的电压阈值)是大约30mV，8bit的数据确定信号最小电压差(即所述规定的电压阈值)是大约8mV。
在步骤S1750中，响应于所述充电电压之差大于规定的电压阈值，确定需要进行 负载补偿。例如，当确定至少一行的像素单元的充电电压与Vmin的差大于所述规定的电压阈值(例如8mV)时，确定该显示基板需要进行负载补偿。
在步骤S1760中，响应于所述负载补偿，确定需要进行负载补偿的n行像素单元，n为大于等于2小于等于N的正整数，其中，所述n行像素单元中每一行像素单元的充电电压与所述第q行像素单元的充电电压之差大于规定的阈值。
例如，确定除第q行像素单元之外的其余行的像素单元的充电电压与Vmin的电压差，找出所述电压差大于所述规定的电压阈值(例如8mV)的所有行的像素单元，将这些行的像素单元确定为需要进行负载补偿的n行像素单元。以此方式，可以精确地确定需要进行负载补充的n行像素单元。
在步骤S1770中，根据所述n行像素单元中每一行像素单元的子像素的数量与所述第q行像素单元的子像素的数量，确定负载补偿单元的负载补偿值，其中，给所述n行像素单元提供扫描信号的多根扫描信号线分别电连接各自的负载补偿单元，所述n行像素单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。以此方式，在精确地确定需要进行负载补充的n行像素单元的基础上，对n行像素单元的扫描信号线进行负载补偿，使得各行像素单元的扫描信号线上的负载基本一致，这样，可以至少改善、甚至消除各个子显示区域的显示不均一等不良现象。
图5为图1A所示的显示基板中的相邻两行像素单元的信号扫描线在负载补偿之前的负载差异比值图，图17B是根据本公开的另一些示例性实施例的应用于显示基板的负载补偿方法的流程图。结合参照图5和图17B，所述负载补偿方法可以包括以下的步骤S1810～S1870。
在步骤S1810中，计算任意相邻两行像素单元的负载差异。例如，所述负载差异可以用相邻两行像素单元的负载差异百分比Ai表示：
Ai＝[(R i*C i-R i+1*C i+1)/R i+1*C i+1]*100％，其中，R i和C i分别表示第i行像素单元的电阻负载值和电容负载值，R i+1和C i+1分别表示第i+1行像素单元的电阻负载值和电容负载值。
在步骤S1820中，比较所述负载差异与规定的负载差异阈值。例如，所述负载差异阈值可以根据使用者是否能够肉眼看出显示差异确定，所述负载差异阈值可以为约2％～5％。
在步骤S1830中，响应于所述负载差异大于规定的负载差异阈值，确定需要进行负载补偿的n行像素单元，n为大于等于2小于等于N的正整数，其中，所述n行像素单元中每一行像素单元与它相邻行的像素单元的负载差异大于所述规定的负载差异阈值。
如图5所示，通过相邻两行像素单元的扫描信号线上的负载差异比值图可以看出：对于图1A所示的实施例，从940行开始Ai值发生突变，一直到960行，因此对第940～960行像素单元进行负载补偿，另外，从950行开始相邻两行间Ai值开始大于所述负载差异阈值，需要对第950～960行像素单元进行补偿，需要补偿区域如图1A中所示的子显示区域AA1。需要说明的是，虽然子显示区域AA2也是异形显示区，既没有出现Ai值突变，且相邻两行间Ai值小于所述负载差异阈值，不需要进行负载补偿。以此方式，可以精确地确定需要进行负载补充的n行像素单元。
在步骤S1840中，根据所述n行像素单元中每一行像素单元的子像素的数量与所述第q行像素单元的子像素的数量，确定负载补偿单元的负载补偿值，其中，所述第q行像素单元为所述N行像素单元中子像素数量最多的一行像素单元，给所述n行像素单元提供扫描信号的多根扫描信号线分别电连接各自的负载补偿单元，所述n行像素单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。以此方式，在精确地确定需要进行负载补充的n行像素单元的基础上，对n行像素单元的扫描信号线进行负载补偿，使得各行像素单元的扫描信号线上的负载基本一致，这样，可以至少改善、甚至消除各个子显示区域的显示不均一等不良现象。
在本公开的实施例中，至少一个所述负载补偿单元包括补偿电容和补偿电阻中的至少一个。
例如，所述补偿电容包括第一补偿电容电极和第二补偿电容电极，所述第一补偿电容电极与所述扫描信号线电连接，所述第二补偿电容电极接入所述公共电压信号，所述第一补偿电容电极在所述衬底基板上的正投影和所述第二补偿电容电极在所述衬底基板上的正投影至少部分交叠。对于所述n行像素单元而言，给各行像素单元提供扫描信号的多根扫描信号引线分别电连接各自的补偿电容，各行像素单元的补偿电容的第一补偿电容电极和第二补偿电容电极之间的交叠面积与该行像素单元包括的子像素的数量负相关。对于所述至少n行像素单元而言，各行像素单元的补偿电容的第一 补偿电容电极和第二补偿电容电极中至少一个在行方向上的尺寸与该行像素单元包括的子像素的数量负相关。
例如，所述补偿电阻包括补偿导电走线。对于所述n行像素单元而言，给各行像素单元提供扫描信号的多根扫描信号引线分别电连接各自的补偿导电走线，各行像素单元的补偿导电走线的电阻值与该行像素单元包括的子像素的数量负相关。对于所述至少n行像素单元而言，各行像素单元的补偿导电走线的长度与该行像素单元包括的子像素的数量负相关，和/或，各行像素单元的补偿导电走线的线径与该行像素单元包括的子像素的数量正相关。
在本公开实施例提供的显示基板中，负载补偿单元对应的扫描信号线上连接的子像素的数量越少，负载补偿单元的补偿负载值越打。利用具有不同补偿负载值的负载补偿单元来补偿具有不同子像素数量的扫描信号线，从而使不同扫描信号线上的负载均一，避免发生显示差异，保证显示品质。
返回参照图1，根据本公开的一些示例性实施例的显示基板可以包括：设置于所述衬底基板100上且位于所述边框区域NA中的驱动芯片110，所述驱动芯片110用于输出扫描信号；以及设置于所述衬底基板100且位于所述边框区域NA中的多根扫描信号引线GLY，所述多根扫描信号引线GLY分别与所述多根扫描信号线GL电连接。例如，所述驱动芯片110可以为用于提供栅极扫描信号的栅极驱动芯片，相应地，所述扫描信号线GL为栅线，所述扫描信号引线GLY为栅极引线。在该实施例中，扫描信号引线GLY电连接于驱动芯片110与扫描信号线GL之间，用于将驱动芯片110生成的扫描信号提供给扫描信号线GL。扫描信号线GL再将扫描信号传输给与其电连接的某行像素单元的各个子像素。在该实施例中，扫描信号引线GLY位于扇出区(即fanout区)，即，扫描信号引线GLY为扇出区走线。
图4A是根据本公开的一些示例性实施例的显示基板的扇出区的示意图。图4B至图4D分别是图4A中的区域III、区域IV、区域V的局部放大图。如图4A至图4D所示，所述显示基板的扇出区FA的空间有限，在该扇出区FA中，需要布置较多数量的扫描信号引线GLY。在这种情况下，在扇出区FA中，对扫描信号引线GLY采取双层布线的方式。即，相邻两行的像素单元的扫描信号引线GLY可以分别位于两个不同的导电层中，以有利于扇出区FA中的布线。
例如，对于奇数行的像素单元而言，扫描信号引线GLY位于第一导电层10中； 对于偶数行的像素单元而言，扫描信号引线GLY位于第二导电层20中。可选地，对于奇数行的像素单元而言，扫描信号引线GLY位于第二导电层20中；对于偶数行的像素单元而言，扫描信号引线GLY位于第一导电层10中。
需要说明的是，在本公开的其他实施例中，例如，在扇出区FA的空间足够的情况下，在扇出区FA中，对扫描信号引线GLY可以采取单层布线的方式。例如，对于N行像素单元而言，所有扫描信号引线GLY均位于第一导电层10中。可选地，对于N行像素单元而言，所有扫描信号引线GLY均位于第二导电层20中。
图6是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了部分行的像素单元的负载补偿单元。图7是图6中所示的显示基板的局部放大图，其示意性示出了第i行的像素单元的负载补偿单元。图8是图6中所示的显示基板的局部放大图，其示意性示出了第i+1行的像素单元的负载补偿单元。图9是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了某两行的像素单元的补偿电容和静电保护电路的平面图。图10是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了某一行的像素单元的补偿电容、静电保护电路和静电保护结构的平面图。图11是根据本公开的一些示例性实施例的显示基板的局部示意图，其示意性示出了某些行的像素单元的补偿电容和补偿电阻的平面图。图12A至图12D分别示意性示出了根据本公开的一些示例性实施例的显示基板的补偿电容的示意截面图。图13A是根据本公开的一些示例性实施例的显示基板在图10中的区域VI处的局部放大图。图13B是沿图13A中的线BB’截取的截面图。图14A是根据本公开的另一些示例性实施例的显示基板在图10中的区域VI处的局部放大图。图14B是沿图14A中的线CC’截取的截面图。图15A是根据本公开的一些示例性实施例的显示基板在图10中的区域VI处的局部放大图。图15B是沿图15A中的线DD’截取的截面图。
在本公开的实施例中，如上所述，扫描信号引线GLY可以采取双层布线的方式。如图7所示，第i行的像素单元的扫描信号引线GLY位于第二导电层20中；如图8所示，第i+1行的像素单元的扫描信号引线GLY位于第一导电层10中。
在本公开的实施例中，所述补偿电容200可以包括第一补偿电容电极210和第二补偿电容电极220。第一补偿电容电极210可以接入扫描信号，例如，栅极扫描信号；第二补偿电容电极220可以接入公共电压信号。
例如，第一补偿电容电极210可以与栅极扫描引线GLY连接。再例如，如图7至 图9所示，彼此连接的所述第一补偿电容电极210和所述扫描信号引线GLY可以为连续延伸的一体结构。
例如，所述第一补偿电容电极210包括自所述扫描信号引线GLY延伸的多段弯曲走线。可选地，所述第一补偿电容电极210包括自所述扫描信号引线GLY延伸的第一导电部，所述第一导电部具有镂空结构。在本公开的实施例中，通过将第一补偿电容电极设置为与扫描信号引线连接，即第一补偿电容电极与扫描信号引线同层设置，有利于形成所述第一补偿电容电极。第一补偿电容电极形成为多段弯曲走线或带镂空结构的导电部，在保证其有较大的导电面积的情况下，可以避免静电聚集在第一补偿电容电极上，有利于静电防护。
如图7所示，所述显示基板还可以包括接入公共电压信号的静电保护环310。第二补偿电容电极220可以与静电保护环310连接，以接入所述公共电压信号。例如，所述第二补偿电容电极220包括自静电保护环310延伸的第二导电部320。
参照图9，对于所述n行像素单元而言，n行像素单元的补偿电容的第二导电部320为连续延伸的一体结构。
参照图10，对于所述n行像素单元而言，n行像素单元的补偿电容的第二导电部320分别自所述静电保护环310朝向所述显示区域AA延伸。
对于需要负载补偿的n行像素单元中的任一行像素单元而言，在该行像素单元的扫描信号引线GLY上连接有所述补偿电容，所述补偿电容的第一补偿电容电极和第二补偿电容电极分别位于不同的导电层，第一补偿电容电极和第二补偿电容电极在衬底基板100上的正投影至少部分交叠，且第一补偿电容电极和第二补偿电容电极之间设置有至少一个绝缘层，以形成电容的结构。
例如，对于奇数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第一导电层10中，如图8、图9、图12A所示。对于偶数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第二导电层20中，如图7、图9、图10、图12B所示。对于全部n行像素单元而言，所述第二补偿电容电极220均位于所述第三导电层30中，如图7-10、图12A、图12B所示。
可选地，对于奇数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第二导电层20中，如图7、图9、图10、图12B所示。对于 偶数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第一导电层10中，如图8、图9、图12A所示。对于全部n行像素单元而言，所述第二补偿电容电极220均位于所述第三导电层30中，如图7-10、图12A、图12B所示。
可选地，对于奇数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第一导电层10中，如图8、图9、图12A所示；所述第二补偿电容电极220位于所述第二导电层20(如图12C所示)或所述第三导电层30中。对于偶数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第二导电层20中，如图7、图9、图10、图12B所示；所述第二补偿电容电极220位于所述第二导电层20(如图12C所示)或所述第三导电层30中。
可选地，对于奇数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第二导电层20中，如图7、图9、图10、图12B所示；所述第二补偿电容电极220位于所述第二导电层20(如图12C所示)或所述第三导电层30中。对于偶数行的像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第一导电层10中，如图8、图9、图12A所示；所述第二补偿电容电极220位于所述第二导电层20(如图12C所示)或所述第三导电层30中。
可选地，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第一导电层10中，以及所述第二补偿电容电极220位于所述第二导电层20或所述第三导电层30中。
可选地，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第二导电层20中，以及所述第二补偿电容电极220位于所述第一导电层10或所述第三导电层30中。
也就是说，对于同一行像素单元而言，所述第一补偿电容电极210和所述扫描信号引线GLY彼此连接，所述第一补偿电容电极210和所述扫描信号引线GLY均位于选自所述第一导电层10和所述第二导电层20中的一个同一导电层；第二补偿电容电极220位于与所述第一补偿电容电极210不同的另一导电层中。
根据本公开的另一些示例性的实施例，所述显示基板可以采用GOA技术，即Gate Driver on Array。在GOA技术中，将驱动电路直接设置于阵列基板或显示基板上，以代替外接驱动芯片。每个GOA单元作为一级移位寄存器，每级移位寄存器与一条扫 描信号线连接，通过各级移位寄存器依序轮流输出开启电压，实现像素的逐行扫描。在一些实施例中，每级移位寄存器也可以与多条扫描信号线连接。这样，可以适应显示基板高分辨率、窄边框的发展趋势。
参照图11，所述显示基板可以包括：设置于所述衬底基板100上且位于所述边框区域NA中的栅极驱动电路120，所述栅极驱动电路120用于输出扫描信号；以及设置于所述衬底基板100且位于所述边框区域NA中的多根扫描信号引线GLY，所述多根扫描信号引线GLY分别与所述多根扫描信号线GL电连接。在该实施例中，扫描信号引线GLY电连接于栅极驱动电路120与扫描信号线GL之间，用于将栅极驱动电路120生成的扫描信号提供给扫描信号线GL。扫描信号线GL再将扫描信号传输给与其电连接的某行像素单元的各个子像素。在该实施例中，扫描信号引线GLY不需要设置于扇出区(即fanout区)。在这种情况下，扫描信号引线GLY可以采取单层布线的方式。
例如，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第一导电层10中，以及所述第二补偿电容电极220位于所述第二导电层20或所述第三导电层30中。
可选地，所述第一补偿电容电极210和所述扫描信号引线GLY均位于所述第二导电层20中，以及所述第二补偿电容电极220位于所述第一导电层10或所述第三导电层30中。
参照图12D，在本公开的一些示例性实施例中，所述补偿电容200可以包括第一子补偿电容200A和第二子补偿电容200B，所述第二补偿电容电极220包括第一子补偿电容电极221和第二子补偿电容电极222，所述第一子补偿电容电极221和第二子补偿电容电极222均接入所述公共电压信号。
例如，所述第一补偿电容电极210位于所述第二导电层20中，所述第一子补偿电容电极221位于所述第一导电层10中，所述第二子补偿电容电极222位于所述第三导电层30中。
所述第一补偿电容电极210在所述衬底基板上的正投影和所述第一子补偿电容电极221在所述衬底基板上的正投影至少部分交叠，以形成所述第一子补偿电容电极200A。
所述第一补偿电容电极210在所述衬底基板上的正投影和所述第二子补偿电容电 极222在所述衬底基板上的正投影至少部分交叠，以形成所述第二子补偿电容电极200B。
在该实施例中，所述补偿电容包括并联的2个电容，通过这样的方式，有利于增大第一补偿电容电极与第二补偿电容电极之间的交叠面积，从而有利于增大补偿电容的电容值。这样，可以在减小补偿电容占用边框区域的宽度的情况下实现相同电容值的补偿电容，从而有利于窄边框显示装置的实现。
在本公开的实施例中，所述负载补偿单元可以包括补偿电容和补偿电阻中的至少一个，例如，所述负载补偿单元可以仅包括上述的补偿电容，所述负载补偿单元可以仅包括补偿电阻，或者，所述负载补偿单元可以包括补偿电容和补偿电阻两者。
参照图10和图11，所述扫描信号引线GLY的一部分形成所述补偿电阻400。
例如，给至少一行像素单元提供扫描信号的所述扫描信号引线GLY的至少一部分包括多段弯曲走线，所述补偿电阻400包括该多段弯曲走线。通过这样的弯曲走线方式，可以增大所述扫描信号引线GLY的长度，从而增大其电阻。以此方式，对所述扫描信号引线进行电阻补偿。
可选地，还可以改变所述扫描信号引线GLY的线径，以对所述扫描信号引线进行电阻补偿。
返回参照图11，相邻两行的像素单元的扫描信号引线GLY均沿行方向X延伸，所述第一补偿电容电极210在列方向Y行位于相邻两行的像素单元的扫描信号引线GLY之间。
参照图7至图11，所述显示基板还包括静电保护电路300，所述静电保护电路300的一端与所述扫描信号引线GLY和所述扫描信号线GL均电连接，所述静电保护电路300的另一端与所述静电保护环310电连接，用于将所述扫描信号引线GLY和所述扫描信号线GL上的静电释放至所述静电保护环310。
图18是根据本公开的一些示例性实施例的静电保护电路的等效电路图。结合参照图7至图11以及图18，所述静电保护电路可以包括四个薄膜晶体管，例如，所述静电保护电路的薄膜晶体管可以和像素驱动电路的薄膜晶体管同时形成。薄膜晶体管T1的栅电极G1和薄膜晶体管T1的源电极S1电连接在一起，形成静电保护电路的第一个外引线，例如，该外引线可以与所述扫描信号引线GLY和所述扫描信号线GL均电连接。薄膜晶体管T2的漏电极D2可以与薄膜晶体管T1的源电极S1电连接。与此类 似，薄膜晶体管T2的栅电极G2和薄膜晶体管T2的源电极S2电连接在一起。薄膜晶体管T1的漏电极D1与薄膜晶体管T2的源电极S2电连接。薄膜晶体管T3的栅电极G3和薄膜晶体管T3的源电极S3电连接在一起，并与薄膜晶体管T1的漏电极D1以及薄膜晶体管T2的栅电极G2电连接在一起。薄膜晶体管T4的漏电极D4与薄膜晶体管T3的源电极S3电连接。与前类似，薄膜晶体管T4的栅电极G4和薄膜晶体管T4的源电极S4电连接在一起，形成静电保护电路的第二个外引线，例如，该外引线可以与所述静电保护环310电连接。薄膜晶体管T3的漏电极D3与薄膜晶体管T4的源电极S4电连接。
在本公开的实施例中，当高电压静电发生在一条扫描信号引线GLY或扫描信号线GL上时，则此高电压静电会通过静电保护电路300分散到所述静电保护环310上，接着通过所述静电保护环310分散至公共电压信号总线上，从而把高电压静电分散至整个显示基板上。以此方式，可以避免高电压静电损坏某一条扫描信号引线GLY或扫描信号线GL。
如图9所示，所述显示基板还包括位于所述第三导电层30中的第一导电转接部330。所述扫描信号引线GLY靠近所述显示区域AA的一端通过第一过孔VH1与所述第一导电转接部330的第一部分电连接，所述扫描信号线GL远离所述显示区域AA的一端通过第二过孔VH2与所述第一导电转接部330的第二部分电连接，所述第一导电转接部330的第三部分通过第三过孔VH3与所述静电保护电路300的一端电连接。
可选地，所述显示基板还可以包括补偿电容的静电保护结构。参照图10，所述显示基板还包括位于所述第三导电层30中的第二导电转接部340。所述扫描信号引线GLY的一部分通过第四过孔VH4与所述第二导电转接部340的一部分电连接，所述第二导电转接部340的另一部分通过第五过孔VH5与所述第一补偿电容电极210的一端电连接。
所述显示基板还包括位于所述第三导电层30中的第三导电转接部350。所述扫描信号引线GLY的另一部分通过第六过孔VH6与所述第三导电转接部350的一部分电连接，所述第三导电转接部350的另一部分通过第七过孔VH7与所述第一补偿电容电极210的另一端电连接。
例如，参照图13A和图13B，扫描信号引线GLY可以位于第一导电层10中，第一补偿电容电极210可以位于第一导电层10中，第二导电转接部340可以位于第三导 电层30中。第一导电层10与第三导电层30之间设置有至少2个绝缘层。在这种情况下，第四过孔VH4、第五过孔VH5、第六过孔VH6和第七过孔VH7分别贯穿所述至少2个绝缘层。位于第一导电层10中的扫描信号引线GLY通过第四过孔VH4与位于第三导电层30中的第二导电转接部340电连接，位于第一导电层10中的第一补偿电容电极210通过第五过孔VH5与位于第三导电层30中的第二导电转接部340电连接，通过这样的导电转接结构，将扫描信号引线GLY和第一补偿电容电极210电连接在一起。通过这样的换层设计，可以减小同种导电走线连续延伸的长度，从而可以防止静电烧伤发生。
例如，参照图14A和图14B，扫描信号引线GLY可以位于第一导电层10中，第一补偿电容电极210可以位于第二导电层20中，第二导电转接部340可以位于第三导电层30中。第一导电层10与第二导电层20之间设置有至少1个绝缘层。第一导电层10与第三导电层30之间设置有至少2个绝缘层。在这种情况下，第四过孔VH4和第六过孔VH6分别贯穿所述至少2个绝缘层，第五过孔VH5和第七过孔VH7分别贯穿所述至少1个绝缘层。位于第一导电层10中的扫描信号引线GLY通过第四过孔VH4与位于第三导电层30中的第二导电转接部340电连接，位于第二导电层20中的第一补偿电容电极210通过第五过孔VH5与位于第三导电层30中的第二导电转接部340电连接，通过这样的导电转接结构，将扫描信号引线GLY和第一补偿电容电极210电连接在一起。通过这样的换层设计，可以减小同种导电走线连续延伸的长度，从而可以防止静电烧伤发生。
例如，参照图15A和图15B，扫描信号引线GLY可以位于第二导电层20中，第一补偿电容电极210可以位于第二导电层20中，第二导电转接部340可以位于第三导电层30中。第二导电层20与第三导电层30之间设置有至少1个绝缘层。在这种情况下，第四过孔VH4、第五过孔VH5、第六过孔VH6和第七过孔VH7分别贯穿所述至少1个绝缘层。位于第二导电层20中的扫描信号引线GLY通过第四过孔VH4与位于第三导电层30中的第二导电转接部340电连接，位于第二导电层20中的第一补偿电容电极210通过第五过孔VH5与位于第三导电层30中的第二导电转接部340电连接，通过这样的导电转接结构，将扫描信号引线GLY和第一补偿电容电极210电连接在一起。通过这样的换层设计，可以减小同种导电走线连续延伸的长度，从而可以防止静电烧伤发生。
参照图10，所述显示基板包括提供所述公共电压信号的公共电压信号总线360。对于至少一行像素单元的负载补偿单元而言，所述补偿电容200在行方向X上位于所述公共电压信号总线360靠近所述显示区域AA的一侧，所述补偿电阻400在行方向X上位于所述补偿电容200靠近所述显示区域AA的一侧，所述静电保护电路300位于所述补偿电阻400靠近所述显示区域AA的一侧。
本公开的至少一些实施例还提供一种显示面板，所述显示面板包括如上所述的显示基板。例如，所述显示面板可以是液晶显示面板。
本公开的至少一些实施例还提供一种显示装置。该显示装置可以包括如上所述的显示基板。所述显示装置包括显示区域AA和边框区域NA，边框区域NA具有较小的宽度，从而实现了窄边框的显示装置。
所述显示装置可以包括任何具有显示功能的设备或产品。例如，所述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴没备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
应该理解，根据本公开实施例的显示装置具有上述显示基板的所有特点和优点，具体可以参见上文的描述，在此不再赘述。
虽然本公开的总体技术构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (27)

  1. 一种显示基板，其特征在于，所述显示基板包括：
    衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；
    位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；
    设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；
    设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及
    设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，
    其中，至少一个所述负载补偿单元包括补偿电容和补偿电阻中的至少一个；
    所述显示基板包括N行像素单元，所述N行像素单元中的n行像素单元包括的子像素的数量彼此不一致，其中，N为大于等于2的正整数，n为大于等于2小于等于N的正整数；以及
    对于所述n行像素单元而言，各行像素单元的扫描信号线分别电连接各自的负载补偿单元，各行像素单元的负载补偿单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。
  2. 根据权利要求1所述的显示基板，其中，所述补偿电容包括第一补偿电容电极和第二补偿电容电极，所述第一补偿电容电极与所述扫描信号线电连接，所述第二补偿电容电极接入所述公共电压信号，所述第一补偿电容电极在所述衬底基板上的正投影和所述第二补偿电容电极在所述衬底基板上的正投影至少部分交叠。
  3. 根据权利要求2所述的显示基板，其中，对于所述n行像素单元而言，给各行像素单元提供扫描信号的多根扫描信号引线分别电连接各自的补偿电容，各行像素单元的补偿电容的第一补偿电容电极和第二补偿电容电极之间的交叠面积与该行像素单元包括的子像素的数量负相关。
  4. 根据权利要求3所述的显示基板，其中，对于所述至少n行像素单元而言，各行像素单元的补偿电容的第一补偿电容电极和第二补偿电容电极中至少一个在行方向上的尺寸与该行像素单元包括的子像素的数量负相关。
  5. 根据权利要求1-4中任一项所述的显示基板，其中，所述补偿电阻包括补偿导电走线；以及
    对于所述n行像素单元而言，给各行像素单元提供扫描信号的多根扫描信号引线分别电连接各自的补偿导电走线，各行像素单元的补偿导电走线的电阻值与该行像素单元包括的子像素的数量负相关。
  6. 根据权利要求5所述的显示基板，其中，对于所述至少n行像素单元而言，各行像素单元的补偿导电走线的长度与该行像素单元包括的子像素的数量负相关，和/或，各行像素单元的补偿导电走线的线径与该行像素单元包括的子像素的数量正相关。
  7. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    设置于所述衬底基板上且位于所述边框区域中的栅极驱动电路，所述栅极驱动电路用于输出扫描信号；以及
    设置于所述衬底基板且位于所述边框区域中的多根扫描信号引线，所述多根扫描信号引线分别与所述多根扫描信号线电连接，
    其中，所述显示基板包括：位于所述衬底基板上的第一导电层；位于所述第一导电层远离所述衬底基板一侧的第二导电层；以及位于所述第二导电层远离所述衬底基板一侧的第三导电层，
    其中，对于同一行像素单元而言，所述第一补偿电容电极和所述扫描信号引线彼此连接，所述第一补偿电容电极和所述扫描信号引线均位于选自所述第一导电层和所述第二导电层中的一个同一导电层。
  8. 根据权利要求7所述的显示基板，其中，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中，以及所述第二补偿电容电极位于所述第二导电层或所述第三导电层中；或者，
    其中，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中，以 及所述第二补偿电容电极位于所述第一导电层或所述第三导电层中。
  9. 根据权利要求7所述的显示基板，其中，所述补偿电容包括第一子补偿电容和第二子补偿电容，所述第二补偿电容电极包括第一子补偿电容电极和第二子补偿电容电极，所述第一子补偿电容电极和第二子补偿电容电极均接入所述公共电压信号；
    所述第一补偿电容电极位于所述第二导电层中，所述第一子补偿电容电极位于所述第一导电层中，所述第二子补偿电容电极位于所述第三导电层中；
    所述第一补偿电容电极在所述衬底基板上的正投影和所述第一子补偿电容电极在所述衬底基板上的正投影至少部分交叠，以形成所述第一子补偿电容电极；
    所述第一补偿电容电极在所述衬底基板上的正投影和所述第二子补偿电容电极在所述衬底基板上的正投影至少部分交叠，以形成所述第二子补偿电容电极。
  10. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    设置于所述衬底基板上且位于所述边框区域中的驱动芯片，所述驱动芯片用于输出扫描信号；以及
    设置于所述衬底基板且位于所述边框区域中的多根扫描信号引线，所述多根扫描信号引线分别与所述多根扫描信号线电连接，
    其中，所述显示基板包括：位于所述衬底基板上的第一导电层；位于所述第一导电层远离所述衬底基板一侧的第二导电层；以及位于所述第二导电层远离所述衬底基板一侧的第三导电层，
    其中，对于同一行像素单元而言，所述第一补偿电容电极和所述扫描信号引线彼此连接，所述第一补偿电容电极和所述扫描信号引线均位于选自所述第一导电层和所述第二导电层中的一个同一导电层。
  11. 根据权利要求10所述的显示基板，其中，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中；对于偶数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中；对于全部n行像素单元而言，所述第二补偿电容电极均位于所述第三导电层中；或者，
    其中，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中；对于偶数行的像素单元而言，所述第一补偿电容电极和所 述扫描信号引线均位于所述第一导电层中；对于全部n行像素单元而言，所述第二补偿电容电极均位于所述第三导电层中。
  12. 根据权利要求10所述的显示基板，其中，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中，所述第二补偿电容电极位于所述第二导电层或所述第三导电层中；以及对于偶数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中，所述第二补偿电容电极位于所述第一导电层或所述第三导电层中；或者，
    其中，对于奇数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第二导电层中，所述第二补偿电容电极位于所述第一导电层或所述第三导电层中；以及对于偶数行的像素单元而言，所述第一补偿电容电极和所述扫描信号引线均位于所述第一导电层中，所述第二补偿电容电极位于所述第二导电层或所述第三导电层中。
  13. 根据权利要求2所述的显示基板，其中，彼此连接的所述第一补偿电容电极和所述扫描信号引线为连续延伸的一体结构。
  14. 根据权利要求13所述的显示基板，其中，所述第一补偿电容电极包括自所述扫描信号引线延伸的多段弯曲走线；或者，
    所述第一补偿电容电极包括自所述扫描信号引线延伸的第一导电部，所述第一导电部具有镂空结构。
  15. 根据权利要求2所述的显示基板，其中，相邻两行的像素单元的扫描信号引线均沿行方向延伸，所述第一补偿电容电极在列方向行位于相邻两行的像素单元的扫描信号引线之间。
  16. 根据权利要求2所述的显示基板，其中，所述显示基板包括接入公共电压信号的静电保护环；以及
    所述第二补偿电容电极包括自静电保护环延伸的第二导电部。
  17. 根据权利要求16所述的显示基板，其中，对于所述n行像素单元而言，n行像素单元的补偿电容的第二导电部为连续延伸的一体结构；或者，
    对于所述n行像素单元而言，n行像素单元的补偿电容的第二导电部分别自所述静电保护环朝向所述显示区域延伸。
  18. 根据权利要求2所述的显示基板，其中，所述显示基板还包括静电保护电路，所述静电保护电路的一端与所述扫描信号引线和所述扫描信号线均电连接，所述静电保护电路的另一端与所述静电保护环电连接，用于将所述扫描信号引线和所述扫描信号线上的静电释放至所述静电保护环。
  19. 根据权利要求18所述的显示基板，其中，所述显示基板还包括位于所述第三导电层中的第一导电转接部；
    所述扫描信号引线靠近所述显示区域的一端通过第一过孔与所述第一导电转接部的第一部分电连接，所述扫描信号线远离所述显示区域的一端通过第二过孔与所述第一导电转接部的第二部分电连接，所述第一导电转接部的第三部分通过第三过孔与所述静电保护电路的一端电连接。
  20. 根据权利要求19所述的显示基板，其中，所述显示基板还包括位于所述第三导电层中的第二导电转接部；所述扫描信号引线的一部分通过第四过孔与所述第二导电转接部的一部分电连接，所述第二导电转接部的另一部分通过第五过孔与所述第一补偿电容电极的一端电连接；和/或，
    所述显示基板还包括位于所述第三导电层中的第三导电转接部；所述扫描信号引线的另一部分通过第六过孔与所述第三导电转接部的一部分电连接，所述第三导电转接部的另一部分通过第七过孔与所述第一补偿电容电极的另一端电连接。
  21. 根据权利要求5所述的显示基板，其中，所述扫描信号引线的一部分形成所述补偿电阻。
  22. 根据权利要求21所述的显示基板，其中，给至少一行像素单元提供扫描信号的所述扫描信号引线的至少一部分包括多段弯曲走线，所述补偿电阻包括该多段弯曲 走线。
  23. 根据权利要求5所述的显示基板，其中，任意相邻两行的像素单元的扫描信号线上的总负载的差异在规定的阈值内，其中，所述总负载包括扫描信号线上的电容负载和电阻负载的乘积。
  24. 根据权利要求18所述的显示基板，其中，所述显示基板包括提供所述公共电压信号的公共电压信号总线；以及
    对于至少一行像素单元的负载补偿单元而言，所述补偿电容在行方向上位于所述公共电压信号总线靠近所述显示区域的一侧，所述补偿电阻在行方向上位于所述补偿电容靠近所述显示区域的一侧，所述静电保护电路位于所述补偿电阻靠近所述显示区域的一侧。
  25. 一种显示装置，包括根据权利要求1-24中任一项所述的显示基板。
  26. 一种应用于显示基板的负载补偿方法，所述显示基板包括：衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，其中，所述显示基板包括N行像素单元，其中，N为大于等于2的正整数，
    其特征在于，所述方法包括：
    驱动所述显示基板显示白画面；
    获取第p行像素单元和第q行像素单元的充电电压，其中，所述第p行像素单元为所述N行像素单元中子像素数量最少的一行像素单元，所述第q行像素单元为所述N行像素单元中子像素数量最多的一行像素单元；
    计算所述第p行像素单元和所述第q行像素单元的充电电压之差；
    比较所述充电电压之差与规定的电压阈值；
    响应于所述充电电压之差大于规定的电压阈值，确定需要进行负载补偿；
    响应于所述负载补偿，确定需要进行负载补偿的n行像素单元，n为大于等于2小于等于N的正整数，其中，所述n行像素单元中每一行像素单元的充电电压与所述第q行像素单元的充电电压之差大于规定的阈值；
    根据所述n行像素单元中每一行像素单元的子像素的数量与所述第q行像素单元的子像素的数量，确定负载补偿单元的负载补偿值，其中，给所述n行像素单元提供扫描信号的多根扫描信号线分别电连接各自的负载补偿单元，所述n行像素单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。
  27. 一种应用于显示基板的负载补偿方法，所述显示基板包括：衬底基板，所述衬底基板包括显示区域和位于所述显示区域至少一侧的边框区域；位于所述显示区域中的多个像素单元，所述多个像素单元沿行方向和列方向成阵列地设置于所述衬底基板，每一行像素单元包括多个子像素；设置于所述衬底基板的多根扫描信号线，所述多根扫描信号线用于分别给多行像素单元提供扫描信号；设置于所述衬底基板上且位于所述边框区域中的多个负载补偿单元，所述多个负载补偿单元分别与所述多根扫描信号线中的至少一些扫描信号线电连接；以及设置于所述衬底基板上的公共电极，所述公共电极的至少一部分位于所述显示区域中，所述公共电极接入公共电压信号，其中，所述显示基板包括N行像素单元，其中，N为大于等于2的正整数，
    其特征在于，所述方法包括：
    计算任意相邻两行像素单元的负载差异；
    比较所述负载差异与规定的负载差异阈值；
    响应于所述负载差异大于规定的负载差异阈值，确定需要进行负载补偿的n行像素单元，n为大于等于2小于等于N的正整数，其中，所述n行像素单元中每一行像素单元与它相邻行的像素单元的负载差异大于所述规定的负载差异阈值；
    根据所述n行像素单元中每一行像素单元的子像素的数量与所述第q行像素单元的子像素的数量，确定负载补偿单元的负载补偿值，其中，所述第q行像素单元为所述N行像素单元中子像素数量最多的一行像素单元，给所述n行像素单元提供扫描信 号的多根扫描信号线分别电连接各自的负载补偿单元，所述n行像素单元的负载补偿值与该行像素单元包括的子像素的数量负相关，所述负载补偿值包括电容补偿值和电阻补偿值中的至少一个。
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CN107221536A (zh) * 2017-05-25 2017-09-29 上海天马微电子有限公司 阵列基板、异形显示器及显示装置
CN107481669A (zh) * 2017-09-08 2017-12-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN107610636A (zh) * 2017-10-30 2018-01-19 武汉天马微电子有限公司 一种显示面板及显示装置
US20190013374A1 (en) * 2017-07-05 2019-01-10 Lg Display Co., Ltd. Display device

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CN107221536A (zh) * 2017-05-25 2017-09-29 上海天马微电子有限公司 阵列基板、异形显示器及显示装置
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