WO2024000376A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2024000376A1
WO2024000376A1 PCT/CN2022/102741 CN2022102741W WO2024000376A1 WO 2024000376 A1 WO2024000376 A1 WO 2024000376A1 CN 2022102741 W CN2022102741 W CN 2022102741W WO 2024000376 A1 WO2024000376 A1 WO 2024000376A1
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WIPO (PCT)
Prior art keywords
signal line
gate
transistor
driving circuit
coupled
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PCT/CN2022/102741
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English (en)
French (fr)
Inventor
王苗
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002023.9A priority Critical patent/CN117642800A/zh
Priority to PCT/CN2022/102741 priority patent/WO2024000376A1/zh
Publication of WO2024000376A1 publication Critical patent/WO2024000376A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • Smart terminal display devices such as mobile phones and tablets are in increasing demand in people's lives, and more diverse application scenarios make While people are pursuing full-screen displays, they also hope to enjoy a larger size and higher resolution visual experience. With the need to optimize display effects, low-frequency display to reduce power consumption has also become a focus.
  • the purpose of this disclosure is to provide a display substrate, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display substrate, including: a plurality of first gate drive circuits and a plurality of second gate drive circuits, a first gate drive signal output by the first gate drive circuit and the The timing of the second gate drive signal output by the second gate drive circuit is different; the first gate drive circuit and the second gate drive circuit share at least one signal line.
  • the display substrate includes a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits and the plurality of second gate driving circuits are located in the peripheral area;
  • At least part of the first gate driving circuit and at least part of the second gate driving circuit are arranged in a mirror image.
  • the first gate driving circuit and the second gate driving circuit share a first level signal line, and the first level signal line transmits a DC signal with a first level.
  • At least part of the orthographic projection of the first level signal line on the base substrate of the display substrate is located between the orthographic projection of the first gate driving circuit on the base substrate and the between the orthographic projections of the second gate driving circuit on the base substrate.
  • the orthographic projection of the first level signal line on the base substrate at least partially overlaps the orthographic projection of the first gate driving circuit on the base substrate; and/or , the orthographic projection of the first level signal line on the base substrate at least partially overlaps the orthographic projection of the second gate driving circuit on the base substrate.
  • the first gate drive circuit and the second gate drive circuit share a first clock signal line and/or a second clock signal line, and the first clock signal transmitted by the first clock signal line and The phase of the second clock signal transmitted by the second clock signal line is opposite.
  • At least part of the first gate drive circuit and at least part of the second gate drive circuit are mirror symmetrical with respect to a first axis of symmetry; the first axis of symmetry is in mirror symmetry with the first clock signal line At least partially overlap, or the first symmetry axis and the second clock signal line at least partially overlap, or the first symmetry axis and the first level signal line at least partially overlap.
  • the orthographic projection of the first level signal line on the base substrate is located at the orthographic projection of the first clock signal line on the base substrate and the second clock signal line is on between the orthographic projections on the base substrate.
  • the orthographic projection of the first clock signal line on the substrate is the same as that of one of the first gate drive circuit and the second gate drive circuit on the substrate.
  • the orthographic projection on the substrate at least partially overlaps; the orthographic projection of the second clock signal line on the base substrate is at least partially overlapped with the other one of the first gate drive circuit and the second gate drive circuit. Orthographic projections on the base substrate at least partially overlap.
  • the first gate drive circuit is coupled to a first frame start signal line
  • the second gate drive circuit is coupled to a second frame start signal line.
  • the orthographic projection of the first level signal line on the substrate is located between the orthographic projection of the first frame starting signal line on the substrate and the starting point of the second frame. between the orthographic projections of the initial signal lines on the base substrate.
  • the orthographic projection of the first frame start signal line on the substrate substrate at least partially overlaps the orthographic projection of the first gate drive circuit on the substrate substrate;
  • the orthographic projection of the second frame start signal line on the base substrate at least partially overlaps the orthographic projection of the second gate driving circuit on the base substrate.
  • the orthographic projection of the first frame start signal line on the substrate substrate and the orthographic projection of the second frame start signal line on the substrate substrate are located on the first clock between the orthographic projection of the signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate.
  • one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line At least one is made of the second source-drain metal layer in the display substrate.
  • one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line At least one includes two conductive layers stacked in a stack, one conductive layer is made of the second source and drain metal layer, and the other conductive layer is made of the third source and drain metal layer in the display substrate.
  • the channel width to length ratio of the output transistor included in the first gate driving circuit is equal to the channel width to length ratio of the output transistor included in the second gate driving circuit.
  • the channel width to length ratio of the output transistor included in the first gate driving circuit is greater than the channel width to length ratio of the output transistor included in the second gate driving circuit.
  • At least part of the target devices having the same function in the first gate driving circuit and the second gate driving circuit are coupled.
  • the gate of the first data writing transistor is coupled to the output terminal of the corresponding first gate drive circuit, and the first pole of the first data writing transistor is coupled to the corresponding data line.
  • the second pole of the first data writing transistor is coupled to the first pole of the first driving transistor;
  • the gate of the first compensation transistor is coupled to the output terminal of the corresponding first gate drive circuit, the first pole of the first compensation transistor is coupled to the second pole of the first drive transistor, and the The second electrode of the first compensation transistor is coupled to the gate electrode of the first driving transistor;
  • the gate of the second reset transistor is coupled to the corresponding output terminal of the second gate drive circuit, and the first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, so The second pole of the second reset transistor is coupled to the corresponding light-emitting element;
  • the display substrate further includes a plurality of second sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines and a plurality of second initialization signal lines.
  • the second sub-pixel driving circuit includes a second driving transistor. , a second data writing transistor, a second compensation transistor and a second reset transistor;
  • the gate of the second data writing transistor is coupled to the output terminal of the corresponding second gate drive circuit, and the first pole of the second data writing transistor is coupled to the corresponding data line.
  • the second pole of the second data writing transistor is coupled to the first pole of the second driving transistor;
  • the gate of the second reset transistor is coupled to the corresponding output terminal of the second gate drive circuit, and the first electrode of the second reset transistor is coupled to the corresponding second initialization signal line, so The second pole of the second reset transistor is coupled to the corresponding light-emitting element.
  • the display substrate also includes:
  • the first electrostatic discharge circuit is coupled to the first gate drive circuit
  • the second electrostatic discharge circuit is coupled to the second gate drive circuit
  • the first electrostatic discharge circuit and the second electrostatic discharge circuit are arranged in a mirror image, and the first electrostatic discharge circuit and the second electrostatic discharge circuit share at least one signal line.
  • the surrounding area also includes:
  • a plurality of light-emitting control drive circuits are divided into multiple groups of light-emitting control drive circuits.
  • Each group of light-emitting control drive circuits includes two of the light-emitting control drive circuits arranged in a mirror image.
  • the two light-emitting control drive circuits are arranged in a mirror image.
  • the control drive circuits share at least one signal line.
  • a second aspect of the present disclosure provides a display device, including the above display substrate.
  • a plurality of first gate drive circuits and a plurality of second gate drive circuits are produced.
  • the first gate drive signal output by the first gate drive circuit and the second gate signal output by the second gate drive circuit are The driving signal timing is different; the first gate driving circuit and the second gate driving circuit share at least one signal line.
  • Figure 1 is a schematic diagram of the change in display brightness over time of a display substrate provided by an embodiment of the present disclosure
  • Figure 4 is a timing diagram of the gate drive circuit driving 8T1C circuit structure provided by the embodiment of the present disclosure.
  • Figure 5 is a schematic circuit structure diagram of a 7T1C provided by an embodiment of the present disclosure.
  • Figure 6 is a timing diagram of the gate drive circuit driving 7T1C circuit structure provided by the embodiment of the present disclosure.
  • Figure 8 is a first layout schematic diagram of the first gate driving circuit and the second gate driving circuit provided by an embodiment of the present disclosure
  • Figure 9 is a schematic diagram of the layout of the active layer and the first gate metal layer in Figure 7;
  • Figure 10 is a schematic diagram of the layout of the second gate metal layer in Figure 7;
  • Figure 12 is a schematic layout diagram of the first source and drain metal layer in Figure 7;
  • Figure 14 is a schematic circuit structure diagram of an electrostatic discharge circuit provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic layout diagram of the active layer and the first gate metal layer in Figure 13;
  • Figure 16 is a schematic diagram of the via hole formed on the interlayer insulating layer in Figure 13;
  • Figure 18 is a second layout schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • Figure 19 is a schematic layout diagram of the active layer and the first gate metal layer in Figure 18;
  • Figure 20 is a schematic diagram of the via hole formed on the interlayer insulating layer in Figure 18;
  • Figure 21 is a schematic layout diagram of the first source and drain metal layer in Figure 18;
  • Figure 22 is a schematic diagram of the via hole formed on the first passivation layer in Figure 18;
  • Figure 23 is a schematic diagram of the via hole formed on the first flat layer in Figure 18;
  • Figure 24 is a schematic layout diagram of the second source and drain metal layer in Figure 18;
  • Figure 25 is a third layout schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • Figure 26 is a fourth layout schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • FIG. 27 is a circuit structure diagram of a light emission control driving circuit provided by an embodiment of the present disclosure.
  • the longV mode is used for driving display, that is, the light-emitting control signal EM has multiple pulse inputs in one frame.
  • the first pulse of the light-emitting control signal EM is the picture refresh frame, which realizes the writing of data signals;
  • the second pulse and the third pulse (not shown in the figure) of the light-emitting control signal EM are the picture holding frames, and the light is emitted within the picture holding frame. Anode reset of the element.
  • the subpixel driving circuit including an 8T1C (ie, 8 transistors and 1 capacitor) circuit structure as an example.
  • the first stage is the reset signal (transmitted by the reset signal line Reset) and the second gate drive signal (transmitted by the second scan line Gate2).
  • the low level is turned on, and N1
  • the node is reset to the first initialization signal (transmitted by the first initialization signal line VINIT1), and the N2 node is reset to the third initialization signal (transmitted by the third initialization signal line VINIT3);
  • 2 stage is the repeated reset stage of the N1 node;
  • 3 stage is the A gate drive signal (transmitted by the first scan line Gate1) is turned on at a low level, and the data signal (transmitted by the data line Vdata) is written into the N1 node; then the light emission control signal EM is at a low level, and the pixel emits light.
  • the light-emitting control signal EM is turned off at a high level and the second gate drive signal is turned on at a low level.
  • the anode of the light-emitting element is reset to the second initialization signal (initiated by the second initialization signal).
  • the signal line VINIT2 transmits), and the N2 node is reset to the third initialization signal (for example: the voltage value of the third initialization signal is 2V); then the light-emitting control signal EM is turned on at a low level, and the pixel emits light.
  • a first gate driving circuit, a second gate driving circuit and a light emission control driving circuit are provided.
  • the light-emitting control drive circuit drives the multi-pulse light-emitting control signal EM output within one frame to control whether to emit light;
  • the second gate drive circuit drives the multi-pulse second gate drive signal output within one frame to control the anode reset and N2 node reset. ;
  • the first gate drive circuit drives the 3pulse first gate drive signal output within one frame to control data signal writing and N1 node reset.
  • the display substrate provided by this application includes multiple sets of gate drive circuits, how to take into account the requirement of a narrow frame of the display substrate has become a focus.
  • the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are connected to the same sub-pixel driving circuit.
  • the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are connected to the same row of sub-pixel driving circuits; or, the first gate driving circuit Gate1-GOA and The second gate driving circuit Gate2-GOA is connected to the sub-pixel driving circuit of the same color.
  • the first gate driving circuit Gate1-GOA includes a plurality of transistors and storage capacitors.
  • the first gate driving circuit Gate1-GOA is connected to the first level signal line VGH and the second level signal line respectively.
  • VGL, the first clock signal line GCK, the second clock signal line GCB and the first frame start signal line GSTV1 are coupled.
  • the first gate drive circuit Gate1-GOA includes a plurality of transistors and storage capacitors that are connected to each of the above signals. Under the common control of the corresponding signals provided by the lines, the first gate driving signal GOUT1 is output.
  • the second gate driving circuit Gate2-GOA includes a plurality of transistors and storage capacitors.
  • the second gate driving circuit Gate2-GOA is connected to the first level signal line VGH and the second level signal line respectively.
  • VGL, the first clock signal line GCK, the second clock signal line GCB and the second frame start signal line GSTV2 are coupled.
  • the second gate drive circuit Gate2-GOA includes a plurality of transistors and storage capacitors in each of the above signals. Under the common control of the corresponding signals provided by the lines, the second gate driving signal GOUT2 is output.
  • the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA have substantially the same circuit structures.
  • the gate of the fourth transistor T4 is coupled to the second pole of the third transistor T3.
  • the second pole of the fourth transistor T4 serves as the output terminal of the gate driving circuit and is output in the first gate driving circuit Gate1-GOA.
  • the terminal outputs the first gate driving signal GOUT1, and the output terminal in the second gate driving circuit Gate2-GOA outputs the second gate driving signal GOUT2.
  • the first plate C21 of the second capacitor C2 is coupled to the gate of the fourth transistor T4, and the second plate C22 of the second capacitor C2 is coupled to the first electrode of the fourth transistor T4.
  • the gate electrode of the fifth transistor T5 is coupled to the second electrode of the eighth transistor T8, the first electrode of the fifth transistor T5 is coupled to the second clock signal line GCB, and the second electrode of the fifth transistor T5 is coupled to the fourth transistor T4.
  • the second pole coupling is coupled to the fifth transistor T5
  • the first plate C11 of the first capacitor C1 is coupled to the gate of the fifth transistor T5, and the second plate C12 of the first capacitor C1 is coupled to the second electrode of the fifth transistor T5.
  • the gate of the sixth transistor T6 is coupled to the gate of the fourth transistor T4, the first electrode of the sixth transistor T6 is coupled to the first level signal line VGH, and the second electrode of the sixth transistor T6 is coupled to the seventh transistor T7.
  • the first pole is coupled.
  • the first level signal transmitted by the first level signal line VGH coupled to Gate1-GOA of the first gate driving circuit and the first level signal coupled to Gate2-GOA of the second gate driving circuit The first level signals transmitted by the level signal lines VGH are the same.
  • the second level signal transmitted by the second level signal line VGL coupled to Gate1-GOA of the first gate driving circuit and the second level signal line coupled to Gate2-GOA of the second gate driving circuit The second level signal transmitted by VGL is the same.
  • the first clock signal transmitted by the first clock signal line GCK coupled to Gate1-GOA of the first gate driving circuit and the first clock signal transmitted by the first clock signal line GCK coupled to Gate2-GOA of the second gate driving circuit The first clock signal is the same.
  • the second clock signal transmitted by the second clock signal line GCB coupled to the first gate driving circuit Gate1-GOA is transmitted by the second clock signal line GCB coupled to the second gate driving circuit Gate2-GOA.
  • the second clock signal is the same.
  • the line width of the first clock signal line GCK and the line width of the second clock signal line GCB are both greater than the line width of the first level signal line VGH, and both are greater than the line width of the second level signal line VGL. Width.
  • the line width of the first level signal line VGH is greater than the line width of the first clock signal line GCK and the second clock signal line GCB, and is greater than the line width of the second level signal line VGL.
  • the display substrate can be effectively improved. Solve the problem of low-frequency flicker of display substrate.
  • the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are effectively reduced in size.
  • the frame width occupied by the drive circuit Gate2-GOA and the signal lines connected to the two is not only conducive to narrowing the frame of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.
  • the display substrate includes a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits Gate1-GOA and the plurality of The second gate drive circuit Gate2-GOA is located in the peripheral area;
  • the fourth transistor T4 in the first gate driving circuit Gate1-GOA is located on a side of the first gate driving circuit Gate1-GOA away from the second gate driving circuit Gate2-GOA.
  • the fifth transistor T5 in the first gate driving circuit Gate1-GOA is located on a side of the first gate driving circuit Gate1-GOA away from the second gate driving circuit Gate2-GOA.
  • the first gate driving circuit Gate2-GOA can be arranged in a mirror image.
  • the space occupied by the gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA is compressed to a minimum, and at the same time, it is beneficial to realize the sharing of signal lines and achieve the purpose of narrowing the frame of the display substrate.
  • the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA are configured to share the first level signal line VGH.
  • the first level signal line VGH transmits a DC signal having a first level.
  • the orthographic projection of the first level signal line VGH on the substrate is set to be located where the first gate drive circuit Gate1-GOA is located.
  • the orthographic projection on the substrate substrate at least partially overlaps; and/or the orthographic projection of the first level signal line VGH on the substrate substrate is at least partially overlapped with the second gate driving circuit Gate2-GOA.
  • the orthographic projections on the base substrate at least partially overlap.
  • the orthographic projection of the first level signal line VGH on the base substrate is at least the same as the orthographic projection of the transistors included in the first gate driving circuit Gate1-GOA on the base substrate. partially overlap; and/or, the orthographic projection of the first level signal line VGH on the base substrate, and the transistor included in the second gate driving circuit Gate2-GOA on the base substrate orthographic projections at least partially overlap.
  • the orthographic projection of the first level signal line VGH on the base substrate is different from the first transistor included in the first gate drive circuit Gate1-GOA.
  • the orthographic projection of the gate of T1 on the base substrate at least partially overlaps; the orthographic projection of the first level signal line VGH on the base substrate is at least partially overlapped with the first gate driving circuit Gate1-
  • the orthographic projection of the gate of the seventh transistor T7 included in the GOA on the base substrate at least partially overlaps.
  • the orthographic projection of the first level signal line VGH on the base substrate is different from the first transistor included in the second gate drive circuit Gate2-GOA.
  • the orthographic projection of the gate of T1 on the base substrate at least partially overlaps; the orthographic projection of the first level signal line VGH on the base substrate is at least partially overlapped with the second gate driving circuit Gate2-
  • the orthographic projection of the gate of the seventh transistor T7 included in the GOA on the base substrate at least partially overlaps.
  • the first gate drive circuit Gate1-GOA and the second gate drive circuit Gate2-GOA are configured to share a first clock signal.
  • line GCK and/or the second clock signal line GCB, the first clock signal transmitted by the first clock signal line GCK and the second clock signal transmitted by the second clock signal line GCB have opposite phases.
  • the first clock signal line GCK includes at least a portion extending along the first direction
  • the second clock signal line GCB includes at least a portion extending along the first direction
  • the first clock signal line GCK includes at least a portion extending along the first direction.
  • the line GCK and the second clock signal line GCB are arranged along the second direction.
  • the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA share the first clock signal line GCK and/or the second clock signal line GCB. , can ensure the normal driving of the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA while reducing a set of clock signal lines, thereby effectively reducing the size of the first gate driving circuit Gate1 -
  • the frame width occupied by the GOA and the second gate drive circuit Gate2-GOA and the signal lines connected between them is not only conducive to narrowing the frame of the display substrate, but also effectively reducing the power consumption of the gate drive circuit.
  • At least part of the first gate driving circuit Gate1-GOA and at least part of the second gate driving circuit Gate2-GOA are mirror symmetrical about the first axis of symmetry;
  • the first axis of symmetry at least partially overlaps the first clock signal line GCK, as shown in Figures 7 to 12, or the first axis of symmetry at least partially overlaps the second clock signal line GCB, As shown in FIGS. 18 to 25 , the first axis of symmetry may at least partially overlap with the first level signal line VGH.
  • the above-mentioned setting of the first symmetry axis overlaps the common signal line first clock signal line GCK, second clock signal line GCB or first level signal line VGH, so that at least one of the first gate driving circuit Gate1-GOA part and at least part of the second gate driving circuit Gate2-GOA can be located on both sides of the common signal line, thereby ensuring that the first gate driving circuit Gate1-GOA and the second gate
  • the reliability of the connection between the driving circuit Gate2-GOA and the common signal line reduces the layout difficulty of the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA.
  • the above-mentioned arrangement of the first symmetry axis and the first level signal line VGH at least partially overlaps such that at least part of the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA At least part of them are respectively located on both sides of the first level signal line VGH. Since the first level signal line VGH transmits a DC signal with a stable potential, the above arrangement is conducive to the first level signal.
  • the line VGH shields signal interference between the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA, thereby effectively improving the stability of the display substrate operation.
  • the orthographic projection of the first level signal line VGH on the substrate is set, and the first clock signal line GCK is located on the substrate. between the orthographic projection on the substrate and the orthographic projection of the second clock signal line GCB on the base substrate.
  • the above arrangement enables the first clock signal line GCK and the second clock signal line GCB to be located on both sides of the first level signal line VGH respectively, thereby effectively shielding the first level signal line VGH The interference between the first clock signal line GCK and the second clock signal line GCB is eliminated, ensuring the working stability of the gate drive circuit.
  • the orthographic projection of the first clock signal line GCK on the substrate is in direct contact with the first gate driving circuit Gate1-GOA and the first gate driving circuit Gate1-GOA.
  • the orthographic projection of one of the two gate driving circuits Gate2-GOA on the substrate at least partially overlaps; the orthographic projection of the second clock signal line GCB on the substrate is at least partially overlapped with the orthographic projection of the second clock signal line GCB on the substrate.
  • Orthographic projections of a gate driving circuit Gate1-GOA and another of the second gate driving circuits Gate2-GOA on the base substrate at least partially overlap.
  • the orthographic projection of the first clock signal line GCK on the base substrate is consistent with one of the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA.
  • the orthographic projection of the transistor included on the base substrate at least partially overlaps; the orthographic projection of the second clock signal line GCB on the base substrate is at least partially overlapped with the first gate driving circuit Gate1-GOA
  • the orthographic projection of the transistor included in another type of the second gate driving circuit Gate2-GOA on the base substrate at least partially overlaps.
  • the orthographic projection of the first clock signal line GCK on the base substrate is consistent with one of the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA.
  • the orthographic projection of the capacitive structure included on the substrate at least partially overlaps; the orthographic projection of the second clock signal line GCB on the substrate is at least partially overlapped with the first gate driving circuit Gate1- Orthographic projections of the capacitive structure included in GOA and another one of the second gate driving circuits Gate2-GOA on the base substrate at least partially overlap.
  • the orthographic projection of the first clock signal line GCK on the base substrate is respectively connected with the gate of the first transistor T1 included in the first gate driving circuit Gate1-GOA.
  • the orthographic projection of the electrode on the base substrate, the orthographic projection of the active pattern of the second transistor T2 included in the first gate driving circuit Gate1-GOA on the base substrate, and the first gate Orthographic projections of the second capacitors included in the driving circuit Gate1-GOA on the substrate at least partially overlap.
  • the orthographic projection of the second clock signal line GCB on the base substrate is respectively connected with the gate of the first transistor T1 included in the second gate driving circuit Gate2-GOA.
  • the orthographic projection of the electrode on the base substrate, the orthographic projection of the active pattern of the second transistor T2 included in the second gate driving circuit Gate2-GOA on the base substrate, and the second gate Orthographic projections of the second capacitor included in the driving circuit Gate2-GOA on the substrate at least partially overlap.
  • the above arrangement method further reduces the frame width occupied by the first gate drive circuit Gate1-GOA, the second gate drive circuit Gate2-GOA and the signal lines connected between them, which is not only conducive to narrowing the frame of the display substrate, but also effectively The power consumption of the gate drive circuit is reduced.
  • the first gate driver circuit Gate1-GOA is coupled to the first frame start signal line GSTV1
  • the second gate driver The circuit Gate2-GOA is coupled to the second frame start signal line GSTV2.
  • the first frame start signal line GSTV1 includes at least a portion extending along the first direction
  • the second frame start signal line GSTV2 includes at least a portion extending along the first direction.
  • the first frame start signal line GSTV1 and the second frame start signal line GSTV2 can be controlled independently.
  • the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are configured to connect to their respective original frame start signal lines and maintain access to their respective original frame start signal lines. frame start signal, so that during subsequent debugging of the gate drive signal, the first gate drive circuit Gate1-GOA and the second gate drive can still be controlled by adjusting the respective accessed frame start signals.
  • the circuit Gate2-GOA outputs different pulses to achieve the purpose of driving low-frequency pixels.
  • the orthographic projection of the first level signal line VGH on the substrate is set to be located at the beginning of the first frame. between the orthographic projection of the signal line GSTV1 on the base substrate and the orthographic projection of the second frame start signal line GSTV2 on the base substrate.
  • the above arrangement enables the first frame start signal line GSTV1 and the second frame start signal line GSTV2 to be located on both sides of the first level signal line VGH respectively, so that the first level signal The line VGH effectively shields the interference between the first frame start signal line GSTV1 and the second frame start signal line GSTV2, ensuring the working stability of the gate drive circuit.
  • the first clock signal line GCK, the second clock signal line GCB, the first level signal line VGH, the first frame start signal line GSTV1 is located between the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA.
  • the first frame start signal line GSTV1 and the second frame start signal GSTV2 are located on the same side of the second clock signal line GCB; the first clock signal line GCK and the first level signal line VGH are located on the second clock signal line GCB of the same side.
  • the first frame start signal line GSTV1 and the second frame start signal GSTV2 are located on the same side of the second clock signal line GCB.
  • the start signal line GSTV1 is coupled to the first gate drive circuit Gate1-GOA
  • the second frame start signal line GSTV2 is coupled to the second gate drive circuit Gate2-GOA
  • the first frame start signal line GSTV1 is located at a distance from the first gate drive circuit Gate1-GOA.
  • the distance between the gate driving circuit Gate1-GOA is greater than the distance between the second frame start signal line GSTV2 and the second gate driving circuit Gate2-GOA.
  • the distance between the first frame start signal line GSTV1 and the first transistor T1 of the first gate drive circuit Gate1-GOA that is, the length of the connecting line segment from the first transistor T1 of the first gate drive circuit Gate1-GOA to GSTV1
  • the distance between the second frame start signal line GSTV2 and the first transistor T1 of the second gate drive circuit Gate2-GOA that is, the distance from the first transistor T1 of the second gate drive circuit Gate2-GOA to the second frame start signal line GSTV2 length of the connecting line segment of the initial signal line GSTV2
  • the distance between the output end of the first gate driving circuit Gate1-GOA and the sub-pixel (or sub-pixel driving circuit) is smaller than the distance between the output terminal of the first gate driving circuit Gate1-GOA and the sub-pixel driving circuit.
  • the distance from the output terminal of the first gate drive circuit Gate1-GOA (for example, the drain of the fifth transistor T5) to the sub-pixel (or sub-pixel drive circuit) is smaller than the second gate
  • the distance from the output end of the drive circuit Gate2-GOA (for example, the drain of the fifth transistor T5) to the subpixel (or subpixel drive circuit) is smaller than the second gate
  • the orthographic projection of the first frame start signal line GSTV1 on the substrate is located where the first gate drive circuit Gate1-GOA is located.
  • the orthographic projection on the substrate substrate at least partially overlaps; the orthographic projection of the second frame start signal line GSTV2 on the substrate substrate and the second gate driving circuit Gate2-GOA on the substrate.
  • the orthographic projections on the base substrate at least partially overlap.
  • the orthographic projection of the first frame start signal line GSTV1 on the substrate is the same as the orthographic projection of the transistors included in the first gate driving circuit Gate1-GOA on the substrate. At least partially overlap; the orthographic projection of the second frame start signal line GSTV2 on the substrate is the orthogonal projection of the transistor included in the second gate driving circuit Gate2-GOA on the substrate. The projections at least partially overlap.
  • the orthographic projection of the first frame start signal line GSTV1 on the substrate is different from the orthographic projection of the first transistor T1 included in the first gate driving circuit Gate1-GOA.
  • the orthographic projection of the active pattern on the base substrate, the orthographic projection of the active pattern of the sixth transistor T6 included in the first gate driving circuit Gate1-GOA on the base substrate, and the third A gate driving circuit Gate1-GOA includes active patterns of the seventh transistor T7 and orthographic projections on the base substrate at least partially overlap.
  • the orthographic projection of the second frame start signal line GSTV2 on the base substrate is different from the orthographic projection of the first transistor T1 included in the second gate driving circuit Gate2-GOA.
  • the orthographic projection of the active pattern on the base substrate, the orthographic projection of the active pattern of the sixth transistor T6 included in the second gate driving circuit Gate2-GOA on the base substrate, and the third The orthographic projections of the active patterns of the seventh transistor T7 included in the two-gate driving circuit Gate2-GOA on the substrate at least partially overlap.
  • the above arrangement further reduces the width of the frame occupied by the first gate drive circuit Gate1-GOA, the second gate drive circuit Gate2-GOA and the frame start signal line connected to them, which is not only conducive to narrowing the frame of the display substrate , and also effectively reduces the power consumption of the gate drive circuit.
  • the orthographic projection of the first frame start signal line GSTV1 on the substrate is set, and the second frame start signal line GSTV2 is set on the substrate.
  • the orthographic projection on the base substrate is located between the orthographic projection of the first clock signal line GCK on the base substrate and the orthographic projection of the second clock signal line GCB on the base substrate.
  • the above arrangement makes the first clock signal line GCK and the second clock signal line GCB far apart, which better shields the connection between the first clock signal line GCK and the second clock signal line GCB. Interference caused by signal transitions.
  • the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, and the first frame start signal line GSTV1 At least one of the second frame start signal line GSTV2 is made of the second source-drain metal layer in the display substrate.
  • the display substrate includes an active layer, a first gate insulating layer, a first gate metal layer, and a second gate layer sequentially stacked on the base substrate in a direction away from the base substrate.
  • the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, the first frame start signal line GSTV1 and the second frame start signal line At least one of the signal lines GSTV2 is made of a conductive layer in the display substrate located on the side of the first source-drain metal layer facing away from the base substrate.
  • Providing at least one of the above signal lines to be made of the second source-drain metal layer in the display substrate not only helps reduce the voltage drop of the signal line, but also prevents short circuits between the signal line and the circuit structure below it, effectively improving the display Substrate reliability.
  • the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, and the first frame start signal line GSTV1 At least one of the second frame start signal line GSTV2 is made of the first source-drain metal layer in the display substrate.
  • the first level signal line VGH, the first clock signal line GCK, the second clock signal line GCB, the first frame start signal line GSTV1 and the second frame At least one of the start signal lines GSTV2 includes two layers of conductive layers arranged in a stack. One conductive layer is made of the second source and drain metal layer, and the other conductive layer is made of the third source and drain metal of the display substrate. layer production.
  • the display substrate further includes the third source-drain metal layer, and the third source-drain metal layer is located on a side of the second source-drain metal layer facing away from the base substrate.
  • Providing at least one of the above signal lines includes two layers of conductive layers arranged in a stack.
  • One conductive layer is made of the second source and drain metal layer, and the other conductive layer is made of the third source and drain metal layer in the display substrate.
  • Production not only helps reduce the voltage drop of the signal line, but also prevents short circuits between the signal line and the circuit structure below it, effectively improving the reliability of the display substrate.
  • the channel width to length ratio of the output transistor included in the first gate drive circuit Gate1-GOA is equal to that of the second gate drive circuit Gate2-GOA.
  • the channel width to length ratio of the output transistor is equal to that of the second gate drive circuit Gate2-GOA.
  • the output transistors include a fourth transistor T4 and a fifth transistor T5.
  • the channel width to length ratio of the output transistor included in the first gate drive circuit Gate1-GOA is greater than that of the output transistor included in the second gate drive circuit Gate2-GOA. Channel width to length ratio.
  • the channel width to length ratio of the output transistor included in the first gate driving circuit Gate1-GOA is 1.25 times that of the output transistor included in the second gate driving circuit Gate2-GOA. , 1.5 times or 2.0 times, but not limited to this.
  • the channel width to length ratio of the output transistor included in the first gate drive circuit Gate1-GOA and the channel width to length ratio of the output transistor included in the second gate drive circuit Gate2-GOA are designed to be differentiated as above, Not only can it be compatible with high-frequency drive mode and low-frequency drive mode at the same time, it can also further reduce the frame width of the display substrate.
  • At least some target devices with the same functions in the first gate driving circuit Gate1-GOA and the second gate driving circuit Gate2-GOA are coupled.
  • the target device with the same function includes a first transistor T1 and a seventh transistor T7.
  • the gate of the first transistor T1 in the first gate driving circuit Gate1-GOA is coupled to the gate of the first transistor T1 in the second gate driving circuit Gate2-GOA.
  • the gate of the seventh transistor T7 in the first gate driving circuit Gate1-GOA is coupled to the gate of the seventh transistor T7 in the second gate driving circuit Gate2-GOA.
  • the target device with the same function also includes a second capacitor C2, and the second plate C22 of the second capacitor C2 in the first gate drive circuit Gate1-GOA is connected to the second plate C22 of the second capacitor C2 in the first gate drive circuit Gate1-GOA.
  • the second plate C22 of the second capacitor C2 in the second gate driving circuit Gate2-GOA is coupled and connected to the first level signal line VGH through a hole.
  • the above arrangement method is beneficial to reducing the wiring length of the signal node, and when the signal is shared, the electrical connection with the common signal line can be achieved through a hole, which is beneficial to simplifying the circuit structure.
  • the display substrate further includes a plurality of first sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines Vdata, a plurality of second initialization signal lines VINIT2 and A plurality of third initialization signal lines VINIT3,
  • the first sub-pixel driving circuit includes a first driving transistor T23, a first data writing transistor T24, a first compensation transistor T22, a second reset transistor T27 and a third reset transistor T28;
  • the gate of the first data writing transistor T24 is coupled to the output terminal of the corresponding first gate driving circuit Gate1-GOA, and the first electrode of the first data writing transistor T24 is connected to the corresponding data line. Vdata is coupled, and the second pole of the first data writing transistor T24 is coupled with the first pole of the first driving transistor T23;
  • the gate of the first compensation transistor T22 is coupled to the output terminal of the corresponding first gate drive circuit Gate1-GOA, and the first electrode of the first compensation transistor T22 is connected to the second electrode of the first drive transistor T23.
  • the second pole of the first compensation transistor T22 is coupled with the gate of the first driving transistor T23;
  • the gate of the second reset transistor T27 is coupled to the corresponding output terminal of the second gate driving circuit Gate2-GOA, and the first electrode of the second reset transistor T27 is coupled to the corresponding second initialization signal.
  • the line VINIT2 is coupled, and the second pole of the second reset transistor T27 is coupled with the corresponding light-emitting element;
  • the gate of the third reset transistor T28 is coupled to the corresponding output terminal of the second gate driving circuit Gate2-GOA, and the first electrode of the third reset transistor T28 is coupled to the corresponding third initialization signal.
  • the line VINIT3 is coupled, and the second pole of the third reset transistor T28 is coupled with the first pole of the first driving transistor T23.
  • the display substrate further includes: a plurality of first initialization signal lines VINIT1, a plurality of first scanning lines Gate1, a plurality of second scanning lines Gate2, a plurality of reset lines Reset, a plurality of light emitting control lines, a plurality of Power line VDD.
  • the sub-pixel driving circuit includes an 8T1C circuit structure.
  • the sub-pixel driving circuit also includes: a first reset transistor T21, a first power control transistor T25 and a first light emission control transistor T26.
  • the first initialization signal line VINIT1 transmits a first initialization signal
  • the second initialization signal line VINIT2 transmits a second initialization signal
  • the third initialization signal line VINIT3 transmits a third initialization signal.
  • the scanning line Gate1 transmits the first gate driving signal GOUT1
  • the second scanning line Gate2 transmits the second gate driving signal GOUT2
  • the lighting control line transmits the lighting control signal EM
  • the reset line Reset transmits the reset signal.
  • the power line VDD transmits the power signal.
  • the gate of the first reset transistor T21 is coupled to the corresponding reset line Reset, and the first pole of the first reset transistor T21 is coupled to the corresponding first initialization signal line VINIT1.
  • the second electrode of T21 is coupled to the gate of the first driving transistor T23.
  • the gate of the first power control transistor T25 is coupled to the corresponding light-emitting control line, and the first pole of the first power control transistor T25 is coupled to the corresponding power line VDD.
  • the first power control transistor The second pole of T25 is coupled with the first pole of the first driving transistor T23.
  • the gate of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting control line, and the first pole of the first light-emitting control transistor T26 is coupled to the second pole of the first driving transistor T23, so The second electrode of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting element.
  • the cathode of the light-emitting element receives the negative power supply signal VSS.
  • the gate of the first data writing transistor T24 is coupled to the output terminal of the corresponding first gate driving circuit Gate1-GOA through the corresponding first scanning line Gate1.
  • the gate of the first compensation transistor T22 is coupled to the output terminal of the corresponding first gate driving circuit Gate1-GOA through the corresponding first scanning line Gate1.
  • the gate of the second reset transistor T27 is coupled to the corresponding output terminal of the second gate driving circuit Gate2-GOA through the corresponding second scan line Gate2.
  • the gate of the third reset transistor T28 is coupled to the corresponding output terminal of the second gate driving circuit Gate2-GOA through the corresponding second scan line Gate2.
  • the display substrate further includes a plurality of second sub-pixel driving circuits, a plurality of light-emitting elements, a plurality of data lines Vdata and a plurality of second initialization signal lines VINIT2,
  • the second sub-pixel driving circuit includes a second driving transistor T33, a second data writing transistor T34, a second compensation transistor T32 and a second reset transistor T27;
  • the gate of the second data writing transistor T34 is coupled to the output terminal of the corresponding second gate driving circuit Gate2-GOA, and the first electrode of the second data writing transistor T34 is connected to the corresponding data line.
  • Vdata is coupled, and the second pole of the second data writing transistor T34 is coupled with the first pole of the second driving transistor T33;
  • the gate of the second compensation transistor T32 is coupled to the output terminal of the corresponding first gate driving circuit Gate1-GOA, and the first electrode of the second compensation transistor T32 is connected to the second terminal of the second driving transistor T33.
  • the second pole of the second compensation transistor T32 is coupled with the gate of the second driving transistor T33;
  • the gate of the second reset transistor T27 is coupled to the corresponding output terminal of the second gate driving circuit Gate2-GOA, and the first electrode of the second reset transistor T27 is coupled to the corresponding second initialization signal.
  • the line VINIT2 is coupled, and the second electrode of the second reset transistor T27 is coupled with the corresponding light-emitting element.
  • the display substrate further includes: a plurality of first initialization signal lines VINIT1, a plurality of first scanning lines Gate1, a plurality of second scanning lines Gate2, a plurality of reset lines Reset, a plurality of light emitting control lines, a plurality of Power line VDD.
  • the sub-pixel driving circuit includes a 7T1C circuit structure.
  • the sub-pixel driving circuit also includes: a first reset transistor T21, a first power control transistor T25 and a first light emission control transistor T26.
  • the first initialization signal line VINIT1 transmits a first initialization signal
  • the second initialization signal line VINIT2 transmits a second initialization signal
  • the first scan line Gate1 transmits a first gate drive signal GOUT1
  • the The second scan line Gate2 transmits the second gate drive signal GOUT2
  • the light-emitting control line transmits the light-emitting control signal EM
  • the reset line Reset transmits the reset signal
  • the power line VDD transmits the power signal.
  • the gate of the first reset transistor T21 is coupled to the corresponding reset line Reset, and the first pole of the first reset transistor T21 is coupled to the corresponding first initialization signal line VINIT1.
  • the second electrode of T21 is coupled to the gate of the second driving transistor T33.
  • the gate of the first power control transistor T25 is coupled to the corresponding light-emitting control line, and the first pole of the first power control transistor T25 is coupled to the corresponding power line VDD.
  • the first power control transistor The second pole of T25 is coupled with the first pole of the second driving transistor T33.
  • the gate of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting control line, and the first pole of the first light-emitting control transistor T26 is coupled to the second pole of the second driving transistor T33, so The second electrode of the first light-emitting control transistor T26 is coupled to the corresponding light-emitting element.
  • the cathode of the light-emitting element receives the negative power supply signal VSS.
  • the gate of the second data writing transistor T34 is coupled to the output terminal of the corresponding second gate driving circuit Gate2-GOA through the corresponding second scanning line Gate2.
  • the gate of the second compensation transistor T32 is coupled to the output terminal of the corresponding first gate driving circuit Gate1-GOA through the corresponding first scanning line Gate1.
  • the gate of the second reset transistor T27 is coupled to the corresponding output terminal of the second gate driving circuit Gate2-GOA through the corresponding second scan line Gate2.
  • the gate driving signals of the second compensation transistor T32 and the second data writing transistor T34 are provided by different gate driving circuits.
  • the second compensation transistor T32 and the second data writing transistor T34 are provided by different gate driving circuits.
  • the first gate driving circuit Gate1-GOA connected to the transistor T32 and the second gate driving circuit Gate2-GOA connected to the second data writing transistor T34 are mirrored, and other signal lines except the frame start signal line can be Achieve sharing.
  • the display substrate adopts the first sub-pixel driving circuit and the second sub-pixel driving circuit, the low-frequency flicker problem can be effectively improved.
  • the display substrate further includes:
  • a first electrostatic discharge circuit (including a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16), the first electrostatic discharge circuit and the first gate driving circuit Gate1- GOA coupling;
  • a second electrostatic discharge circuit (including a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12), the second electrostatic discharge circuit is coupled to the second gate drive circuit Gate2-GOA catch;
  • the first electrostatic discharge circuit and the second electrostatic discharge circuit are arranged in a mirror image, and the first electrostatic discharge circuit and the second electrostatic discharge circuit share at least one signal line.
  • the first electrostatic discharge circuit and the second electrostatic discharge circuit share at least one signal line. , which is more conducive to narrowing the bezel of the display substrate.
  • the first electrostatic discharge circuit and the second electrostatic discharge circuit share a first level line VGH and/or a second level line VGL.
  • the peripheral area also includes:
  • a plurality of light-emitting control drive circuits EM-GOA are divided into multiple groups of light-emitting control drive circuits EM-GOA.
  • Each group of light-emitting control drive circuits EM-GOA includes two light-emitting control drive circuits EM-GOA arranged in a mirror image.
  • the two light-emitting control driving circuits EM-GOA share at least one signal line.
  • the at least one common signal line includes: at least one signal line among the first level signal line VGH, the third clock signal line ECK, and the fourth clock signal line ECB.
  • one light-emitting control drive circuit EM-GOA is connected to the third frame start signal line ESTV1, and the other light-emitting control drive circuit EM-GOA Connect the fourth frame start signal line ESTV2.
  • the third frame start signal line ESTV1 and the fourth frame start signal line ESTV2 can be controlled independently.
  • a light emission control driving circuit EM-GOA can be used to control the first power control transistor T25 in Figure 2 or Figure 5
  • another light emission control driving circuit EM-GOA can be used to control the first power control transistor T25 in Figure 2 or Figure 5.
  • the first power control transistor T25 can be used to control the first power control transistor T25 in Figure 2 or Figure 5.
  • the light emission control driving circuit EM-GOA can adopt a circuit structure as shown in Figure 27, but is not limited to this.
  • Figure 27 illustrates that the light emitting control driving circuit EM-GOA includes a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, a forty-fourth transistor T44, a forty-fifth transistor T45, a fourth Sixteenth transistor T46, forty-seventh transistor T47, forty-eighth transistor T48, forty-ninth transistor T49, fiftieth transistor T50, third capacitor C3, fourth capacitor C4, fifth capacitor C5, and light emission control The output terminal EOUT1 of the driving circuit EM-GOA.
  • An embodiment of the present disclosure also provides a display device, including the above display substrate.
  • the display device can be any product or component with a display function such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc.
  • the display device also includes a flexible circuit board, a printed circuit board and a back panel. Board etc.
  • the display substrate provided by the above embodiments, by arranging the display substrate to include a plurality of first gate driving circuits and a plurality of second gate driving circuits, the low-frequency flicker problem of the display substrate is effectively improved. Moreover, by arranging the first gate driving circuit and the second gate driving circuit to share at least one signal line, the first gate driving circuit and the second gate driving circuit and the signal lines connecting them are effectively reduced in size.
  • the jointly occupied frame width is not only conducive to narrowing the frame of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be described again here.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate.
  • the manufacturing method includes:
  • a plurality of first gate drive circuits and a plurality of second gate drive circuits are produced.
  • the first gate drive signal output by the first gate drive circuit and the second gate signal output by the second gate drive circuit are The driving signal timing is different; the first gate driving circuit and the second gate driving circuit share at least one signal line.
  • the display substrate provided by the embodiments of the present disclosure, by arranging the display substrate to include a plurality of first gate driving circuits and a plurality of second gate driving circuits, the low-frequency flicker problem of the display substrate is effectively improved. Moreover, by arranging the first gate driving circuit and the second gate driving circuit to share at least one signal line, the first gate driving circuit and the second gate driving circuit and the signal lines connecting them are effectively reduced in size.
  • the jointly occupied frame width is not only conducive to narrowing the frame of the display substrate, but also effectively reduces the power consumption of the gate drive circuit.
  • the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, and the main part extends in a certain direction.
  • the extension length of the main part along a certain direction is greater than the extension length of the secondary part along other directions.
  • serial numbers of each step cannot be used to limit the order of each step.
  • sequence of each step can be changed. It is also within the protection scope of this disclosure.

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Abstract

本公开提供一种显示基板及其制作方法、显示装置。所述显示基板包括：多个第一栅极驱动电路和多个第二栅极驱动电路，所述第一栅极驱动电路输出的第一栅极驱动信号和所述第二栅极驱动电路输出的第二栅极驱动信号时序不同；所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线。

Description

显示基板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
随着智能化的迅速发展，市场对于智能终端显示设备的需求和期望越来越高，手机和平板电脑等智能终端显示设备在人们的生活中需求越来越大，而且更加多样的应用场景使得人们在追求全面屏显示的同时，也希望能够享受更大尺寸和更高分辨率的视觉感受。在优化显示效果的需求下，低频显示以降低功耗也成为了重点。
发明内容
本公开的目的在于提供一种显示基板及其制作方法、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：多个第一栅极驱动电路和多个第二栅极驱动电路，所述第一栅极驱动电路输出的第一栅极驱动信号和所述第二栅极驱动电路输出的第二栅极驱动信号时序不同；所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线。
可选的，所述显示基板包括显示区域和包围所述显示区域的周边区域；所述多个第一栅极驱动电路和所述多个第二栅极驱动电路均位于所述周边区域；
在靠近所述显示区域同一侧的周边区域中，所述第一栅极驱动电路的至少部分与所述第二栅极驱动电路的至少部分呈镜像设置。
可选的，所述第一栅极驱动电路和所述第二栅极驱动电路共用第一电平信号线，所述第一电平信号线传输具有第一电平的直流信号。
可选的，所述第一电平信号线在所述显示基板的衬底基板上的正投影的至少部分，位于所述第一栅极驱动电路在所述衬底基板上的正投影和所述第 二栅极驱动电路在所述衬底基板上的正投影之间。
可选的，所述第一电平信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路在所述衬底基板上的正投影至少部分交叠；和/或，所述第一电平信号线在所述衬底基板上的正投影，与所述第二栅极驱动电路在所述衬底基板上的正投影至少部分交叠。
可选的，所述第一栅极驱动电路和所述第二栅极驱动电路共用第一时钟信号线和/或第二时钟信号线，所述第一时钟信号线传输的第一时钟信号和所述第二时钟信号线传输的第二时钟信号的相位相反。
可选的，所述第一栅极驱动电路的至少部分与所述第二栅极驱动电路的至少部分关于第一对称轴呈镜像对称；所述第一对称轴与所述第一时钟信号线至少部分交叠，或者所述第一对称轴与所述第二时钟信号线至少部分交叠，或者所述第一对称轴与所述第一电平信号线至少部分交叠。
可选的，所述第一电平信号线在所述衬底基板上的正投影，位于所述第一时钟信号线在所述衬底基板上的正投影和所述第二时钟信号线在所述衬底基板上的正投影之间。
可选的，所述第一时钟信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路和所述第二栅极驱动电路中的一种在所述衬底基板上的正投影至少部分交叠；所述第二时钟信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路和所述第二栅极驱动电路中的另一种在所述衬底基板上的正投影至少部分交叠。
可选的，所述第一栅极驱动电路耦接第一帧起始信号线，所述第二栅极驱动电路耦接第二帧起始信号线。
可选的，所述第一电平信号线在所述衬底基板上的正投影，位于所述第一帧起始信号线在所述衬底基板上的正投影和所述第二帧起始信号线在所述衬底基板上的正投影之间。
可选的，所述第一帧起始信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路在所述衬底基板上的正投影至少部分交叠；所述第二帧起始信号线在所述衬底基板上的正投影，与所述第二栅极驱动电路在所述衬底基板上的正投影至少部分交叠。
可选的，所述第一帧起始信号线在所述衬底基板上的正投影和所述第二帧起始信号线在所述衬底基板上的正投影，位于所述第一时钟信号线在所述衬底基板上的正投影和所述第二时钟信号线在所述衬底基板上的正投影之间。
可选的，所述第一电平信号线，所述第一时钟信号线，所述第二时钟信号线，所述第一帧起始信号线和所述第二帧起始信号线中的至少一个采用所述显示基板中的第二源漏金属层制作。
可选的，所述第一电平信号线，所述第一时钟信号线，所述第二时钟信号线，所述第一帧起始信号线和所述第二帧起始信号线中的至少一个包括层叠设置的两层导电层，一层导电层采用所述第二源漏金属层制作，另一层导电层采用所述显示基板中的第三源漏金属层制作。
可选的，所述第一栅极驱动电路包括的输出晶体管的沟道宽长比等于所述第二栅极驱动电路包括的输出晶体管的沟道宽长比。
可选的，所述第一栅极驱动电路包括的输出晶体管的沟道宽长比大于所述第二栅极驱动电路包括的输出晶体管的沟道宽长比。
可选的，所述第一栅极驱动电路和所述第二栅极驱动电路中至少部分具有相同功能的目标器件相耦接。
可选的，所述显示基板还包括多个第一子像素驱动电路，多个发光元件，多条数据线，多条第二初始化信号线和多条第三初始化信号线，所述第一子像素驱动电路包括第一驱动晶体管，第一数据写入晶体管，第一补偿晶体管，第二复位晶体管和第三复位晶体管；
所述第一数据写入晶体管的栅极与对应的第一栅极驱动电路的输出端耦接，所述第一数据写入晶体管的第一极与对应的所述数据线耦接，所述第一数据写入晶体管的第二极与所述第一驱动晶体管的第一极耦接；
所述第一补偿晶体管的栅极与对应的第一栅极驱动电路的输出端耦接，所述第一补偿晶体管的第一极与所述第一驱动晶体管的第二极耦接，所述第一补偿晶体管的第二极与所述第一驱动晶体管的栅极耦接；
所述第二复位晶体管的栅极与对应的所述第二栅极驱动电路的输出端耦接，所述第二复位晶体管的第一极与对应的所述第二初始化信号线耦接，所述第二复位晶体管的第二极与对应的发光元件耦接；
所述第三复位晶体管的栅极与对应的所述第二栅极驱动电路的输出端耦接，所述第三复位晶体管的第一极与对应的所述第三初始化信号线耦接，所述第三复位晶体管的第二极与所述第一驱动晶体管的第一极耦接。
可选的，所述显示基板还包括多个第二子像素驱动电路，多个发光元件，多条数据线和多条第二初始化信号线，所述第二子像素驱动电路包括第二驱动晶体管，第二数据写入晶体管，第二补偿晶体管和第二复位晶体管；
所述第二数据写入晶体管的栅极与对应的第二栅极驱动电路的输出端耦接，所述第二数据写入晶体管的第一极与对应的所述数据线耦接，所述第二数据写入晶体管的第二极与所述第二驱动晶体管的第一极耦接；
所述第二补偿晶体管的栅极与对应的第一栅极驱动电路的输出端耦接，所述第二补偿晶体管的第一极与所述第二驱动晶体管的第二极耦接，所述第二补偿晶体管的第二极与所述第二驱动晶体管的栅极耦接；
所述第二复位晶体管的栅极与对应的所述第二栅极驱动电路的输出端耦接，所述第二复位晶体管的第一极与对应的所述第二初始化信号线耦接，所述第二复位晶体管的第二极与对应的发光元件耦接。
可选的，所述显示基板还包括：
第一静电释放电路，所述第一静电释放电路与所述第一栅极驱动电路耦接；
第二静电释放电路，所述第二静电释放电路与所述第二栅极驱动电路耦接；
所述第一静电释放电路与所述第二静电释放电路呈镜像设置，所述第一静电释放电路与所述第二静电释放电路共用至少一条信号线。
可选的，所述周边区域还包括：
多个发光控制驱动电路，所述多个发光控制驱动电路划分为多组发光控制驱动电路，每组发光控制驱动电路包括呈镜像设置的两个所述发光控制驱动电路，该两个所述发光控制驱动电路共用至少一条信号线。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示基板的 制作方法，用于制作上述显示基板，所述制作方法包括：
制作多个第一栅极驱动电路和多个第二栅极驱动电路，所述第一栅极驱动电路输出的第一栅极驱动信号和所述第二栅极驱动电路输出的第二栅极驱动信号时序不同；所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的显示基板显示亮度随时间变化示意图；
图2为本公开实施例提供的8T1C的电路结构示意图；
图3为本公开实施例提供的显示基板在画面刷新和画面保持时的工作时序图；
图4为本公开实施例提供的栅极驱动电路驱动8T1C电路结构的时序图；
图5为本公开实施例提供的7T1C的电路结构示意图；
图6为本公开实施例提供的栅极驱动电路驱动7T1C电路结构的时序图；
图7为本公开实施例提供的栅极驱动电路的第一布局示意图；
图8为本公开实施例提供的第一栅极驱动电路和第二栅极驱动电路的第一布局示意图；
图9为图7中有源层和第一栅金属层的布局示意图；
图10为图7中第二栅金属层的布局示意图；
图11为图7中层间绝缘层上形成的过孔的示意图；
图12为图7中第一源漏金属层的布局示意图；
图13本公开实施例提供的栅极驱动电路和静电释放电路的布局示意图；
图14本公开实施例提供的静电释放电路的电路结构示意图；
图15为图13中有源层和第一栅金属层的布局示意图；
图16为图13中层间绝缘层上形成的过孔的示意图；
图17为图13中第一源漏金属层的布局示意图；
图18为本公开实施例提供的栅极驱动电路的第二布局示意图；
图19为图18中有源层和第一栅金属层的布局示意图；
图20为图18中层间绝缘层上形成的过孔的示意图；
图21为图18中第一源漏金属层的布局示意图；
图22为图18中第一钝化层上形成的过孔的示意图；
图23为图18中第一平坦层上形成的过孔的示意图；
图24为图18中第二源漏金属层的布局示意图；
图25为本公开实施例提供的栅极驱动电路的第三布局示意图；
图26为本公开实施例提供的栅极驱动电路的第四布局示意图；
图27为本公开实施例提供的发光控制驱动电路的电路结构图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
参见表1，图2和图3，由于子像素驱动电路中，N1节点周围的T2M节点和T1M节点的电压会对N1节点产生漏电影响，导致一帧内N1节点电压会持续被写高(如写高△N1＝0.0713V)，无法保持稳定，从而导致亮度变暗(如N4节点发生电位变化△N4＝0.064V)，参见图1，人眼能够明显观察到亮度的变化情况，观察到画面闪烁。
Figure PCTCN2022102741-appb-000001
表1
由于屏幕出现画面闪烁的主要因素为N1节点在一帧内存在电压变化，因此在改善低频闪烁的问题时，会采用增加一组栅极驱动电路的方式进行驱动。
如图2和图3所示，在低频显示时，采用longV模式进行驱动显示，即发光控制信号EM一帧内存在多脉冲(pulse)输入。发光控制信号EM的第一 pulse为画面刷新帧，实现数据信号写入；发光控制信号EM的第二pulse和第三pulse(图中未示出)等为画面保持帧，画面保持帧内进行发光元件的阳极复位。
更详细地说，以子像素驱动电路包括8T1C(即8个晶体管1个电容)电路结构为例。
在画面刷新帧内，共存在三个电压写入阶段，①阶段为复位信号(由复位信号线Reset传输)及第二栅极驱动信号(由第二扫描线Gate2传输)低电平打开，N1节点复位为第一初始化信号(由第一初始化信号线VINIT1传输)，N2节点复位为第三初始化信号(由第三初始化信号线VINIT3传输)；②阶段为N1节点重复复位阶段；③阶段为第一栅极驱动信号(由第一扫描线Gate1传输)低电平打开，数据信号(由数据线Vdata传输)写入N1节点；随后发光控制信号EM低电平，像素发光。
在画面保持帧内，存在④阶段，④阶段中发光控制信号EM高电平关闭，第二栅极驱动信号低电平打开，此时发光元件的阳极复位为第二初始化信号(由第二初始化信号线VINIT2传输)，且N2节点复位为第三初始化信号(例如：第三初始化信号的电压值为2V)；随后发光控制信号EM低电平打开，像素发光。
本公开提供的显示基板中，设置第一栅极驱动电路，第二栅极驱动电路和发光控制驱动电路。发光控制驱动电路驱动一帧内多pulse发光控制信号EM输出，用来控制发光与否；第二栅极驱动电路驱动一帧内多pulse第二栅极驱动信号输出，控制阳极复位和N2节点复位；第一栅极驱动电路驱动一帧内3pulse第一栅极驱动信号输出，用来控制数据信号写入及N1节点复位。
由于本申请提供的显示基板中包括了多组栅极驱动电路，因此，如何兼顾显示基板窄边框的需求成为了重点。
请参阅图4，图6，图7和图12，本公开实施例提供一种显示基板，包括：多个第一栅极驱动电路Gate1-GOA和多个第二栅极驱动电路Gate2-GOA，所述第一栅极驱动电路Gate1-GOA输出的第一栅极驱动信号GOUT1和所述第二栅极驱动电路Gate2-GOA输出的第二栅极驱动信号GOUT2时序不同；所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用至少 一条信号线。
示例性的，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA连接到同一子像素驱动电路。
示例性的，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA连接到同一行子像素驱动电路；或者，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA连接到同一颜色的子像素驱动电路。
示例性的，所述第一栅极驱动电路Gate1-GOA包括多个晶体管和存储电容，所述第一栅极驱动电路Gate1-GOA分别与第一电平信号线VGH，第二电平信号线VGL，第一时钟信号线GCK，第二时钟信号线GCB和第一帧起始信号线GSTV1耦接，所述第一栅极驱动电路Gate1-GOA包括的多个晶体管和存储电容在上述各信号线提供的相应的信号的共同控制下，实现输出第一栅极驱动信号GOUT1。
示例性的，所述第二栅极驱动电路Gate2-GOA包括多个晶体管和存储电容，所述第二栅极驱动电路Gate2-GOA分别与第一电平信号线VGH，第二电平信号线VGL，第一时钟信号线GCK，第二时钟信号线GCB和第二帧起始信号线GSTV2耦接，所述第二栅极驱动电路Gate2-GOA包括的多个晶体管和存储电容在上述各信号线提供的相应的信号的共同控制下，实现输出第二栅极驱动信号GOUT2。
更详细地说，如图8至图12所示，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA的电路结构大致相同。
第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA包括第一晶体管T1至第八晶体管T8，第一电容C1和第二电容C2。
所述第一晶体管T1的栅极与第一时钟信号线GCK耦接，所述第一晶体管T1的第一极与第一帧起始信号线GSTV1耦接，所述第一晶体管T1的第二极与第二晶体管T2的栅极耦接。
第二晶体管T2的第一极与第一时钟信号线GCK耦接，所述第二晶体管T2的第二极与第三晶体管T3的第二极耦接。
第三晶体管T3的栅极与所述第一时钟信号线GCK耦接，第三晶体管T3 的第一极与第二电平信号线VGL耦接。
第四晶体管T4的栅极与第三晶体管T3的第二极耦接，所述第四晶体管T4的第二极作为栅极驱动电路的输出端，在第一栅极驱动电路Gate1-GOA中输出端输出第一栅极驱动信号GOUT1，在第二栅极驱动电路Gate2-GOA中输出端输出第二栅极驱动信号GOUT2。
第二电容C2的第一极板C21与第四晶体管T4的栅极耦接，第二电容C2的第二极板C22与所述第四晶体管T4的第一极耦接。
第五晶体管T5的栅极与第八晶体管T8的第二极耦接，第五晶体管T5的第一极与第二时钟信号线GCB耦接，第五晶体管T5的第二极与第四晶体管T4的第二极耦接。
第一电容C1的第一极板C11与第五晶体管T5的栅极耦接，第一电容C1的第二极板C12与第五晶体管T5的第二极耦接。
第六晶体管T6的栅极与第四晶体管T4的栅极耦接，第六晶体管T6的第一极与第一电平信号线VGH耦接，第六晶体管T6的第二极与第七晶体管T7的第一极耦接。
第七晶体管T7的栅极与第二时钟信号线GCB耦接，第七晶体管T7的第二极与第一晶体管T1的第二极耦接。
第八晶体管T8的栅极与第二电平信号线VGL耦接，第八晶体管T8的第一极与第七晶体管T7的第二极耦接。
示例性的，所述第一栅极驱动电路Gate1-GOA耦接的第一电平信号线VGH传输的第一电平信号，与所述第二栅极驱动电路Gate2-GOA耦接的第一电平信号线VGH传输的第一电平信号相同。所述第一栅极驱动电路Gate1-GOA耦接的第二电平信号线VGL传输的第二电平信号，与所述第二栅极驱动电路Gate2-GOA耦接的第二电平信号线VGL传输的第二电平信号相同。所述第一栅极驱动电路Gate1-GOA耦接的第一时钟信号线GCK传输的第一时钟信号，与所述第二栅极驱动电路Gate2-GOA耦接的第一时钟信号线GCK传输的第一时钟信号相同。所述第一栅极驱动电路Gate1-GOA耦接的第二时钟信号线GCB传输的第二时钟信号，与所述第二栅极驱动电路Gate2-GOA耦接的第二时钟信号线GCB传输的第二时钟信号相同。
值得注意，因第一栅极驱动电路Gate1-GOA与第二栅极驱动电路Gate2-GOA同样均为一行栅极驱动电路驱动一行像素，即一对一驱动的设计，因此，所述第一栅极驱动电路Gate1-GOA接入的第一时钟信号和第二栅极驱动电路Gate2-GOA接入的第一时钟信号具有相同的脉冲宽度及频率，所述第一栅极驱动电路Gate1-GOA接入的第二时钟信号和第二栅极驱动电路Gate2-GOA接入的第二时钟信号具有相同的脉冲宽度及频率。
示例性的，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用所述第一电平信号线VGH，所述第二电平信号线VGL，所述第一时钟信号线GCK和所述第二时钟信号线GCB中的至少一条信号线。
示例性的，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用的信号线的线宽，大于未被共用的信号线的线宽，但不仅限于此。
可选地，第一时钟信号线GCK的线宽和所述第二时钟信号线GCB的线宽均大于第一电平信号线VGH的线宽，且均大于第二电平信号线VGL的线宽。
可选地，第一电平信号线VGH的线宽，大于第一时钟信号线GCK和所述第二时钟信号线GCB线宽，且大于第二电平信号线VGL的线宽。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，通过设置显示基板包括多个第一栅极驱动电路Gate1-GOA和多个第二栅极驱动电路Gate2-GOA，有效改善了显示基板的低频闪烁问题。而且，通过设置所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用至少一条信号线，有效缩小了第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA以及二者连接的信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
如图7至图12所示，在一些实施例中，所述显示基板包括显示区域和包围所述显示区域的周边区域；所述多个第一栅极驱动电路Gate1-GOA和所述多个第二栅极驱动电路Gate2-GOA均位于所述周边区域；
在靠近所述显示区域同一侧的周边区域中，所述第一栅极驱动电路Gate1-GOA的至少部分与所述第二栅极驱动电路Gate2-GOA的至少部分呈镜像设置。
示例性的，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA可以分布在所述显示基板的左边框和/或右边框。
如图9，图10和图12所示，示例性的，在所述显示基板的左边框和/或右边框，所述第一栅极驱动电路Gate1-GOA的至少部分与所述第二栅极驱动电路Gate2-GOA的至少部分呈镜像设置。示例性的，该呈镜像设置的至少部分包括晶体管，电容和/或一些导电连接部等，但不仅限于此。
示例性的，所述第一栅极驱动电路Gate1-GOA的至少部分在所述显示基板的衬底基板上的正投影，与所述第二栅极驱动电路Gate2-GOA的至少部分在所述衬底基板上的正投影关于第一对称轴呈镜像对称，所述第一对称轴在所述衬底基板上的正投影，位于所述第一栅极驱动电路Gate1-GOA在所述衬底基板上的正投影和所述第二栅极驱动电路Gate2-GOA在所述衬底基板上的正投影之间。
如图9，图10和图12所示，示例性的，所述第一栅极驱动电路Gate1-GOA的至少部分与所述第二栅极驱动电路Gate2-GOA的至少部分呈镜像设置时，所述第一栅极驱动电路Gate1-GOA中的第四晶体管T4位于第一栅极驱动电路Gate1-GOA远离所述第二栅极驱动电路Gate2-GOA的一侧。所述第一栅极驱动电路Gate1-GOA中的第五晶体管T5位于第一栅极驱动电路Gate1-GOA远离所述第二栅极驱动电路Gate2-GOA的一侧。
如图9，图10和图12所示，示例性的，所述第一栅极驱动电路Gate1-GOA的至少部分与所述第二栅极驱动电路Gate2-GOA的至少部分呈镜像设置时，所述第二栅极驱动电路Gate2-GOA中的第四晶体管T4位于第二栅极驱动电路Gate2-GOA远离所述第一栅极驱动电路Gate1-GOA的一侧。所述第二栅极驱动电路Gate2-GOA中的第五晶体管T5位于第二栅极驱动电路Gate2-GOA远离所述第一栅极驱动电路Gate1-GOA的一侧。
上述实施例提供的显示基板中，通过设置所述第一栅极驱动电路Gate1-GOA的至少部分与所述第二栅极驱动电路Gate2-GOA的至少部分呈镜像设置，能够将所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA占用的空间压缩至最小，同时有利于实现信号线的共用，达到缩窄显示基板边框的目的。
如图7至图12所示，在一些实施例中，设置所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用第一电平信号线VGH，所述第一电平信号线VGH传输具有第一电平的直流信号。
示例性的，所述第一电平信号线VGH包括沿第一方向延伸的至少部分，所述第一栅极驱动电路Gate1-GOA在所述衬底基板上的正投影与所述第二栅极驱动电路Gate2-GOA在所述衬底基板上的正投影沿第二方向排列，所述第一方向与所述第二方向相交。示例性的，所述第一方向包括纵向，所述第二方向包括横向，但不仅限于此。
上述设置方式有效缩小了第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA以及二者连接的第一电平信号线VGH共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
如图7至图12所示，在一些实施例中，设置所述第一电平信号线VGH在所述显示基板的衬底基板上的正投影的至少部分，位于所述第一栅极驱动电路Gate1-GOA在所述衬底基板上的正投影和所述第二栅极驱动电路Gate2-GOA在所述衬底基板上的正投影之间。
上述设置方式使得所述第一栅极驱动电路Gate1-GOA的至少部分和所述第二栅极驱动电路Gate2-GOA的至少部分分别位于所述第一电平信号线VGH的两侧，由于所述第一电平信号线VGH传输具有稳定电位的直流信号，因此，上述设置方式有利于所述第一电平信号线VGH屏蔽所述第一栅极驱动电路Gate1-GOA与所述第二栅极驱动电路Gate2-GOA之间的信号干扰，从而有效提升了显示基板工作的稳定性。
如图18至图24所示，在一些实施例中，设置所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA在所述衬底基板上的正投影至少部分交叠；和/或，所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第二栅极驱动电路Gate2-GOA在所述衬底基板上的正投影至少部分交叠。
示例性的，所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA包括的晶体管在所述衬底基板上的正投影至少部分交叠；和/或，所述第一电平信号线VGH在所述衬底基板上的正投影， 与所述第二栅极驱动电路Gate2-GOA包括的晶体管在所述衬底基板上的正投影至少部分交叠。
示例性的，如图18和图19所示，所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA包括的第一晶体管T1的栅极在所述衬底基板上的正投影至少部分交叠；所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA包括的第七晶体管T7的栅极在所述衬底基板上的正投影至少部分交叠。
示例性的，如图18和图19所示，所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第二栅极驱动电路Gate2-GOA包括的第一晶体管T1的栅极在所述衬底基板上的正投影至少部分交叠；所述第一电平信号线VGH在所述衬底基板上的正投影，与所述第二栅极驱动电路Gate2-GOA包括的第七晶体管T7的栅极在所述衬底基板上的正投影至少部分交叠。
上述设置方式进一步缩小了第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA以及二者连接的信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
如图7至图12，图18至图24所示，在一些实施例中，设置所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用第一时钟信号线GCK和/或第二时钟信号线GCB，所述第一时钟信号线GCK传输的第一时钟信号和所述第二时钟信号线GCB传输的第二时钟信号的相位相反。
示例性的，所述第一时钟信号线GCK包括沿所述第一方向延伸的至少部分，所述第二时钟信号线GCB包括沿所述第一方向延伸的至少部分，所述第一时钟信号线GCK和所述第二时钟信号线GCB沿所述第二方向排列。
上述实施例提供的显示基板中，通过设置所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA共用第一时钟信号线GCK和/或第二时钟信号线GCB，能够在保证所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA正常驱动的同时，减少一组时钟信号线，从而有效缩小了第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA以及二者连接的信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
在一些实施例中，所述第一栅极驱动电路Gate1-GOA的至少部分与所述第二栅极驱动电路Gate2-GOA的至少部分关于第一对称轴呈镜像对称；
所述第一对称轴与所述第一时钟信号线GCK至少部分交叠，如图7至图12所示，或者所述第一对称轴与所述第二时钟信号线GCB至少部分交叠，如图18至图25所示，或者所述第一对称轴与所述第一电平信号线VGH至少部分交叠。
上述设置所述第一对称轴与共用信号线第一时钟信号线GCK，第二时钟信号线GCB或者第一电平信号线VGH交叠，使得所述第一栅极驱动电路Gate1-GOA的至少部分和所述第二栅极驱动电路Gate2-GOA的至少部分能够分别位于共用信号线的两侧，从而很好的保证了所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA与共用信号线之间的连接信赖性，降低了所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA的布局难度。
上述设置所述第一对称轴与所述第一电平信号线VGH至少部分交叠，使得所述第一栅极驱动电路Gate1-GOA的至少部分和所述第二栅极驱动电路Gate2-GOA的至少部分分别位于所述第一电平信号线VGH的两侧，由于所述第一电平信号线VGH传输具有稳定电位的直流信号，因此，上述设置方式有利于所述第一电平信号线VGH屏蔽所述第一栅极驱动电路Gate1-GOA与所述第二栅极驱动电路Gate2-GOA之间的信号干扰，从而有效提升了显示基板工作的稳定性。
如图18至图25所示，在一些实施例中，设置所述第一电平信号线VGH在所述衬底基板上的正投影，位于所述第一时钟信号线GCK在所述衬底基板上的正投影和所述第二时钟信号线GCB在所述衬底基板上的正投影之间。
上述设置方式使得所述第一时钟信号线GCK和所述第二时钟信号线GCB能够分别位于所述第一电平信号线VGH的两侧，从而使得所述第一电平信号线VGH有效屏蔽了所述第一时钟信号线GCK和所述第二时钟信号线GCB之间的干扰，保证了栅极驱动电路的工作稳定性。
如图18至图24所示，在一些实施例中，所述第一时钟信号线GCK在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA和所述第二栅 极驱动电路Gate2-GOA中的一种在所述衬底基板上的正投影至少部分交叠；所述第二时钟信号线GCB在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA中的另一种在所述衬底基板上的正投影至少部分交叠。
示例性的，所述第一时钟信号线GCK在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA中的一种包括的晶体管在所述衬底基板上的正投影至少部分交叠；所述第二时钟信号线GCB在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA中的另一种包括的晶体管在所述衬底基板上的正投影至少部分交叠。
示例性的，所述第一时钟信号线GCK在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA中的一种包括的电容结构在所述衬底基板上的正投影至少部分交叠；所述第二时钟信号线GCB在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA中的另一种包括的电容结构在所述衬底基板上的正投影至少部分交叠。
如图18和图19所示，所述第一时钟信号线GCK在所述衬底基板上的正投影，分别与所述第一栅极驱动电路Gate1-GOA中包括的第一晶体管T1的栅极在所述衬底基板上的正投影，所述第一栅极驱动电路Gate1-GOA中包括的第二晶体管T2的有源图形在所述衬底基板上的正投影，以及第一栅极驱动电路Gate1-GOA中包括的第二电容在所述衬底基板上的正投影均至少部分交叠。
如图18和图19所示，所述第二时钟信号线GCB在所述衬底基板上的正投影，分别与所述第二栅极驱动电路Gate2-GOA中包括的第一晶体管T1的栅极在所述衬底基板上的正投影，所述第二栅极驱动电路Gate2-GOA中包括的第二晶体管T2的有源图形在所述衬底基板上的正投影，以及第二栅极驱动电路Gate2-GOA中包括的第二电容在所述衬底基板上的正投影均至少部分交叠。
上述设置方式进一步缩小了第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA以及二者连接的信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
如图7至图12，图18至图24所示，在一些实施例中，所述第一栅极驱动电路Gate1-GOA耦接第一帧起始信号线GSTV1，所述第二栅极驱动电路Gate2-GOA耦接第二帧起始信号线GSTV2。
示例性的，所述第一帧起始信号线GSTV1包括沿所述第一方向延伸的至少部分，所述第二帧起始信号线GSTV2包括沿所述第一方向延伸的至少部分。所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2能够独立控制。
上述实施例提供的显示基板中，设置所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA连接各自原有的帧起始信号线，保持接入各自原有的帧起始信号，使得后续进行栅极驱动信号的调试时，仍然能够通过调整各自接入的帧起始信号达到控制所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA输出不同的脉冲，从而达到驱动低频像素的目的。
如图7至图12，图18至图24所示，在一些实施例中，设置所述第一电平信号线VGH在所述衬底基板上的正投影，位于所述第一帧起始信号线GSTV1在所述衬底基板上的正投影和所述第二帧起始信号线GSTV2在所述衬底基板上的正投影之间。
上述设置方式使得所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2能够分别位于所述第一电平信号线VGH的两侧，从而使得所述第一电平信号线VGH有效屏蔽了所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2之间的干扰，保证了栅极驱动电路的工作稳定性。
示例性的，如图7至图12所示，在一些实施例中，第一时钟信号线GCK，第二时钟信号线GCB，第一电平信号线VGH，第一帧起始信号线GSTV1，第二帧起始信号GSTV2位于第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA之间。例如：第一帧起始信号线GSTV1，第二帧起始信号GSTV2位于第二时钟信号线GCB的同一侧；第一时钟信号线GCK，第一电平信号线VGH位于第二时钟信号线GCB的同一侧。
示例性的，如图7至图12所示，在一些实施例中，第一帧起始信号线GSTV1，第二帧起始信号GSTV2位于第二时钟信号线GCB的同一侧，第一帧起始信号线GSTV1耦接到第一栅极驱动电路Gate1-GOA，第二帧起始信号线 GSTV2耦接到第二栅极驱动电路Gate2-GOA，且第一帧起始信号线GSTV1距离第一栅极驱动电路Gate1-GOA的距离大于第二帧起始信号线GSTV2距离第二栅极驱动电路Gate2-GOA的距离。例如：第一帧起始信号线GSTV1距离第一栅极驱动电路Gate1-GOA的第一晶体管T1的距离(也即第一栅极驱动电路Gate1-GOA的第一晶体管T1到GSTV1的连接线段长度)，大于第二帧起始信号线GSTV2距离第二栅极驱动电路Gate2-GOA的第一晶体管T1的距离(也即第二栅极驱动电路Gate2-GOA的第一晶体管T1到第二帧起始信号线GSTV2的连接线段长度)。
示例性的，如图7至图12所示，在一些实施例中，第一栅极驱动电路Gate1-GOA的输出端到子像素(或子像素驱动电路)的距离，小于第二栅极驱动电路Gate2-GOA输出端到同一子像素(或子像素驱动电路)的距离。例如：第一栅极驱动电路Gate1-GOA的输出端(例如第五晶体管T5的漏极)到子像素(或子像素驱动电路)的距离(例如：GOUT1连接线段长度),小于第二栅极驱动电路Gate2-GOA的输出端(例如第五晶体管T5的漏极)到子像素(或子像素驱动电路)的距离(例如：GOUT 2连接线段长度)。
示例性的，如图7至图12所示，在一些实施例中，第二栅极驱动电路Gate2-GOA的输出端GOUT2(第二栅极驱动电路Gate2-GOA耦接到子像素的连接线段)与第一时钟信号线GCK，第二时钟信号线GCB，第一电平信号线VGH，第一帧起始信号线GSTV1，第二帧起始信号GSTV2均存在交叠。例如：第二栅极驱动电路Gate2-GOA的输出端GOUT2在衬底基板上的正投影与第一时钟信号线GCK，第二时钟信号线GCB，第一电平信号线VGH，第一帧起始信号线GSTV1，第二帧起始信号GSTV2在衬底基板上的正投影垂直。
如图18至图24所示，在一些实施例中，所述第一帧起始信号线GSTV1在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA在所述衬底基板上的正投影至少部分交叠；所述第二帧起始信号线GSTV2在所述衬底基板上的正投影，与所述第二栅极驱动电路Gate2-GOA在所述衬底基板上的正投影至少部分交叠。
示例性的，所述第一帧起始信号线GSTV1在所述衬底基板上的正投影，与所述第一栅极驱动电路Gate1-GOA包括的晶体管在所述衬底基板上的正投 影至少部分交叠；所述第二帧起始信号线GSTV2在所述衬底基板上的正投影，与所述第二栅极驱动电路Gate2-GOA包括的晶体管在所述衬底基板上的正投影至少部分交叠。
如图18和图19所示，所述第一帧起始信号线GSTV1在所述衬底基板上的正投影，分别与所述第一栅极驱动电路Gate1-GOA包括的第一晶体管T1的有源图形在所述衬底基板上的正投影，所述第一栅极驱动电路Gate1-GOA包括的第六晶体管T6的有源图形在所述衬底基板上的正投影，以及所述第一栅极驱动电路Gate1-GOA包括的第七晶体管T7的有源图形在所述衬底基板上的正投影均至少部分交叠。
如图18和图19所示，所述第二帧起始信号线GSTV2在所述衬底基板上的正投影，分别与所述第二栅极驱动电路Gate2-GOA包括的第一晶体管T1的有源图形在所述衬底基板上的正投影，所述第二栅极驱动电路Gate2-GOA包括的第六晶体管T6的有源图形在所述衬底基板上的正投影，以及所述第二栅极驱动电路Gate2-GOA包括的第七晶体管T7的有源图形在所述衬底基板上的正投影均至少部分交叠。
上述设置方式进一步缩小了第一栅极驱动电路Gate1-GOA和第二栅极驱动电路Gate2-GOA以及二者连接的帧起始信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
图18至图25所示，在一些实施例中，设置所述第一帧起始信号线GSTV1在所述衬底基板上的正投影和所述第二帧起始信号线GSTV2在所述衬底基板上的正投影，位于所述第一时钟信号线GCK在所述衬底基板上的正投影和所述第二时钟信号线GCB在所述衬底基板上的正投影之间。
上述设置方式使得所述第一时钟信号线GCK与所述第二时钟信号线GCB之间间隔较远，更好的屏蔽了所述第一时钟信号线GCK与所述第二时钟信号线GCB之间信号跳变带来的干扰。
如图24所示，在一些实施例中，所述第一电平信号线VGH，所述第一时钟信号线GCK，所述第二时钟信号线GCB，所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2中的至少一个采用所述显示基板中的第二源漏金属层制作。
示例性的，所述显示基板包括沿远离所述衬底基板的方向依次层叠设置于所述衬底基板上的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，层间绝缘层，第一源漏金属层，第一钝化层，第一平坦层，第二源漏金属层，第二钝化层，第二平坦层等。
示例性的，所述第一电平信号线VGH，所述第一时钟信号线GCK，所述第二时钟信号线GCB，所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2中的至少一个采用所述显示基板中位于第一源漏金属层背向衬底基板一侧的导电层制作。
设置上述信号线中的至少一个采用所述显示基板中的第二源漏金属层制作，不仅有利于降低信号线的压降，还能够避免信号线与其下方的电路结构发生短路，有效提升了显示基板的信赖性。
如图12所示，在一些实施例中，所述第一电平信号线VGH，所述第一时钟信号线GCK，所述第二时钟信号线GCB，所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2中的至少一个采用所述显示基板中的第一源漏金属层制作。
在一些实施例中，所述第一电平信号线VGH，所述第一时钟信号线GCK，所述第二时钟信号线GCB，所述第一帧起始信号线GSTV1和所述第二帧起始信号线GSTV2中的至少一个包括层叠设置的两层导电层，一层导电层采用所述第二源漏金属层制作，另一层导电层采用所述显示基板中的第三源漏金属层制作。
示例性的，所述显示基板还包括所述第三源漏金属层，所述第三源漏金属层位于所述第二源漏金属层背向所述衬底基板的一侧。
设置上述信号线中的至少一个包括层叠设置的两层导电层，一层导电层采用所述第二源漏金属层制作，另一层导电层采用所述显示基板中的第三源漏金属层制作，不仅有利于降低信号线的压降，还能够避免信号线与其下方的电路结构发生短路，有效提升了显示基板的信赖性。
如图18和图19所示，在一些实施例中，所述第一栅极驱动电路Gate1-GOA包括的输出晶体管的沟道宽长比等于所述第二栅极驱动电路Gate2-GOA包括的输出晶体管的沟道宽长比。
示例性的，所述输出晶体管包括第四晶体管T4和第五晶体管T5。
上述设置方式更有利于所述第一栅极驱动电路Gate1-GOA与第二栅极驱动电路Gate2-GOA实现镜像对称，有利于显示基板的窄边框化。
如图25所示，在一些实施例中，所述第一栅极驱动电路Gate1-GOA包括的输出晶体管的沟道宽长比大于所述第二栅极驱动电路Gate2-GOA包括的输出晶体管的沟道宽长比。
示例性的，所述第一栅极驱动电路Gate1-GOA包括的输出晶体管的沟道宽长比是所述第二栅极驱动电路Gate2-GOA包括的输出晶体管的沟道宽长比的1.25倍，1.5倍或者2.0倍，但不仅限于此。
上述将所述第一栅极驱动电路Gate1-GOA包括的输出晶体管的沟道宽长比和所述第二栅极驱动电路Gate2-GOA包括的输出晶体管的沟道宽长比做差异化设计，不仅能够同时兼容高频驱动模式和低频驱动模式，还能够进一步减小显示基板的边框宽度。
如图19所示，在一些实施例中，所述第一栅极驱动电路Gate1-GOA和所述第二栅极驱动电路Gate2-GOA中至少部分具有相同功能的目标器件相耦接。
示例性的，所述具有相同功能的目标器件包括第一晶体管T1，第七晶体管T7。所述第一栅极驱动电路Gate1-GOA中的第一晶体管T1的栅极与所述第二栅极驱动电路Gate2-GOA中的第一晶体管T1的栅极相耦接。所述第一栅极驱动电路Gate1-GOA中的第七晶体管T7的栅极与所述第二栅极驱动电路Gate2-GOA中的第七晶体管T7的栅极相耦接。
如图18和图19所示，所述具有相同功能的目标器件还包括第二电容C2，所述第一栅极驱动电路Gate1-GOA中的第二电容C2的第二极板C22与所述第二栅极驱动电路Gate2-GOA中的第二电容C2的第二极板C22相耦接，并打孔连接至第一电平信号线VGH。
上述设置方式有利于减小信号节点的走线长度，而且在共用信号时，可通过一个打孔实现与共用信号线之间的电连接，有利于简化电路结构。
如图2至图4所示，在一些实施例中，所述显示基板还包括多个第一子像素驱动电路，多个发光元件，多条数据线Vdata，多条第二初始化信号线VINIT2和多条第三初始化信号线VINIT3，所述第一子像素驱动电路包括第一 驱动晶体管T23，第一数据写入晶体管T24，第一补偿晶体管T22，第二复位晶体管T27和第三复位晶体管T28；
所述第一数据写入晶体管T24的栅极与对应的第一栅极驱动电路Gate1-GOA的输出端耦接，所述第一数据写入晶体管T24的第一极与对应的所述数据线Vdata耦接，所述第一数据写入晶体管T24的第二极与所述第一驱动晶体管T23的第一极耦接；
所述第一补偿晶体管T22的栅极与对应的第一栅极驱动电路Gate1-GOA的输出端耦接，所述第一补偿晶体管T22的第一极与所述第一驱动晶体管T23的第二极耦接，所述第一补偿晶体管T22的第二极与所述第一驱动晶体管T23的栅极耦接；
所述第二复位晶体管T27的栅极与对应的所述第二栅极驱动电路Gate2-GOA的输出端耦接，所述第二复位晶体管T27的第一极与对应的所述第二初始化信号线VINIT2耦接，所述第二复位晶体管T27的第二极与对应的发光元件耦接；
所述第三复位晶体管T28的栅极与对应的所述第二栅极驱动电路Gate2-GOA的输出端耦接，所述第三复位晶体管T28的第一极与对应的所述第三初始化信号线VINIT3耦接，所述第三复位晶体管T28的第二极与所述第一驱动晶体管T23的第一极耦接。
示例性的，所述显示基板还包括：多条第一初始化信号线VINIT1，多条第一扫描线Gate1，多条第二扫描线Gate2，多条复位线Reset，多条发光控制线，多条电源线VDD。所述子像素驱动电路包括8T1C电路结构。所述子像素驱动电路还包括：第一复位晶体管T21，第一电源控制晶体管T25和第一发光控制晶体管T26。
示例性的，所述第一初始化信号线VINIT1传输第一初始化信号，所述第二初始化信号线VINIT2传输第二初始化信号，所述第三初始化信号线VINIT3传输第三初始化信号，所述第一扫描线Gate1传输第一栅极驱动信号GOUT1，所述第二扫描线Gate2传输第二栅极驱动信号GOUT2，所述发光控制线传输发光控制信号EM，所述复位线Reset传输复位信号，所述电源线VDD传输电源信号。
所述第一复位晶体管T21的栅极与对应的所述复位线Reset耦接，所述第一复位晶体管T21的第一极与对应的第一初始化信号线VINIT1耦接，所述第一复位晶体管T21的第二极与所述第一驱动晶体管T23的栅极耦接。
所述第一电源控制晶体管T25的栅极与对应的所述发光控制线耦接，所述第一电源控制晶体管T25的第一极与对应的电源线VDD耦接，所述第一电源控制晶体管T25的第二极与所述第一驱动晶体管T23的第一极耦接。
所述第一发光控制晶体管T26的栅极与对应的所述发光控制线耦接，所述第一发光控制晶体管T26的第一极与所述第一驱动晶体管T23的第二极耦接，所述第一发光控制晶体管T26的第二极与对应的发光元件耦接。所述发光元件的阴极接收负电源信号VSS。
所述第一数据写入晶体管T24的栅极通过对应的第一扫描线Gate1与对应的第一栅极驱动电路Gate1-GOA的输出端耦接。
所述第一补偿晶体管T22的栅极通过对应的所述第一扫描线Gate1与对应的第一栅极驱动电路Gate1-GOA的输出端耦接。
所述第二复位晶体管T27的栅极通过对应的所述第二扫描线Gate2与对应的所述第二栅极驱动电路Gate2-GOA的输出端耦接。
所述第三复位晶体管T28的栅极通过对应的所述第二扫描线Gate2与对应的所述第二栅极驱动电路Gate2-GOA的输出端耦接。
如图5和图6所示，在一些实施例中，所述显示基板还包括多个第二子像素驱动电路，多个发光元件，多条数据线Vdata和多条第二初始化信号线VINIT2，所述第二子像素驱动电路包括第二驱动晶体管T33，第二数据写入晶体管T34，第二补偿晶体管T32和第二复位晶体管T27；
所述第二数据写入晶体管T34的栅极与对应的第二栅极驱动电路Gate2-GOA的输出端耦接，所述第二数据写入晶体管T34的第一极与对应的所述数据线Vdata耦接，所述第二数据写入晶体管T34的第二极与所述第二驱动晶体管T33的第一极耦接；
所述第二补偿晶体管T32的栅极与对应的第一栅极驱动电路Gate1-GOA的输出端耦接，所述第二补偿晶体管T32的第一极与所述第二驱动晶体管T33的第二极耦接，所述第二补偿晶体管T32的第二极与所述第二驱动晶体管T33 的栅极耦接；
所述第二复位晶体管T27的栅极与对应的所述第二栅极驱动电路Gate2-GOA的输出端耦接，所述第二复位晶体管T27的第一极与对应的所述第二初始化信号线VINIT2耦接，所述第二复位晶体管T27的第二极与对应的发光元件耦接。
示例性的，所述显示基板还包括：多条第一初始化信号线VINIT1，多条第一扫描线Gate1，多条第二扫描线Gate2，多条复位线Reset，多条发光控制线，多条电源线VDD。所述子像素驱动电路包括7T1C电路结构。所述子像素驱动电路还包括：第一复位晶体管T21，第一电源控制晶体管T25和第一发光控制晶体管T26。
示例性的，所述第一初始化信号线VINIT1传输第一初始化信号，所述第二初始化信号线VINIT2传输第二初始化信号，所述第一扫描线Gate1传输第一栅极驱动信号GOUT1，所述第二扫描线Gate2传输第二栅极驱动信号GOUT2，所述发光控制线传输发光控制信号EM，所述复位线Reset传输复位信号，所述电源线VDD传输电源信号。
所述第一复位晶体管T21的栅极与对应的所述复位线Reset耦接，所述第一复位晶体管T21的第一极与对应的第一初始化信号线VINIT1耦接，所述第一复位晶体管T21的第二极与所述第二驱动晶体管T33的栅极耦接。
所述第一电源控制晶体管T25的栅极与对应的所述发光控制线耦接，所述第一电源控制晶体管T25的第一极与对应的电源线VDD耦接，所述第一电源控制晶体管T25的第二极与所述第二驱动晶体管T33的第一极耦接。
所述第一发光控制晶体管T26的栅极与对应的所述发光控制线耦接，所述第一发光控制晶体管T26的第一极与所述第二驱动晶体管T33的第二极耦接，所述第一发光控制晶体管T26的第二极与对应的发光元件耦接。所述发光元件的阴极接收负电源信号VSS。
所述第二数据写入晶体管T34的栅极通过对应的第二扫描线Gate2与对应的第二栅极驱动电路Gate2-GOA的输出端耦接。
所述第二补偿晶体管T32的栅极通过对应的所述第一扫描线Gate1与对应的第一栅极驱动电路Gate1-GOA的输出端耦接。
所述第二复位晶体管T27的栅极通过对应的所述第二扫描线Gate2与对应的所述第二栅极驱动电路Gate2-GOA的输出端耦接。
采用上述7T1C结构的子像素驱动电路时，在高低频应用中，将第二补偿晶体管T32和第二数据写入晶体管T34的栅极驱动信号采用不同的栅极驱动电路提供，这时第二补偿晶体管T32连接的第一栅极驱动电路Gate1-GOA与第二数据写入晶体管T34连接的第二栅极驱动电路Gate2-GOA进行镜像设置，且除帧起始信号线以外的其他信号线均可以实现共用。
所述显示基板采用上述第一子像素驱动电路和所述第二子像素驱动电路时，均能够有效改善低频闪烁问题。
如图13至图17所示，在一些实施例中，所述显示基板还包括：
第一静电释放电路(包括第十三晶体管T13，第十四晶体管T14，第十五晶体管T15和第十六晶体管T16)，所述第一静电释放电路与所述第一栅极驱动电路Gate1-GOA耦接；
第二静电释放电路(包括第九晶体管T9，第十晶体管T10，第十一晶体管T11和第十二晶体管T12)，所述第二静电释放电路与所述第二栅极驱动电路Gate2-GOA耦接；
所述第一静电释放电路与所述第二静电释放电路呈镜像设置，所述第一静电释放电路与所述第二静电释放电路共用至少一条信号线。
上述实施例提供的显示基板中，通过设置所述第一静电释放电路与所述第二静电释放电路呈镜像设置，所述第一静电释放电路与所述第二静电释放电路共用至少一条信号线，更有利于显示基板的窄边框化。
在一些实施例中，所述第一静电释放电路与所述第二静电释放电路共用第一电平线VGH和/或第二电平线VGL。
如图26所示，在一些实施例中，所述周边区域还包括：
多个发光控制驱动电路EM-GOA，所述多个发光控制驱动电路EM-GOA划分为多组发光控制驱动电路EM-GOA，每组发光控制驱动电路EM-GOA包括呈镜像设置的两个所述发光控制驱动电路EM-GOA，该两个所述发光控制驱动电路EM-GOA共用至少一条信号线。
如图26所示，示例性的，共用的所述至少一条信号线包括：第一电平信 号线VGH，第三时钟信号线ECK和第四时钟信号线ECB中的至少一条信号线。
如图26所示，呈镜像设置的两个所述发光控制驱动电路EM-GOA中，一个发光控制驱动电路EM-GOA连接第三帧起始信号线ESTV1，另一个发光控制驱动电路EM-GOA连接第四帧起始信号线ESTV2。第三帧起始信号线ESTV1和第四帧起始信号线ESTV2能够独立控制。
示例性的，一个发光控制驱动电路EM-GOA可以用来控制图2或图5中的第一电源控制晶体管T25，另一个发光控制驱动电路EM-GOA可以用来控制图图2或图5中的第一电源控制晶体管T25。
示例性的，所述显示基板包括低温多晶硅氧化物显示基板。
值得注意，发光控制驱动电路EM-GOA可以采用如图27所示的电路结构，但不仅限于此。图27中示意了发光控制驱动电路EM-GOA包括第四十一晶体管T41，第四十二晶体管T42，第四十三晶体管T43，第四十四晶体管T44，第四十五晶体管T45，第四十六晶体管T46，第四十七晶体管T47，第四十八晶体管T48，第四十九晶体管T49，第五十晶体管T50，第三电容C3，第四电容C4，第五电容C5，以及发光控制驱动电路EM-GOA的输出端EOUT1。
本公开实施例还提供了一种显示装置，包括上述显示基板。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
上述实施例提供的显示基板中，通过设置显示基板包括多个第一栅极驱动电路和多个第二栅极驱动电路，有效改善了显示基板的低频闪烁问题。而且，通过设置所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线，有效缩小了第一栅极驱动电路和第二栅极驱动电路以及二者连接的信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
本公开实施例还提供了一种显示基板的制作方法，用于制作上述显示基板，所述制作方法包括：
制作多个第一栅极驱动电路和多个第二栅极驱动电路，所述第一栅极驱动电路输出的第一栅极驱动信号和所述第二栅极驱动电路输出的第二栅极驱动信号时序不同；所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线。
采用本公开实施例提供的显示基板中，通过设置显示基板包括多个第一栅极驱动电路和多个第二栅极驱动电路，有效改善了显示基板的低频闪烁问题。而且，通过设置所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线，有效缩小了第一栅极驱动电路和第二栅极驱动电路以及二者连接的信号线共同占用的边框宽度，不仅有利于显示基板的窄边框化，还有效减小了栅极驱动电路的功耗。
需要说明，信号线沿某方向延伸是指：信号线包括主要部分和与所述主要部分连接的次要部分，所述主要部分是线、线段或条形状体，所述主要部分沿某方向延展，且所述主要部分沿某方向延展的长度大于次要部分沿其它方向伸展的长度。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种显示基板，包括：多个第一栅极驱动电路和多个第二栅极驱动电路，所述第一栅极驱动电路输出的第一栅极驱动信号和所述第二栅极驱动电路输出的第二栅极驱动信号时序不同；所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板包括显示区域和包围所述显示区域的周边区域；所述多个第一栅极驱动电路和所述多个第二栅极驱动电路均位于所述周边区域；
    在靠近所述显示区域同一侧的周边区域中，所述第一栅极驱动电路的至少部分与所述第二栅极驱动电路的至少部分呈镜像设置。
  3. 根据权利要求2所述的显示基板，其中，所述第一栅极驱动电路和所述第二栅极驱动电路共用第一电平信号线，所述第一电平信号线传输具有第一电平的直流信号。
  4. 根据权利要求3所述的显示基板，其中，所述第一电平信号线在所述显示基板的衬底基板上的正投影的至少部分，位于所述第一栅极驱动电路在所述衬底基板上的正投影和所述第二栅极驱动电路在所述衬底基板上的正投影之间。
  5. 根据权利要求4所述的显示基板，其中，所述第一电平信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路在所述衬底基板上的正投影至少部分交叠；和/或，所述第一电平信号线在所述衬底基板上的正投影，与所述第二栅极驱动电路在所述衬底基板上的正投影至少部分交叠。
  6. 根据权利要求3所述的显示基板，其中，所述第一栅极驱动电路和所述第二栅极驱动电路共用第一时钟信号线和/或第二时钟信号线，所述第一时钟信号线传输的第一时钟信号和所述第二时钟信号线传输的第二时钟信号的相位相反。
  7. 根据权利要求6所述的显示基板，其中，所述第一栅极驱动电路的至少部分与所述第二栅极驱动电路的至少部分关于第一对称轴呈镜像对称；所述第一对称轴与所述第一时钟信号线至少部分交叠，或者所述第一对称轴与 所述第二时钟信号线至少部分交叠，或者所述第一对称轴与所述第一电平信号线至少部分交叠。
  8. 根据权利要求6所述的显示基板，其中，所述第一电平信号线在所述衬底基板上的正投影，位于所述第一时钟信号线在所述衬底基板上的正投影和所述第二时钟信号线在所述衬底基板上的正投影之间。
  9. 根据权利要求6所述的显示基板，其中，所述第一时钟信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路和所述第二栅极驱动电路中的一种在所述衬底基板上的正投影至少部分交叠；所述第二时钟信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路和所述第二栅极驱动电路中的另一种在所述衬底基板上的正投影至少部分交叠。
  10. 根据权利要求6所述的显示基板，其中，所述第一栅极驱动电路耦接第一帧起始信号线，所述第二栅极驱动电路耦接第二帧起始信号线。
  11. 根据权利要求10所述的显示基板，其中，所述第一电平信号线在所述衬底基板上的正投影，位于所述第一帧起始信号线在所述衬底基板上的正投影和所述第二帧起始信号线在所述衬底基板上的正投影之间。
  12. 根据权利要求10所述的显示基板，其中，所述第一帧起始信号线在所述衬底基板上的正投影，与所述第一栅极驱动电路在所述衬底基板上的正投影至少部分交叠；所述第二帧起始信号线在所述衬底基板上的正投影，与所述第二栅极驱动电路在所述衬底基板上的正投影至少部分交叠。
  13. 根据权利要求10所述的显示基板，其中，所述第一帧起始信号线在所述衬底基板上的正投影和所述第二帧起始信号线在所述衬底基板上的正投影，位于所述第一时钟信号线在所述衬底基板上的正投影和所述第二时钟信号线在所述衬底基板上的正投影之间。
  14. 根据权利要求10所述的显示基板，其中，所述第一电平信号线，所述第一时钟信号线，所述第二时钟信号线，所述第一帧起始信号线和所述第二帧起始信号线中的至少一个采用所述显示基板中的第二源漏金属层制作。
  15. 根据权利要求14所述的显示基板，其中，所述第一电平信号线，所述第一时钟信号线，所述第二时钟信号线，所述第一帧起始信号线和所述第二帧起始信号线中的至少一个包括层叠设置的两层导电层，一层导电层采用 所述第二源漏金属层制作，另一层导电层采用所述显示基板中的第三源漏金属层制作。
  16. 根据权利要求1所述的显示基板，其中，所述第一栅极驱动电路包括的输出晶体管的沟道宽长比等于所述第二栅极驱动电路包括的输出晶体管的沟道宽长比。
  17. 根据权利要求1所述的显示基板，其中，所述第一栅极驱动电路包括的输出晶体管的沟道宽长比大于所述第二栅极驱动电路包括的输出晶体管的沟道宽长比。
  18. 根据权利要求1所述的显示基板，其中，所述第一栅极驱动电路和所述第二栅极驱动电路中至少部分具有相同功能的目标器件相耦接。
  19. 根据权利要求1所述的显示基板，其中，所述显示基板还包括多个第一子像素驱动电路，多个发光元件，多条数据线，多条第二初始化信号线和多条第三初始化信号线，所述第一子像素驱动电路包括第一驱动晶体管，第一数据写入晶体管，第一补偿晶体管，第二复位晶体管和第三复位晶体管；
    所述第一数据写入晶体管的栅极与对应的第一栅极驱动电路的输出端耦接，所述第一数据写入晶体管的第一极与对应的所述数据线耦接，所述第一数据写入晶体管的第二极与所述第一驱动晶体管的第一极耦接；
    所述第一补偿晶体管的栅极与对应的第一栅极驱动电路的输出端耦接，所述第一补偿晶体管的第一极与所述第一驱动晶体管的第二极耦接，所述第一补偿晶体管的第二极与所述第一驱动晶体管的栅极耦接；
    所述第二复位晶体管的栅极与对应的所述第二栅极驱动电路的输出端耦接，所述第二复位晶体管的第一极与对应的所述第二初始化信号线耦接，所述第二复位晶体管的第二极与对应的发光元件耦接；
    所述第三复位晶体管的栅极与对应的所述第二栅极驱动电路的输出端耦接，所述第三复位晶体管的第一极与对应的所述第三初始化信号线耦接，所述第三复位晶体管的第二极与所述第一驱动晶体管的第一极耦接。
  20. 根据权利要求1所述的显示基板，其中，所述显示基板还包括多个第二子像素驱动电路，多个发光元件，多条数据线和多条第二初始化信号线，所述第二子像素驱动电路包括第二驱动晶体管，第二数据写入晶体管，第二 补偿晶体管和第二复位晶体管；
    所述第二数据写入晶体管的栅极与对应的第二栅极驱动电路的输出端耦接，所述第二数据写入晶体管的第一极与对应的所述数据线耦接，所述第二数据写入晶体管的第二极与所述第二驱动晶体管的第一极耦接；
    所述第二补偿晶体管的栅极与对应的第一栅极驱动电路的输出端耦接，所述第二补偿晶体管的第一极与所述第二驱动晶体管的第二极耦接，所述第二补偿晶体管的第二极与所述第二驱动晶体管的栅极耦接；
    所述第二复位晶体管的栅极与对应的所述第二栅极驱动电路的输出端耦接，所述第二复位晶体管的第一极与对应的所述第二初始化信号线耦接，所述第二复位晶体管的第二极与对应的发光元件耦接。
  21. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    第一静电释放电路，所述第一静电释放电路与所述第一栅极驱动电路耦接；
    第二静电释放电路，所述第二静电释放电路与所述第二栅极驱动电路耦接；
    所述第一静电释放电路与所述第二静电释放电路呈镜像设置，所述第一静电释放电路与所述第二静电释放电路共用至少一条信号线。
  22. 根据权利要求1所述的显示基板，其中，所述周边区域还包括：
    多个发光控制驱动电路，所述多个发光控制驱动电路划分为多组发光控制驱动电路，每组发光控制驱动电路包括呈镜像设置的两个所述发光控制驱动电路，该两个所述发光控制驱动电路共用至少一条信号线。
  23. 一种显示装置，包括如权利要求1～22中任一项所述的显示基板。
  24. 一种显示基板的制作方法，用于制作如权利要求1～22中任一项所述的显示基板，所述制作方法包括：
    制作多个第一栅极驱动电路和多个第二栅极驱动电路，所述第一栅极驱动电路输出的第一栅极驱动信号和所述第二栅极驱动电路输出的第二栅极驱动信号时序不同；所述第一栅极驱动电路和所述第二栅极驱动电路共用至少一条信号线。
PCT/CN2022/102741 2022-06-30 2022-06-30 显示基板及其制作方法、显示装置 WO2024000376A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120139881A1 (en) * 2010-12-06 2012-06-07 Samsung Electronics Co., Ltd. Display substrate, method of manufacturing the same, and display apparatus having the same
CN111986607A (zh) * 2020-08-19 2020-11-24 武汉华星光电技术有限公司 显示面板及显示装置
CN112449712A (zh) * 2019-07-01 2021-03-05 京东方科技集团股份有限公司 显示面板及其显示驱动方法、显示装置
CN113471225A (zh) * 2021-09-03 2021-10-01 北京京东方技术开发有限公司 显示基板和显示面板
CN114299848A (zh) * 2021-12-30 2022-04-08 武汉天马微电子有限公司 显示面板及显示装置

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Publication number Priority date Publication date Assignee Title
US20120139881A1 (en) * 2010-12-06 2012-06-07 Samsung Electronics Co., Ltd. Display substrate, method of manufacturing the same, and display apparatus having the same
CN112449712A (zh) * 2019-07-01 2021-03-05 京东方科技集团股份有限公司 显示面板及其显示驱动方法、显示装置
CN111986607A (zh) * 2020-08-19 2020-11-24 武汉华星光电技术有限公司 显示面板及显示装置
CN113471225A (zh) * 2021-09-03 2021-10-01 北京京东方技术开发有限公司 显示基板和显示面板
CN114299848A (zh) * 2021-12-30 2022-04-08 武汉天马微电子有限公司 显示面板及显示装置

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