WO2023280474A1

WO2023280474A1 - Transmission module and method for transmitting differential signals in a serial bus system

Info

Publication number: WO2023280474A1
Application number: PCT/EP2022/064764
Authority: WO
Inventors: Steffen Walker; Felix Lang
Original assignee: Robert Bosch Gmbh
Priority date: 2021-07-08
Filing date: 2022-05-31
Publication date: 2023-01-12
Also published as: CN117957818A; DE102021207199A1

Abstract

A transmission module (121; 1210) and a method for transmitting differential signals in a serial bus system (1) are provided. The transmission module (121; 1210) has a first transmission stage (121A; 121A0) for generating transmission currents (I1 to ln) for a first signal (CAN_H) that is to be transmitted onto a bus (40) of the bus system (1), a second transmission stage (121B; 121B0) for generating transmission currents (I1 to ln) for a second signal (CAN_L) that is to be transmitted, as a differential signal with respect to the first signal (CAN_H), onto the bus (40), a third transmission stage (121C; 121C0) for generating transmission currents (I1 to ln) for the first signal (CAN_H), and a fourth transmission stage (121D; 121D0) for generating transmission currents (I1 to ln) for the second signal (CAN_L), wherein the first to fourth transmission stages (121A to 121D; 121A0 to 121D0) are connected in a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A0, 121D0) are connected in series and the third and second transmission stages (121C, 121B; 121C0, 121B0) are connected in series, wherein each of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0) has at least two current stages (S1 to Sn) that are connected in parallel, wherein each of the at least two current stages (S1 to Sn) has a switchable resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and wherein the switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of a transmission stage (121A to 121D; 121A0 to 121D0) have different resistances.

Description

description

title

Transmission module and method for transmitting differential signals in a serial bus system

The present invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, which can be used in particular for CAN XL.

State of the art

Serial bus systems are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control devices in a vehicle or a technical production facility, etc. There are various standards or data transmission protocols for data transmission. In particular, a CAN bus system, an LVDS bus system (LVDS=Low Voltage Differential Signaling), an MSC bus system (MSC=Micro Second Channel), and a 10BASE-T1S Ethernet are known.

In a CAN bus system, messages are transmitted using the CAN and/or CAN FD protocol, as described in the ISO-11898-1:2015 standard as a CAN protocol specification with CAN FD. With CAN FD, during transmission on the bus, there is a switch back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). With a CAN FD bus system, a data transmission rate of more than 1 MBit per second (1Mbps) is possible in the second communication phase. CAN FD becomes used by most manufacturers in the first step with 500kbit/s arbitration bit rate and 2Mbit/s data bit rate in the vehicle.

In order to enable even higher data rates in the second communication phase, there are successor bus systems for CAN FD, such as CANSIC and CAN XL. With CANSIC according to the CiA601-4 standard, a data rate of around 5 to 8 Mbit/s can be achieved in the second communication phase. With CAN XL, a data rate of > 10 Mbit/s is required in the second communication phase, whereby the standard (CiA610-3) for this is currently being defined by the CAN in Automation (CiA) organization. In addition to pure data transport via the CAN bus, CAN XL should also support other functions such as functional safety (safety), data security (security) and quality of service (QoS = Quality of Service). These are elementary properties that are required in an autonomously driving vehicle.

In all of the above-mentioned CAN-based bus systems, a bus signal CAN_H and ideally a bus signal CAN_L are driven onto a bus separately for a transmission signal TxD. In this case, at least in the first communication phase, a bus state is actively driven in the bus signals CAN_H, CAN_L. The other bus state is not driven and is set due to a terminating resistor for bus lines or bus cores of the bus. As a result of the differently driven states, the signal forms of the bus signals CAN_H, CAN_L can deviate from the ideal signal form in a real bus system. The reasons for this lie in particular in the bus system design, such as stub lines, switching delays in the switching stages for bus signals CAN_H, CAN_L, etc. Such mismatches in the two bus signals CAN_H, CAN_L can lead to errors in the evaluation of the bus signals received from the bus.

In order to send and receive the bus signals, transceivers, which are also referred to as CAN transceivers or CAN FD transceivers, etc., are usually used in a CAN bus system for the individual communication participants. The CAN transceivers or CAN FD transceivers must not be allowed to transmit or

Emission does not exceed the limit values for operation in the vehicle. Tranceivers for CAN XL must comply with even more stringent limit values that are specified in the IEC62228-3 standard. This is the only way to operate the bus system at the specified higher bit rates than with CAN FD and CAN SIC. Depending on the semiconductor technology available, compliance with these strict limits poses a major challenge.

Compared to CAN FD, transceivers for CAN SIC or transceivers for CAN XL must have a third state in the arbitration phase, which is also called SIC mode or SIC operating mode, in addition to the states recessive (rec) and dominant (dom). , the state sic, are generated. In order to meet the emission requirements of the IEC62228-3 standard, a common mode voltage of the bus lines for the CAN_H, CAN_L signals must be kept within narrow limits in three transmission states, namely recessive, dominant, sic. The common-mode voltage is generated across a common-mode choke, which is used in particular in a certification measurement to check compliance with the IEC62228-3 standard. The common mode choke is also called common mode choke (CMC). The task of the common-mode choke is to allow differential signals (DM=differential mode) to pass without being influenced and to suppress common-mode signals (CM=common mode) as completely as possible. However, in real operation, the common-mode choke generates a differential signal with an undesired common-mode signal superimposed on it at the output from a differential signal without a common-mode component at the input. This is unfavorable since this is fed directly into the CAN bus on the bus side and is visible to other CAN modules.

Disclosure of Invention

It is therefore the object of the present invention to provide a transmission module and a method for transmitting differential signals in a serial bus system which solve the aforementioned problems. In particular, the transmission module and the method for sending differential signals in a serial bus system are intended to allow compensation for disturbance variables that affect the emission behavior of the transmission module. The object is achieved by a transmission module for sending differential signals in a serial bus system having the features of claim 1. The transmission module has a first transmission stage for generating transmission currents for a first signal that is to be sent to a bus of the bus system, a second transmission stage for generating transmission currents for a second signal that is applied to the bus as a signal that is different from the first signal is to send, a third transmission stage for generating transmission currents for the first signal, and a fourth transmission stage for generating transmission currents for the second signal, the first to fourth transmission stages being connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, each of the first to fourth transmission stages having at least two current stages which are connected in parallel with one another, each of the at least two current stages having a switchable resistor, and the switchable resistors of a transmitter stage having different resistance values to have.

The transmission module described enables the required limit values for the emission of a transmission/reception device for CAN XL to be achieved. In particular, the transmitter module meets the IEC62228-3 standard, which defines the limit values to be observed for the bus states dom, sic and rec.

For example, in the sic state, the transmission module can adapt the impedance between the bus lines for the signals CAN_H and CAN_L very well to the characteristic characteristic impedance or impedance of the bus line used. For the impedance Zw of the bus line used, Zw = 1000hm or Zw = 1200hm applies. As a result, the transmitter module prevents reflections and thus allows operation in the bus system at higher bit rates.

By dividing its four transmission stages into n parts, the transmission module described permits a chronologically staggered and controlled switching process. Switching on according to the Gaussian error function can be implemented here. This enables a soft behavior to be set during the switch-on process. In addition, the possible variation of time stages when switching on prevents the occurrence of a narrow-band frequency line in the emission frequency spectrum. Alternatively, it is possible to carry out a staggered and controlled switching process using fixed time steps and varied voltage steps with the transmission module described. This can also influence the emission behavior of the transmission module in such a way that the specified limit values are complied with.

In addition, the transmission module described can reduce effects due to asymmetrical behavior of the transmission stages, which can occur in the transmission states dom, sic, rec and worsen the emission. The transmit module prevents unequal behavior of components in transmit stages A, B (effect 1) of a full bridge, so that in the dom state a change in the common-mode voltage is minimized or prevented compared to the rec state. In addition, the transmit module can prevent unequal behavior of components in transmit stages A/D and C/B of the full bridge (Effect 2), so that in the sic state, a change in the common-mode voltage is minimized or prevented compared to the rec state will. This is particularly advantageous since an adequate emission result can only be achieved if, starting from the common mode level of the rec state, the common levels in the dom state and in the sic state match those of the rec state, however, the causes , which lead to the behavior of effect 1 can be different than those lead to effect 2.

Advantageous further configurations of the transmission module are described in the dependent claims.

The output connections of the full bridge can be provided for connection to a terminating resistor of the bus.

A number n of the at least two current stages may be the same for each of the first to fourth transmission stages, where n is a natural number greater than 1.

In one configuration, each of the at least two current stages has a CMOS transistor for switching the resistance of the current stage. According to one embodiment, the CMOS transistor of the current stages of the first transmission stage is a PMOS transistor, the CMOS transistor of the current stages of the second transmission stage being an NMOS transistor, the CMOS transistor of the current stages of the third transmission stage being a PMOS transistor, and wherein the CMOS transistor of the current stages of the fourth transmit stage is an NMOS transistor.

Each of the first to fourth transmission stages can also have a polarity reversal diode to protect against positive feedback in a connection for the bus voltage supply and negative feedback from a connection for ground, and at least one cascode to protect the CMOS transistors.

According to another exemplary embodiment, at least two cascodes are connected in parallel with one another, with a number y of the cascodes being the same for each of the first to fourth transmission stages, with y being a natural number greater than 1, and with the on-resistance of the at least two cascodes being different.

The transmission module can also have at least a first current-limiting module as a current source, which is connected between a connection for the bus voltage supply and the full bridge, and at least a second current-limiting module as a current sink, which is connected between a connection for ground and the full bridge.

According to one embodiment, at least two first current-limiting modules are connected in parallel to one another, the on-resistance of which is different, with at least two second current-limiting modules being connected in parallel to one another, the on-resistance of which is different, and the number x of the first current-limiting modules is equal to the number x of the second current-limiting modules, where x is a natural number greater than 1.

The transmission module can also have a control circuit for controlling switchable components of the first to fourth transmission stage depending on a digital transmission signal and an operating mode set for the transmission module. The drive circuit may be designed for the time-staggered and controlled switching of the resistance values of the at least two current stages.

The transmission module described above can be part of a transmission/reception device for a subscriber station for a serial bus system, which also has a reception module for receiving signals from the bus.

The transmitting/receiving device can be part of a subscriber station for a serial bus system, which also has a communication control device for controlling communication in the bus system and for generating a digital transmission signal for driving the first to fourth transmission stages.

The subscriber station may be designed for communication in a bus system in which exclusive, collision-free access by a subscriber station to the bus of the bus system is guaranteed at least temporarily.

The aforementioned object is also achieved by a method for sending differential signals in a serial bus system having the features of claim 15. The method is carried out with a transmission module, the method having the steps of generating, with a first transmission stage, transmission streams for a first signal that is to be sent to a bus of the bus system, generating with a second transmission stage, transmission streams for a second signal, which is to be sent to the bus as a signal that is differential with respect to the first signal, generating, with a third transmission stage, transmission currents for the first signal, and generating, with a fourth transmission stage, transmission currents for the second signal, the first to fourth transmission stages are connected in a full bridge, in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, each of the first to fourth transmission stages having at least two current stages connected in parallel with one another, wherein each of the at least two current stages has a switchable resistor, and where the switchable resistors of a transmission stage have different resistance values.

The method offers the same advantages as those mentioned above with regard to the transmission module.

Further possible implementations of the invention also include combinations of features or embodiments described above or below with regard to the exemplary embodiments that are not explicitly mentioned. The person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

drawings

The invention is described in more detail below with reference to the attached drawing and using exemplary embodiments. Show it:

1 shows a simplified block diagram of a bus system according to a first exemplary embodiment;

2 shows a diagram to illustrate the structure of a message that can be sent by a subscriber station of the bus system according to the first exemplary embodiment;

FIG. 3 shows an example of the ideal time profile of bus signals CAN_H, CAN_L in the bus system of FIG. 1;

FIG. 4 shows the time profile of a differential voltage VDIFF which forms on the bus of the bus system as a result of the bus signals from FIG. 4;

5 shows an example of a time profile of a digital transmission signal which is to be converted into bus signals CAN_H, CAN_L for a bus of the bus system of FIG. 1 in the arbitration phase (SIC operating mode); 6 shows the time profile of the bus signals CAN_H, CAN_L when changing from a recessive bus state to a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase (SIC operating mode) on the basis of the transmission signal from FIG. 5;

FIG. 7 shows an example of a time profile of a digital transmission signal which is to be converted in the data phase into bus signals CAN_H, CAN_L for the bus of the bus system from FIG. 1;

FIG. 8 shows the time course of the bus signals CAN_H, CAN_L, which are sent to the bus in the data phase on the basis of the transmission signal from FIG. 6;

9 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to the first exemplary embodiment;

FIG. 10 is a timing diagram showing the turn-on of various power stages of a transmit stage for a first specific example of the transmit module of FIG. 9;

Figure 11 shows a detail of a transmission stage for a second specific example of the transmission module of Figure 9; and

12 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to a second exemplary embodiment.

In the figures, elements that are the same or have the same function are provided with the same reference symbols unless otherwise stated.

Description of the exemplary embodiments

1 shows a bus system 1 which, for example, can be a CAN bus system, a CAN FD bus system, etc., at least in sections. The bus system 1 can be used in a vehicle, particularly an automobile, an airplane, etc., or in a hospital, etc.

In FIG. 1, the bus system 1 has a large number of subscriber stations 10, 20, 30, which are each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus cores 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46, 47 in the form of signals can be transmitted between the individual subscriber stations 10, 20, 30 via the bus 40. The subscriber stations 10, 20, 30 can be, for example, control devices or display devices of a motor vehicle.

As shown in Fig. 1, the subscriber stations 10, 30 each have a communication control device 11 and a transceiver 12. The transceiver 12 has a transmit module 121 and a receive module 122.

Subscriber station 20 has a communication control device 21 and a transceiver 22. Transceiver 22 has a transmit module 221 and a receive module 222.

The transmitting/receiving devices 12 of the subscriber stations 10, 30 and the transmitting/receiving device 22 of the subscriber station 20 are each connected directly to the bus 40, even if this is not shown in FIG.

The communication control devices 11, 21 are each used to control communication between the respective subscriber station 10, 20, 30 via the bus 40 and at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

The communication control devices 11 create and read first messages 45, 47, which are modified CAN messages 45, 47, for example. In this case, the modified CAN messages 45, 47 are constructed, for example, on the basis of the CAN SIC format or the CAN XL format. The transceiver 12 is used to send and receive the Messages 45, 47 from the bus. The transmission module 121 receives a digital transmission signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this into signals on the bus 40. The reception module 121 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them.

The reception module 122 sends the reception signal RxD to the communication control device 11.

The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, i.e. like a CAN FD tolerant Classical CAN controller or a CAN FD controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages 46. The transceiver 22 is used to send and receive the messages 46 from the bus 40. The transmission module 221 receives a digital transmission signal TxD and created by the communication control device 21 converts this into signals for a message 46 on the bus 40. The reception module 221 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them. Otherwise, the transceiver 22 can be designed like a conventional CAN transceiver.

For sending the messages 45, 47 with CAN XL or CAN SIC, proven properties are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular frame structure with identifier and arbitration according to the known CSMA/CR method. The consequence of the CSMA/CR method is that there must be so-called recessive states on the bus 40 which can be overwritten by other subscriber stations 10, 20, 30 with dominant levels or dominant states on the bus 40.

The two subscriber stations 10, 30 can be used to form and then transmit messages 45 with different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, and to receive such messages 45, as described in more detail below. 2 shows a frame 450 for the message 45, which is in particular a CAN XL frame, as is provided by the communication control device 11 for the transceiver 12 for transmission onto the bus 40. Here, in the present exemplary embodiment, the communication control device 11 creates the frame 450 as compatible with CAN FD. Alternatively, the frame 450 is compatible with CAN SIC.

According to FIG. 2, the frame 450 for the CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a data field 455, a checksum field 456 and a frame termination field 457.

In the arbitration phase 451, an identifier (ID) with, for example, bits ID28 to ID18 in the arbitration field 453 is used to negotiate bit by bit between the subscriber stations 10, 20, 30 as to which subscriber station 10, 20, 30 is sending the message 45, 46 with the highest priority wants and therefore gets exclusive access to the bus 40 of the bus system 1 for the next time for sending in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).

An important point during phase 451 is that the known CSMA/CR method is used, which allows subscriber stations 10, 20, 30 to access the bus 40 simultaneously without the higher-priority message 45, 46 being destroyed. As a result, further bus subscriber stations 10, 20, 30 can be added to the bus system 1 relatively easily, which is very advantageous.

The consequence of the CSMA/CR method is that there must be so-called recessive states on the bus 40 which are detected by other subscriber stations 10, 20,

30 can be overwritten with dominant levels or dominant states on the bus 40. In the recessive state prevail at the individual subscriber stations 10, 20, 30 have high-impedance conditions, which, in combination with the parasites of the bus wiring, results in longer time constants. This leads to a limitation of the maximum bit rate of today's CAN FD physical layer to around 2 megabits per second in real vehicle use.

In the data phase 452, in addition to part of the control field 454, the user data of the CAN-XL frame 450 or the message 45 from the data field 455 and the checksum field 456 are sent. A checksum over the data of the data phase 452 including the stuff bits can be contained in the checksum field 456, which the sender of the message 45 inserts as an inverse bit after a predetermined number of identical bits, in particular 10 identical bits. At the end of the data phase 452, the arbitration phase 451 is switched back to.

At least one acknowledge bit may be included in an end field in the frame completion phase 457 . There may also be a sequence of 11 same bits indicating the end of the CAN XL frame 450. The at least one acknowledge bit can be used to communicate whether a receiver has discovered an error in the received CAN XL frame 450 or the message 45 or not.

A sender of the message 45 does not start sending bits of the data phase 452 to the bus 40 until the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending .

Thus, in the arbitration phase 451, the subscriber stations 10, 30 partially use a format known from CAN/CAN-FD in accordance with ISO11898-1:2015 as the first communication phase, in particular up to the FDF bit (inclusive). However, compared to CAN or CAN FD in the data phase 452 as the second communication phase, the net data transmission rate can be increased, in particular to more than 10 megabits per second. In addition, it is possible to increase the size of the user data per frame, in particular to around 2 kbyte or any other value. 3 shows on the left side that the subscriber stations 10, 20, 30 send signals CAN_H, CAN_L to the bus 40 in the arbitration phase 451, which alternately have at least one dominant state 401 or at least one recessive state 402. After the arbitration in the arbitration phase 451, one of the subscriber stations 10, 20, 30 is the winner. Assume that subscriber station 10 has won the arbitration. Then the transceiver 12 of the subscriber station 10 switches its physical layer at the end of the arbitration phase 451 from a first operating mode (SLOW) to a second operating mode (FAST_TX), since the subscriber station 10 is the sender of the message 45 in the data phase 452. In the data phase 452 or in the second operating mode (FAST_TX), the transmission module 121 then generates the states L0 or LI for the signals CAN_H,

CAN_L on the bus 40. The frequency of the signals CAN_H, CAN_L may be increased in the data phase 452 as shown on the right side in FIG. Thus, the net data transfer rate in the data phase 452 is increased compared to the arbitration phase 451. In contrast, the transceiver 12 of the subscriber station 30 switches its physical layer at the end of the arbitration phase 451 from the first mode (SLOW) to a third mode (FAST_RX), since the subscriber station 30 in the data phase 452 only receives, i.e. no transmitter, of the frame is 450. After the end of the arbitration phase 451, all transmitting/receiving devices 12 of the subscriber stations 10, 30 switch their operating mode to the first operating mode (SLOW). Thus, all transceivers 12 also switch their physical layer.

4 forms in the arbitration phase 451 in the ideal case on the bus 40, a difference signal VDIFF = CAN_H - CAN_L with values of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402. This is on the left side in 4 shown. In contrast, a differential signal VDIFF=CAN_H−CAN_L with states L0, LI is formed on bus 40 in data phase 452, as shown on the right-hand side in FIG. State L0 has a value VDIFF = IV. State LI has a value VDIFF = -IV. The receiving module 122 can distinguish between the states 401, 402 and L0, LI with the receiving thresholds that are in the ranges TH_T1, TH_T2, TH_T3. The receiving module uses 122 at least the reception threshold TI of, for example, 0.7 V in the arbitration phase 451. The reception module 122 uses the reception threshold T2 of, for example, -0.35 V, for example in the arbitration phase 451, but possibly also in the data phase 452. The reception threshold T3 of, for example, 0, 0V is used in the data phase 452. When switching between the first to third operating modes (SLOW, FAST_TX, FAST_RX), which are described above with reference to FIG. 3 , the receiving module 122 switches the receiving thresholds in each case.

5 shows an example of a part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451 and generates the signals CAN_H, CAN_L for the bus 40 therefrom. In FIG. 5, the transmission signal TxD changes from a state LW (low=low) to a state H1 (high=high) and back to the state LW (low=low).

As shown in more detail in FIG. 6, the transmission module 121 for the transmission signal TxD from FIG. 5 generates the signals CAN_H, CAN_L for the bus cores 41, 42 in such a way that a state 403 (sic) is also present. State 403 (sic) can have different lengths, as shown with state 403_0 (sic) when transitioning from state 402 (rec) to state 401 (dom) and state 403_1 (sic) when transitioning from state 401 ( dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic). In order to generate signals according to FIG. 6, the transmission module 121 is switched to a SIC operating mode (SIC mode).

Going through the short sic state 403_0 is not required in CiA610-3 and the state depends on the type of implementation. The duration of the "long" state 403_1 (sic) is specified for CAN-SIC as well as for the SIC operating mode in CAN-XL as t_sic < 530ns, beginning with the rising edge on the transmit signal TxD of Fig. 5.

In the “long” state 403_1 (sic), the transmission module 121 should match the impedance between the bus cores 41 (CANH) and 42 (CANL) as well as possible to the characteristic wave impedance Zw of the bus line used. Zw=1000hm or 1200hm applies here. This adjustment prevents reflections and thus allows operation at higher bit rates. For the sake of simplicity, the term 403 (sic) or sic state 403 is always used below. The transmission module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL.

Table 1: CAN_Typen for transmission module 121 Thus, the transmission module status can be seen not only with CAN-SIC or CAN-XL

(xl_sic) are generated. The transmission module status sic can also be generated with CAN FD. In CAN-FD, however, the time for the transmit module status sic can be shorter than in CAN-SIC or CAN-XL. 7 shows an example of another part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the data phase 452 and generates the signals CAN_H, CAN_L for the bus 40 therefrom. In FIG. 7, the transmission signal TxD changes several times from state HI (high=high) to state LW (low=low) and again to state HI (high=high) and so on.

As shown in more detail in FIG. 8, the transmission module 121 generates the signals CAN_H, CAN_L for the bus cores 41, 42 for the transmission signal TxD from FIG the LO state develops for a LW (low = low) state. In addition, the state LI forms for a state H1 (high=high).

Fig. 9 shows the basic structure of the transmission module 121 for one of the subscriber stations 10, 30. The transmission module 12 can signals CAN_H, CAN_L according to FIG. 5 with the states 401, 402, 403 and signals CAN_H, CAN_L according to FIG. 8 with the states Generate LO, LI.

The transmission module 121 has four transmission stages, namely a first transmission stage 121A, a second transmission stage 121B, a third transmission stage 121C and a fourth transmission stage 121D. As shown in FIG. 9, the transmission stages 121A to 121D are connected as a full bridge. In addition, the transmission module 121 has current-limiting modules 1211, 1212. The current-limiting modules 1211, 1212 and components of the transmission stages 121 A to 121 D, which are described in more detail below, are controlled via at least one control device 124. At least one control device 124 sends at least one signal to control connections 125, to to which the current-limiting modules 1211, 1212 and/or the components of the transmission stages 121A to 121D are connected. For the sake of clarity, not all line connections for this are shown in FIG.

The transmission module 121 is connected to the bus 40, more precisely its first bus wire 41 for CAN_H or CAN-XL_H and its second bus wire 42 for CAN_L or CAN-XL_L. Each of the transmission stages 121A to 121D is connected to the bus 40.

The power supply for supplying the first and second bus wires 41, 42 with electrical energy, in particular with the CAN supply voltage of usually 5V, takes place via at least one connection 43. The connection to ground or CAN_GND is implemented via a connection 44.

The first and second bus wires 41, 42 are terminated with a terminating resistor 49. The terminating resistor 49 is connected to the full bridge as an external load resistor. The resistor 49 is connected in the bridge branch between the connections for the bus wires 41, 42. The first transmission stage 121A of FIG. 9 has a polarity reversal diode D_A, a transistor HVP_A and a parallel circuit 121A1 in which a first through n-th current stage are connected in parallel, where n is a natural number >1. A control circuit T_A is also present. The first current stage has a series connection of a resistor R_A1 and a transistor P_A1. The nth current stage has a series circuit made up of a resistor R_An and a transistor P_An. The transistor HVP_A can be a CMOS transistor, in particular a PMOS transistor. The transistors P_A1 to P_An are CMOS transistors, in particular PMOS transistors. The acronym "CMOS" denotes a semiconductor device that uses both p-channel and n-channel MOSFETs on a common substrate. The abbreviation CMOS stands for the English term "Complementary metal-oxide-semiconductor", which means "complementary / complementary metal-oxide-semiconductor". The abbreviation "MOSFET" stands for metal oxide field effect transistor. The control circuit T_A controls the transistors P_A1 to P_An of the first to the nth current stage in accordance with the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121 .

The second transmission stage 121B of FIG. 9 has a polarity reversal diode D_B, a transistor HVN_B and a parallel circuit 121B1 in which a first to n-th current stage is connected in parallel, where n is the natural number>1. A control circuit T_B is also present. The first current stage S1 has a series circuit made up of a resistor R_B1 and a transistor N_B1. The nth current stage has a series connection of a resistor R_Bn and a transistor N_Bn. The transistor HVP_B can be a CMOS transistor, in particular an NMOS transistor. The transistors N_B1 to N_Bn are CMOS transistors, in particular NMOS transistors. The control circuit T_B controls the transistors N_B1 to N_Bn of the first to the nth current stage according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121 .

The third transmission stage 121C of FIG. 9 has a polarity reversal diode D_C, a transistor HVP_C and a parallel circuit 121C1 in which a first through n-th current stage are connected in parallel, where n is the natural number>1. A control circuit T_C is also present. The first power stage has a Series connection of a resistor R_C1 and a transistor P_C1. The nth current stage has a series circuit made up of a resistor R_An and a transistor P_An. The transistor HVP_C can be a CMOS transistor, in particular a PMOS transistor. The transistors P_C1 to P_Cn are CMOS transistors, in particular PMOS transistors. The control circuit T_C controls the transistors P_C1 to P_Cn of the first to the nth current stage in accordance with the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121 .

The fourth transmission stage 121D of FIG. 9 has a polarity reversal diode D_D, a transistor HVN_D and a parallel circuit 121D1 in which a first to n-th current stage is connected in parallel, where n is the natural number>1. A control circuit T_D is also present. The first current stage has a series connection of a resistor R_D1 and a transistor N_D1. The nth current stage has a series connection of a resistor R_Dn and a transistor P_Dn. The transistor HVP_D can be a CMOS transistor, in particular an NMOS transistor. The transistors N_D1 to N_Dn are CMOS transistors, in particular NMOS transistors. The control circuit T_D controls the transistors N_D1 to N_Dn of the first to the nth current stage in accordance with the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121 .

The current stages S1 to Sn of the transmission stages 121A to 121D are thus designed as resistance stages. The resistance levels are set by selecting the resistance value of the respective current level, for example by selecting the resistors R_A1 to R_An for the transmission stage 121A, etc. Current levels are set as a result of the setting of the resistance values of the resistors. The number n can be chosen arbitrarily. In particular, the number n and thus the number of stages or number of resistance stages or current stages can be selected between 1 and 60. Alternatively, however, a number greater than 60 can be selected for n.

Each of the polarity reversal diodes D_A, D_B, D_C, D_D protects the associated transmission stage against positive feedback on connection 44 (CAN-Supply) and negative feedback on connection 43 (CAN_GND). Each of the Reverse polarity diodes D_A, D_B, D_C, D_D can also be referred to as blocking diodes.

Each of the parallel circuits 121A1, 121B1, 121C1, 121D1, more precisely the associated control circuit T_A, T_B, T_C, T_D, provides a resistance value for the associated transmission stage 121A, 121B, 121C, 121D depending on the operating mode (SLOW or SIC, FAST_TX) of the Transmission module 121 and the transmission signal TxD. The resistance value of the individual transmission stages 121A, 121B, 121C, 121D can thus be set depending on the operating mode (SLOW or SIC, FAST_TX) of the transmission module 121 and the transmission signal TxD. This is described in more detail below with reference to FIGS. 10 and 11 as well as Table 2 and Table 3.

Each of the transistors HVP_A, HVN_B, HVP_C, HVN_D is an HV cascode and may also be referred to as an HV standoff device. The transistor HVP_A protects the CMOS transistors P_A1 to P_An of the associated parallel circuit 121A1 by the transistor HVP_A absorbing high voltage drops. Each of the transistors HVN_B, HVP_C, HVN_D has the same function for the CMOS transistors of the associated parallel circuit 121B1, 121C1, 121D1. Each of the transistors HVP_A, HVN_B, HVP_C, HVN_D is connected to the terminal 125 at its control terminal. Thus, each of the transistors HVP_A, HVN_B, HVP_C, HVN_D can be controlled by the at least one control device 124.

The current limiting modules 1211, 1212 are each designed as a transistor. The current limiting modules 1211, 1212 in the example of FIG. 9 are each CMOS transistors. The current limit module 1211 of Figure 9 is a PMOS transistor. Thus, the current limit module 1211 forms a current source. The current limit module 1212 of Figure 9 is an NMOS transistor. Thus, the current limit module 1212 forms a current sink. The current limiting modules 1211, 1212 are provided to protect the transmission module 121 and the external components, in particular other components of the subscriber station 10 and/or the bus 40. The arrangement of the current limiting modules 1211, 1212 in the circuit of the transmission stage 121 is suitable for the dom state 401 and for the sic state 403 of FIG. in the According to the design and specification, twice as much electrical current flows in the dom state 401 as in the sic state, but the current in the dom state 401 only flows on one path of the transmitter module 121. In contrast, in the sic state the current flows in two paths of the transmit module 121. The two paths are designed or configured the same. The same voltage drop thus occurs at the current-limiting modules 1211, 1212.

In the case of the transmission module 121, the transmission stage 121A is connected between the connection 43 for the voltage supply and the connection 41 (CANH) for the signal CAN_H. The transmission stage 121C is connected between the connection 43 for the voltage supply and the connection 42 (CANL) and the connection 43 for ground or the connection 44 (CAN_GND). The transmission stage 121D is connected between the connection 41 (CANH) for the CAN_H signal and the connection 43 for ground or the connection 44 (CAN_GND). The transmission stage 121B is connected between the connection 42 (CANL) for the signal CAN_L and the connection 43 for ground or the connection 44 (CAN_GND). Thus, in the case of the transmission module 121, the transmission stage 121A is switched into the CANH path. On the other hand, the transmission stage 121D is connected to the CANH path. On the one hand, the transmission stage 121C is switched into the CANL path. On the other hand, the transmission stage 121B is switched to the CANL path.

Thus, the transmission module 121 in the CANH path and in the CANL path consists of a parallel circuit 121A1, 121B1, 121C1, 121D1 of a specific number of current stages. A single current stage is realized by a series circuit consisting of a CMOS switch and a resistor as previously described. The parallel connection of all current stages is connected in series with an HV cascode HVP_A, HVN_B, HVP_C, HVN_D and a polarity reversal diode D_A, D_B, D_C, D_D in the CANH path and in the CANL path, as previously described. The HV cascodes HVP_A, HVN_B, HVP_C, HVN_D allow compliance with limit values (maximum rating parameters), such as voltage at CANH and CANL -27V to +40V.

The functioning of the circuit of Fig. 9 depending on the operating mode of the transmission module 121 and the bus state 401 (dom), 403 (sic), 402 (rec) in the SIC operating mode (arbitration phase 451) and L0, LI in the data phase 452 is explained using Table 2 below. Depending on the state of the transmission module 121 and the operating mode of the phases 451, 452, Table 2 specifies the required impedance depending on the state of the transmission module 121 and the impedance of the transmission stages 121A/121B and impedance of the transmission stages 121C/121D.

Table 2: Required impedance depending on the transmission condition

If the impedance is “infinite”, the transmission module 121 or the respective transmission stage 121A, 121B, 121C, 121D is switched off or not switched to be conductive.

The division of each parallel circuit 121A1, 121B1, 121C1, 121D1 of Fig. 9 into n parts or the n current stages allows a time-staggered and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC mode) 451 or the Bus states L0, LI of the data phase 452. The resistance values of the resistors of the n current stages are set for this, as illustrated in a special example with FIG.

10 shows an example of the current level per switching stage or current stage S1 to S12. Thus, in the example shown, twelve current stages S1, S2 to S6 to S12 are used for each of the parallel circuits 121A1, 121B1, 121C1, 121D1. So n = 12 applies.

The value of the current I (vertical axis in FIG. 10) or II, 12, 16, 112 etc. is set by the selection of the series resistance value of the respective current stage S1 to S12. The individual current stages S1 to S12 (horizontal axis in FIG. 10) thus have different resistance values.

To generate the bus states 401, 402, 403 in the arbitration phase (SIC mode) 451 or the bus states L0, LI of the data phase 452, the individual current stages S1 to S12 are switched on or off with a time offset using the CMOS transistors of the current stages S1 to S12 . As a result, a corresponding electric current I flows in the CANH path or CANL path into which the higher-order transmission stage 121A, 121B, 121C, 121D is connected.

In general, it is advantageous to design the staggering (stagger stages) and resistances per switching stage or current stage S1 to S12 in such a way that the form of the difference signal VDIFF follows the Gaussian error function. This analytically produces the lowest emissions. For the transition from a state 402 (recessive) to a state 401 (dominant), which corresponds to a rising edge of the differential voltage VDIFF of Fig.

4 corresponds, the current in the CANH path and in the CANL path for generating a dominant level on the bus 40 is gradually increased by the time-staggered connection of the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1. The transition from a state 401 (dominant) to a state 402 (recessive), which corresponds to a falling edge of the differential voltage VDIFF of FIG Current in the CANH and CANL path is gradually reduced. The entire current, which is given by the sum of the currents II to I12 or II to In of all current stages S1 to Sn, flows during state 401 (dominant). Here all current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 are switched on and the total current for generating the dominant level of nominal VDIFF = 2V flows through the bus resistor or terminating resistor 49.

By setting the time and by selecting the current levels of the individual current stages S1 to S12 by setting the resistance values of their resistors, as described above, it is possible to align the bus signals CAN_H, CAN_L with one another during the transition between states 401, 402, so that the symmetrical course of CAN_H and CAN_L according to FIG. 6 is realized. The structure of the transmission module 121 enables the individual current stages of the parallel circuits 121A1, 121B1, 121C1, 121D1 to be switched on at different times. This time control makes it possible to align the signal form of CAN_H and CAN_L as required according to FIG. Targeted shaping of the signal curves for CAN_H and CAN_L is possible. Overall, the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, LI of the data phase 452 can be formed depending on the specifications.

The resistances of the individual current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 and thus their respective proportion of the total current can be selected in different ways in order to achieve the lowest possible emission, in particular a low emission of the transmission module 121. It is advantageous for a low emission to add or remove a small amount of current I (high resistance value) at the beginning and at the end of a switching process between bus states 401, 402 and to add or remove a large amount of current (low resistance value) in the middle of the switching process. Therefore, the setting of the currents of the current stages S1 to S12 shown in FIG. 10 is very advantageous.

In contrast to an implementation with identical resistances in the current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1, the configuration according to FIG. 10 avoids a current increase during turn-off, the transition from state 401 (dominant) to state 402 (Recessive).

The granularity of the time grading (staggering) for switching the individual current stages S1 to S12 on or off is in a range of around 2 ns. Such small steps or time staggering steps cause little common mode interference and have little negative impact on the emission. The voltage steps, which are set via the resistors or resistance levels of the current levels S1, S2 to S6 to S12, are kept fixed and the grading over time varies, so that the behavior is as soft as possible during the switch-on process (according to the Gaussian error function) . The variation of the time steps or time stages also prevents the occurrence of a narrow-band frequency line in the emission frequency spectrum.

Alternatively, the staggering steps can be carried out using fixed time steps and varied voltage steps.

The structure of the transmission module 121 shown enables symmetrical switching of the bus signals CAN_H and CAN_L (Fig. 6) with steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, LI of the data phase 452 allows.

On the one hand, due to the structure of the transmission module 121 shown, fast CMOS switches or CMOS transistors are used much steeper switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, LI of the data phase 452 are realized. On the other hand, the symmetry of the time profile of the bus signals CAN_H and CAN_L, which is necessary to comply with the emission limit values, is achieved during the switching processes. An adjustment (matching) of the characteristic curves is achieved by selecting or using the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1. This means that the matching of the characteristic curves is less dependent on the parameters of the transistors used in the parallel circuits 121A1, 121B1, 121C1,

121D1.

The CMOS transistors of the transmission stages 121A1, 121B1, 121C1, 121D1 are operated as switches, i. H. with a maximum voltage between the gate terminal and the source terminal. The adjustment (matching) of the individual transmission stages 121A1, 121B1, 121C1, 121D1 thus depends significantly on the adjustment (matching) of the resistors R_A1 to R_An, R_B1 to R_Bn, R_C1 to R_Cn, R_D1 to R_Dn and no longer on the transistors P_A1 to P_An and P_C1 to P_Cn (PMOS) on bus wire 41 (CANH) and the transistors N_D1 to N_Dn and N_B1 to N_Bn (NMOS) on bus wire 42 (CANL).

The dominant state 401 (dom) is determined by matching the resistors R_A1 to R_An (transmission stage 121A) with the resistors R_B1 to R_Bn (transmission stage 121B). Here and also in the following, the term “adjustment” means an active trimming step according to one possibility. According to another possibility, "matching" means that the resistor values match as well as possible, which by default is done without a matching or trimming step.

The Sic state (sic) is determined by matching resistors R_A1 to R_An (transmitter stage 121A) with resistors R_C1 to R_Cn (transmitter stage 121C) and by matching resistors R_D1 to R_Dn (transmitter stage 121D) with the resistors R_B1 to R_Bn (transmission stage 121B). In the XL-Fast operating mode, the LO state is determined by matching resistors R_A1 to R_An (transmitter stage 121A) with resistors R_B1 to R_Bn (transmitter stage 121B). The state LI is determined by a comparison (matching) of the resistors R_C1 to R_Cn (transmission stage 121C) with the resistors R_D1 to R_Dn (transmission stage 121D).

The on-resistance Ron of the respective transistors of the transmission stages 121A1, 121B1, 121C1, 121D1 should be significantly smaller than the series-connected resistance of the individual current stages of the transmission stages 121A1, 121B1, 121C1, 121D1.

Fig. 11 shows a special example of the structure of the transmission stage 121 B of Fig. 9. Accordingly, the transmission stage 121 B in the parallel circuit 121 Bl has three current stages S_l, S_ll, S_l II. The first current stage S_l has a resistor R_B1_I and an in Series-connected transistor N_B1_I. The second current stage S_ll has a resistor R_B1_II and a transistor N_B1_II connected in series. The third current stage S_l II has a resistor R_B1_III and a transistor N_B1_I II connected in series.

For the following description of the circuit of Fig. 9 with the configuration according to Fig. 11, it is assumed that each of the transmission stages 121A, 121C, 121D in its associated parallel circuit 121A1, 121C1, 121D1 has three current stages S_l, S_ll, S_l II according to the example of Fig. 11 has.

Table 3 below shows the activation of the three transistors N_B1_I, N_B1_II, N_B1_I II of the transmission stage 121B of Fig. 11 and the corresponding transistors of the transmission stages 121A, 121C, 121D of Fig. 9, each depending on the transmission stages 121A/ 121B and the transmission stages 121C , 121D.

Table 3: Required impedance depending on the transmission condition

In this way, the required steeper edges on the bus signals CAN_H and CAN_L can be generated with the transmission module 121 and the emission limit values can be complied with.

Alternatively, more than three current stages can be used in the respective transmission stages 121A, 121B, 121C, 121D, as previously described. 12 shows a transmission module 1210 according to a second exemplary embodiment.

The transmission module 1210 is constructed in many parts in the same way as the transmission module 121 according to the first embodiment. Therefore, only the differences from the first exemplary embodiment are described below In contrast to the first exemplary embodiment, the transmission module 1210 according to the present exemplary embodiment has transmission stages 121A0, 121B0, 121C0, 121D0. The transmission stages 121A0, 121B0, 121C0, 121D0 are connected as a full bridge. The terminating resistor 49 is connected in the bridge branch between the connections for the bus wires 41, 42. In addition, the transmission module 1210 has, instead of the current limiting modules 1211, 1212, a first to xth current limiting module 1211_1 to 1211x and a first to xth current limiting module 1212_1 to 1212_x. Here x is a natural number > 1.

The current limiting modules 1211_1 to 1211_x, 1212_1 to 1212_x are each designed as a transistor. The current limiting modules 1211_1 to 1211_x, 1212_1 to 1212_x in the example of FIG. 12 are each CMOS transistors. The current limiting modules 1211_1 to 1211_x of FIG. 12 are each a PMOS transistor. The current limiting modules 1211_1 to 1211_x thus each form a current source. The current limit modules 1212_1 to 1212_x of FIG. 12 are each an NMOS transistor. The current limiting modules 1212_1 to 1212_x thus each form a current sink.

In contrast to the transmission stage 121A of the first exemplary embodiment, which has the transistor HVP_A, the transmission stage 121 A0 has a first to y-th transistor HVP_A1 to HVP_Ay, where y is a natural number >1. Each of the first through y-th transistors HVP_A1 through HVP_Ay is a CMOS transistor, specifically a PMOS transistor, as previously described for transistor HVP_A with respect to FIG.

In contrast to the transmission stage 121B of the first exemplary embodiment, which has the transistor HVN_B, the transmission stage 121B0 has a first to yth transistor HVN_B1 to HVN_By, where y is the natural number>1. Each of the first through y-th transistors HVN_B1 through HVN_By is a CMOS transistor, specifically an NMOS transistor, as previously described for transistor HVP_B with respect to FIG.

In contrast to the transmission stage 121C of the first exemplary embodiment, which has the transistor HVP_C, the transmission stage 121C0 has a first to y-th transistor HVP_C1 to HVP_Cy, where y is the natural number >1. Each of the first through y-th transistors HVP_C1 through HVP_Cy is a CMOS transistor, specifically a PMOS transistor, as previously described for the transistor HVP_C with respect to FIG.

In contrast to the transmission stage 121D of the first exemplary embodiment, which has the transistor HVN_D, the transmission stage 121D0 has a first to yth transistor HVN_D1 to HVN_Dy, where y is the natural number>1. Each of the first through y-th transistors HVN_D1 through HVN_Dy is a CMOS transistor, specifically an NMOS transistor, as previously described for transistor HVP_D with respect to FIG.

In addition to the functions of the transmission module 121 according to the first embodiment, the transmission module 1210 of FIG. 12 has the following functions.

Due to its design, the transmission module 1210 is able to reduce effects due to asymmetrical behavior of the transmission stages, which can occur in the transmission states dom (401), sic (403), rec (402) and increase the overshoot and therefore worsen the emission . The transmission module 1210 prevents unequal behavior of components in the transmission stages 121A0, 121B0 (Effect 1) of the full bridge of FIG or prevented.

In order to prevent effect 1, the resistance Ron (switch-on resistance) of the cascodes in the transmission stages 121A0, 121B0 can be changed, in particular by driving with the respectively associated control circuit T_A, T_B. This is done by changing the up to y parallel-connected transistors HVP_A1 to HVP_Ay and/or the up to y parallel-connected transistors HVN_B1 to HVN_By. In order not to change the symmetry of the two series circuits of the transmission stages 121A0, 121D0 and the transmission stages 121C0, 121B0 in the sic state 403, the cascodes from the transmission stages 121DO, 121C0 must also experience the same change. Therefore, the up to y parallel connected transistors HVN_D1 to HVP_Dy and/or up to y parallel-connected transistors HVP_C1 to HVP_Cy changed accordingly. For this purpose, each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVP_Dy is connected to a connection 125 at its control connection (gate connection). Each of these transistors can thus be controlled by the at least one control device 124 . The intervention for correcting the common mode level in the dom state 401 takes place via an equal or the same change from HVP_A1 to HVP_Ay and HVP_C1 to HVP_Cy or via an equal or the same change from HVP_D1 to HVN_Dy and HVP_B1 to HVN_By.

In addition, the transmission module 1210 can prevent unequal behavior of components in transmission stages 121A0 / 121D0 and 121C0 / 121B0 of the full bridge (Effect 2), so that in the sic state a change in the common-mode voltage is minimized compared to the rec state 402 or prevented.

For this purpose, the resistance Ron (switch-on resistance) of the current-limiting transistors or current-limiting modules 1211, 1212 can be changed. This takes place via the up to x current-limiting modules 1211_1 to 1211_x connected in parallel and/or the up to x current-limiting modules 1212_1 to 1212_x connected in parallel, in particular by activation by the at least one control device 124. State 403 takes place via the up to x current-limiting modules 1211_1 to 1211_x connected in parallel or the up to x current-limiting modules 1212_1 to 1212_x connected in parallel. For example, x=4. In this case, four different levels of the resistance Ron (on resistance) of the current-limiting transistors or current-limiting modules 1211, 1212) can be set.

This prevention of effect 2 is particularly advantageous since only if, starting from the common mode level of the rec state 402, the common levels in the dom state 401 and in the sic state 403 match those of the rec state 402, a sufficient Emission result can be achieved, however, the causes that lead to the behavior of effect 1 can be different than the lead to effect 2. The configuration of the transmission module 1210 can prevent substrate current losses in particular in the polarity reversal diodes D_A and D_B from causing the common mode level in the dom state 401 to no longer be correct. In the sic state, the polarity reversal diodes D_A and D_B are energized to a lesser extent and all polarity reversal diodes D_A, D_B, D_C, D_D of the four transmission stages 121A0, 121B0, 121C0, 121D0 are also active. The transmit module 1210 can prevent different common mode levels from being present in the dom state and in the sic state. In addition, it can be prevented that effects of the same quality are produced by unequal behavior in the cascodes.

In this way, the transmission module 1210 can positively influence the effects on the emission values of the transmission/reception device 12, which are decisively influenced by the transmission module 1210.

All previously described configurations of the transmitter module 121, 1210, the transmitter/receiver devices 12, 22, the subscriber stations 10, 20, 30, the bus system 1 and the method carried out therein according to the first and second exemplary embodiment and their modifications can be used individually or in all possible combinations are used. In addition, the following modifications in particular are conceivable.

The previously described bus system 1 according to the first and second exemplary embodiment is described using a bus system based on the CAN protocol. However, the bus system 1 according to the first and/or second exemplary embodiment can alternatively be another type of communication network in which the signals are transmitted as differential signals. It is advantageous, but not an essential requirement, that in the bus system 1 exclusive, collision-free access by a subscriber station 10, 20, 30 to the bus 40 is guaranteed at least for certain periods of time.

The bus system 1 according to the first and/or second exemplary embodiment and modifications thereof is in particular a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 can be different Be communication network in which the signals are transmitted as differential signals and serially over the bus.

Thus, the functionality of the exemplary embodiments described above can be used, for example, in transceivers 12, 22 that are in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system are operable. It is possible that for the two bus states 401, 402, at least temporarily, no dominant and recessive bus state is used, but instead a first bus state and a second bus state are used, both of which are driven. An example of such a bus system is a CAN XL bus system.

The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 according to the first and second exemplary embodiment and their modifications is arbitrary. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first or second exemplary embodiment.

Claims

Expectations

1) Transmission module (121; 1210) for transmitting differential signals in a serial bus system (1), with a first transmission stage (121A; 121A0) for generating transmission currents (II to In) for a first signal (CAN_H) which is applied to a Bus (40) of the bus system (1) is to be sent, a second transmission stage (121B; 121B0) for generating transmission currents (II to In) for a second signal (CAN_L), which is used as a differential signal to the first signal (CAN_H). is to be sent onto the bus (40), a third transmission stage (121C; 121C0) for generating transmission streams (II to In) for the first signal (CAN_H), and a fourth transmission stage (121D; 121D0) for generating transmission streams (II to In) for the second signal (CAN_L), the first to fourth transmission stages (121 A to 121 D; 121 AO to 121D0) being connected in a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A0, 121D0 ) are connected in series and the third and second transmission stages (121C, 121B; 121C0, 121B0) are connected in series si nd, wherein each of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0) has at least two current stages (S1 to Sn) which are connected in parallel with one another, each of the at least two current stages (S1 to Sn) having a switchable resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn ), and wherein the switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of a transmission stage (121A to 121D; 121A0 to 121D0) have different resistance values. 2) transmission module (121; 1210) according to claim 1, wherein the output connections (41, 42) of the full bridge are provided for connection to a terminating resistor (49) of the bus (40).

3) transmission module (121; 1210) according to claim 1 of 2, wherein a number n of the at least two current stages (S1 to Sn) for each of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0) is the same, where n is a natural number is greater than 1.

4) transmission module (121; 1210) according to any one of the preceding claims, wherein each of the at least two current stages (S1 to Sn) a CMOS transistor for switching the resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) the current stage (S1 to Sn).

5) Transmission module (121; 1210) according to one of the preceding claims, wherein the CMOS transistor of the current stages (S1 to Sn) of the first transmission stage (121 A; 121A0) is a PMOS transistor, the CMOS transistor of the current stages (S1 to Sn) of the second transmission stage (121B; 121B0) is an NMOS transistor, wherein the CMOS transistor of the current stages (S1 to Sn) of the third transmission stage (121C; 121C0) is a PMOS transistor, and the CMOS transistor of the Current stages (S1 to Sn) of the fourth transmission stage (121 D; 121 DO) is an NMOS transistor.

6) transmission module (121; 1210) according to one of claims 4 or 5, wherein each of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0) also has a reverse polarity diode (D_A; D_B; D_C; D_D) for protection against a positive Feedback in a connection (43) for the bus voltage supply and negative feedback from a connection (44) for ground, and at least one cascode (HVP_A; HVN_B; HVP_C; HVN_D) to protect the CMOS transistors. 7) transmission module (1210) according to claim 6, wherein at least two cascodes (HVP_A; HVN_B; HVP_C; HVN_D) are connected in parallel with one another, with a number y of the cascodes (HVP_A; HVN_B; HVP_C; HVN_D) for each of the first to fourth transmission stages (121A to 121D;

121A0 to 121DO) is the same, where y is a natural number greater than 1, and where the on-resistance of the at least two cascodes (HVP_A; HVN_B; HVP_C; HVN_D) is different.

8) transmission module (121; 1210) according to one of the preceding claims, also with at least one first current-limiting module (1211) as a current source, which is connected between a connection (43) for the bus voltage supply and the full bridge, and at least one second current-limiting module (1212) as a current sink, which is connected between a connection (44) for ground and the full bridge.

9) transmission module (1210) according to claim 8, wherein at least two first current-limiting modules (1211_1 to 1211_x) are connected in parallel to one another, the on-resistance of which is different, wherein at least two second current-limiting modules (1212_1 to 1211_x) are connected in parallel to one another, the on-resistance of which is different, and wherein the number x of the first current limiting modules (1211_1 to 1211_x) is equal to the number x of the second current limiting modules (1212_1 to 1211_x), where x is a natural number greater than 1.

10) transmission module (121; 1210) according to any one of the preceding claims, also with a drive circuit (T_A; T_B; T_C; T_D) for driving switchable components of the first to fourth transmission stage (121A to 121D; 121A0 to 121D0) depending on a digital transmission signal (TxD) and an operating mode (SIC; FAST_TX) set for the transmission module (121; 1210).

11) Transmitting module (121; 1210) according to claim 10, wherein the control circuit (T_A; T_B; T_C; T_D) is designed for staggered and controlled switching of the resistance values of the at least two current stages (S1 to Sn).

12) Transmitting/receiving device (12; 22) for a subscriber station (20) for a serial bus system (1), with a transmitting module (121; 1210) according to one of the preceding claims, and a receiving module (122) for receiving signals from the bus (40).

13) Subscriber station (10; 20; 30) for a serial bus system (1), with a transmitting/receiving device (12; 22) according to claim 12, and a communication control device (11; 21) for controlling the communication in the bus system (1 ) and for generating a digital transmission signal (TxD) for controlling the first to fourth transmission stages (121A to 121D; 121A0 to 121D0).

14) Subscriber station (10; 20; 30) according to claim 13, wherein the subscriber station (10; 20; 30) is designed for communication in a bus system (1) in which at least temporarily an exclusive, collision-free access of a subscriber station (10, 20, 30) on the bus (40) of the bus system (1) is guaranteed.

15) Method for sending differential signals in a serial bus system (1), the method being carried out with a transmission module (121; 1210), and the method having the steps,

Generating, with a first transmission stage (121A; 121A0), transmission currents (II to In) for a first signal (CAN_H) which is to be transmitted to a bus (40) of the bus system (1), Generating, with a second transmission stage (121B; 121B0), transmission streams (II to In) for a second signal (CAN_L), which is to be transmitted to the bus (40) as a differential signal to the first signal (CAN_H). , with a third transmission stage (121C; 121C0), from

Transmission currents (II to In) for the first signal (CAN_H), and

Generating, with a fourth transmission stage (121 D; 121 DO) of transmission currents (II to In) for the second signal (CAN_L), the first to fourth transmission stages (121 A to 121 D; 121 AO to 121D0) being connected in a full bridge are, at which the first and fourth

transmission stages (121A, 121D; 121A0, 121D0) are connected in series and the third and second transmission stages (121C, 121B; 121C0, 121B0) are connected in series, each of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0 ) has at least two current stages (S1 to Sn) which are connected in parallel to one another, each of the at least two current stages (S1 to Sn) having a switchable resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and wherein the switchable resistors (R_A1 to R_An; R_B1 to

R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of a transmission stage (121A to 121D; 121A0 to 121D0) have different resistance values.