CN117957818A - Transmitting module and method for transmitting differential signal in serial bus system - Google Patents

Abstract

A transmission module (121; 1210) and a method for transmitting differential signals in a serial bus system (1) are provided. The transmission module (121; 1210) has: a first transmission stage (121A; 121A 0) for generating a transmission current (I1 to In) for a first signal (CAN_H) which CAN be transmitted to a bus (40) of the bus system (1); a second transmission stage (121B; 121B 0) for generating a transmission current (I1 to In) for a second signal (CAN_L) which CAN be transmitted as a differential signal relative to the first signal (CAN_H) onto the bus (40); a third transmission stage (121C; 121C 0) for generating transmission currents (I1 to In) for the first signal (CAN_H); and a fourth transmission stage (121D; 121D 0) for generating a transmission current (I1 to In) for the second signal (CAN_L), wherein the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) are coupled In a full bridge In which the first and fourth transmission stages (121A, 121D;121A0, 121D 0) are coupled In series and the third and second transmission stages (121C, 121B;121C0, 121B 0) are coupled In series, wherein each of the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) has at least two current stages (S1 to Sn) coupled In parallel with respect to each other, wherein each of the at least two current stages (S1 to Sn) has a switchable resistance (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_D1; cn_D1 to R_Dn; and wherein each of the first to 121A to 121D0 has a switchable resistance (R_A1 to R_Bn), and wherein each of the at least two current stages (S1 to Sn) has a switchable resistance (R_R_A 1 to R_an; R_R_1 to R_Bn; R_1 to R_D1 to R_Dn).

Description

Transmitting module and method for transmitting differential signal in serial bus system

Technical Field

The invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, which CAN be used in particular for CAN XL.

Background

Serial bus systems are used for message transmission or data transmission in technical installations. The serial bus system enables communication between a sensor and a controller in a vehicle or a technical production facility, for example. Different standards or data transfer protocols exist for data transfer. In particular, CAN bus systems, LVDS bus systems (lvds=low Voltage DIFFERENTIAL SIGNALING), MSC bus systems (msc=micro-Second-Channel), 10 BASE-T1S-ethernet are known.

In CAN bus systems, messages are transferred by means of the CAN protocol and/or CANFD protocol, as in ISO-11898-1: the 2015 standard is described as a CAN protocol specification with CAN FD. In CAN FD, switching is performed between a slow mode of operation in the first communication phase (arbitration phase) and a fast mode of operation in the second communication phase (data phase) during the transfer on the bus. In the CAN FD bus system, a data transmission rate of more than 1 megabit per second (1 Mbps) CAN be achieved in the second communication stage. CANFD was first used in vehicles by most manufacturers at an arbitration bit rate of 500kbit/s (kilobit/s) and a data bit rate of 2Mbit/s (megabit/s).

In order to be able to achieve a still higher data transmission rate in the second communication phase, there are subsequent bus systems for CAN FD, such as CAN-SIC and CAN XL, for example. In CAN-SIC according to the CiA601-4 standard, a data transmission rate of about 5 to 8Mbit/s CAN be achieved in the second communication phase. In CANXL, a data transmission rate of > 10Mbit/s in the second communication phase is required, wherein the standard for this (CiA 610-3) is currently established in the CAN automation organization (CiA). In addition to pure data transfer via the CAN bus, CAN XL should also support other functions such as functional Security (Security), data Security (Security) and quality of service (qos= Quality ofService (quality of service)). These are the basic characteristics required in an autonomous vehicle.

In all of the above-mentioned CAN-based bus systems, the bus signal can_h is driven onto the bus independently of the transmission signal TxD and ideally simultaneously the bus signal can_l is driven onto the bus. In this case, the bus state is actively driven at least in a first communication phase in the bus signal can_ H, CAN _l. The other bus state is not driven and is set due to the termination resistance of the bus line or bus line. Due to the differently driven states, the signal shape of the bus signal can_ H, CAN _l may deviate from the ideal signal shape in an actual bus system. The reasons for this are, inter alia, bus system designs, such as branches, switching delays for switching stages of the bus signal CAN H, CAN L, etc. Such a false adaptation of the two bus signals CAN H, CAN L may lead to errors in evaluating the bus signals received by the bus.

In order to transmit and receive bus signals, a transmitting/receiving device, which is also called a CAN transceiver or a CAN FD transceiver or the like, is generally used in a CAN bus system for each communication subscriber. CAN transceivers or CAN FD transceivers do not allow the limit value for operation in the vehicle to be exceeded in terms of transmission or radiation by conduction (leitungsgebunden). The transceiver for CAN XL must also for this purpose follow more stringent limits, which are determined in the IEC62228-3 standard. Only then CAN the bus system be operated at a predetermined higher bit rate than in CAN FD and CAN SIC. Following these strict limits presents a major challenge, depending on the semiconductor technology available.

In contrast to CANFD, in a transceiver for CAN-SIC or for CAN-XL, a third state, the SIC state, must be generated in addition to the implicit (rec) and explicit (dom) states in an arbitration phase, also referred to as SIC mode or SIC mode of operation. In order to meet the radiation requirements of the IEC62228-3 standard, the common mode voltage of the bus line must be kept within narrow limits for the signal can_ H, CAN _l in the three transmission states, i.e. recessive, dominant, sic. The common mode voltage occurs at a common mode choke, which is used in particular in certification measures for verifying compliance with the IEC62228-3 standard. Common Mode Choke is also known as Common-Mode-Choke (CMC). The common mode choke has the purpose of letting the differential signal (dm= DIFFERENTIAL MODE (differential mode)) pass as far as possible without effect and suppressing the common mode signal (cm=common mode) as far as possible. However, in actual operation, the common-mode choke produces at the output a differential signal with an undesired common-mode signal superimposed on the differential signal from the differential signal at the input without a common-mode contribution. This is disadvantageous because it is then fed directly into the CAN bus on the bus side and is visible to other CAN modules.

Disclosure of Invention

It is therefore an object of the present invention to provide a transmitting module and a method for transmitting differential signals in a serial bus system that solves the aforementioned problems. In particular, a transmission module and a method for transmitting differential signals in a serial bus system should be able to compensate for interference parameters acting on the radiation characteristics of the transmission module.

This object is achieved by a transmitting module for transmitting differential signals in a serial bus system having the features of claim 1. The transmission module has: a first transmitting stage for generating a transmit current for a first signal which can be transmitted onto a bus of the bus system; a second transmitting stage for generating a transmit current for a second signal which can be transmitted onto the bus as a differential signal relative to the first signal; a third transmitting stage for generating a transmitting current for the first signal; and a fourth transmission stage for generating a transmission current for the second signal, wherein the first to fourth transmission stages are coupled in a full bridge in which the first and fourth transmission stages are coupled in series and the third and second transmission stages are coupled in series, wherein each of the first to fourth transmission stages has at least two current stages coupled in parallel with respect to each other, wherein each of the at least two current stages has a switchable resistance, and wherein the switchable resistances of the transmission stages have different resistance values.

The described transmission module makes it possible to achieve the required limit values for the radiation of the transmission/reception device for the CAN XL. The transmission module in this case satisfies in particular the IEC62228-3 standard, which determines the limit values to be followed for the bus states dom, sic and rec.

The transmitting module CAN adapt the impedance between the bus lines for the signals can_h and can_l very well to the characteristic wave resistance or impedance of the bus line used, for example, in the sic state. The impedance Zw of the bus line used here applies zw=100 ohms or zw=120 ohms. The transmission module thus prevents reflections and thus allows operation at higher bit rates in the bus system.

The described transmit module allows for a time interleaved and controlled switching process by dividing its four transmit stages into n parts. Here, the access can be implemented as a gaussian error function. This enables setting the soft (weichen) characteristics at the time of the access procedure. Furthermore, the possible variation of the time level (Zeitstufen) during access prevents narrowband frequency lines from occurring in the transmission spectrum.

Alternatively, it is possible to implement an interleaved and controlled switching process with the described transmission module with fixed time steps and varying voltage steps. The radiation characteristic of the transmission module can also be influenced in such a way that a predefined limit value is followed.

Furthermore, the described transmission module can reduce effects due to the asymmetrical nature of the transmission stage, which may occur in the transmission state dom, sic, rec and deteriorate the radiation. The transmit module blocks the non-identical characteristics of the components in the transmit stage A, B of the full bridge (effect 1), thereby minimizing or preventing the variation of the common mode voltage in the dom state compared to the rec state. Furthermore, the transmit module is able to block the non-identical characteristics of the components of the transmit stages a/D and C/B of the full bridge (effect 2), thereby minimizing or preventing the variation of the common mode voltage in the sic state compared to the rec state. This is particularly advantageous because sufficient radiation results can only be obtained when the common mode level in the dom state and in the sic state is adapted to the common mode level of the rec state starting from the common mode level of the rec state, however, the cause of the characteristics leading to effect 1 may be different from the cause leading to effect 2.

Advantageous further embodiments of the transmission module are described in the dependent claims.

The output connection of the full bridge can be provided for coupling with a termination resistor of the bus.

In a possible manner, the number n of at least two current stages is the same for each of the first to fourth transmission stages, where n is a natural number greater than 1.

In one embodiment, each of the at least two current stages has a CMOS transistor for switching the resistance of the current stage.

According to one embodiment, the CMOS transistor of the current stage of the first transmitting stage is a PMOS transistor, wherein the CMOS transistor of the current stage of the second transmitting stage is an NMOS transistor, wherein the CMOS transistor of the current stage of the third transmitting stage is a PMOS transistor, and wherein the CMOS transistor of the current stage of the fourth transmitting stage is an NMOS transistor.

Each of the first to fourth transmission stages can furthermore have a diode with a reverse polarity for protection against positive feedback in the connection for the bus voltage supply and against negative feedback in the connection for the ground, and at least one cascode structure (Kaskode) for protection of the CMOS transistors.

According to another embodiment, at least two cascode structures are coupled in parallel to each other, wherein the number y of cascode structures is the same for each of the first to fourth transmission stages, wherein y is a natural number greater than 1, and wherein the access resistances of the at least two cascode structures are different.

The transmitting module can furthermore have at least one first current limiting module as a power source, which is coupled between the connection for the bus voltage supply and the full bridge, and at least one second current limiting module as a current sink, which is coupled between the connection for the ground and the full bridge.

According to one embodiment, at least two first current limiting modules are coupled in parallel to each other, their access resistances being different, wherein at least two second current limiting modules are coupled in parallel to each other, their access resistances being different, and wherein the number x of first current limiting modules is equal to the number x of second current limiting modules, wherein x is a natural number greater than 1.

The transmission module can furthermore have a control circuit for controlling the switchable components of the first to fourth transmission stages as a function of the digital transmission signal and as a function of the operating mode set for the transmission module. In a practical manner, the control circuit is designed to switch the resistance values of at least two current levels in a time-staggered and controlled manner.

The transmission module described above can be part of a transmission/reception device for a subscriber station of a serial bus system, which transmission/reception device furthermore has a reception module for receiving signals from the bus.

The transmitting/receiving device can be part of a subscriber station for a serial bus system, which subscriber station furthermore has a communication control device for controlling the communication in the bus system and generating digital transmission signals for actuating the first to fourth transmission stages.

In a practical manner, the subscriber station is designed for communication in a bus system in which a special, collision-free access of the subscriber station to the bus of the bus system is ensured at least temporarily.

The aforementioned object is furthermore achieved by a method for transmitting differential signals in a serial bus system having the features of claim 15. The method is implemented by a transmitting module, wherein the method comprises the following steps: generating a transmit current for a first signal with a first transmit stage, the first signal being capable of being transmitted onto a bus of a bus system; generating a transmit current for a second signal using a second transmit stage, the second signal being capable of being transmitted onto the bus as a differential signal relative to the first signal; generating a transmit current for the first signal with a third transmit stage and generating a transmit current for the second signal with a fourth transmit stage, wherein the first to fourth transmit stages are coupled in a full bridge in which the first and fourth transmit stages are coupled in series and the third and second transmit stages are coupled in series, wherein each of the first to fourth transmit stages has at least two current stages coupled in parallel with respect to each other, wherein each of the at least two current stages has a switchable resistance, and wherein the switchable resistances of the transmit stages have different resistance values.

This approach provides the same advantages as mentioned previously in relation to the transmitting module.

Further possible implementations of the invention also include combinations of features or embodiments described in the foregoing or in the following with respect to the examples that are not explicitly mentioned. The person skilled in the art also adds the individual aspects as improvements or additions to the corresponding basic form of the invention.

Drawings

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings and according to embodiments. Wherein:

Fig. 1 shows a simplified block diagram of a bus system according to a first embodiment;

Fig. 2 shows a diagram for elucidating the structure of a message which can be sent by a subscriber station of the bus system according to the first embodiment;

FIG. 3 illustrates an embodiment of an ideal time profile for the bus signal CAN_ H, CAN _L in the bus system of FIG. 1;

Fig. 4 shows the time profile of a differential voltage VDIFF, which is formed on the bus of the bus system on the basis of the bus signal of fig. 4;

Fig. 5 shows an embodiment for the time profile of a digital transmission signal which is to be converted in an arbitration phase (SIC mode of operation) into a bus signal can_ H, CAN _l for the bus of the bus system of fig. 1;

Fig. 6 shows the temporal behavior of the bus signal CAN H, CAN L, which is transmitted onto the bus in the arbitration phase (SIC mode of operation) on the basis of the transmission signal of fig. 5, when switching between the recessive bus state to the dominant bus state and back to the recessive bus state;

fig. 7 shows an embodiment for the time profile of a digital transmission signal which is to be converted in a data phase into a bus signal CAN H, CAN L for the bus of the bus system of fig. 1;

fig. 8 shows the time profile of the bus signal CAN H, CAN L, which is transmitted in the data phase onto the bus on the basis of the transmission signal of fig. 6;

Fig. 9 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to the first embodiment;

FIG. 10 shows a timing diagram for showing different current levels into which a transmit stage is coupled for a first specific embodiment of the transmit module of FIG. 9;

FIG. 11 shows details of the transmit stage for a second specific embodiment of the transmit module of FIG. 9; and

Fig. 12 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to the second embodiment.

Detailed Description

In the drawings, identical or functionally identical elements are provided with the same reference numerals unless otherwise specified.

Fig. 1 shows a bus system 1, which CAN be, for example, a CAN bus system, a CAN FD bus system, or the like, at least in sections. The bus system 1 can be used in a vehicle, in particular a motor vehicle, a flying tool or the like, or in a hospital or the like.

In fig. 1, the bus system 1 has a plurality of subscriber stations 10, 20, 30, which are each coupled to a bus 40 or bus line having a first bus core 41 and a second bus core 42. For signals on the bus 40, the bus cores 41, 42 CAN also be referred to as can_h and can_l. Messages 45, 46, 47 can be signalled between the individual subscriber stations 10, 20, 30 via the bus 40. The subscriber stations 10, 20, 30 can be, for example, controllers or display devices of motor vehicles.

As shown in fig. 1, the subscriber stations 10, 30 have a communication control device 11 and a transmitting/receiving device 12, respectively. The transmitting/receiving device 12 has a transmitting module 121 and a receiving module 122.

The subscriber station 20 has communication control means 21 and transmitting/receiving means 22. The transmitting/receiving device 22 has a transmitting module 221 and a receiving module 222.

The transmitting/receiving means 12 of the subscriber stations 10, 30 and the transmitting/receiving means 22 of the subscriber station 20 are each directly coupled to the bus 40, even though they are not shown in fig. 1.

The communication control means 11, 21 are each adapted to control the communication of the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber station 10, 20, 30, which other subscriber station is coupled to the bus 40.

The communication control device 11 creates and reads a first message 45, 47, for example a modified CAN message 45, 47. The modified CAN messages 45, 47 are formed, for example, in accordance with the CAN SIC format or CAN XL format. The transmitting/receiving means 12 are arranged to transmit and receive messages 45, 47 to and from the bus. The transmission module 121 receives the digital transmission signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this digital transmission signal into a signal onto the bus 40. The receiving module 121 receives the signals sent on the bus 40 corresponding to the messages 45 to 47 and generates therefrom a digital received signal RxD. The reception module 122 transmits the reception signal RxD to the communication control device 11.

The communication control device 21 can be as according to ISO 11898-1:2015, that is to say as a CAN FD-compatible classical CAN controller or CANFD controller. Communication control device 21 creates and reads a second message 46, such as CANFD message 46. The transmitting/receiving device 22 is used to transmit and receive messages 46 to and from the bus 40. The transmission module 221 receives the digital transmission signal TxD created by the communication control device 21 and converts the digital transmission signal into a signal for the message 46 onto the bus 40. The receiving module 221 receives the signals sent on the bus 40 corresponding to the messages 45 to 47 and generates therefrom a digital received signal RxD. Furthermore, the transmitting/receiving device 22 CAN be implemented as a conventional CAN transceiver.

The verified characteristics responsible for the robustness and user friendliness of CAN and CAN FD are taken in order to send messages 45, 47 with CAN XL or CAN SIC, in particular a frame structure with identifiers and arbitration according to the known CSMA/CR method. The CSMA/CR method results in that a so-called implicit state has to be given on the bus 40, which may be overwritten by other subscriber stations 10, 20, 30 having an explicit level or an explicit state on the bus 40.

The use of two subscriber stations 10, 30 enables messages 45 having different CAN formats, in particular CAN FD format or CAN SIC format or CAN XL format, to be formed and then transmitted and such messages 45 received, as described in more detail below.

Fig. 2 shows, for message 45, a frame 450, in particular a CAN XL frame, as it is provided by communication control device 11 to transmitting/receiving device 12 for transmission onto bus 40. Here, communication control device 11 creates frame 450 in a manner compatible with CANFD in the present embodiment. Alternatively, frame 450 is compatible with CAN SIC.

According to fig. 2, the frame 450 is divided into different communication phases 451, 452 for CAN communication on the bus 40, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). Frame 450 has an arbitration field 453, a control field 454, a data field 455, a checksum field 456, and an end of frame field 457 after the start bit SOF.

In the arbitration phase 451, it is agreed between the subscriber stations 10, 20, 30 bit by means of an Identifier (ID) with bits ID28 to ID18, for example in the arbitration field 453, which subscriber station 10, 20, 30 wants to send the message 45, 46 with the highest priority and thus obtains a dedicated access to the bus 40 of the bus system 1 for the next time for transmission in the subsequent data phase 452. The physical layer is used in the arbitration phase 451 as in CAN and CAN-FD. The physical layer corresponds to the bit transport layer or layer 1 of the known OSI model (Open Systems Interconnection Modell (open systems interconnection model)).

An important point during stage 451 is that the known CSMA/CR method is used, which allows the subscriber stations 10, 20, 30 to access the bus 40 simultaneously without destroying the higher priority messages 45, 46. It is thereby relatively easy to add further bus subscriber stations 10, 20, 30 to the bus system 1, which is highly advantageous.

The CSMA/CR method results in that a so-called implicit state has to be given on the bus 40, which may be overwritten by other subscriber stations 10, 20, 30 having an explicit level or an explicit state on the bus 40. There is a high impedance condition at each subscriber station 10, 20, 30 in the implicit state, which in combination with parasitics of the bus circuit results in a longer time constant. This results in practical vehicle applications that currently limit the maximum bit rate of the CAN-FD physical layer today to about 2 megabits per second.

In the data phase 452, the CAN-XL frame 450 or the valid data of the message 45 from the data field 455 is transmitted in addition to a part of the control field 454, together with a checksum field 456. In the checksum field 456, a checksum can be included for the data of the data phase 452, which contains padding bits, which are inserted as counter bits by the transmitter of the message 45 in each case after a predetermined number of identical bits, in particular 10 identical bits. The switch back to the arbitration phase 451 is made again at the end of the data phase 452.

At least one acknowledgement bit can be included in the end field in the end of frame stage 457. In addition, there can be a sequence of 11 identical bits representing the end of CANXL frames 450. The receiver CAN be informed with at least one acknowledgement bit whether an error was found in the received CAN XL frame 450 or message 45.

The transmitter of the message 45 starts transmitting bits of the data phase 452 onto the bus 40 only if the subscriber station 10 has won arbitration as the transmitter and the subscriber station 10 has thus dedicated access to the bus 40 of the bus system 1 for transmission.

Thus, the subscriber stations 10, 30 in the arbitration phase 451 as the first communication phase partly, in particular until the FDF bit (inclusive), use the data according to ISO11898-1:2015 is a format known by CAN/CAN-FD. However, in comparison to CAN or CANFD, the net data transmission rate CAN be increased in the data phase 452 as the second communication phase, in particular to more than 10 megabits per second. Furthermore, the size of the effective data per frame can be increased, in particular to about 2 kbytes (kilobytes) or any other value.

Fig. 3 shows on the left that the subscriber stations 10, 20, 30 transmit a signal can_ H, CAN _l onto the bus 40 in the arbitration phase 451, which signal alternately has at least one dominant state 401 or at least one recessive state 402. After arbitration in arbitration phase 451, one of the subscriber stations 10, 20, 30 determines as a winner. Suppose subscriber station 10 has won arbitration. The transmitting/receiving means 12 of the subscriber station 10 then switches its physical layer from the first operating mode (SLOW) to the second operating mode (FAST TX) at the end of the arbitration phase 451, since the subscriber station 10 is the transmitter of the message 45 in the data phase 452. The transmitting module 121 then generates states L0 or L1 for the signal can_ H, CAN _l on the bus 40 in the data phase 452 or in the second operating mode (fast_tx) in dependence on the transmission signal TxD one after the other and thus in series. The frequency of signal CAN H, CAN L CAN be increased in the data phase 452, as shown on the right side in fig. 3. The net data transfer rate is thus increased in the data stage 452 compared to the arbitration stage 451. In contrast, the transmitting/receiving device 12 of the subscriber station 30 switches its physical layer from the first operating mode (SLOW) to the third operating mode (fast_rx) at the end of the arbitration phase 451, since the subscriber station 30 is only the receiver of the frame 450, i.e. not its transmitter, in the data phase 452. After the end of the arbitration phase 451, all transmitting/receiving devices 12 of the subscriber stations 10, 30 switch their operating mode into a first operating mode (SLOW). Therefore, all the transmitting/receiving devices 12 also switch their physical layers.

According to fig. 4, in the arbitration phase 451, a differential signal vdiff=can_h-can_l is ideally formed on the bus 40, which has a value of vdiff=2v for the dominant state 401 and a value of vdiff=0v for the recessive state 402. This is shown on the left side in fig. 4. In contrast, in the data phase 452, a differential signal vdiff=can_h-can_l is formed on the bus 40, which differential signal has states L0, L1, as shown on the right side in fig. 4. State L0 has a value of vdiff=1v. State L1 has a value of vdiff= -1V. The receiving module 122 can distinguish between the states 401, 402 and L0, L1 using receiving thresholds in the ranges th_t1, th_t2, th_t3, respectively. The receiving module 122 uses at least a receiving threshold T1 of, for example, 0.7V in the arbitration phase 451. The receiving module 122 uses a receiving threshold T2 of, for example, -0.35V, for example in the arbitration phase 451, if necessary, however also in the data phase 452. A receive threshold T3 of, for example, 0.0V is used in the data stage 452. Upon switching between the first to third modes of operation (SLOW, fast_tx, fast_rx) described above with respect to fig. 3, the reception module 122 switches the reception thresholds, respectively.

Fig. 5 shows an embodiment for a part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451 and thereby generates the signal can_ H, CAN _l for the bus 40. In fig. 5, the transmission signal TxD transitions from the state LW (low=low) to the state HI (high=high) and again transitions back to the state LW (low=low).

As is shown in more detail in fig. 6, the transmission module 121 generates the signal can_ H, CAN _l for the bus lines 41, 42 for the transmission signal TxD of fig. 5 in such a way that additionally a state 403 (sic) is present. The state 403 (sic) can be of different lengths of time, as shown with state 403_0 (sic) when transitioning from state 402 (rec) to state 401 (dom), and with state 403_1 (sic) when transitioning from state 401 (dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic). To generate the signal according to fig. 6, the transmitting module 121 switches into the SIC operation mode (SIC mode).

The shorter sic state 403_0 is not required to run in CiA610-3 and depends on the type of implementation. The temporal duration of the "longer" state 403_1 (SIC) is designated in CAN-XL for CAN-SIC and also for SIC operation as t_sic < 530ns, starting with the rising edge at the transmit signal TxD of fig. 5.

The transmitting module 121 should adapt the impedance between the bus lines 41 (CANH) and 42 (CANL) in the "longer" state 403_1 (sic) as well as possible to the characteristic wave resistance (WELLENWIDERSTAND) Zw of the bus line used. Zw=100 ohms or 120 ohms are suitable here. This adaptation prevents reflections (Reflexionen) and thus allows operation at higher bit rates. For simplicity, the state 403 (sic) or sic state 403 is always referred to hereinafter.

The transmitting module 121 CAN be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL.

Table 1: CAN type for the transmitting module 121.

Thus, not only CAN the transmit module status SIC be generated in CAN-SIC or CAN-XL (xl_sic). Furthermore, the transmit module status sic CAN be generated in the CAN-FD. In CAN-FD, the time for the transmit module state SIC CAN however be shorter than in CAN-SIC or CAN-XL.

Fig. 7 shows an embodiment for the other part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in a data phase 452 and thereby generates the signal can_ H, CAN _l for the bus 40. In fig. 7, the transmission signal TxD is shifted from the state HI (high=high) to the state LW (low=low) and again to the state HI (high=high) a plurality of times and so on.

As shown in more detail in fig. 8, the transmission module 121 generates the signal can_ H, CAN _l for the bus lines 41, 42 for the transmission signal TxD of fig. 7 in such a way that a state L0 for the state LW (low=low) is formed. Further, a state L1 for the state HI (high=high) is constructed.

Fig. 9 shows a basic structure of a transmitting module 121 for one of the subscriber stations 10, 30. The transmitting module 12 CAN generate a signal can_ H, CAN _l according to fig. 5 with states 401, 402, 403 and a signal can_ H, CAN _l according to fig. 8 with states L0, L1.

The transmitting module 121 has four transmitting stages, namely, a first transmitting stage 121A, a second transmitting stage 121B, a third transmitting stage 121C, and a fourth transmitting stage 121D. As shown in fig. 9, the transmitting stages 121A to 121D are coupled as a full bridge. Further, the transmission module 121 has flow restriction modules 1211, 1212. The components of the flow-limiting modules 1211, 1212 and the transmission stages 121A to 121D, which are described in more detail below, are controlled by at least one control device 124. At least one control device 124 sends at least one signal to a control connection 125, to which the current limiting modules 1211, 1212 and/or components of the sending stages 121A to 121D are coupled. For clarity, not all wire connections for this are shown in fig. 9.

The transmitting module 121 is coupled to the bus 40, more precisely to a first bus line 41 of the bus for can_h or CAN-xl_h and to a second bus line 42 of the bus for can_l or CAN-xl_l. Each of the transmit stages 121A through 121D is coupled to the bus 40.

The voltage Supply is carried out via at least one connection 43 for supplying the first and second bus-line conductors 41, 42 with electrical energy, in particular with a voltage CAN-Supply of typically 5V. Connection to ground or can_gnd is achieved via connection 44. The first and second bus lines 41, 42 terminate with a termination resistor 49. Termination resistor 49 is coupled into the full bridge as an external load resistor. Resistor 49 is coupled into the bridge leg between the junctions for bus wires 41, 42.

The first transmission stage 121A of fig. 9 has an inverse diode d_a, a transistor hvp_a, and a parallel circuit 121A1 in which first to nth current stages are connected in parallel, where n is a natural number > 1. Furthermore, a steering circuit t_a is present. The first current stage has a series circuit of a resistor r_a1 and a transistor p_a1. The nth current stage has a series circuit of a resistor r_an and a transistor p_an. The transistor hvp_a can be a CMOS transistor, in particular a PMOS transistor. The transistors p_a1 to p_an are CMOS transistors, in particular PMOS transistors. The abbreviation "CMOS" means a semiconductor element in which not only a p-channel MOSFET but also an n-channel MOSFET is used on a common substrate. The abbreviation CMOS means the english name "Complementary metal-oxide-semiconductor", which means "complementary metal oxide semiconductor" after translation. The abbreviation "MOSFET" means metal oxide field effect transistor. The control circuit t_a controls the transistors p_a1 to p_an of the first to n-th current stages in accordance with the transmission signal TxD and the set operating modes SIC, fast_tx of the transmission module 121.

The second transmitting stage 121B of fig. 9 has an inverse diode d_b, a transistor hvn_b, and a parallel circuit 121B1 in which first to nth current stages are connected in parallel, where n is a natural number > 1. Furthermore, a steering circuit t_b is present. The first current stage S1 has a series circuit of a resistor r_b1 and a transistor n_b1. The nth current stage has a series circuit of a resistor r_bn and a transistor n_bn. The transistor hvp_b can be a CMOS transistor, in particular an NMOS transistor. The transistors n_b1 to n_bn are CMOS transistors, in particular NMOS transistors. The control circuit t_b controls the transistors n_b1 to n_bn of the first to N-th current stages in accordance with the transmission signal TxD and the set operating modes SIC, fast_tx of the transmission module 121.

The third transmitting stage 121C of fig. 9 has an inverse diode d_c, a transistor hvp_c, and a parallel circuit 121C1 in which first to nth current stages are connected in parallel, where n is a natural number > 1. Furthermore, a steering circuit t_c is present. The first current stage has a series circuit of a resistor r_c1 and a transistor p_c1. The nth current stage has a series circuit of a resistor r_an and a transistor p_an. The transistor hvp_c can be a CMOS transistor, in particular a PMOS transistor. The transistors p_c1 to p_cn are CMOS transistors, in particular PMOS transistors. The control circuit t_c controls the transistors p_c1 to p_cn of the first to n-th current stages in accordance with the transmission signal TxD and the set operating modes SIC, fast_tx of the transmission module 121.

The fourth transmitting stage 121D of fig. 9 has an inverse diode d_d, a transistor hvn_d, and a parallel circuit 121D1 in which first to nth current stages are connected in parallel, where n is a natural number > 1. Furthermore, a steering circuit t_d is present. The first current stage has a series circuit of a resistor r_d1 and a transistor n_d1. The nth current stage has a series circuit of a resistor r_dn and a transistor p_dn. The transistor hvp_d can be a CMOS transistor, in particular an NMOS transistor. The transistors n_d1 to n_dn are CMOS transistors, in particular NMOS transistors. The control circuit t_d controls the transistors n_d1 to n_dn of the first to N-th current stages in accordance with the transmission signal TxD and the set operating modes SIC, fast_tx of the transmission module 121.

The current stages S1 to Sn of the transmitting stages 121A to 121D are thus designed as resistive stages. The resistance stage is set by selecting the resistance value of the corresponding current stage, for example, by selecting the resistances r_a1 to r_an and the like for the transmission stage 121A. The current level is set due to the setting of the resistance value of the resistor. The number n can be arbitrarily selected. In particular, the number n and thus the number of stages or numbers of resistor stages or current stages can be selected between 1 and 60. Alternatively, however, a number greater than 60 can be selected for n.

Each of the counter diodes d_ A, D _ B, D _ C, D _d protects the associated transmitting stage against positive feedback to the connection 44 (CAN-Supply) and negative feedback to the connection 43 (can_gnd). Each of the reverse diode d_ A, D _ B, D _ C, D _d can also be referred to as a blocking diode.

Each of the parallel circuits 121A1, 121B1, 121C1, 121D1 has a hierarchical circuit, more precisely an associated control circuit t_ A, T _ B, T _ C, T _d, which is an associated transmission stage 121A, 121B, 121C, 121D, which sets a resistance value as a function of the operating mode (SLOW or SIC, fast_tx) of the transmission module 121 and as a function of the transmission signal TxD. The resistance values of the individual transmission stages 121A, 121B, 121C, 121D can thus be set according to the operating mode (SLOW or SIC, fast_tx) of the transmission module 121 and the transmission signal TxD. This is described in more detail below with reference to fig. 10 and 11 and tables 2 and 3.

Each of the transistors hvp_ A, HVN _ B, HVP _ C, HVN _d is an HV cascode structure and can also be referred to as an HV isolation device. The transistor hvp_a protects the CMOS transistors p_a1 to p_an of the parallel circuit 121A1 to which it is attached by: the transistor hvp_a absorbs (aufnehmen) the high voltage drop. Each of the transistors hvn_ B, HVP _ C, HVN _d has the same function for the CMOS transistors of the parallel circuits 121B1, 121C1, 121D1 respectively associated. Each of the transistors hvp_ A, HVN _ B, HVP _ C, HVN _d is coupled at its control terminal to terminal 125. Thus, each of the transistors hvp_ A, HVN _ B, HVP _ C, HVN _d can be controlled by the at least one control device 124.

The current limiting modules 1211, 1212 are each designed as a transistor. The current limiting modules 1211, 1212 are CMOS transistors, respectively, in the embodiment of fig. 9. The current limiting module 1211 of fig. 9 is a PMOS transistor. Thus, the current limiting module 1211 forms a power source. The current limiting module 1212 of fig. 9 is an NMOS transistor. Thus, the current limiting module 1212 forms a current sink (Stromsenke). The current limiting modules 1211, 1212 are provided for protecting the transmission module 121 and external components, in particular the subscriber station 10 and/or other components of the bus 40. The arrangement of the current limiting modules 1211, 1212 in the circuit of the transmitting stage 121 is adapted for the dom state 401 of fig. 6 and for the sic state 403. According to the design and specifications, twice as much current as in the sic state flows in the dom state 401, however, current flows in the dom state 401 on only one path of the transmitting module 121. Instead, current flows in two paths of the transmitting module 121 in the sic state. Both paths are of identical design or configuration. Thus, the same voltage drop occurs at the current limiting modules 1211, 1212.

In the transmitting module 121, the transmitting stage 121A is coupled between the connection 43 for the voltage supply and the connection 41 (CANH) for the signal can_h. The transmitting stage 121C is coupled between the connection 43 for the voltage supply and the connection 42 (CANL) and the connection 43 or the connection 44 for the ground (can_gnd). The transmitting stage 121D is coupled between the connection 41 (CANH) for the signal can_h and the connection 43 or the connection 44 (can_gnd) for the ground. The transmitting stage 121B is coupled between a connection 42 (CANL) for the signal can_l and a connection 43 or a connection 44 (can_gnd) for ground. Thus, in the transmitting module 121, on the one hand, the transmitting stage 121A is coupled into the CANH path. On the other hand, the transmitting stage 121D is coupled into the CANH path. In one aspect, the transmit stage 121C is coupled to a path in CANL. On the other hand, the transmitting stage 121B is coupled into the CANL path.

Therefore, the transmitting module 121 is configured by the parallel circuits 121A1, 121B1, 121C1, 121D1 of the determined number of current stages in the CANH path and in the CANL path. The individual current stages are realized by a series circuit of CMOS switches and resistors, as described above. The parallel circuit of all current stages is coupled in series with HV cascode structure hvp_ A, HVN _ B, HVP _ C, HVN _d and counter diode d_ A, D _ B, D _ C, D _d in the CANH path and in the CANL path as described previously. The HV cascode structure hvp_ A, HVN _ B, HVP _ C, HVN _d is able to achieve voltages of-27V to +40V following the limit values (maximum rated parameters), like CANH and CANL.

The functional manner of the circuit of fig. 9 depends on the bus states 401 (dom), 403 (SIC), 402 (rec) in the operation manner of the transmitting module 121 and the SIC operation manner (arbitration phase 451) and L0, L1 in the data phase 452 are explained according to table 2 below. Table 2 shows the impedance required according to the state of the transmitting module 121 and the impedance of the transmitting stage 121A/121B and the impedance of the transmitting stage 121C/121D according to the state of the transmitting module 121 and the operation of the stages 451, 452.

Table 2: depending on the impedance required for the transmission state.

If the impedance is "infinite", the transmitting module 121 or the respective transmitting stage 121A, 121B, 121C, 121D is switched off or non-conductively.

The division of each parallel circuit 121A1, 121B1, 121C1, 121D1 of fig. 9 into n sections or n current levels allows for a time-interleaved (gestaffelt) and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC mode of operation) 451 or between the bus states L0, L1 of the data phase 452. For this purpose, the resistance values of the resistances of the n current levels are set, as is shown in the specific embodiment using fig. 10.

Fig. 10 shows an exemplary embodiment of the current levels for each switching stage or current stage S1 to S12. Thus, twelve current stages S1, S2 to S6 to S12 are used for each of the parallel circuits 121A1, 121B1, 121C1, 121D1 in the illustrated embodiment. Then n=12 applies.

The value of the current I (vertical axis in fig. 10) or I1, I2, I6, I12, etc. is set by selecting the series resistance value of the respective current stage S1 to S12. The individual current stages S1 to S12 (horizontal axis in fig. 10) therefore have different resistance values.

To generate the bus states 401, 402, 403 in the arbitration phase (SIC operation mode) 451 or the bus states L0, L1 of the data phase 452, the individual current stages S1 to S12 are switched on or off in a time-staggered manner by means of the CMOS transistors of the current stages S1 to S12. Thus, a corresponding current I flows in the CANH path or CANL path to which the upper transmission stage 121A, 121B, 121C, 121D is coupled.

It is particularly advantageous to design the interleaving (interleaving stage) and the resistance of each switching stage or current stage S1 to S12 in such a way that the form of the differential signal VDIFF follows a gaussian error function. Thus producing the least radiation in an analytical manner.

For the transition from state 402 (recessive) to state 401 (dominant) corresponding to the rising edge of the differential voltage VDIFF of fig. 4, the current in the CANH path and in the CANL path is gradually increased by switching on the resistances of the parallel circuits 121A1, 121B1, 121C1, 121D1 with a time offset for generating a dominant level at the bus 40. The transition from state 401 (dominant) to state 402 (recessive), corresponding to the falling edge of differential voltage VDIFF of fig. 4, is correspondingly achieved by switching off the resistances of parallel circuits 121A1, 121B1, 121C1, 121D1 in a time-staggered manner, thereby gradually reducing the current in the CANH and CANL paths. The total current, which is given by the sum of the currents I1 to I12 or I1 to In of all current stages S1 to Sn, flows during state 401 (dominant). Here, all current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 are connected in, and the total current for generating a dominant level of nominal vdiff=2v flows through the bus resistance or termination resistance 49.

As described above, by setting and selecting the current levels of the individual current levels S1 to S12 in time by means of the setting of the resistance values of the resistors of the current levels, it is possible to adapt the bus signals can_ H, CAN _l to one another during the transition between the states 401, 402, so that a symmetrical profile of can_h and can_l according to fig. 6 is achieved. The configuration of the transmitting module 121 enables the respective current levels of the parallel circuits 121A1, 121B1, 121C1, 121D1 to be connected in a time-staggered manner. By means of this time control, it is then possible to adapt the signal shapes of can_h and can_l, as is required according to fig. 6. A targeted shape (shaping) of the signal profiles for can_h and can_l CAN be achieved. In general, the bus states 401, 402, 403 of the arbitration phase (SIC operation mode) 451 or the bus states L0, L1 of the data phase 452 can be shaped according to a preset.

The resistances of the individual current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 and thus their respective occupation ratios at the total current can be selected in different ways in order to achieve as low radiation, in particular low radiation, of the transmitting module 121 as possible. For lower emissions, it is advantageous to switch on or off less current I (higher resistance value) at the beginning and end of the switching process between the bus states 401, 402 and to switch on or off more current (lower resistance value) in the middle of the switching process. Therefore, the setting shown in fig. 10 for the currents of the current stages S1 to S12 is very advantageous.

In contrast to the implementation with the same resistances in the current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1, the configuration according to fig. 10 avoids an increase in current during the off, transition from state 401 (dominant) to state 402 (recessive).

The granularity of the temporal interleaving (STAGGERING (spread tuning)) for switching on or off the individual current stages S1 to S12 is in the range of about 2 ns. Such small levels or steps for temporal interleaving cause lower common-mode interference and have lower negative impact on radiation. The voltage steps set by the resistances or resistance levels of the current stages S1, S2 to S6 to S12 remain fixed, and the temporal interleaving changes, so that the characteristics (as a gaussian error function) that are as soft as possible are set during the switching-in process. The change in the time steps or time levels furthermore prevents the occurrence of narrowband frequency lines in the radiation spectrum.

Alternatively, the interleaving step (stagger tuning step) can be implemented by a fixed time step and a varying voltage step.

By the illustrated structure of the transmitting module 121, a symmetrical switching of the bus signals can_h and can_l (fig. 6) between the bus states 401, 402, 403 in the arbitration phase (SIC mode of operation) 451 or between the bus states L0, L1 of the data phase 452 CAN be achieved at steep switching edges.

On the one hand, with the illustrated construction of the transmitting module 121, a much steeper switching edge is achieved between the bus states 401, 402, 403 in the arbitration phase (SIC mode of operation) 451 or between the bus states L0, L1 of the data phase 452 due to the use of fast CMOS switches or CMOS transistors. On the other hand, the symmetry of the time profiles of the bus signals can_h and can_l necessary for following the radiation limit is achieved during the switching process. Balancing (matching) of the characteristic curves is achieved by selecting or using the resistances of the parallel circuits 121A1, 121B1, 121C1, 121D 1. Therefore, the balance (matching) of the characteristic curves is less dependent on the parameters of the transistors used for the parallel circuits 121A1, 121B1, 121C1, 121D 1.

The CMOS transistors of the transmitting stages 121A1, 121B1, 121C1, 121D1 operate as switches, that is to say with a maximum voltage between the gate and source connections. The balancing (matching) of the individual transmission stages 121A1, 121B1, 121C1, 121D1 is thus decisively dependent on the balancing (matching) of the resistors r_a1 to r_an, r_b1 to r_bn, r_c1 to r_cn, r_d1 to r_dn and no longer on the transistors p_a1 to p_an and p_c1 to P_cn (PMOS) at the bus-line core 41 (CANH) and the transistors n_d1 to n_dn and n_b1 to N_bn (NMOS) at the bus-line core 42 (CANL).

The dominant state 401 (dom) is determined by balancing (matching) the resistors r_a1 to r_an (the transmission stage 121A) with the resistors r_b1 to r_bn (the transmission stage 121B). The term "balancing" here and also in the following means an active trimming step according to a possible scheme. According to other possible variants, "balancing" means that the resistance values cooperate as well as possible, which is done according to the standard without a balancing step or a trimming step.

The Sic state (Sic) is determined by balancing (matching) the resistors r_a1 to r_an (the transmission stage 121A) and the resistors r_c1 to r_cn (the transmission stage 121C) and balancing (matching) the resistors r_d1 to r_dn (the transmission stage 121D) and the resistors r_b1 to r_bn (the transmission stage 121B).

In the operating mode XL-Fast, the state L0 is determined by the balancing (matching) of the resistors R_A1 to R_An (transmission stage 121A) and the resistors R_B1 to R_Bn (transmission stage 121B). The state L1 is determined by balancing (matching) the resistors r_c1 to r_cn (the transmission stage 121C) and the resistors r_d1 to r_dn (the transmission stage 121D). The switching resistance Ron of the respective transistors of the transmission stages 121A1, 121B1, 121C1, 121D1 should be significantly smaller than the resistance of the respective series connection of the individual current stages of the transmission stages 121A1, 121B1, 121C1, 121D 1.

Fig. 11 shows a specific embodiment for the structure of the transmitting stage 121B of fig. 9. Thus, the transmitting stage 121B has three current stages s_ I, S _ii, s_iii in the parallel circuit 121B 1. The first current stage s_i has a resistor r_b1_i and a transistor n_b1_i coupled in series. The second current stage s_ii has a resistor r_b1_ii and a transistor n_b1_ii connected in series. The third current stage s_iii has a resistor r_b1_iii and a transistor n_b1_iii coupled in series.

For the following description of the circuit of fig. 9 with the configuration according to fig. 11, it is to be assumed that each of the transmission stages 121A, 121C, 121D also has three current stages s_ I, S _ii, s_iii according to the embodiment of fig. 11 in its associated parallel circuit 121A1, 121C1, 121D 1.

Table 3 below shows three transistors n_b1_ I, N _b1_ii, n_b1_iii of the transmitting stage 121B of fig. 11 and the corresponding transistors of the transmitting stages 121A, 121C, 121D of fig. 9, depending on the transmitting stage 121A/121B and the transmitting stages 121C, 121D, respectively.

Table 3: depending on the impedance required for the transmission state.

In this way, the use of the transmitting module 121 makes it possible to produce the required steeper edges at the bus signals can_h and can_l and to follow the radiation limits.

Alternatively, more than three current levels can be used in the respective transmitting stages 121A, 121B, 121C, 121D, as described previously.

Fig. 12 shows a transmission module 1210 according to the second embodiment. The transmission module 1210 is configured into a plurality of parts in the same manner as the transmission module 121 according to the first embodiment. Therefore, only the differences from the first embodiment are described hereinafter.

Unlike the first embodiment, the transmission module 1210 has transmission stages 121A0, 121B0, 121C0, 121D0 according to the present embodiment. The transmitting stages 121A0, 121B0, 121C0, 121D0 are coupled as full bridges. Termination resistor 49 is coupled into the bridge leg between the junctions for bus wires 41, 42. Further, the transmission module 1210 has first to xth flow limiting modules 1211_1 to 1211x and first to xth flow limiting modules 1212_1 to 1212_x in place of the flow limiting modules 1211, 1212. Here, x is a natural number > 1.

The current limiting modules 1211_1 to 1211_x, 1212_1 to 1212_x are respectively designed as transistors. The current limiting modules 1211_1 to 1211_x, 1212_1 to 1212_x are CMOS transistors in the embodiment of fig. 12, respectively. The current limiting modules 1211_1 to 1211_x of fig. 12 are PMOS transistors, respectively. Accordingly, the current limiting modules 1211_1 to 1211_x respectively form power sources. The current limiting modules 1212_1 to 1212_x of fig. 12 are NMOS transistors, respectively. Thus, the current limiting modules 1212_1 to 1212_x respectively form current sink grooves.

Unlike the transmission stage 121A of the first embodiment having the transistor hvp_a, the transmission stage 121A0 has the first to y-th transistors hvp_a1 to hvp_ay, where y is a natural number > 1. Each of the first to y-th transistors hvp_a1 to hvp_ay is a CMOS transistor, in particular a PMOS transistor, as described above with respect to fig. 9 for the transistor hvp_a.

Unlike the transmission stage 121B of the first embodiment having the transistor hvn_b, the transmission stage 121B0 has the first to y-th transistors hvn_b1 to hvn_by, where y is a natural number > 1. Each of the first to y-th transistors hvn_b1 to hvn_by is a CMOS transistor, in particular an NMOS transistor, as described above with respect to fig. 9 for the transistor hvp_b.

Unlike the transmission stage 121C of the first embodiment having the transistor hvp_c, the transmission stage 121C0 has the first to y-th transistors hvp_c1 to hvp_cy, where y is a natural number > 1. Each of the first to y-th transistors hvp_c1 to hvp_cy is a CMOS transistor, in particular a PMOS transistor, as described above with respect to fig. 9 for transistor hvp_c.

Unlike the transmission stage 121D of the first embodiment having the transistor hvn_d, the transmission stage 121D0 has the first to y-th transistors hvn_d1 to hvn_dy, where y is a natural number > 1. Each of the first to y-th transistors hvn_d1 to hvn_dy is a CMOS transistor, particularly an NMOS transistor, as described above with respect to fig. 9 for the transistor hvp_d.

The transmission module 1210 of fig. 12 has the following functions in addition to the functions of the transmission module 121 according to the first embodiment.

Based on its design, the transmission module 1210 can reduce effects due to the asymmetrical nature of the transmission stage, which can occur in the transmission states dom (401), sic (403), rec (402) and increase overshoot and thus deteriorate the radiation. The transmit module 1210 blocks the non-identical characteristics of the components in the transmit stages 121A0, 121B0 of the full bridge of fig. 12 (effect 1), thereby minimizing or preventing the variation of the common mode voltage in the dom state 401 compared to the rec state 402.

In order to prevent effect 1, the resistance Ron (switching resistance) of the cascode structure in the transmitting stage 121A0, 121B0 can be varied, in particular by actuation using a respectively associated actuation circuit t_ A, T _b. This is achieved By varying up to y parallel-coupled transistors hvp_a1 to hvp_ay and/or up to y parallel-coupled transistors hvn_b1 to hvn_by. In order not to change the symmetry of the two series circuits of the transmitting stages 121A0, 121D0 and the transmitting stages 121C0, 121B0 in the sic state 403, the cascode structure of the transmitting stages 121D0, 121C0 must also undergo the same change. Thus, up to y parallel-coupled transistors hvn_d1 to hvp_dy and/or up to y parallel-coupled transistors hvp_c1 to hvp_cy also vary correspondingly. To this end, each of the transistors hvp_a1 to hvp_ay, hvn_b1 to hvn_by, hvp_c1 to hvp_cy, hvn_d1 to hvp_dy is coupled at its control terminal (gate terminal) to terminal 125. Thus, each of these transistors can be controlled by at least one control device 124. Intervention for correction of the common mode level in the dom state 401 is achieved By changing hvp_a1 to hvp_ay and hvp_c1 to hvp_cy similarly or identically or By changing hvp_d1 to hvn_dy and hvp_b1 to hvn_by similarly or identically.

Furthermore, the transmit module 1210 is capable of preventing the non-identical characteristics of the components in the transmit stages 121A0/121D0 and 121C0/121B0 of the full bridge (effect 2), thereby minimizing or preventing the variation of the common mode voltage in the sic state compared to the rec state 402.

For this purpose, the resistance Ron (switching resistance) of the current limiting transistors or current limiting modules 1211, 1212 can be varied. This is achieved by up to x parallel-connected flow-limiting modules 1211_1 to 1211_x and/or up to x parallel-connected flow-limiting modules 1212_1 to 1212_x, in particular by actuation by means of at least one control device 124. Intervention for correction of the common mode level in the sic state 403 is achieved by up to x parallel coupled current limiting modules 1211_1 to 1211_x or up to x parallel coupled current limiting modules 1212_1 to 1212_x. For example, x=4 applies. In this case, four different levels of the resistance Ron (switching-in resistance) of the current limiting transistors or current limiting modules 1211, 1212 can be set.

This blocking of effect 2 is particularly advantageous because sufficient radiation results can only be obtained when the common mode level in the dom state 401 and in the sic state 403 is adapted to the common mode level of the rec state 402 starting from the common mode level of the rec state 402, however, the cause of the characteristics leading to effect 1 may be different from the cause leading to effect 2.

The configuration of the transmission module 1210 prevents, in particular, that the substrate current losses in the diode inverters d_a and d_b lead to a common-mode level in the dom state 401 no longer being identical (stimmen). In the sic state, the counter diodes d_a and d_b are not energized so strongly, and furthermore all the counter diodes d_ A, D _ B, D _ C, D _d of the four transmitting stages 121A0, 121B0, 121C0, 121D0 are activated. The transmit module 1210 is capable of preventing different common mode levels from being present in the dom state and in the sic state. In addition, it can be prevented that the same effect is produced qualitatively (qualitativ) due to the different properties in the cascode structure.

The transmission module 1210 can thus positively influence the effect on the radiation value of the transmission/reception device 12, which is decisively influenced by the transmission module 1210.

All the previously described designs of the transmission module 121, 1210, the transmission/reception device 12, 22, the subscriber station 10, 20, 30, the bus system 1 and the method implemented therein according to the first and second embodiments and variants thereof can be used individually or in all possible combinations. In addition, the following variants are particularly conceivable.

The previously described bus system 1 according to the first and second embodiments is described in terms of a CAN-protocol based bus system. However, the bus system 1 according to the first and/or second embodiment can alternatively be another type of communication network in which signals are transmitted as differential signals. It is advantageous, but not mandatory, to ensure in the bus system 1a special, collision-free access to the bus 40 by the subscriber stations 10, 20, 30 at least for a determined period of time.

The bus system 1 according to the first and/or second embodiment and variants thereof is in particular a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 can be another communication network in which signals are transmitted as differential signals and serially through the bus.

The functionality of the embodiments described above CAN thus be used, for example, in the transmitting/receiving device 12, 22, which CAN be operated in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or CANXL bus system.

It is possible that for both bus states 401, 402 no explicit and implicit bus state is used at least temporarily, but in other words a first bus state and a second bus state, both bus states being driven. An example for such a bus system is a CAN XL bus system.

The number and arrangement of subscriber stations 10, 20, 30 in the bus system 1 according to the first and second embodiments and variants thereof is arbitrary. In particular, only the subscriber station 10 or only the subscriber station 30 is present in the bus system 1 of the first embodiment or the second embodiment.

Claims (15)

1. A transmission module (121; 1210) for transmitting differential signals in a serial bus system (1), the transmission module having:

A first transmission stage (121A; 121A 0) for generating a transmission current (I1 to In) for a first signal (CAN_H) which CAN be transmitted to a bus (40) of the bus system (1),

A second transmission stage (121B; 121B 0) for generating a transmission current (I1 to In) for a second signal (CAN_L) which CAN be transmitted onto the bus (40) as a differential signal with respect to the first signal (CAN_H),

A third transmission stage (121C; 121C 0) for generating a transmission current (I1 to In) for the first signal (CAN_H), and

A fourth transmission stage (121D; 121D 0) for generating a transmission current (I1 to In) for the second signal (CAN_L),

Wherein the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) are coupled in a full bridge in which the first and fourth transmission stages (121A, 121D;121A0, 121D 0) are coupled in series and the third and second transmission stages (121C, 121B;121C0, 121B 0) are coupled in series,

Wherein each of the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) has at least two current stages (S1 to Sn) coupled in parallel with respect to each other,

Wherein each of the at least two current stages (S1 to Sn) has a switchable resistance (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and

Wherein the switchable resistances (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the transmission stages (121A to 121D;121A0 to 121D 0) have different resistance values.

2. The transmitting module (121; 1210) according to claim 1, wherein the output connection (41, 42) of the full bridge is provided for coupling with a termination resistor (49) of the bus (40).

3. The transmitting module (121; 1210) according to claim 1 or 2, wherein the number n of the at least two current stages (S1 to Sn) is the same for each of the first to fourth transmitting stages (121A to 121D;121A0 to 121D 0), wherein n is a natural number greater than 1.

4. The transmitting module (121; 1210) according to any of the preceding claims, wherein each of the at least two current stages (S1 to Sn) has a CMOS transistor for switching the resistances (r_a1 to r_an; r_b1 to r_bn; r_c1 to r_cn; r_d1 to r_dn) of the current stages (S1 to Sn).

5. The transmitting module (121; 1210) according to any of the preceding claims,

Wherein the CMOS transistors of the current stages (S1 to Sn) of the first transmitting stage (121A; 121A 0) are PMOS transistors,

Wherein the CMOS transistors of the current stages (S1 to Sn) of the second transmission stage (121B; 121B 0) are NMOS transistors,

Wherein the CMOS transistors of the current stages (S1 to Sn) of the third transmission stage (121C; 121C 0) are PMOS transistors, and

Wherein the CMOS transistors of the current stages (S1 to Sn) of the fourth transmission stage (121D; 121D 0) are NMOS transistors.

6. The transmission module (121; 1210) according to any of the preceding claims 4 or 5, wherein each of the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) furthermore has:

A counter diode (D_A; D_B; D_C; D_D) for protection against positive feedback in the connection (43) for the bus voltage supply and against negative feedback in the connection (44) for the ground, and

At least one cascode structure (hvp_a; hvn_b; hvp_c; hvn_d) for protecting the CMOS transistors.

7. The transmitting module (1210) according to claim 6,

Wherein at least two cascode structures (HVP_A; HVN_B; HVP_C; HVN_D) are coupled in parallel with each other,

Wherein the number y of the cascode structures (hvp_a; hvn_b; hvp_c; hvn_d) is the same for each of the first to fourth transmission stages (121A to 121D;121A0 to 121D 0), wherein y is a natural number greater than 1, and

Wherein the access resistances of the at least two cascode structures (hvp_a; hvn_b; hvp_c; hvn_d) are different.

8. The transmitting module (121; 1210) according to any of the preceding claims, further having:

at least one first current limiting module (1211) as a power source, coupled between a connection (43) for the bus voltage supply and the full bridge, and

At least one second current limiting module (1212) as a current sink is coupled between the connection (44) for the ground and the full bridge.

9. The transmitting module (1210) according to claim 8,

Wherein at least two first current limiting modules (1211_1 to 1211_x) are coupled in parallel to each other, their access resistances are different,

Wherein at least two second current limiting modules (1212_1 to 1211_x) are coupled in parallel to each other, their access resistances are different, and

Wherein the number x of the first current limiting modules (1211_1 to 1211_x) is equal to the number x of the second current limiting modules (1212_1 to 1211_x), wherein x is a natural number greater than 1.

10. The transmitting module (121; 1210) according to any of the preceding claims, further having:

-a control circuit (T_A; T_B; T_C; T_D) for controlling the switchable components of the first to fourth transmission stages (121A to 121D, 121A0 to 121D 0) in dependence on a digital transmission signal (TxD) and in dependence on a mode of operation (SIC; FAST_TX) set for the transmission module (121; 1210).

11. The transmitting module (121; 1210) according to claim 10, wherein the steering circuit (t_a; t_b; t_c; t_d) is designed for the temporally staggered and controlled switching of the resistance values of the at least two current stages (S1 to Sn).

12. A transmitting/receiving device (12; 22) for a subscriber station (20) of a serial bus system (1) has:

The transmitting module (121; 1210) according to any of the preceding claims, and

-A receiving module (122) for receiving signals of the bus (40).

13. Subscriber station (10; 20; 30) for a serial bus system (1), having:

The transmitting/receiving device (12; 22) according to claim 12, and

Communication control means (11; 21) for controlling the communication in the bus system (1) and for generating a digital transmission signal (TxD) for actuating the first to fourth transmission stages (121A to 121D;121A0 to 121D 0).

14. Subscriber station (10; 20; 30) according to claim 13, wherein the subscriber station (10; 20; 30) is designed for communication in the bus system (1) in which a special, collision-free access of a subscriber station (10, 20, 30) to a bus (40) of the bus system (1) is ensured at least temporarily.

15. Method for transmitting differential signals in a serial bus system (1), wherein the method is implemented with a transmitting module (121; 1210), and wherein the method has the following steps:

Generating a transmission current (I1 to In) for a first signal (CAN_H) by means of a first transmission stage (121A; 121A 0), which CAN be transmitted to a bus (40) of the bus system (1),

Generating a transmission current (I1 to In) for a second signal (CAN_L) by means of a second transmission stage (121B; 121B 0), which CAN be transmitted as a differential signal with respect to the first signal (CAN_H) onto the bus (40),

Generating a transmission current (I1 to In) for the first signal (CAN_H) using a third transmission stage (121C; 121C 0), and

Generating a transmission current (I1 to In) for the second signal (CAN_L) using a fourth transmission stage (121D; 121D 0),

Wherein the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) are coupled in a full bridge in which the first and fourth transmission stages (121A, 121D;121A0, 121D 0) are coupled in series and the third and second transmission stages (121C, 121B;121C0, 121B 0) are coupled in series,

Wherein each of the first to fourth transmission stages (121A to 121D;121A0 to 121D 0) has at least two current stages (S1 to Sn) coupled in parallel with respect to each other,

Wherein each of the at least two current stages (S1 to Sn) has a switchable resistance (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and

Wherein the switchable resistances (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the transmission stages (121A to 121D;121A0 to 121D 0) have different resistance values.