CN111713077B

CN111713077B - Subscriber station for a serial bus system and method for transmitting messages in a serial bus system

Info

Publication number: CN111713077B
Application number: CN201880090002.0A
Authority: CN
Inventors: S·沃克尔
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2017-12-22
Filing date: 2018-12-20
Publication date: 2022-02-22
Anticipated expiration: 2038-12-20
Also published as: WO2019122211A1; EP3744049A1; CN111713077A; DE102018202168A1

Abstract

A subscriber station (20; 30) for a bus system (1) and a method for transmitting messages at different bit rates in a bus system (1) are provided. The user station (20; 30) comprises a transmission stage (2200) for transmitting messages (4; 5) onto a bus line (3) of the bus system (1), wherein the transmission stage (2200) has an output stage (225, 226, 2270, 2280) for switching differential bus signals for a message (5) between a high bus state (461; 462) and a low bus state (471), wherein the transmission stage (2200) is designed such that for at least one first phase for transmitting data of the message (5) the differential bus signals (CAN _ EL _ H2; CAN _ EL _ L2) have the same level for the low bus state (471) and drive the low bus state (471) with low ohms, and wherein the transmission stage (2200) is designed such that for a second phase (453; 454; 455) for transmitting data of the message (5), a bus state (461) similar to the high bus state (462) has a smaller differential voltage between the differential bus signals (CAN _ EL _ H1; CAN _ EL _ L1) than the differential voltage between the differential bus signals (CAN _ EL _ H1; CAN _ EL _ L1) in the high bus state (462).

Description

Subscriber station for a serial bus system and method for transmitting messages in a serial bus system

Technical Field

The invention relates to a subscriber station for a serial bus system and to a method for transmitting messages in a serial bus system which operates at a high data rate and with great robustness against errors.

Background

For example, in vehicles, bus systems are frequently used for communication between sensors and control devices, in which data are transmitted as messages as standard ISO11898-l:2015 of the CAN protocol specification with CAN FD. Messages are transmitted between bus users of the bus system, such as sensors, control devices, transmitters (Geber), etc.

As the number of functions of technical devices or vehicles increases, the data communication in the bus system also increases. For this purpose, it is also often required that data be transmitted from the transmitter to the receiver more quickly than before. As a result, the required bandwidth of the bus system is further increased.

In order to be able to transmit data at a higher bit rate than in CAN, an option for switching to a higher bit rate is created within the message in CAN FD message format. With this technique, the maximum possible data rate is increased by using a higher timing (Taktung) in the range of the data field by a value exceeding 1 MBit/s. Such a message is also referred to as CAN FD frame or CAN FD message later. In CAN FD the effective data length is extended from 8 bytes up to 64 bytes and the data transfer rate is significantly higher than in CAN.

Even though CAN-or CAN FD-based communication networks offer a great advantage in view of their robustness, they have a significantly lower speed compared to data transmission in, for example, 100Base-T1 ethernet. Furthermore, the effective data length of up to 64 bytes achieved to date with CAN FD is too low for some applications.

Disclosure of Invention

It is therefore an object of the present invention to provide a subscriber station for a serial bus system and a method for transmitting messages in a serial bus system, which subscriber station and method solve the problems mentioned above. In particular, a user station for a serial bus system and a method for transmitting messages in a serial bus system are to be provided, with which a high data rate and an increase in the amount of useful data per frame can be achieved with great robustness to errors.

This object is achieved by a subscriber station for a serial bus system having the features of claim 1. The subscriber station comprises a transmitting stage for transmitting a message onto a bus line of the bus system, wherein the transmitting stage has an output stage for switching a differential bus signal for the message between a high bus state and a low bus state, wherein the transmitting stage is designed such that, for at least one phase of the data for transmitting the message, the differential bus signal has the same level for the low bus state and drives the low bus state with low impedance, and wherein the transmitting stage is designed such that, for a second phase of the data for transmitting the message, a bus state similar to the high bus state has a lower differential voltage than the differential voltage between the differential bus signals in the high bus state.

A significant increase in the bit rate and thus in the transmission speed from the transmitter to the receiver can be achieved with the subscriber station. In this case, however, a great robustness against errors is ensured at the same time.

The subscriber station based design no longer requires Error-Frames (Error-Frames). This also helps to achieve a net data rate of at least 10 Mbps. Also, the size of valid data may be up to 4096 bytes per frame.

Another advantage is that multiple domains can be connected to each other as needed via the switch. This reduces the wiring complexity between the individual components of the technical system or the vehicle. This is a particularly significant advantage in particular in vehicles with regard to less time consumption, reduced material use and thus reduced weight.

The method performed by the subscriber station CAN also be used if at least one CAN subscriber station and/or at least one CAN FD subscriber station transmitting messages according to the CAN protocol and/or the CAN FD protocol are also present in the bus system.

Further advantageous embodiments of the subscriber station are specified in the dependent claims.

According to one specific embodiment variant, the transmission stage is designed to switch to a first operating mode with two different first bus states for a message if data of a first phase are to be transmitted by the message, which data are to be transmitted at a first bit rate, and the transmission stage is designed to switch to a second operating mode with a high bus state and a low bus state for a message if data of a second phase are to be transmitted by the message, which second phase is to be transmitted at a second bit rate that is faster than the first bit rate.

According to a further specific embodiment, the transmitting stage is designed to switch to the second operating mode for transmitting data only if exclusive collision-free access to the bus lines of the bus system is guaranteed for the subscriber station within a predetermined time.

According to another specific embodiment, the transmitting stage has: a first output stage connected between a terminal for voltage supply and a first bus line; a second output stage which is connected between the second bus line and the terminal for ground, wherein the output stage operates more ohmically for a high bus state of the second phase of the data for transmitting messages than for a high bus state of the first phase of the data for transmitting messages.

According to another specific embodiment, the transmitting stage has: a first output stage connected between a terminal for voltage supply and a first bus line of a bus line; a second output stage connected between a second bus core of the bus line and a terminal for ground; a third output stage connected between the first bus core of the bus line and the first voltage source as a reference for a low bus state; and a fourth output stage connected between the second voltage source as a reference for the low bus state and the second bus conductor of the bus line.

It is conceivable that the first output stage has PMOS transistors and the second output stage has NMOS transistors. In this case, it is possible for the fourth output stage to have PMOS transistors and for the third output stage to have NMOS transistors.

Possibly, the output stages are designed to reduce the driver capability of the first and second output stages and to switch the third and fourth output stages on for low bus states.

It is possible that the message has a data field with a variable length, wherein the variable length is between 1 byte and 4096 bytes.

The previously described subscriber station can be part of a bus system which furthermore comprises a parallel bus line and at least two subscriber stations which are connected to one another via the bus line such that they can communicate with one another. In this case, at least one of the at least two subscriber stations is the previously described subscriber station.

Furthermore, the aforementioned object is achieved by a method for transmitting messages in a serial bus system according to claim 11. The method comprises the following steps: transmitting a message onto a bus line of the bus system with a transmitting stage of a subscriber station of the bus system, wherein the transmitting stage switches a differential bus signal for a message with an output stage between a high bus state and a low bus state, wherein the transmitting stage is designed such that for at least one phase of the data for transmitting the message the differential bus signal has the same level for the low bus state and drives the low bus state with low resistance, and wherein the transmitting stage is designed such that for a second phase of the data for transmitting the message the bus state similar to the high bus state has a smaller differential voltage than the differential voltage between the differential bus signals in the high bus state.

This method provides the same advantages as previously mentioned with respect to the subscriber station.

Other possible embodiments of the invention also include combinations of features or embodiments not explicitly mentioned previously or in the following with respect to the examples. The person skilled in the art will also add individual aspects here as an improvement or supplement to the corresponding basic form of the invention.

Drawings

The invention is described in more detail hereinafter with reference to the accompanying drawings and by way of example.

Fig. 1 shows a simplified block diagram of a bus system according to a first embodiment;

fig. 2 shows a diagram for illustrating the structure of a message that can be sent by a subscriber station of the bus system according to the first embodiment;

fig. 3 shows a circuit diagram of a transmit stage of a subscriber station of the bus system according to the first embodiment;

fig. 4 shows a diagram of an example of a time-voltage curve of differential bus signals CAN _ H and CAN _ L which are generated by the transmission stage according to the first embodiment for a part of a message;

fig. 5 shows a diagram of an example of the time-voltage curve of the bus signal after the switching of the transmitting stage according to the first embodiment into a faster data transmission operating mode than in fig. 4;

fig. 6 shows a diagram of an example of a time-voltage curve of the bus signals CAN _ H and CAN _ L for a part of a message in a second embodiment;

fig. 7 shows a circuit diagram of a transmit stage of a subscriber station of a bus system according to a second embodiment;

fig. 8 and 9 show diagrams of examples of time-voltage curves of differential bus signals for different parts of a message, respectively, in a third embodiment;

fig. 10 shows a circuit diagram of a transmit stage of a subscriber station of a bus system according to a third embodiment;

fig. 11 and 12 show diagrams of examples of time-voltage curves of differential bus signals for different parts of a message, respectively, in a fourth embodiment;

fig. 13 shows a circuit diagram of the coupling of the transmit stage of a subscriber station on a bus core of a bus system according to a fifth embodiment; and

fig. 14 shows a circuit diagram of the coupling of the transmit stages of subscriber stations on a bus core of a bus system according to a modification of the fifth embodiment.

In the figures, identical or functionally identical elements are provided with the same reference symbols, unless otherwise specified.

Detailed Description

Fig. 1 shows, as an example, a bus system 1, which is designed in particular substantially for a CAN bus system, a CAN FD bus system, a CAN EL bus system and/or variants thereof, as will be described later. The bus system 1 can be used in vehicles, in particular in motor vehicles, aircraft, etc., or in hospitals, etc.

In fig. 1, a bus system 1 has a particularly parallel bus line 3 to which a plurality of user stations 10, 20, 30 are connected. The messages 4, 5 can be transmitted in the form of signals serially between the individual user stations 10, 20, 30 via the bus line 3. The user stations 10, 20, 30 are, for example, control devices, sensors, display devices of a motor vehicle, etc.

As shown in fig. 1, the subscriber station 10 has a communication control device 11 and a transmission/reception device 12. And the subscriber station 20 has communication control means 21 and transmission/reception means 22. The subscriber station 30 has a communication control means 31 and a transmitting/receiving means 32. The transmit/receive

means

12, 22, 32 of the subscriber stations 10, 20, 30 are each connected directly to the bus line 3, even if this is not illustrated in fig. 1.

The communication control means 11, 21, 31 are each used to control the communication of the respective subscriber station 10, 20, 30 with another subscriber station of the subscriber stations 10, 20, 30 connected to the bus line 3 via the bus line 3.

The communication control device 11 CAN be implemented as a conventional CAN controller. The communication control device 11 creates and reads a first message 4, for example a typical CAN message 4. A typical CAN message 4 is constructed according to a typical basic format, in which case up to 8 number of data bytes CAN be included in the message 4. Alternatively, typical CAN message 4 is constructed as a CAN FD message in which a number of data bytes of up to 64 CAN be included, which data bytes are also transmitted at a significantly faster data rate than in the case of typical CAN message 4. In the latter case, the communication control means 11 are implemented as a conventional CAN FD controller.

The communication control means 21 create and read a second message 5, which is for example a modified CAN message 5. In this case, the modified CAN message 5 is constructed based on the CAN EL format, which is described in more detail with respect to fig. 2.

The communication control device 31 CAN be implemented to provide the transmitting/receiving device 32 with the exemplary CAN message 4 or CAN EL message 5 or to receive the exemplary CAN message 4 or CAN EL message 5 by the transmitting/receiving device 32, as required. The communication control device 21 thus creates and reads the first message 4 or the second message 5, the first and second messages 4, 5 being distinguished by their data transmission standard, i.e. CAN or CAN EL in this case. Alternatively, typical CAN message 4 is constructed as a CAN FD message. In the latter case, the communication control means 11 are implemented as a conventional CAN FD controller.

The transmitting/receiving means 12 may be implemented as a conventional CAN transceiver or CAN FD transceiver. The transmitting/receiving means 22 CAN be implemented as a CAN EL transceiver, except for the differences described in more detail later. The transmitting/receiving means 32 CAN be embodied to provide the communication control means 31 with messages 4 according to the current CAN base format or messages 5 according to the CAN EL format, or to receive messages 4 according to the current CAN base format or messages 5 according to the CAN EL format by the communication control means 31, as required. The transmitting/receiving means 22, 23 may additionally or alternatively be implemented as a conventional CAN FD transceiver.

The formation and then transmission of a message 5 in CAN EL format and the reception of such a message 5 CAN be realized with two subscriber stations 20, 30.

Fig. 2 shows a CAN El frame 45 for message 5 as transmitted by the transmitting/receiving device 22 or the transmitting/receiving device 32. The CAN-EL frame 45 is divided into different fields for CAN communication on the bus line 3, namely a start field 451, an arbitration field 452, a control field 453, a data field 454, a checksum field 455 and an end field 456.

The start field 451 has, for example, a bit, which is also referred to as SOF bit and indicates the start of a frame or the start of a frame. An identifier for identifying the sender of the message, in particular having 32 bits, is contained in the arbitration field 452. A Data-Length Code (Data-Length Code), in particular 13 bits long, is contained in the control field 453, which may have a value of up to 4096 with a step size of 1. The data field 454 contains the valid data of the CAN-EL frame or message 5. Valid data may have up to 4096 bytes depending on the value of the data length code. The checksum field 455 contains a checksum about the data in the data field 454 including a padding bit that is inserted by the transmitter of message 5 as an inverted bit after every 10 identical bits. The end field 456 contains at least one acknowledgement bit and furthermore contains a sequence of 11 identical bits indicating the end of the CAN EL frame 45. The receiver is informed, by means of at least one acknowledgement bit, whether an error has been found in the received CAN EL frame 45 or message 5.

In the phase for transmitting the arbitration field 452 and the end field 456, the physical layer is used as in CAN and CAN-FD. An important point during this phase is that a known CSMA/CR method is used which allows simultaneous access of the subscriber stations 10, 20, 30 to the bus line 3 without corrupting the higher priority messages 4, 5. It is thus possible to add the other bus user stations 10, 20, 30 to the bus system 1 relatively simply, which is very advantageous.

The CSMA/CR method results in that a so-called recessive state must be present on the bus line 3, which can be "traversed" by the other subscriber stations 10, 20, 30 in a dominant state on the bus line 3. In the recessive state, a high-ohmic situation exists at the respective subscriber station 10, 20, 30, which, in combination with the parasite of the bus connection, leads to a longer time constant. This results in limiting the current maximum bit rate of the CAN-FD physical layer to the current 2Mbps in real vehicle use.

If the subscriber station 20 has won arbitration as transmitter and the subscriber station 20 as transmitter therefore has exclusive access to the bus line 3 of the bus system 1 for transmitting the fields 453 to 456, the control field 453 and the data field 454 are first transmitted by the transmitter of the message 5 onto the bus line 3. During the arbitration, the subscriber stations 10, 20, 30 negotiate bit by means of the identifier in the arbitration field 452 between the subscriber stations 10, 20, 30, which subscriber stations 10, 20, 30 want to transmit the messages 4, 5 with the highest priority and thus get exclusive access to the bus line 3 of the bus system 1 for the transmission of the fields 453 to 455 in the next time.

The arbitration at the beginning of frame 45 or message 4, 5 and the acknowledgement in end field 456 at the end of frame 45 or message 4, 5 is only possible if the bit time is significantly more than twice the length of the signal run time between two arbitrary subscriber stations 10, 20, 30. Thus, the bit rate in the arbitration phase is selected to be slower when transmitting

fields

451, 452, 456 than in the remaining fields of frame 45.

Fig. 3 shows a design of the transmitting stage 220 of the transmitting/receiving device 22 in the present exemplary embodiment. The receiving stage is not shown in fig. 3, but may be implemented as a conventional receiving stage for CAN or CAN FD messages.

In fig. 3, the transmitting stage 220 is connected at its

terminals

221, 222 to the parallel bus line 3, more precisely to the first bus core 41 of the bus line for CAN _ H and to the second bus core 42 of the bus line for CAN _ L. In order to supply the first and

second bus lines

41, 42 with voltage, a terminal 223 is provided in the transmitting/receiving device 12. The voltage supply CAN be carried out in particular according to standard ISO11898-1:2015, which is a CAN protocol specification with CAN FD, using a voltage Vcc or CAN supply of, for example, approximately 2.5V. However, naturally, other voltage values may be selected as the voltage Vcc. The connection of the transmitting/receiving device 22 to ground or CAN _ GND is effected via a terminal 224. In order to terminate the first and

second bus lines

41, 42, a terminating resistor or an external bus load resistor 43 is provided in the example shown.

According to fig. 3, the transmission stage 220 has a first output stage 225 for the signal CAN _ H for the first bus conductor 41 and a second output stage 226 for the signal CAN _ L for the second bus conductor 42. Furthermore, the transmitting stage 220 has a third output stage 227 for the first bus core 41 and a fourth output stage 228 for the second bus core 42. The first and fourth output stages 225 and 228 have diodes and PMOS transistors (PMOS = p-type conductivity or p-channel metal oxide semiconductor), respectively. The second and third output stages 226 and 227 have diodes and NMOS transistors (NMOS = n-type conductivity or n-channel metal oxide semiconductor), respectively. The output stages 225 to 228 CAN be designed as corresponding output stages of a conventional output stage for CAN. The transistors of the output stages 225 to 228 may be connected at their gates to the terminal 211, respectively, directly or via a switch 229. The transmission signal TxD of the communication control device 11 is input from the terminal 211 into the transmission stage 220. The two switches 229 form a switching device. The two switches 229 may in particular be switched together.

In the phase for transmitting the start field 451, the arbitration field 452 and the end field 456, the transmitting/receiving device 22 activates in the transmitting stage 220 only the first output stage 225 for the signal CAN _ H for the first bus core 41 and the second output stage 226 for the signal CAN _ L for the second bus core 42 in order to drive the dominant bus state. While the third and fourth output stages 227 and 228 remain inactive, more precisely not only for the recessive bus state but also when the output stage 220 has to drive the dominant bus state. This can take place, for example, by switching the switch 229 into the open position shown in fig. 4, or only via a corresponding signal at the terminal 221 if the transistors of the output stages 225 to 228 are each connected directly to the terminal 211 at their gates. If the output stage 220 should drive a recessive bus state, all

output stages

225, 226, 227, 228 are turned off or not activated. The signal CAN _ H, CAN _ L thus appears, which is shown in fig. 4 and described in more detail below.

In contrast, in the phase for transmitting the control field 453, the data field 454 and the checksum field 455, the transmit/receive device 22 activates in the transmit stage 220 not only the first and third output stages 225, 227 for the signal 411 on the first bus core 41 but also the second and fourth output stages 226, 228 for the signal 421 on the second bus core 42, as will be described in more detail below. Accordingly, all output stages 225 through 228 are active during this phase of transmission, as described in more detail subsequently. This can be done, for example, by switching the switch 229 into a closed position, in which the terminal 211 is connected to the gates of the respective transistors of the output stages 227, 228 for the transmission signal TxD of the communication control device 11. Alternatively, the signal states 411, 421 may also be switched just via the corresponding signals at the terminal 211, as mentioned previously.

Signals

411, 421 thus occur, as is shown in fig. 5 and described in more detail below.

In the state of the transmitting stage 220 shown in fig. 4, the bus level for CAN _ H, CAN _ L CAN be generated with a bus load resistor 43 of approximately 60 ohms. While the bus level is generated with a bus load resistance 43 of approximately 90 ohms in the state of the transmitting stage 220 in which the switch 229 in fig. 3 is closed. The switching of the bus resistor 43 can take place, in particular, via a corresponding optional resistor 230 of the output stage 220, which can be connected in parallel with the bus load resistor 43. Thus, the resistance value of the active

bus load resistance

43 or 43, 230 may be caused to change from a first or lesser resistance value in the arbitration

phase including fields

456, 451, 452 to a second or greater resistance value in the data phase including fields 453-455. If the resistor 230 is not present, the bus load resistance 43 may remain the same for the arbitration phase and the data phase, respectively. In particular, the bus load resistance 43 may then be selected to a value between 60 ohms and 90 ohms, for example 70 ohms or another suitable value.

Only the dominant state of the differential signal CAN _ H, CAN _ L is driven differently according to fig. 4 with the output stage 220. While the bus level on the bus line 3 is supplied for a recessive state with a voltage Vcc or CAN equal, for example, about 2.5V. For voltage VDIFF = CAN _ H-CAN _ L, a value of 0V is thus obtained for the recessive state and a value of approximately 2.0V is obtained for the dominant state, as CAN be seen from fig. 4.

If the transmit/receive device 22 recognizes the end of the arbitration phase, the transmit stage 220 switches from the state shown in fig. 4 into a state in which the signal profiles of fig. 5 are derived for the bus levels respectively generated by the transmit stage 220.

According to fig. 5, in the faster data phase comprising fields 453 to 455, for

signals

411, 421 after the switching of the state of fig. 4, an idle state idle _ LP is reached directly after the switching, in which idle state a bus level of about 0V occurs in the case of the specific example of fig. 5. Normally, a state of the bus level of about 0V should not occur after switching. Thereafter, an idle state idle is reached, in which a bus level of approximately 2.5V occurs before reaching the bus states corresponding to the Data states Data _0 and Data _1 in the case of the specific example of fig. 5. In this case, signal 411 is pulled to approximately 1.5V via the NMOS transistor of third output stage 227 for the bus state corresponding to Data state Data _ 0. While signal 421 is pulled to approximately 3.5V via the PMOS transistor of fourth output stage 228 for the bus state corresponding to Data state Data _ 0. Data _1 is reached as follows: the signal 411 is pulled to about 3.5V via the PMOS transistor of the first output stage 225 and the signal 421 is pulled to about 1.5V via the NMOS transistor of the second output stage 226. In the state described, there is a bus level of between approximately-0.6V and approximately-2V in state Data _0 and a bus level of between approximately 0.6V and approximately 2V in state Data _1 on the bus line 3. In states Data _0 and Data _1, the differential voltage U _ D of

signals

421, 411 therefore typically has a maximum amplitude of about 1.4V.

In other words, in the first operating mode according to fig. 4, the transmitting stage 220 generates a first Data state, for example Data _1, as a bus state with different bus levels for the two

bus cores

41, 42 of the bus line, and a second Data state, for example Data _0, as a bus state with the same bus level for the two

bus cores

41, 42 of the bus line 3.

Furthermore, if a first Data state, for example the state Data _1, is to be driven onto the bus line 3, the transmitting stage 220 switches both the first and second output stages 225, 226 on and the output stages 227, 228 off in the second operating mode, which includes the Data phases, for the time profile of the

signals

411, 421 according to fig. 5. If, on the other hand, a second Data state, for example the state Data _0, is to be driven onto the bus line 3, the transmitting stage 220 switches the third and fourth output stages 227 and 228 on and switches the output stages 225, 226 off. In the second operating state, the transmitting stage 220 is therefore designed to generate the first and second data states as bus states having different bus levels for the two

bus cores

41, 42 of the bus line 3. By the described switching of the transmission stage 220, a much higher data rate CAN be achieved in the data phase than with CAN or CAN FD. Further, the data length in the data field 454 may be increased up to 4096 bytes. The advantages of CAN with regard to arbitration CAN thereby be maintained and, however, a greater number of data CAN be transmitted more efficiently in a shorter time than hitherto, i.e. without the need for data to be repeated due to errors, as explained later.

A further advantage is that no error frames are required in the transmission of the message 5 in the bus system 1. Thus, the message 5 is no longer corrupted, which eliminates the reason for the need for dual transmission messages. Thereby, the net data rate increases.

Furthermore, a plurality of domains or sub-bus systems 1 can be connected to one another as required by means of the transmission stage 220 via switches which are not described in greater detail here. The networking in the technical system, for example in a vehicle, can therefore be expanded significantly.

Fig. 6 shows voltage curves of

bus signals

412, 422 and 413, 423 according to a second embodiment. The voltage curves of the bus signals 412, 422 and 413, 423 are derived as follows: the switch 229 of the transmitting stage 220 of fig. 3 is cancelled or kept in a closed state, so that the transistors of the output stages 227, 228 are also directly connected with the terminal 211.

Fig. 7 shows the resulting transmission stage 220A of the second embodiment.

The physical layer is therefore used according to the second embodiment for the entire frame 45 of fig. 2, which allows the mentioned arbitration phases for the

fields

451, 452 and 456 and the long and fast data phases for the

fields

453, 454, 455. The advantage of switching the transmitting stage 220A into this operating mode is that the transmitting stage 220A is constructed completely symmetrically and also operates symmetrically in all communication phases. Thus, the value of the bus load resistance 43 is not switched, as previously described with respect to fig. 3 and 4.

The bus signals generated in such a transmitting stage 220A in all four possible bus states DF1, DF2, a1, a2 are shown in fig. 6. The differential voltage U _ D2 of the bus state DF1, DF2 has a larger magnitude than the differential voltage U _ D3 of the bus state a1, a 2. In this case, the magnitude of the differential voltage U _ D2 has a value that is n times the value of the magnitude of the differential voltage U _ D3, where n is a natural number that can be arbitrarily selected. However, the upper limit for the number of user stations 10, 20, 30 in the bus system 1 is calculated as n-1. The amplitude of the differential voltage U _ D3 may therefore also be referred to as an amplitude fundamental unit.

The two bus states DF1 and DF2 are utilized to communicate in the data phase, i.e. in fields 453 to 455, after the end of arbitration. This is similar to the process as previously described with respect to fig. 5. The bus state DF1 causes a positive differential voltage Vdiff = U _ D2 (V _ Plus-V _ Minus). The bus state DF2 causes a negative differential voltage Vdiff = -U _ D2. Bus state a1 causes a positive differential voltage Vdiff = U _ D3 (V _ Plus-V _ Minus). Bus state a2 causes a negative differential voltage Vdiff = -U _ D3.

Bus states a1 and a2 are introduced to allow arbitration. The bus states a1, a2 are qualitatively the same as the bus states DF1 and DF2, but are driven more weakly by the transmitting stage 220A than the bus states DF1, DF2, as illustrated in fig. 7. Thus, the bus state A1, A2 may be overwritten by other subscriber stations 10, 30 for arbitration purposes.

During the arbitration phase, the subscriber station 10, 20, 30, in particular the transmit stage 220A, is designed to transmit a differential voltage Vdiff having a basic unit of amplitude, i.e. U _ D3=1 unit, onto the bus line 3 and to check which differential voltage Vdiff is present on the bus line 3. If there is a differential voltage Vdiff of more than 1 unit or basic unit of amplitude, the subscriber station 10, 20, 30 concerned exits and is therefore the loser of the arbitration.

Thus, in the present exemplary embodiment, if the data of the arbitration or

first phase

456, 451, 452 should be transmitted by the message 5, the transmitting stage 220A switches between two different first bus states a1, a2 for the message in the first operating mode. Furthermore, if the data of the data phase or

second phase

453, 454, 455 are to be transmitted by the message 5, the transmitting stage 220A switches in the second operating mode with two different second bus states DF1, DF2 for the message 5. The transmitting stage 220A therefore switches between more than two different bus states DF1, DF2, a1, a2 in order to transmit a message 5 or a frame 45. In this case, the two bus states DF1, DF2 are respectively symmetrical to each other. Furthermore, the two bus states a1, a2 are symmetrical to each other. Naturally, also more than the four bus states mentioned are possible.

Thus, in the present exemplary embodiment, all components of the transmitting stage 220A are always active and involved, both in the arbitration phase and in the data phase, which results in maximum symmetry. Thus, advantages are derived in terms of the bit timing or temporal behavior of the bits of the message 5 and the electromagnetic compatibility (EMV).

Furthermore, the same advantages as previously described in relation to the first embodiment can be obtained in the present embodiment with the design of the transmitting stage 220A.

According to a modification of the second embodiment, instead of the bus states a1 and a2, one of the following combinations of bus states is used during arbitration:

bus state DF1 and bus state A2

Bus state DF2 and bus state a 1.

According to a further modification of the second embodiment, in a further embodiment all four bus states DF1, DF2, a1, a2 are used at least for sending the data field 454. Furthermore, the four bus states DF1, DF2, a1, a2 may be used in the

fields

453, 455. The bit rate can thus be increased by encoding.

According to a further modification of the second embodiment, the frequency of the

signals

412, 422, 413, 423 is reduced. Thereby, improvement in EMV characteristics can be achieved. By the previously described encoding into more than two bus states, the bit rate can be kept constant despite the lower frequency.

Otherwise, the same contents as those described previously in connection with the first embodiment are applicable.

Fig. 8 and 9 show voltage curves of the bus signal CAN _ H, CAN _ L for explaining the characteristics of the bus system 1 according to the third embodiment.

Fig. 8 shows known voltage profiles of bus signals CAN _ H and CAN _ L which are used for the arbitration phases 456, 451, 452 of the frame 45 according to the present exemplary embodiment for transmitting the message 5 or the frame 45. The voltage profiles of the bus signals CAN _ H and CAN _ L show a significantly slower state transition when transitioning from the dominant state 46 to the recessive state 47 and when transitioning from the recessive state 47 to the dominant state 46.

In contrast to this, however, in the present exemplary embodiment the signals CAN _ EL _ H and CAN _ EL _ L according to fig. 9 with a high state 461 and a low state 471 are generated for the data phases 453, 454, 455 of the frame 45. The signal according to fig. 9 is generated with a physical layer in which the high state 461 is the same as the dominant state 46 of CAN or CAN FD as shown in fig. 8 and with voltage values CAN _ H =3.5V and CAN _ L = 1.5V. Furthermore, a low state 471 results in the physical layer according to fig. 9, which is equal in level to the recessive state 47 of CAN or CAN FD as shown in fig. 8 and having a value CAN _ H = CAN _ L = 2.5V.

As shown in fig. 9, the transition from the high state 461 to the low state 471 occurs approximately as fast as the transition from the low state 471 to the high state 461.

This is achieved by driving low state 471 low ohmically. ("low-ohmic recessive"). The slower transition from the dominant state 46 to the recessive state 47 as shown in fig. 8 is thereby accelerated in the case of the signal of fig. 9. Subsequently for

data phases

453, 454, 455 of frame 45 a bit rate significantly exceeding 2Mbps can be achieved.

Thus, in the present exemplary embodiment, a switchover from the CAN physical layer to the other physical layer is made with the transmitting/receiving device 22 and/or the transmitting/receiving device 32 upon detection of the end of the arbitration phase. Since Error Frames or Error-Frames can be discarded, other subscriber stations 10, 20, 30 do not have to be able to traverse the currently transmitting subscriber station 10, 20, 30 during the data phase. Therefore, no recessive (high ohmic) bus state is required in the data phase.

The physical layer for the signal profile according to fig. 9 can be obtained, for example, with the transmitting stage 2200 according to fig. 10.

As shown in fig. 10, the transmit stage 2200 therefore has a third output stage 2270 connected to the voltage source 232 and a fourth output stage 2280 connected to the voltage source 233, unlike the transmit stage 220 of fig. 3 according to the current embodiment. The third output stage 2270 has an NMOS transistor and a diode. The fourth output stage 2280 has a PMOS transistor and a diode. The transistors of the first and second output stages 225, 226 are operated with the transmit signal TxD via a driver circuit 230. The transistors of the third and fourth output stages 225, 226 are operated with the transmit signal TxD via the driver circuit 231.

In the data phase of frame 45, i.e. in case of high bit rate, the high state 461 is mapped as follows: the output stages 225, 226 operated via the driver circuit 230 become conductive or are switched active and the output stages 227, 228 and the

voltage sources

232, 233 operated via the driver circuit 231 are high-ohmic or off. For driving the low state 471 (recessive driven low-ohmic), the driver capability is greatly reduced in particular for the output stages 225, 226 operated via the driver circuit 230, and the output stages 227, 228 operated via the driver circuit 231 and the

voltage sources

232, 233 become conductive. The reduction in drive capability also includes the following: the output stages 225, 226 are switched off, which means the strongest reduction in driver capability. Thus, the NMOS transistor of the third output stage 2270 pulls the terminal 221 for CAN-EL _ H to 2.5V and the PMOS transistor of the fourth output stage 2280 raises the terminal 221 for CAN-EL _ L to 2.5V, thereby forming a low bus state 471.

The circuit of fig. 10 is particularly interesting in junction isolated semiconductor technology.

This results in a very good symmetry of the bus signals in the data phase in the present exemplary embodiment. Thus, advantages are derived in terms of the bit timing or temporal behavior of the bits of the message 5 and the electromagnetic compatibility (EMV).

Furthermore, the same advantages as previously described in relation to the first and second embodiments can be obtained in the present embodiment with the design of the sending stage 2200.

The previously mentioned principle of low-ohmic driving of the low state 471 (recessive driven low-ohmic) can alternatively be used for all other serial bus systems in which a recessive state exists.

Fig. 11 and 12 show voltage curves of the bus signals CAN _ EL _ H1, CAN _ EL _ L1 and CAN _ EL _ H2, CAN _ EL _ L2 for explaining the characteristics of the bus system 1 according to the fourth embodiment.

The voltage curves of the bus signals CAN _ EL _ H1, CAN _ EL _ L1 of fig. 11 are the same as the voltage curves of the bus signals CAN _ EL _ H, CAN _ EL _ L of fig. 9. However, in contrast, the transmitting stage 2200 of fig. 10 produces the voltage profile of the bus signals CAN _ EL _ H1, CAN _ EL _ L1 of fig. 11 in the arbitration phase of frame 45. However, the voltage profile of the bus signal CAN _ H, CAN _ L of fig. 8 may alternatively be used in the arbitration phase of frame 45.

In the present exemplary embodiment, however, upon detection of the end of the arbitration phase, the transmitting stage 2200 switches to an operating mode in which the transmitting stage 2200 generates the voltage profiles of the bus signals CAN _ EL _ H2, CAN _ EL _ L2 of fig. 12 for the data of the data phase of the frame 45. The bus signal CAN _ EL _ H2 of fig. 12 has a voltage level of approximately 3.0V in the dominant state 462. The high state 461 of FIG. 11, which is also the dominant state, corresponds to the dominant state 462 of FIG. 12. The bus signal CAN _ EL _ L2 of fig. 12 has a voltage level of approximately 2.0V in the dominant bus state 462. Thus, the dominant bus state 462 has a reduced voltage level for the bus signals CAN _ EL _ H2, CAN _ EL _ L2 relative to the voltage level of the dominant bus state 461 used for the bus signals CAN _ EL _ H1, CAN _ EL _ L1 in the arbitration phase. Thus, assuming that the bus load resistance 43 remains unchanged, the differential voltage Vdiff = CAN _ EL _ H2-CAN _ EL _ L2 of the signal of fig. 12 is also only 1.0V and is therefore smaller than the differential voltage Vdiff of the signal of fig. 11 or 8, more precisely only half of the differential voltage Vdiff of the signal of fig. 11 or 8. While the low state 471 does not change.

In the present exemplary embodiment, a more stable signal profile of Vdiff results compared to the bus signals of the preceding exemplary embodiments according to fig. 8 and 9, which enables a lower transmission level to be received by the subscriber stations 20, 30, more precisely their transmission/

reception devices

22, 32.

With the described signals of fig. 11 and 12, not only a greatly increased bit rate of more than 12 mbps and a data quantity of up to 4096 bytes can be conveyed (gefahren) in at least the data field 454, as already described previously. However, by switching the bus signal in the data phase to the bus signals CAN _ EL _ H2, CAN _ EL _ L2, the current consumption and thus the energy consumption of the transmitting stage 2200 CAN be significantly reduced compared to the previous embodiments, even if a much greater number of switching processes are carried out per unit time than in CAN or CAN FD. This is accomplished by reducing the magnitude or transmit level of VDIFF in at least the data field 454.

In order to achieve useful signal integrity at elevated bit rates, the topology of the bus system 1 must be greatly simplified. The following advantages therefore result here: with the reduced transmission level, there is also lower radiation and therefore improved EMV compatibility.

Otherwise, the same contents as those described previously in connection with the third embodiment are applicable.

In a modification of the third embodiment, the transmitting stage 2200 of fig. 10 does not have

output stages

2270, 2280. The transmission stage 2200 of fig. 10 is in this case designed like a conventional CAN transmission stage. In order to obtain the previously described signal profiles of fig. 11 and 12, such a conventional CAN transmit stage is controlled such that the driver or

output stage

225, 226 operates "normally" as in CAN for the dominant or high state 461 outside the data phase, i.e. according to the signal profile of fig. 11. Whereas for the dominant state 462 of fig. 12, i.e. in the data phases 225 and 226, the driver or

output stage

225, 226 operates more ohmically, whereby the level of the respective dominant state 462 is reduced compared to the level of the respective dominant or high state 461.

Fig. 13 shows an example for coupling the transmitting/receiving device 22 to a bus line 3, which bus line 3 has its two

bus cores

41, 42. This coupling can be used in all transmitting/receiving means 22, 32 and their transmitting

stages

220, 220A, 2200 of the previous embodiments.

For coupling the transmitting/receiving means 22 to the bus line 3, a first coupling capacitor 251 is provided for coupling the transmitting/receiving means 22 to the first bus conductor 41 and a second coupling capacitor 251 is provided for coupling the transmitting/receiving means 22 to the second bus conductor 42. Furthermore, a resistor 255 is provided between the terminal 223 for the voltage supply of the first and

second bus lines

41, 42 and the terminal 221 for the first bus line 41. Further, a resistor 256 is provided between the terminal 223 and the terminal 222 for the second bus line 42.

The capacitances or

coupling capacitors

251, 252 are arranged outside the respective transmitting/receiving device 22. The

coupling capacitors

251, 252, in contrast to the other serial bus systems 1, such as CAN or CAN FD or Flexray, provide galvanically isolated connections of the respective transmitting/receiving device 22 to the

bus lines

41, 42.

An advantage of the AC coupling or the AC voltage coupling or the AC current coupling by means of the

coupling capacitors

251, 252 is that Common-Mode interference (Common-Mode interference) on the bus line 3 does not interfere with the preceding exemplary embodiments or the respectively present transmitting

stages

220, 220A, 2200 according to fig. 13. Another advantage is that the preceding exemplary embodiments or the respectively present transmit

stages

220, 220A, 2200 according to fig. 13 can be implemented in low-voltage CMOS technology due to galvanic isolation or isolation (CMOS = Complementary Metal-Oxide-Semiconductor) = Semiconductor devices, in which both p-channel MOS transistors and n-channel MOS transistors are used on a common substrate). Thus, a significantly higher accuracy and faster switching time between the two pin driver stages of the output stages 225, 226 results. Thereby, the speed of transmission of data in the bus system 1 of the previously described embodiment can be further increased.

In the circuit of FIG. 13, the transmit stage is constructed to pull the first and second coupling capacitors (251, 252) at a high or low current to corresponding levels of a dominant or recessive bus state or a high bus state (461; 462) and a low bus state (471).

As shown very schematically in fig. 14, according to a modification of the fifth embodiment, instead of the resistor 255 provided between the terminal 223 for the voltage supply of the first and

second bus lines

41, 42 and the terminal 221 for the first bus line 41, a transistor 257 is provided. Further, instead of the resistor 256 provided between the terminal 223 and the terminal 222 for the second bus line 42, a transistor 258 is provided. In this way, the galvanically isolated connection of the respective transmitting/receiving device 22 to the

bus lines

41, 42 can also be implemented using the

coupling capacitors

251, 252.

All previously described embodiments of the bus system 1, of the subscriber stations 10, 20, 30, 40 and of the method implemented by these subscriber stations can be used individually or in all possible combinations. In particular, all features of the previously described embodiments and/or modifications thereof may be combined arbitrarily. In addition or alternatively, the following modifications are particularly conceivable.

The previously described bus system 1 according to the embodiment is described in terms of a bus system based on the CAN protocol. The bus system 1 according to the exemplary embodiment can however also be another type of communication network in which data can be transmitted serially with two different bit rates. Advantageously, but not compulsorily, the precondition is: exclusive, collision-free access of the subscriber stations 10, 20, 30 to the common channel is ensured in the bus system 1 at least for a specific time interval. The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 of the embodiment described is arbitrary. In particular, the subscriber station 10 can be omitted from the bus system 1. It is possible that one or more of the subscriber stations 20 or 30 are present in the bus system 1.

Claims

1. Subscriber station (20; 30) for a serial bus system (1), having

A transmitting stage (2200) for transmitting messages (4; 5) onto a bus line (3) of the bus system (1),

wherein the sending stage (2200) has an output stage (225, 226, 2270, 2280) for switching a differential bus signal between a high bus state (461; 462) and a low bus state (471) for a message (5),

wherein the sending stage (2200) has:

a first output stage (225) which is connected between a terminal (223) for voltage supply and a first bus conductor (41) of the bus line (3);

a second output stage (226) which is connected between a second bus conductor (42) of the bus line (3) and a terminal (224) for ground;

a third output stage (2270) connected between the first bus conductor (41) of the bus line (3) and a first voltage source (232) as a reference for the low bus state (471), wherein the first voltage source (232) is connected between the third output stage (2270) and a terminal (224) for ground; and

a fourth output stage (2280) which is connected between a second voltage source (233) as a reference for the low bus state (471) and a second bus conductor (42) of the bus line (3), wherein the second voltage source (233) is connected between the fourth output stage (2280) and a terminal (224) for ground,

wherein the transmission stage (2200) is designed such that, for at least one first phase of the data for transmitting the message (5), a first high bus state (461) is generated and the differential bus signal (CAN _ EL _ H2; CAN _ EL _ L2) has the same level for a low bus state (471) and drives the low bus state (471) with low resistance using a third and a fourth output stage (2270, 2280), and

wherein the transmitting stage (2200) is constructed such that for a second phase (453; 454; 455) for transmitting data of the message (5) a second high bus state (462) is generated, which second high bus state (462) has a smaller differential voltage between the differential bus signals (CAN _ EL _ H1; CAN _ EL _ L1) than between the differential bus signals (CAN _ EL _ H1; CAN _ EL _ L1) in the first high bus state (461).

2. Subscriber station (20; 30) according to claim 1,

wherein the sending stage (2200) is designed to switch into a first operating mode for generating a first high bus state (461) and a low bus state (471) for a message (5) if data of a first phase (456; 451; 452) are to be sent by the message (5), which data are to be sent at a first bit rate, and

wherein the sending stage (2200) is designed to switch into a second operating mode for generating the second high bus state (462) and the low bus state (471) for the message (5) if data of a second phase (453; 454; 455) is to be sent by the message (5), which second phase is to be sent at a second bit rate, which is faster than the first bit rate.

3. Subscriber station (20; 30) according to claim 2,

the transmission stage (2200) is designed to switch into a second operating mode for transmitting data only if exclusive collision-free access to the bus lines (3) of the bus system (1) is guaranteed for the user stations (20; 30) for a predetermined time.

4. Subscriber station (20; 30) according to one of the preceding claims 1 to 3,

wherein the transmission stage (2200) is designed to operate the output stage (225; 226) with a higher ohmic resistance for the second high bus state (462) of the second phase (453; 454; 455) for transmitting the data of the message (5) than for the first high bus state (461) of the first phase for transmitting the data of the message (5).

5. Subscriber station (20; 30) according to any of the preceding claims 1 to 3,

wherein the first output stage (225) has PMOS transistors, and

wherein the second output stage (226) has NMOS transistors.

6. Subscriber station (20; 30) according to any of the preceding claims 1 to 3,

wherein the fourth output stage (2280) has PMOS transistors, and

wherein the third output stage (2270) has NMOS transistors.

7. Subscriber station (20; 30) according to any of the preceding claims 1 to 3,

wherein the output stage (2200) is designed to reduce the driver capability of the first and second output stages (225, 226) and to switch the third and fourth output stages (2270, 2280) on for a low bus state (471).

8. Subscriber station (20; 30) according to one of the preceding claims 1 to 3,

wherein the message (5) has a data field (454) having a variable length, wherein the variable length is between 1 byte and 4096 bytes.

9. A bus system (1) having:

parallel bus lines (3), and

at least two user stations (10; 20; 30) which are connected to one another via the bus line (3) in such a way that they can communicate with one another,

wherein at least one of the at least two subscriber stations (10; 20; 30) is a subscriber station (20; 30) according to any one of the preceding claims.

10. Method for transmitting messages (5) in a serial bus system (1), wherein the method has the steps:

the transmission stage (2200) of a user station (20; 30) of the bus system (1) is used to transmit a message (4; 5) onto a bus line (3) of the bus system (1),

wherein the transmitting stage (2200) switches the differential bus signal between a high bus state (461; 462) and a low bus state (471) for a message (5) with the output stage (225, 226, 2270, 2280),

wherein the sending stage (2200) has:

wherein the transmitting stage (2200) is designed such that, for at least one first phase of the data for transmitting the message (5), a first high bus state (461) is generated and the differential bus signals (CAN _ EL _ H2; CAN _ EL _ L2) have the same level for a low bus state (471), and the transmitting stage (2200) drives the low bus state (471) with low resistance using a third and a fourth output stage (2270, 2280), and