WO2019122211A1

WO2019122211A1 - Participant station for a serial bus system, and method for transmitting a message in a serial bus system

Info

Publication number: WO2019122211A1
Application number: PCT/EP2018/086339
Authority: WO
Inventors: Steffen Walker
Original assignee: Robert Bosch Gmbh
Priority date: 2017-12-22
Filing date: 2018-12-20
Publication date: 2019-06-27
Also published as: EP3744049A1; CN111713077A; DE102018202168A1; CN111713077B

Abstract

The invention relates to a participant station (20; 30) for a bus system (1) and to a method for transmitting a message at different bitrates in a bus system (1). The participant station (20; 30) comprises a transmission stage (2200) for transmitting a message (4; 5) on a bus line (3) of the bus system (1). The transmission stage (2200) has output stages (225, 226, 2270, 2280) for switching differential bus signals for a message (5) between a high bus state (461; 462) and a low bus state (471). The output stage (2200) is designed such that for at least one first phase for transmitting data of the message (5), the differential bus signals (CAN_EL_H2; CAN_EL_L2) for a low bus state (471) have the same level, and the low bus state (471) is operated with a low impedance, and for a second phase (453; 454; 455) for transmitting data of the message (5), a bus state (461) which is comparable to the high bus state (462) has a lower differential voltage between the differential bus signals (CAN_EL_H1; CAN_EL_L1) than the differential voltage between the differential bus signals (CAN_EL_H1; CAN_EL_L1) in the high bus state (462).

Description

description

Subscriber station for a serial bus system and method for sending a

Message in a serial bus system

Technical area

The present invention relates to a subscriber station for a serial bus system and a method for transmitting a message in a serial bus system operating at high data rate and with high error robustness.

State of the art

For communication between sensors and control devices, for example in vehicles, a bus system is frequently used, in which data is transmitted as messages in the standard ISO11898-1: 2015 as CAN protocol specification with CAN FD. The news will be between the

Bus participants of the bus system, such as sensor, controller, encoder, etc., transferred.

With increasing number of functions of a technical system or of a vehicle, the data traffic in the bus system also increases. Moreover, it is often required that the data transfer faster from the transmitter to the receiver than before. The consequence of this is that the required bandwidth of the bus system will continue to increase.

In order to transmit data at a higher bitrate than CAN, the CAN FD message format has created an option to switch to a higher bit rate within a message. With such techniques, the maximum possible data rate is increased beyond a value of 1 Mbit / s by using a higher clock rate in the area of the data fields. Such news are also referred to below as CAN FD frames or CAN FD messages. With CAN FD, the user data length has been extended from 8 to 64 bytes and the data transmission rates are significantly higher than with CAN.

Even if a CAN or CAN FD based communication network in

With regard to its robustness, for example, it offers many advantages, but it has a much lower speed compared to one

Data transmission with, for example, 100 Base-Tl Ethernet. In addition, the user data length of up to 64 bytes achieved so far with CAN FD is too low for some applications.

Disclosure of the invention

Therefore, it is an object of the present invention to provide a subscriber station for a serial bus system and a method for transmitting a message in a serial bus system which solve the aforementioned problems. In particular, a subscriber station for a serial bus system and a method for transmitting a message in a serial bus system are to be provided in which a high error robustness is required

Data rate and an increase in the amount of payload per frame can be realized.

The object is achieved by a subscriber station for a serial bus system with the features of claim 1. The subscriber station comprises a transmission stage for transmitting a message to a bus line of the bus system, wherein the transmission stage comprises output stages for switching differential bus signals for a message between a high-bus state and a low-bus state, wherein the transmission stage is constructed such that for at least one Phase for transmitting data of the message, the differential bus signals for a low bus state have the same level and the low bus state is driven low, and wherein the transmission stage is constructed such that for a second phase for transmitting data of the message, a bus state, which is comparable to the high bus state, has a smaller differential voltage between the differential bus signals than a differential voltage between the differential bus signals in the high bus state. With the subscriber station, a significant increase in the bit rate and thus the transmission speed from transmitter to receiver can be realized. At the same time, however, a large error robustness is ensured.

Due to the configuration of the subscriber station no error frames (error frames) are required more. This helps to realize a net data rate of at least 10 Mbps. In addition, the size of the user data can be up to 4096 bytes per frame.

Another advantage is that multiple domains can be interconnected by switches as needed. That lowers the

Cabling effort between the individual components of a technical system or vehicle. This is in terms of lower time, reduced use of materials and thus reduced weight, especially in a vehicle a particularly clear plus.

The method performed by the subscriber station can also be used if there is also at least one CAN subscriber station and / or at least one CAN FD subscriber station in the bus system

Send messages according to the CAN protocol and / or CAN FD protocol.

Advantageous further embodiments of the subscriber station are specified in the dependent claims.

According to a particular embodiment, the transmission stage is configured to switch to a first mode with two first different bus states for a message when data of a first phase to be transmitted from the message is to be transmitted at a first bit rate, and wherein the

Transmitter is configured to switch to a second mode with the high bus state and the low bus state for a message when from the

Message is to send data of a second phase, which is to be sent at a second bitrate that is faster than the first bitrate. According to a further specific embodiment variant, the transmission stage is designed to switch to the second operating mode for transmitting data only if exclusive, collision-free access to the bus line of the bus system is ensured for the subscriber station for a predetermined time.

According to a further specific embodiment variant, the transmission stage has a first output stage which is connected between a connection for a voltage supply and a first bus line, a second output stage which is connected between a second bus line and a connection for ground,

wherein the second stage high bus stage amplifiers are operated to have a higher impedance for transmitting data of the message than for first stage high bus conditions for transmitting data of the message.

According to a further specific embodiment, the transmission stage has a first output stage which is connected between a connection for a voltage supply and a first bus wire of the bus line, a second output stage which is connected between a second bus wire of the bus line and a connection for ground, a third output stage that between the first bus of the

Bus line and a first voltage source is connected as a reference for the low-bus state, and

a fourth output stage, which is connected between a second voltage source as a reference for the low-bus state and the second bus wire of the bus line.

It is conceivable that the first output stage has a PMOS transistor, and the second output stage has an NMOS transistor. In this case, it is possible that the fourth output stage has a PMOS transistor, and the third output stage has an NMOS transistor.

Possibly, the transmission stage is designed to reduce the driving capability of the first and second output stage for a low bus state and to switch the third and fourth output stage conductive.

It is possible for the message to have a data field of variable length, the variable length being from 1 byte to 4096 bytes. The subscriber station described above may be part of a bus system, which also comprises a parallel bus line and at least two subscriber stations, which are connected to one another via the bus line so that they can communicate with each other. In this case, at least one of the at least two subscriber stations is a subscriber station described above.

The above object is further achieved by a method for transmitting a message in a serial bus system according to claim 11. The method has the step of transmitting, with a transmission stage of a subscriber station of the bus system, a message to a bus line of the bus system, wherein the transmission stage with output stages switches differential bus signals for a message between a high-bus state and a low-bus state, wherein the

Transmission stage is constructed such that for at least one phase to

Transmission of data of the message, the differential bus signals for a low-bus state have the same level and the low-bus state drives low, and wherein the transmission stage is constructed such that for a second phase for transmitting data of the message, a bus state associated with the High bus state is comparable, a smaller difference voltage between the differential bus signals than a difference voltage between the differential bus signals in the high-bus state.

The method offers the same advantages as previously described in relation to the

Subscriber station are called.

Further possible implementations of the invention also include not explicitly mentioned combinations of before or below with respect to the

Embodiments described features or embodiments. The skilled person will also add individual aspects as improvements or additions to the respective basic form of the invention.

drawings

The invention is described in more detail below with reference to the accompanying drawings and to exemplary embodiments. Show it: 1 is a simplified block diagram of a bus system according to a first embodiment;

FIG. 2 is a diagram for illustrating the structure of messages sent from subscriber stations of the bus system according to the first embodiment

Embodiment can be sent;

3 shows a circuit diagram of a transmission stage of a subscriber station of the bus system according to the first embodiment;

4 shows a representation of an example of a temporal voltage profile of differential bus signals CAN_H and CAN_L, which are generated by the transmission stage according to the first exemplary embodiment for part of a message;

5 shows a representation of an example of a temporal voltage curve of bus signals after a switching of the transmission stage according to the first exemplary embodiment into a faster data transmission mode than in FIG. 4;

6 shows a representation of an example of a temporal voltage profile of the bus signals CAN_H and CAN_L for a part of a message in a second embodiment;

7 is a circuit diagram of a transmission stage of a subscriber station of the bus system according to the second embodiment;

8 and 9 each show a representation of an example of a temporal voltage profile of differential bus signals for different parts of a message in a third embodiment;

10 is a circuit diagram of a transmission stage of a subscriber station of a

Bus system according to a third embodiment; 11 and FIG. 12 are each an illustration of an example of a temporal waveform of differential bus signals for various parts of a message in a fourth embodiment; FIG.

13 shows a circuit diagram of a coupling of the transmission stage of a subscriber station to bus wires of a bus system according to a fifth exemplary embodiment; and

14 is a circuit diagram of a coupling of the transmission stage of a subscriber station to bus wires of a bus system according to a modification of the fifth

Embodiment.

In the figures, identical or functionally identical elements are provided with the same reference numerals, unless stated otherwise.

Description of the embodiments

1 shows, as an example, a bus system 1, which is designed in particular fundamentally for a CAN bus system, a CAN FD bus system, a CAN EL bus system, and / or modifications thereof, as described below. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in the hospital, etc.

In Fig. 1, the bus system 1 has a, in particular parallel, bus line 3, to which a plurality of subscriber stations 10, 20, 30 are connected. Messages 4, 5 in the form of signals between the individual subscriber stations 10, 20, 30 can be transmitted serially via the bus line 3. The

Subscriber stations 10, 20, 30 are, for example, control devices, sensors, display devices, etc. of a motor vehicle.

As shown in Fig. 1, the subscriber station 10 has a

In contrast, the subscriber station 20 has a communication control device 21 and a transceiver 22. The subscriber station 30 has a communication control device 31 and a transceiver 32. The transceiver devices 12, 22, 32 of the subscriber stations 10, 20, 30 are each connected directly to the bus line 3, even if this is shown in FIG.

I is not illustrated.

The communication control devices 11, 21, 31 each serve to control a communication of the respective subscriber station 10, 20, 30 via the bus line 3 with another subscriber station of the subscriber stations 10,

20, 30, which are connected to the bus line 3.

The communication controller 11 may be implemented like a conventional CAN controller. The communication control device 11 creates and reads first messages 4, for example Classic CAN messages 4. The Classic CAN messages 4 are constructed in accordance with the Classic basic format in which a number of up to 8 data bytes can be included in the message 4. Alternatively, the Classic CAN message 4 is constructed as a CAN FD message in which a number of up to 64 bytes of data can be included, which are still transmitted at a much faster data rate than the Classic CAN message 4. In the latter case, the

Communication controller 11 as a conventional CAN FD controller executed.

The communication controller 21 prepares and reads second messages 5, which are modified CAN messages 5, for example. Here, the modified CAN messages 5 are constructed on the basis of a CAN EL format, which is described in more detail with reference to FIG.

The communication controller 31 may be configured to provide or receive a Classic CAN message 4 or a CAN EL message 5 to the transceiver 32 as needed. The communication control device 21 thus creates and reads a first message 4 or a second message 5, wherein the first and second messages 4, 5 differ by their data transmission standard, namely in this case CAN or CAN EL. Alternatively, the Classic CAN message 4 is constructed as a CAN FD message. In the latter case, the communication control device

II like a conventional CAN FD controller. The transceiver 12 may be like a conventional CAN

Transceiver or CAN FD transceiver be executed. The transmitting / receiving device 22 may be even more accurate except as follows

be described differences as CAN EL transceiver. The transceiver 32 may be configured to provide or receive messages 4 according to the current CAN base format or messages 5 according to the CAN EL format for the communication controller 31 as needed. The transceivers 22, 32 are additionally or alternatively like a

Conventional CAN FD transceiver executable.

With the two subscriber stations 20, 30 can be a formation and then

Transmission of messages 5 with the CAN EL format and the reception of such messages 5 can be realized.

FIG. 2 shows for the message 5 a CAN EL frame 45 as it is transmitted by the transceiver 22 or the transceiver 32. The CAN-EL frame 45 is subdivided into different fields for the CAN communication on the bus line 3, namely a start field 451

Arbitration field 452, a control field 453, a data field 454, a checksum field 455 and an end field 456.

For example, the start field 451 has one bit, also called SOF bit, indicating the beginning of the frame. Arbitration field 452 contains an identifier, in particular 32 bits, for identifying the sender of the message. The control field 453 contains an in particular 13-bit long data length code (data length code), which can have values up to 4096 with the increment of 1. In the data field 454, the user data of the CAN-EL frame and the message 5 are included. The payload data may have up to 4096 bytes according to the value of the data length code. The checksum field 455 contains a checksum of the data in the data field 454 including the stuff bits which are inserted by the sender of the message 5 every 10 equal bits as an inverse bit. The end field 456 contains at least one acknowledge bit and also a sequence of 11 equal bits indicating the end of the CAN EL frame 45. With the At least one acknowledge bit is informed as to whether a receiver has detected an error in the received CAN EL frame 45 or the message 5 or not.

In the phases for sending the arbitration field 452 and the end field 456, a physical layer as in CAN and CAN-FD is used. An important point during these phases is that the well-known CSMA / CR method

Is used, which simultaneous access of the subscriber stations 10,

20, 30 allowed on the bus line 3, without the higher priority message 4,

5 is destroyed. As a result, further bus subscriber stations 10, 20, 30 can be added to the bus system 1 relatively simply, which is very advantageous.

The consequence of the CSMA / CR method is that there must be so-called recessive states on the bus line 3, which can be "crossed over" by other subscriber stations 10, 20, 30 with dominant states on the bus line 3. In the recessive state prevail at the individual subscriber station 10, 20, 30 high-impedance conditions, which in combination with the parasitic bus circuitry has longer time constants result. This leads to a limitation of the maximum bit rate of today's CAN-FD physical layer to currently 2 Mbps in real vehicle use.

The control field 453 and the data field 454 are only sent to the bus line 3 by a sender of the message 5 when the subscriber station 20 has won the arbitration as the sender and the subscriber station 20 as sender therefore has exclusive access to send the fields 453 to 456 the bus line 3 of the bus system 1 has. In arbitration, using the identifier in the arbitration field 452, bitwise between the

Subscriber stations 10, 20, 30 negotiated which subscriber station 10, 20, 30 would like to send the message 4, 5 with the highest priority and therefore gets the exclusive access to the bus line 3 of the bus system 1 for the next time to send the fields 453-455 ,

The arbitration at the beginning of a frame 45 or the message 4, 5 and the acknowledgment in the end field 456 at the end of the frame 45 or the message 4, 5 is only possible if the bit time significantly more than twice is long as the signal transit time between any two subscriber stations 10, 20, 30 of the bus system 1. Therefore, the bit rate in the Arbitrationphase when transmitting the fields 451, 452, 456 is selected to be slower than in the remaining fields of the frame 45th

3 shows the embodiment of a transmission stage 220 of the transceiver 22 in the present embodiment. The

Receive stage is not shown in Fig. 3, but may be implemented as a conventional receiving stage for CAN or CAN FD messages.

In FIG. 3, the transmission stage 220 is connected at its terminals 221, 222 to the parallel bus line 3, more precisely its first bus wire 41 for CAN_H and its second bus wire 42 for CAN_L. For the voltage supply for the first and second bus wires 41, 42, a connection 223 is provided at the transceiver 12. The voltage supply can be carried out in particular with a voltage Vcc or CAN supply of, for example, about 2.5 V according to the standard ISO11898-1: 2015 as a CAN protocol specification with CAN FD. Of course, however, voltage values other than voltage Vcc are selectable. The connection of the transmitting / receiving device 22 to ground or CAN_GND is realized via a connection 224. For termination of the first and second bus wires 41, 42 is in the example shown a

Terminating resistor or external bus load resistor 43 is provided.

According to FIG. 3, the transmission stage 220 has a first output stage 225 for the signal CAN_H for the first bus wire 41 and a second output stage 226 for the signal CAN_L for the second bus wire 42. In addition, the transmission stage 220 has a third output stage 227 for the first bus wire 41 and a fourth output stage 228 for the second bus line 42. The first and fourth output stages 225 and 228 each have a diode and a PMOS transistor (PMOS = p-type metal oxide semiconductor). The second and third output stages 226 and 227 each have a diode and an NMOS transistor (NMOS = n-type and n-type metal oxide semiconductor, respectively). The output stages 225 to 228 can be designed like the corresponding output stages for a conventional output stage of CAN. The transistors of the output stages 225 to 228 are at their gates directly or via a

Switch 229 can be connected to a connection 211. From port 211 becomes a transmission signal TxD of the communication control device 11 is input to the transmission stage 220. The two switches 229 form a switching device. The two switches 229 are in particular switchable together.

In the phase for transmitting the start field 451, the arbitration field 452 and the end field 456, the transceiver 22 in the transmission stage 220 for driving a dominant bus state activates only the first output stage 225 for the signal CAN_H for the first bus core 41 and the second output stage 226 for the signal CAN_L for the second bus line 42. On the other hand, the third and fourth power stages 227 and 228 remain inactive, not only for a recessive one

Bus state but even if the transmission level 220 a dominant

Bus state must drive. This can be done, for example, by switching the switches 229 to the open position, which is shown in FIG. 4, or only via a corresponding signal at the terminal 211, when the transistors of the output stages 225 to 228 are respectively connected directly to the terminal 211 at their gates , If the transmission stage 220 is to drive a recessive bus state, all output stages 225, 226, 227, 228 are disabled or inactive. As a result, signals CAN_H, CAN_L appear, which are shown in FIG. 4 and described in more detail below.

In the phase for sending the control field 453, the data field 454 and the checksum field 455, however, the transmitting / receiving device 22 in the transmitting stage 220 activates both the first and third output stages 225, 227 for a signal 411 on the first bus core 41 and the second one and fourth output stage 226, 228 for a signal 421 on the second bus wire 42, as described in more detail below. Thus, in this phase of transmission, all output stages 225 to 228 are active, as described in more detail below. This can

For example, by switching the switch 229 in the closed position, in which the terminal 211 for the transmission signal TxD of

Communication control device 11 is connected to the gate of the respective transistor of the output stages 227, 228. Alternatively, the switching is the

Signal states 411, 421 only via a corresponding signal at the terminal 211 possible, as previously mentioned. As a result, signals 411, 421 turn on, as shown in FIG. 5 and described in more detail below. In the state of the transmission stage 220 shown in FIG. 4, the bus levels for CAN_H, CAN_L can be generated with a bus load resistance 43 of approximately 60 ohms. In contrast, the bus levels in the state of the transmission stage 220, in which the switches 229 are closed in Fig. 3, with a

Bus load resistance 43 of about 90 ohms can be generated. The switching of the bus load resistor 43 can be effected in particular by a corresponding optional resistor 230 of the transmission stage 220, which is switchable parallel to the bus load resistor 43. This is a change of

Resistance value of the effective bus load resistor 43 or 43, 230 from a first or lower resistance in the arbitration phase, which includes the fields 456, 451, 452, to a second or greater resistance value in the data phase, which includes the fields 453-455 , If the resistor 230 is not present, the bus load resistor 43 for the

Arbitration phase and the data phase remain the same. In particular, the bus load resistor 43 is then selectable as a value between 60 and 90 ohms, for example, 70 ohms or other suitable value.

According to FIG. 4, only the dominant states of the differential signals CAN_H, CAN_L are driven differently with the transmission stage 220. In contrast, the bus levels on the bus line 3 for the recessive states are equal to the voltage Vcc or CAN supply, for example, about 2.5 V. Thus, for a voltage VDIFF = CAN_H - CAN_L for the recessive states, a value of 0V and for the dominant states have a value of approximately 2.0 V, as can be read from FIG. 4.

If the transceiver 22 detects the end of the arbitration phase, the transmission stage 220 is switched from the state shown in FIG. 4 to the state in which the signal curves of FIG. 5 result for the respective bus levels generated by the transmission stage 220.

Referring to FIG. 5, in the faster data phase comprising fields 453-455, for signals 411, 421, after switching from the state of FIG. 4, an idle state idle_LP is reached directly after switching, which in the particular example of FIG Fig. 5 sets a bus level of about 0V. In general, the state of a bus level should be about 0V after the Switchover does not occur. Thereafter, an idle state idle is reached at which, in the particular example of FIG. 5, a bus level of approximately 2.5V is established before bus states corresponding to data states Data_0 and Data_l are reached. Here, the signal 411 for the bus state corresponding to the data state Data_0 via the NMOS transistor of the third output stage 227 is pulled to about 1.5V. On the other hand, the bus state signal 421 corresponding to the data state Data_0 is pulled to about 3.5V via the PMOS transistor of the fourth output stage 228. Data_l is achieved by pulling the signal 411 to about 3.5 V via the PMOS transistor of the first output stage 225 and pulling the signal 421 to about 1.5 V via the NMOS transistor of the second output stage 226. In the states described, bus level 3 has bus level between about -0.6 V and about -2 V in the state Data_0 and bus level between about 0.6 V and about 2 V in the state Data_l. In the states Data_0 and Data_l, a differential voltage U_D of the signals 421, 411 thus as a rule has a maximum amplitude of approximately 1.4 V.

In other words, in a first operating mode according to FIG. 4, the transmission stage 220 generates a first data state, for example Data_l, as bus state with different bus levels for two bus wires 41, 42 of the bus line and a second data state, for example Data_0, as bus state with the same bus level for the bus two bus wires 41, 42 of the bus line 3.

In addition, in a second mode comprising the data phase, the transmit waveform 220 for the waveforms 411, 421 of FIG. 5, both the first and second output stages 225, 226 conduct and disable the final stages 227, 228 when a first data state For example, the state Data_l, to be driven to the bus line 3. In contrast, the transmission stage 220 switches the third and fourth output stages 227 and 228 conductive and blocks the output stages 225, 226 when a second data state, for example the state Data_0, is to be driven onto the bus line 3. Thus, in the second mode, the transmission stage 220 is configured to generate the first and second data states as a bus state having different bus levels for the two bus wires 41, 42 of the bus line 3, respectively As a result of the described switching of the transmission stage 220, in the data phase far higher data rates than with CAN or CAN-FD can be achieved. In addition, the data length in the data field 454 can be increased up to 4096 bytes. Thereby, the advantages of CAN with respect to the arbitration can be maintained and yet a larger number of data can be effectively transmitted in a shorter time than before, that is, without a repetition of the data due to a fault would be necessary, as explained below.

Another advantage is that error frames in the bus system 1 are not required in the transmission of messages 5. As a result, messages 5 are no longer destroyed, which eliminates a cause for the need for duplicate message transmission. This increases the net data rate.

In addition, it is possible with the transmission stage 220, several domains or

Sub-bus 1 to connect here by means not described in detail switches as needed. Thus, the networking in a technical system, for example, in a vehicle can be significantly expanded.

FIG. 6 shows voltage profiles of bus signals 412, 422 and 413, 423 according to a second exemplary embodiment. The voltage curves of the bus signals 412, 422 and 413, 423, arise when the switches 229 of the transmission stage 220 of FIG. 3 omitted or kept in the closed state, so that the transistors of the output stages 227, 228 connected directly to the terminals 211 are.

Fig. 7 shows the resulting transmission stage 220A of the second

Embodiment.

Thus, according to the second embodiment, a physical layer is used for the entire frame 45 of FIG

Arbitration phase for the fields 451, 452 and 456 and a long and fast data phase for the fields 453, 454, 455 allowed. The advantage of switching the transmitting stage 220A into such an operating mode is that the transmitting stage 220A is constructed completely symmetrical and also in all communication phases works symmetrically. Thus, the value of the bus load resistor 43 is not switched as described above with reference to FIGS. 3 and 4.

In Fig. 6, the resulting bus signals are shown in all four possible bus states DF1, DF2, A1, A2 in such a transmit stage 220A. The

Differential voltage U_D2 of the bus states DF1, DF2 has a greater amplitude than the differential voltage U_D3 of the bus states Al, A2. Here, the amplitude of the differential voltage U_D2 has a value that is n times greater than a value of the amplitude of the differential voltage U_D3, where n is a natural number that can be selected as desired. However, the upper limit for the number of subscriber stations 10, 20, 30 in the bus system 1 is calculated as n-1. The amplitude of the differential voltage U_D3 can therefore also be referred to as the amplitude basic unit.

The two bus states DF1 and DF2 are communicated after completed arbitration in the data phase, ie in fields 453 to 455. This is similar to the procedure described above with respect to FIG. The bus state DF1 has a positive differential voltage Vdiff = U_D2 (V_Plus - V_minus). The bus state DF2 has a negative differential voltage Vdiff = -U_D2. The bus state Al results in a positive differential voltage Vdiff = U_D3 (V_Plus - V_minus). Bus state A2 results in a negative differential voltage Vdiff = -U_D3.

Bus states Al and A2 are introduced to allow arbitration. The bus states Al, A2 are qualitatively equal to the bus states DF1 and DF2, but are driven weaker by the transmit stage 220A than the bus states DF1, DF2, as illustrated in FIG. Therefore, the bus states Al, A2 can be overwritten by other subscriber stations 10, 30 for arbitration purposes.

During an arbitration phase, the subscriber stations 10, 20, 30, in particular the transmitting stage 220A, are configured to transmit a differential voltage Vdiff having an amplitude basic unit, ie U_D3 = 1 unit, to the bus line 3 and to check which differential voltage Vdiff is present on the bus line 3. If a differential voltage Vdiff> 1 unit or Amplitude basic unit, the affected subscriber station 10, 20,

30 back and is therefore losers of arbitration.

Thus, in the present embodiment, the transmit stage 220A, in a first mode of operation, switches between the two first different bus states A1, A2 for the message, when data of the arbitration phase or first phase 456, 451, 452 is to be sent from the message 5. In addition, the switches

Sending 220A in a second mode with the two second different bus states DF1, DF2 for the message 5, when data 5 of the data phase or second phase 453, 454, 455 are to be sent from the message. The transmission stage 220A thus switches between more than two different bus states DF1, DF2, A1, A2 in order to transmit the message 5 or the frame 45. In each case, the two bus states DF1, DF2 are symmetrical to each other. In addition, the two bus states Al, A2 are symmetrical to each other. Of course, even more than the four bus states mentioned above are possible.

Thereby, in the present embodiment both in the

Arbitration as well as in the data phase always all components of

Transmission level 220A active and involved, resulting in maximum symmetry.

As a result, there are advantages in the bit timing and timing of the message 5 bits and electromagnetic compatibility (EMC).

In addition, with the configuration of the transmission stage 220A in the present embodiment, the same advantages as previously described with respect to the first embodiment can be obtained.

According to a modification of the second embodiment, arbitration instead of the bus states Al with A2 becomes one of the following

Combinations of bus states used:

- Bus state DF1 with bus state A2

- Bus state DF2 with bus state Al

According to a further modification of the second exemplary embodiment, in a further embodiment, all four bus states DF1, DF2, A1, A2 are used at least for transmitting the data field 454. In addition, one use of the four Bus states DF1, DF2, A1, A2 in the fields 453, 455 possible. By

Coding can thus increase the bitrate.

According to yet another modification of the second embodiment, the frequency of the signals 412, 422, 413, 423 is reduced. This is one

Improvement in the EMC behavior achievable. Due to the coding described above in more than two bus states, the bit rate can be kept constant despite lower frequency.

Otherwise, the same applies, as previously described in connection with the first embodiment.

FIGS. 8 and 9 show voltage profiles of bus signals CAN_H, CAN_L for explaining the behavior of a bus system 1 according to a third exemplary embodiment.

8 shows the known voltage profiles of the bus signals CAN_H and CAN_L, which are used to transmit a message 5 or a frame 45 according to the present embodiment for the arbitration phase 456, 451, 452 of the frame 45. The voltage profiles of the bus signals CAN_H and CAN_L show a significantly slower state change in the case of a transition from a dominant state 46 to a recessive state 47 than during a transition from the recessive state 47 to the dominant state 46.

In contrast, however, in the present exemplary embodiment, signals CAN_EL_H and CAN_EL_L according to FIG. 9 are generated for the data phase 453, 454, 455 of the frame 45, which have a high state 461 and a low state 471. The signals according to FIG. 9 are generated with a physical layer, in which the high states 461 resemble a dominant state 46 of CAN or CAN FD, as shown in FIG. 8 and FIG

Voltage values for CAN_H = 3.5 V and CAN_L = 1.5 V has. In addition, in the physical layer according to FIG. 9, low states 471 are generated which, in terms of their level, resemble a recessive state 47 of CAN or CAN FD, as shown in FIG. 8, and values for CAN_H = CAN_L = 2 , 5 V has. As shown in FIG. 9, the transition from the high state 461 to the low state 471 occurs about as fast as the transition from the low state 471 to the high state 461.

This is accomplished by driving the low states 471 low-ohmic.

G, low-ohmic recessive "). Thereby, the slower transition from the dominant state 46 to the recessive state 47 as shown in FIG. 8 is accelerated in the signals of FIG. As a result, for the

Data phase 453, 454, 455 of the frame 45 bit rates can be achieved well above 2 Mbps.

Therefore, in the present embodiment, with the transceiver 22 and / or the transceiver 32, when the end of the arbitration phase is detected, the CAN physical layer is switched to another physical layer. Since error frames or error frames can be dispensed with, no other subscriber station 10, 20, 30 must be able to drive over the currently transmitting subscriber station 10, 20, 30 in the data phase. Consequently, in the data phase, no recessive (high-impedance)

Bus states needed.

The physical layer for the waveforms according to FIG. 9 can be achieved, for example, with a transmission stage 2200 according to FIG. 10.

Thus, as shown in FIG. 10, unlike the transmitting stage 220 of FIG. 3, the transmitting stage 2200 according to the present embodiment thus has a third output stage 2270 connected to a voltage source 232 and a fourth output stage 2280 connected to a voltage source 233 is. The third output stage 2270 has an NMOS transistor and a diode. The fourth output stage 2280 has a PMOS transistor and a diode. The transistors of the first and second output stage 225, 226 are driven via a driver circuit 230 with the transmission signal TxD. The transistors of the third and fourth output stage 225, 226 are driven via a driver circuit 231 with the transmission signal TxD. In the data phase of the frame 45, that is, at a high bit rate, a high state 461 is imaged in that the output stages 225, 226 controlled via the driver circuit 230 become conductive or are switched active, and the output stages 227, 228 and 13 controlled via the driver circuit 231

Voltage sources 232, 233 are high-impedance or switched off. In order to drive a low state 471 (low-impedance driven recess), the drive capability, in particular high, of the output stages 225, 226 controlled via the driver circuit 230 is reduced and that via the driver circuit 231

Controlled output stages 227, 228 and voltage sources 232, 233 become conductive. The reduction of the drive capability also includes the case that the output stages 225, 226 are turned off, which means the strongest reduction of the drive capability. Thus, the NMOS transistor of the third output stage 2270 pulls the terminal 221 for CAN-EL_H at 2.5 V and the PMOS transistor of the fourth output stage 2280 raises the terminal 221 for CAN-EL_L to 2.5 V, thereby a low-bus state 471 arises.

The circuit of FIG. 10 is particularly useful in junction-isolated semiconductor technologies.

As a result, in the present exemplary embodiment, a very good symmetry of the bus signals is achieved in the data phase. As a result, there are advantages in the bit timing and timing of the message 5 bits and electromagnetic compatibility (EMC).

In addition, with the embodiment of the transmission stage 2200 in the present embodiment, the same advantages can be achieved as previously described with respect to the first and second embodiments.

The above-mentioned low-state low-resistance 471 (low-resistance recessed) principle can alternatively be used for all other serial bus systems in which recession states are present.

Otherwise, the same applies, as previously described in connection with the first embodiment. FIGS. 11 and 12 show voltage profiles of bus signals CAN_EL_H1, CAN_EL_L1 and CAN_EL_H2, CAN_EL_L2 for explaining the behavior of a bus system 1 according to a fourth exemplary embodiment.

The voltage profiles of the bus signals CAN_EL_H1, CAN_EL_L1 of FIG. 11 are equal to the voltage characteristics of the bus signals CAN_EL_H, CAN_EL_L of FIG. 9. The difference, however, is that the transmission stage 2200 of FIG. 10 shows the voltage characteristics of the bus signals CAN_EL_H1, CAN_EL_L1 of FIG generated in the arbitration phase of the frame 45. Alternatively, however, the voltage characteristics of the bus signals CAN_H, CAN_L of Fig. 8 in the

Arbitration phase of the frame 45 usable.

In contrast, the transmission stage switches 2200 at the present

Embodiment, when the end of the arbitration phase is detected, in a mode in which the transmission stage 2200 generates the voltage waveforms of the bus signals CAN_EL_H2, CAN_EL_L2 of FIG. 12 for the data of the data phase of the frame 45. The bus signal CAN_EL_H2 of FIG. 12 has a voltage level of about 3.0V in a dominant state 462. The high state 461 of FIG. 11, which is also a dominant state, corresponds to the dominant state 462 of FIG Bus signal CAN_EL_L2 of FIG. 12 has a voltage level of about 2.0 V in the dominant bus state 462. Thus, the dominant bus state 462 has voltage levels for the bus signals CAN_EL_H2, CAN_EL_L2 which are opposite to the voltage levels for the dominant bus state 461 of the bus signals CAN_EL_H1, CAN_EL_L1 in FIG the arbitration phase are reduced. As a result, the differential voltage Vdiff = CAN_EL_H2 - CAN_EL_L2 of the signals from FIG. 12 is also only 1.0 V and is thus smaller than, more precisely, only half as large as, the difference voltage Vdiff of the signals from FIG. 11 or FIG. provided the bus load resistor 43 remains the same. By contrast, the low states 471 are unchanged.

Compared to the bus signals according to FIG. 8 and FIG. 9 of the preceding exemplary embodiment, more stable signal paths to Vdiff result in the present exemplary embodiment, which means that smaller transmission levels are received by the subscriber stations 20, 30, more precisely their transceivers 22, 32, allows. With the described signals of FIG. 11 and FIG. 12, a greatly increased bit rate of> 12 Mpbs and a data volume of up to 4096 bytes can be run both in at least the data field 454, as already described above. However, by switching over the bus signals in the data phase to the bus signals CAN_EL_H2, CAN_EL_L2, the current consumption and thus the power consumption of the transmission stage 2200 can be significantly reduced compared with the preceding embodiments, even if much more per time

Switching operations take place as with CAN or CAN FD. This is achieved by lowering the transmission level or the amplitude of VDIFF at least in the data field 454.

In order to achieve usable signal integrity with increasing bit rate, the topologies of the bus systems 1 must be greatly simplified. Thus, there is the advantage here that due to the reduced transmission level also a lower radiation is present and thereby the EMC compatibility is improved.

Otherwise, the same applies, as previously described in connection with the third embodiment.

In a modification of the third embodiment, the transmit stage 2200 of FIG. 10 has no output stages 2270, 2280. In this case, the transmit stage 2200 of FIG. 10 is configured as a conventional CAN transmit stage. In order to achieve the above-described signal profiles of FIGS. 11 and 12, such a conventional CAN transmission stage is controlled such that for dominant states or high states 461 outside the data phase, that is to say signal curves according to FIG The output stages 225, 226 are operated "normally" as with CAN. In contrast, for dominant states 462 of FIG. 12, ie in the data phase 225 and 226, the driver or power amplifiers 225, 226 are operated at higher impedance, whereby the level of the respective dominant states 462 compared to the level of the respective dominant states or High states 461 is reduced.

Fig. 13 shows an example of a coupling of the transmitting / receiving devices 22 to the bus line 3 with its two bus wires 41, 42. The coupling can at all transceivers 22, 32 of the preceding

Embodiments and their transmission levels 220, 220A, 2200 are used.

For the coupling of the transmitting / receiving device 22 to the bus line 3, a first coupling capacitor 251 for the coupling of the transmitting / receiving devices 22 to the first bus core 41 and a second

Coupling capacitor 251 for the coupling of the transmitting / receiving devices 22 to the second bus line 42 is provided. In addition, a resistor 255 is provided between the terminal 223 for the power supply for the first and second bus wires 41, 42 and the terminal 221 for the first bus wire 41. In addition, a resistor 256 is provided between the terminal 223 and the terminal 222 for the second bus wire 42.

The capacitors or coupling capacitors 251, 252 are provided externally of the respective transceivers 22. The

Coupling capacitors 251, 252 realize in contrast to other serial bus systems 1, such as CAN or CAN-FD or Flexray, etc., a galvanically isolated connection of the respective transmitting / receiving device 22 to the bus wires 41, 42nd

Advantageous to the AC coupling or AC coupling or

AC coupling by means of the coupling capacitors 251, 252 is that common mode noise (common mode interference) on the bus line 3, the respective existing transmission stage 220, 220A, 2200 of the preceding

Embodiments or as shown in FIG. 13 do not disturb. Another advantage is that the respective existing transmission stage 220, 220A, 2200 of

preceding embodiments or according to FIG. 13 due to galvanic insulation or separation in low-voltage CMOS technology (CMOS = complementary metal-oxide semiconductor = semiconductor components in which both p-channel and n-channel MOS Transistors can be used on a common substrate).

As a result, a significantly higher accuracy between the two pin driver stages of the output stages 225, 226 and faster switching times result. As a result, the speed of transmission of the data in the bus system 1 of the previously described embodiments can be further increased.

In the circuit of Fig. 13, the transmission stage is configured to connect the first and second coupling capacitors (251, 252) with high or low

Currents to the respective levels of a dominant or recessive bus state and the high bus state (461; 462) and the low bus state (471), respectively.

As shown very schematically in FIG. 14, according to a modification of the fifth embodiment, instead of the resistor 255, which is interposed between the

Terminal 223 is provided for the power supply for the first and second bus wires 41, 42 and the terminal 221 for the first bus wire 41, a transistor 257 is provided. In addition, instead of the resistor 256 provided between the terminal 223 and the terminal 222 for the second bus wire 42, a transistor 258 is provided. Also in this way can be performed with the coupling capacitors 251, 252, the galvanically isolated connection of the respective transmitting / receiving device 22 to the bus wires 41, 42.

All of the previously described embodiments of the bus system 1, the

Subscriber stations 10, 20, 30 and the method carried out by them can be used individually or in all possible combinations. In particular, all the features of the previously described

Embodiments and / or their modifications are arbitrarily combined. Additionally or alternatively, in particular the following modifications are conceivable.

The bus system 1 according to the exemplary embodiments described above is described on the basis of a bus system based on the CAN protocol. However, the bus system 1 according to the embodiments may be another type of communication network in which data is serially transferable at two different bit rates. It is advantageous, but not necessarily a prerequisite, that in the bus system 1 at least for certain periods of time an exclusive, collision-free access of a

Subscriber station 10, 20, 30 is ensured on a common channel. The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 of the embodiments is arbitrary. In particular, the subscriber station 10 can be omitted in the bus system 1. It is possible that one or more of the subscriber stations 20 or 30 are present in the bus system 1.

Claims

claims

1) subscriber station (20; 30) for a serial bus system (1), with

a transmission stage (2200) for transmitting a message (4; 5) to a bus line (3) of the bus system (1),

wherein the transmitting stage (2200) includes power amplifiers (225, 226, 2270, 2280) for switching differential bus signals for a message (5) between a high bus state (461; 462) and a low bus state (471),

wherein the transmission stage (2200) is configured such that for at least a first phase for transmitting data of the message (5), the differential bus signals (CAN_EL_H2; CAN_EL_L2) for a low bus state (471) have the same level and the low bus state (471) is driven low impedance, and

wherein the transmit stage (2200) is configured such that for a second phase (453; 454; 455) to transmit data of the message (5), a bus state (461) comparable to the high bus state (462) smaller difference voltage between the differential bus signals (CAN_EL_H1; CAN_EL_L1) than a differential voltage between the differential bus signals

(CAN_EL_H1; CAN_EL_L1) in the high bus state (462).

2) subscriber station (20; 30) according to claim 1,

wherein the sending stage (2200) is configured to switch to a first mode with two first different bus states (461, 471) for a message (5) when the first message (456; 451; 452) is received by the message (5). which are to be sent at a first bit rate, and

wherein the transmit stage (2200) is configured to switch to a second mode with the high bus state (462) and the low bus state (471) for a message (5) when from the message (5) Data of a second phase (453; 454; 455) to be transmitted at a second bit rate faster than the first bit rate.

3) subscriber station (20; 30) according to claim 2, wherein the transmission stage

(2200) is adapted to switch to only the second mode for transmitting data when the subscriber station (20; 30) has exclusive, collision-free access to the data for a predetermined time

Bus line (3) of the bus system (1) is guaranteed.

4) The subscriber station (20; 30) according to one of the preceding claims, wherein the transmission stage comprises (2200)

a first output stage (225) which is connected between a connection (223) for a voltage supply and a first bus line (41),

a second output stage (226) connected between a second bus line (42) and a ground terminal (224),

wherein the second stage high bus states (462) (225, 226) are operative to have a higher impedance for transmitting data of the message (5) than for first stage high bus conditions (461, 454; 455) of data of the message (5).

5) subscriber station (20; 30) according to one of claims 1 to 3,

The subscriber station (20; 30) of any one of the preceding claims, wherein the transmit stage comprises (2200)

a first output stage (225) connected between a terminal (223) for a power supply and a first bus wire (41) of the

Bus line (3) is connected,

a second output stage (226) connected between a second bus core (42) of the bus line (3) and a ground terminal (224),

a third output stage (2270) connected between the first bus core (41) of the bus line (3) and a first voltage source (232) as a reference for the low bus state (471), and a fourth output stage (2280) connected between a second

Voltage source (233) as a reference for the low-bus state (471) and the second bus wire (42) of the bus line (3) is connected.

6) subscriber station (20; 30) according to claim 4 or 5,

wherein the first output stage (225) comprises a PMOS transistor, and

wherein the second output stage (226) comprises an NMOS transistor.

7) subscriber station (20; 30) according to claim 5,

wherein the fourth output stage (2280) comprises a PMOS transistor, and

wherein the third output stage (2270) comprises an NMOS transistor.

The subscriber station (20; 30) of any of claims 5 to 7, wherein the transmit stage (2200) is configured to reduce the drive capability of the first and second output stages (225, 226) for a low bus state (471) and the third one and fourth output stage (2270, 2280) to turn conductive.

The subscriber station (20; 30) of any of the preceding claims, wherein the message (5) comprises a data field (454) of variable length, the variable length being between 1 byte and 4096 bytes.

10) Bus system (1), with

a parallel bus line (3), and

at least two subscriber stations (10; 20; 30) which are connected to one another via the bus line (3) such that they can communicate with one another,

wherein at least one of the at least two subscriber stations (10; 20; 30) has a subscriber station (20; 30) according to one of the

preceding claims. 11) A method of transmitting a message (5) in a serial bus system (1), the method comprising the step of:

Transmitting, with a transmission stage (2200) of a subscriber station (20; 30) of the bus system (1), a message (4; 5) onto a bus line

(3) of the bus system (1),

wherein the transmit stage (2200) with power amplifiers (225, 226, 2270, 2280) switches differential bus signals for a message (5) between a high bus state (461; 462) and a low bus state (471), the transmit stage (2200 ) is constructed such that for at least a first phase for transmitting data of the message (5) the differential bus signals (CAN_EL_H2; CAN_EL_L2) for a low bus state (471) have the same level and the low bus state (471) is driven low impedance will, and

(CAN_EL_H1; CAN_EL_L1) in the high bus state (462).