WO2023280472A1

WO2023280472A1 - Receiving module and method for receiving differential signals in a serial bus system

Info

Publication number: WO2023280472A1
Application number: PCT/EP2022/064757
Authority: WO
Inventors: Steffen Walker; Felix Lang
Original assignee: Robert Bosch Gmbh
Priority date: 2021-07-08
Filing date: 2022-05-31
Publication date: 2023-01-12
Also published as: DE102021207188A1

Abstract

The invention relates to a receiving module (122) and a method for transmitting differential signals in a serial bus system (1). The receiving module (122) has a comparator (1224) for analyzing the differential signals (CAN_H, CAN_L) received by a bus (40) of the bus system (1) using a reception threshold (T1; T3); a voltage divider (1221) which is connected to the bus (40) for providing the differential signals (CAN_H, CAN_L) received by the bus (40) to the comparator (1224), and a receiver bit time adapting circuit (15) for compensating for a bit time distortion in a signal (CA) output by the comparator (1224), wherein the receiver bit time adapting circuit (15) has at least one change stage (151) for time-shifting a flank in the signal (CA) output by the comparator (1224).

Description

description

title

Receiving module and method for receiving differential signals in a serial bus system

The present invention relates to a receiving module and a method for receiving differential signals in a serial bus system, which can be used in a transceiver.

State of the art

Serial bus systems are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control devices in a vehicle or a technical production facility, etc. There are various standards or data transmission protocols for data transmission. In particular, a CAN bus system, an LVDS bus system (LVDS=Low Voltage Differential Signaling), an MSC bus system (MSC=Micro Second Channel), and a 10BASE-T1S Ethernet are known.

In a CAN bus system, messages are transmitted using the CAN and/or CAN FD protocol, as described in the ISO-11898-1:2015 standard as a CAN protocol specification with CAN FD. With CAN FD, during transmission on the bus, there is a switch back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). With a CAN FD bus system, a data transmission rate of more than 1 MBit per second (1Mbps) is possible in the second communication phase. CAN FD becomes used by most manufacturers in the first step with 500kbit/s arbitration bit rate and 2Mbit/s data bit rate in the vehicle.

In order to enable even higher data rates in the second communication phase, there are successor bus systems for CAN FD, such as CANSIC and CAN XL. With CANSIC according to the CiA601-4 standard, a data rate of around 5 to 8 Mbit/s can be achieved in the second communication phase. With CAN XL, a data rate of > 10 Mbit/s is required in the second communication phase, whereby the standard (CiA610-3) for this is currently being defined by the CAN in Automation (CiA) organization. In addition to pure data transport via the CAN bus, CAN XL should also support other functions such as functional safety (safety), data security (security) and quality of service (QoS = Quality of Service). These are elementary properties that are required in an autonomously driving vehicle.

In all of the above-mentioned CAN-based bus systems, a bus signal CAN_H and ideally a bus signal CAN_L are driven onto a bus separately for a transmission signal TxD. In this case, at least in the first communication phase, a bus state is actively driven in the bus signals CAN_H, CAN_L. The other bus state is not driven and is set due to a terminating resistor for bus lines or bus cores of the bus. As a result, the edge steepness in a transition from the driven bus state to the non-driven bus state is lower than in a transition from the non-driven bus state to the driven bus state.

In order to send and receive the bus signals, transceivers, which are also referred to as CAN transceivers or CAN FD transceivers, etc., are usually used in a CAN bus system for the individual communication participants. With CAN XL, the transmitting/receiving devices must be able to send the bus signals CAN_H, CAN_L to the bus in the second communication phase with a different physical layer than in the first communication phase. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection model). This means that with CAN XL the data in the second communication phase can be sent to the bus at a significantly higher data rate than in the first communication phase.

The bus signals CAN_H, CAN_L on the bus have the different bus states dominant and recessive at least in the first communication phase. Since the dominant bus state is actively driven, but the recessive one is not, the resulting differential signal VDIFF = CAN_H - CAN_L does not have an ideal square-wave curve over time, but the edges fall relatively flat, especially at the transition from a dominant to a recessive state. Since the permissible values for VDIFF may vary from 1.5 V to 3.0 V, sampling the difference signal VDIFF with the same reception threshold results in very different time durations for the non-driven bus state (recessive).

In addition, the bit durations vary during operation of the bus system due to, for example, the variation in the supply voltage of the transceiver or the variation in the junction temperature of semiconductors in the transceiver. All of this makes it difficult or impossible for specified limit values for bit timing to be met. As a result, the correct evaluation of the levels of the bus signals CAN_H, CAN_L is not always ensured.

Disclosure of Invention

It is therefore the object of the present invention to provide a receiving module and a method for receiving differential signals in a serial bus system which solve the aforementioned problems. In particular, the receiving module and the method for receiving differential signals in a serial bus system are intended to enable reliable and uncomplicated compliance with the required values for the bit timing even when the framework conditions in the running bus system change.

The object is achieved by a receiving module for receiving differential signals in a serial bus system having the features of claim 1 solved. The receiving module has a comparator for evaluating the differential signals received from a bus of the bus system with a receiving threshold, a voltage divider connected to the bus for providing the differential signals received from the bus for the comparator, and a receiver bit time adjustment circuit for compensating for a bit time distortion in a signal output by the comparator, the receiver bit time adjustment circuit having at least one modification stage for shifting an edge in time in the signal output by the comparator.

The receiving module described is designed in such a way that bit-time distortions can be minimized. In this way, effects can be compensated for which arise from variations in the sizes of the communication during ongoing operation of the bus system and thus of the receiving module. This ensures that the bits sent on the bus can be received correctly.

The receiving module can meet bit timing limits, particularly for the delta_trec parameter. The delta_trec parameter specifies the variation of a bit width that may occur when receiving with the transceiver ("receiver timing symmetry"). delta_trec=time length of a recessive bit of the received signal RxD—time length of a recessive bit on the bus.

In particular, the receiving module can detect the variation in the amplitude of the differential voltage VDIFF = CAN_H - CAN_L, which occurs in the transmitting module of its own transmitting/receiving device, the variation in the supply voltage of the transmitting/receiving device, the variation in the junction temperature of semiconductors in the transmitting/receiving device Receiving device, compensate for fluctuations and mismatches (mismatch) in the manufacturing process for the components used in the receiving module. This is particularly advantageous for compliance with the limit values of the delta_trec parameter, since the variation in the amplitude of the differential voltage VDIFF = CAN_H - CAN_L of the transmission module can vary from 1.5V to 3.0V according to the CiA610-3 standard and has a major impact on the value of the delta trec parameter. In addition, the design of the receiving module helps to comply with the delta_tbit_RxD parameter in accordance with the CiA610-3 standard. The parameter delta_tbit_RxD specifies the variation of a bit width of a recessive bit that may occur when sending and receiving with one and the same transceiver ("received bit width variation"). delta_ tbit_RxD=temporal length of a recessive bit of the received signal RxD-temporal length of a recessive bit of the transmitted signal TxD.

The design of the receiving module thus contributes significantly to reliable and safe detection of bus signals during operation of the bus system. This also applies in particular to such communication in which the physical layer is switched between two communication phases for communication on the bus.

In this case, the receiver module described enables the requirements for communication to be met in accordance with the requirements of CAN XL, which are specified in particular in the CiA610-3 standard. In addition, the requirements for CAN FD or CAN SIC, for example, can be met.

As a result, the receiving module allows the error rate of communication on the bus to be low. This means that not only is communication in the bus system implemented with higher bit rates, but also that the transmittable bit rate is not reduced by communication errors.

Advantageous further configurations of the receiving module are described in the dependent claims.

The at least one modification stage may include a resistor and a capacitor that are adjustable to adjust the timing shift of the edge.

According to one embodiment, the at least one change stage also has a current mirror with a first and a second transistor, the resistor being connected between the first and second transistor, the The capacitor is connected in series with the first transistor and the capacitor is connected in parallel with a series combination of the resistor and the second transistor.

Possibly the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

According to one configuration, the receiver bit-time adjustment circuit also has a logic module which is designed as an inverter, the receiver bit-time adjustment circuit having a first change stage and a second change stage, and the logic module being connected before the second change stage, so that in the first change stage the inverted signal output from the comparator is input.

According to one embodiment, the receiver bit time adjustment circuit also has a logic circuit for outputting a signal processed by at least a first modification stage or a signal processed by at least a second modification stage in response to a selection signal.

Optionally, the amount of the change over time in the bit time of a first change level can be set differently from the amount of the change over time in the bit time of a second change level.

The receiving module can also have a drive circuit for driving the receiver bit time adjustment circuit in such a way that the circuit outputs a signal with an extended bit time or a signal with a shortened bit time for a recessive bit of the differential signals received from a bus of the bus system.

Here the control circuit is possibly designed to switch over the receiving threshold for evaluating the differential signals received from the bus depending on an operating mode of the receiving module into which the receiving module is to be switched for a first or second communication phase of a communication on the bus. It is conceivable that the configuration of the receiver bit time adjustment circuit can be set differently depending on an operating mode of the receiving module.

For example, the amount of the change over time in the bit time of the at least one change stage can be set differently depending on an operating mode of the receiving module.

According to one embodiment, the receiver bit time adjustment circuit can be bypassed depending on an operating mode of the receiving module.

The voltage divider can have a circuit of resistors to which an input filter for the comparator is connected.

The receiving module can also have an input filter which is connected between the voltage divider and the comparator, the input filter having an RC element for a first signal of the differential signals and an RC element for a second signal of the differential signals, and the voltage divider comprises a circuit of resistors to which the input filter is connected.

The reception module described above can be part of a transmission/reception device for a subscriber station for a serial bus system. The transceiver can also have a transmission module for sending signals to a bus of the bus system.

The transmitting/receiving device described above can be part of a subscriber station for a serial bus system. The subscriber station can also have a communication control device for controlling the communication in the bus system and for generating a digital transmission signal for the transmission module.

Optionally, the subscriber station is designed for communication in a bus system in which exclusive, collision-free access of a subscriber station to the bus of the bus system is guaranteed at least temporarily. The aforementioned object is also achieved by a method for receiving differential signals in a serial bus system having the features of claim 15. The procedure comprises the steps

Receiving, with a receiving module, differential signals from a bus of the bus system, the receiving module being connected to the bus with a voltage divider, providing the differential signals with the voltage divider for a comparator, evaluating the differential signals with the comparator with a receiving threshold, and Compensating, with a receiver bit time adjustment circuit, a bit time distortion in a signal output by the comparator, wherein the receiver bit time adjustment circuit has at least one modification stage for shifting in time an edge in the signal output by the comparator.

The method offers the same advantages as previously mentioned in relation to the receiving module.

Further possible implementations of the invention also include combinations of features or embodiments described above or below with regard to the exemplary embodiments that are not explicitly mentioned. The person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

drawings

The invention is described in more detail below with reference to the attached drawing and using exemplary embodiments. Show it:

1 shows a simplified block diagram of a bus system according to a first exemplary embodiment;

2 shows a diagram to illustrate the structure of a message that can be sent by a subscriber station of the bus system according to the first exemplary embodiment; FIG. 3 shows an example of the ideal time profile of bus signals CAN_H, CAN_L in the bus system of FIG. 1;

FIG. 4 shows the time profile of a differential voltage VDIFF which forms on the bus of the bus system as a result of the bus signals from FIG. 4;

5 shows a simplified block diagram of a transceiver with a receiver module for a subscriber station of the bus system according to the first exemplary embodiment;

6 is a circuit diagram of the receiving module according to the first embodiment;

FIG. 7 shows a first example of an output signal of an output filter of the receiving module of FIG. 6;

FIG. 8 shows an output signal of a receiver bit time adjustment circuit of the receiving module of FIG. 6, which results from the signal of FIG. 7;

FIG. 9 shows a second example of an output signal of the output filter of the receiving module of FIG. 6;

FIG. 10 shows an output signal of the receiver bit time adjustment circuit of the receiving module of FIG. 6, which results from the signal of FIG. 9;

11 is a circuit diagram of a receiver bit time adjustment circuit of the receiving module according to the first embodiment;

12 shows a simplified block diagram of a transceiver with a receiver module for a subscriber station of the bus system according to a second exemplary embodiment;

13 shows an example of a time profile of a digital transmission signal which, according to the second exemplary embodiment, is in the arbitration phase (SIC operating mode) is to be converted into bus signals CAN_H, CAN_L for a bus of the bus system of FIG. 1;

14 shows the time profile of the bus signals CAN_H, CAN_L when changing from a recessive bus state to a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase (SIC operating mode) on the basis of the transmission signal from FIG. 13;

15 shows an example of a time profile of a digital transmission signal which, according to the second exemplary embodiment, is to be converted in the data phase into bus signals CAN_H, CAN_L for the bus of the bus system from FIG. 1; and

FIG. 16 shows the time course of the bus signals CAN_H, CAN_L, which are sent to the bus in the data phase on the basis of the transmission signal from FIG.

In the figures, elements that are the same or have the same function are provided with the same reference symbols unless otherwise stated.

Description of the exemplary embodiments

1 shows a bus system 1 which, for example, can be a CAN bus system, a CAN FD bus system, etc., at least in sections. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an airplane, etc., or in a hospital, etc.

In FIG. 1, the bus system 1 has a large number of subscriber stations 10, 20, 30, which are each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus cores 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46, 47 in the form of signals can be transmitted between the individual subscriber stations 10, 20, 30 via the bus 40. the Subscriber stations 10, 20, 30 can be control units or display devices of a motor vehicle, for example.

As shown in Fig. 1, the subscriber stations 10, 30 each have a communication control device 11 and a transceiver 12. The transceiver 12 has a transmit module 121 and a receive module 122.

Subscriber station 20 has a communication control device 21 and a transceiver 22. Transceiver 22 has a transmit module 221 and a receive module 222.

The transmitting/receiving devices 12 of the subscriber stations 10, 30 and the transmitting/receiving device 22 of the subscriber station 20 are each connected directly to the bus 40, even if this is not shown in FIG.

The communication control devices 11, 21 are each used to control communication between the respective subscriber station 10, 20, 30 via the bus 40 and at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

The communication control devices 11 create and read first messages 45, 47, which are modified CAN messages 45, 47, for example. In this case, the modified CAN messages 45, 47 are constructed, for example, on the basis of the CAN XL format. Transmitting/receiving device 12 is used to send and receive messages 45, 47 from bus 40. Transmitting module 121 receives a digital transmission signal TxD created by communication control device 11 for one of messages 45, 47 and converts this into signals on bus 40 around. The reception module 121 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them. The reception module 122 sends the reception signal RxD to the communication control device 11.

The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, ie like a CAN FD tolerant Classical CAN controller or a CAN FD controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages 46. The transceiver 22 is used to send and receive the messages 46 from the bus 40. The transmission module 221 receives a digital transmission signal TxD and created by the communication control device 21 converts this into signals for a message 46 on the bus 40. The reception module 221 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them. Otherwise, the transceiver 22 can be designed like a conventional CAN transceiver.

For sending the messages 45, 47 with CAN SIC or CAN XL, proven properties are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular frame structure with identifier and arbitration according to the known CSMA/CR method. The consequence of the CSMA/CR method is that there must be so-called recessive states on the bus 40 which can be overwritten by other subscriber stations 10, 20, 30 with dominant levels or dominant states on the bus 40.

With the two subscriber stations 10, 30, a formation and then transmission of messages 45 with different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, and the receipt of such messages 45 can be implemented, as described in more detail below .

2 shows a frame 450 for the message 45, which is in particular a CAN XL frame, as is provided by the communication control device 11 for the transceiver 12 for transmission onto the bus 40. Here, in the present exemplary embodiment, the communication control device 11 creates the frame 450 as compatible with CAN FD. Alternatively, the frame 450 is compatible with CAN SIC.

According to Fig. 2, the frame 450 for the CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a data field 455, a checksum field 456 and a frame termination field 457.

In the arbitration phase 451, an identifier (ID) with, for example, bits ID28 to ID18 in the arbitration field 453 is used to negotiate bit by bit between the subscriber stations 10, 20, 30 as to which subscriber station 10, 20, 30 is sending the message 45, 46 with the highest priority wants and therefore gets exclusive access to the bus 40 of the bus system 1 for the next time for sending in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).

An important point during phase 451 is that the known CSMA/CR method is used, which allows subscriber stations 10, 20, 30 to access the bus 40 simultaneously without the higher-priority message 45, 46 being destroyed. As a result, further bus subscriber stations 10, 20, 30 can be added to the bus system 1 relatively easily, which is very advantageous.

The consequence of the CSMA/CR method is that there must be so-called recessive states on the bus 40 which are detected by other subscriber stations 10, 20,

30 can be overwritten with dominant levels or dominant states on the bus 40. In the recessive state, the individual subscriber stations 10, 20, 30 have high-impedance conditions, which, in combination with the parasites of the bus wiring, results in longer time constants. This leads to a limitation of the maximum bit rate of today's CAN FD physical layer to around 2 megabits per second in real vehicle use.

In the data phase 452, in addition to part of the control field 454, the user data of the CAN-XL frame 450 or the message 45 from the data field 455 and the checksum field 456 are sent. In the checksum field 456, a checksum over the data of the data phase 452 including the stuff bits be included, which are inserted as an inverse bit by the sender of the message 45 after a predetermined number of identical bits, in particular 10 identical bits. At the end of the data phase 452, the arbitration phase 451 is switched back to.

At least one acknowledge bit may be included in an end field in the frame completion phase 457 . There may also be a sequence of 11 same bits indicating the end of the CAN XL frame 450. The at least one acknowledge bit can be used to communicate whether a receiver has discovered an error in the received CAN XL frame 450 or the message 45 or not.

A sender of the message 45 does not start sending bits of the data phase 452 to the bus 40 until the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending .

Thus, in the arbitration phase 451, the subscriber stations 10, 30 partially use a format known from CAN/CAN-FD in accordance with ISO11898-1:2015 as the first communication phase, in particular up to the FDF bit (inclusive). However, compared to CAN or CAN FD in the data phase 452 as the second communication phase, the net data transmission rate can be increased, in particular to more than 10 megabits per second. In addition, it is possible to increase the size of the user data per frame, in particular to around 2 kbyte or any other value.

3 shows on the left side that the subscriber stations 10, 20, 30 send signals CAN_H, CAN_L to the bus 40 in the arbitration phase 451, which alternately have at least one dominant state 401 or at least one recessive state 402. After the arbitration in the arbitration phase 451, one of the subscriber stations 10, 20, 30 is the winner. Assume that subscriber station 10 has won the arbitration. Then the transmitting / receiving device 12 of the subscriber station 10 switches its physical layer at the end of the arbitration phase 451 from a first mode (SLOW) to a second mode (FAST_TX), since the subscriber station 10 in the data phase 452 the transmitter Message 45 is. In the data phase 452 or in the second operating mode (FAST_TX), the transmission module 121 then generates the states LO or LI for the signals CAN_H,

CAN_L on the bus 40. The frequency of the signals CAN_H, CAN_L may be increased in the data phase 452 as shown on the right side in FIG. Thus, the net data transfer rate in the data phase 452 is increased compared to the arbitration phase 451. In contrast, the transceiver 12 of the subscriber station 30 switches its physical layer at the end of the arbitration phase 451 from the first mode (SLOW) to a third mode (FAST_RX), since the subscriber station 30 in the data phase 452 only receives, i.e. no transmitter, of the frame is 450. After the end of the arbitration phase 451, all transmitting/receiving devices 12 of the subscriber stations 10, 30 switch their operating mode to the first operating mode (SLOW). Thus, all transceivers 12 also switch their physical layer.

4 forms in the arbitration phase 451 in the ideal case on the bus 40, a difference signal VDIFF = CAN_H - CAN_L with values of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402. This is on the left side in 4 shown. In contrast, a differential signal VDIFF=CAN_H−CAN_L with states L0, LI is formed on bus 40 in data phase 452, as shown on the right-hand side in FIG. State L0 has a value VDIFF = IV. State LI has a value VDIFF = -IV.

The receiving module 122 can distinguish between the states 401, 402 with at least one of the receiving thresholds TI, T2, T3, which are in the ranges TH_T1, TH_T2, TH_T3. For this purpose, it is possible for the receiving module 122 to work in a time-continuous manner or to sample the signals from FIG. 3 or FIG. 4 at times t_A. Alternatively or additionally, the received signal RxD generated by the receiving module 122, more precisely the RxD level/bit, can be sampled in the communication control device 11 at the time of the sample point t_A. To evaluate the scanning result, the receiving module 122 uses the receiving threshold TI of, for example, 0.7 V in the arbitration phase 451, and in the case of CAN XL also the receiving threshold T2, for example -0.35 V. In contrast, the receiving module 122 in the data phase 452 only uses signals the one with the receiving threshold T3 = 0.0 V were evaluated. When switching between the first through third modes (SLOW, FAST_TX, FAST_RX) previously described with reference to FIG. 3, the receiving module 122 switches the receiving thresholds TI, 2, T3, respectively, as required 122 is switched over by a device which recognizes that there is a change in the coding of the data of the transmission signal TxD. In particular, NRZ coding in the transmission signal TxD can indicate that a switch is to be made to the arbitration phase 451 (SLOW). In particular, PWM coding in the transmission signal TxD can indicate which of the operating modes for the data phase 452 is to be switched to, namely FAST TX (subscriber station is the sender of the frame 450) or FAST RX (subscriber station is only the receiver of the frame 450).

The receiving threshold T2 is used to identify whether the bus 40 is free when the subscriber station 12 is newly added to the communication on the bus 40 and tries to integrate into the communication on the bus 40. In the standard for CAN, the receiving threshold T2 is called OOB for short (= Out-of- Boundary = outside the limit value). The conditions for a traffic-free CAN XL bus are that no dominant state 401 occurs, which typically has the differential voltage VDIFF = 2V. Thus, the reception threshold TI of 0.7 V, for example, must not be exceeded. In addition, no levels according to the LI state may occur, which typically has the differential voltage VDIFF=-IV. This means that the reception threshold T2, for example -0.35 V, must not be undershot.

Each subscriber station 10, 30 switches the operating mode of the transceiver 12 to the operating mode of the arbitration phase 451 when the subscriber station 12 is newly added to the communication on the bus 40.

On the one hand, it may be necessary to connect the subscriber station 10 if the subscriber station 10 is initially started and is to be integrated into the communication on the bus 40 . On the other hand, it may be necessary for the subscriber station 10 to be connected if the subscriber station 10 attempts to reintegrate itself into the communication on the bus 40 after an error in the bus communication. Only when it is recognized that the bus is free, the subscriber station 10 itself may send data, in particular messages 45, 47, to the bus 40 in the cases mentioned.

5 shows the basic structure of the transceiver 12 with an application-specific integrated circuit (ASIC) 16, in which the receiver module 122 is installed, in particular integrated. The ASIC has a memory 160 for storing at least one configuration value 161 for the transceiver 12. In addition, at least one value or at least one value range of a parameter 162 can be stored in the memory 160, which must be observed by the transceiver 12 during operation is. Such a parameter 162 is in particular the parameter delta_trec or another parameter.

For example, the ASIC is or has a circuit for safety-related functions of a technical system, in particular a vehicle. Such safety-related functions of a vehicle are, in particular, collision detection, a skid lane assistant, light control, reversing camera control, a fluid level indicator, in particular hydraulic oil for a brake system, washer fluid for a windscreen washer system, engine oil pressure detection, etc. For example, the system ASIC 16 is or has a circuit for comfort-relevant functions of a technical system, in particular a vehicle. Such comfort-related functions of a vehicle are in particular a navigation control, a parking assistance system, an automatically controlled windshield wiper system, etc. The system ASIC 16 has a circuit or circuit parts for an application of the vehicle in general, in particular for a control for special functions for operating the vehicle.

The transmission module 121 is only shown very simplified in FIG. The transmission module 121 is connected directly to the bus 40 in order to be able to transmit the transmission signal TxD from the communication control device 11 to the bus 40 in order to generate signals on the bus 40 in accordance with FIG.

The receiving module 122 has a voltage divider 1221, a bus biasing source 1222, an input filter 1223, a reception comparator 1224, an output filter 1224, a receiver bit time adjustment circuit 15 and a driver 1226 for the digital reception signal RxD. The receive comparator 1224 is a low voltage comparator.

In addition, the transceiver 12 has a control device 125 for controlling the receiver bit time adjustment circuit 15. For this purpose, the control device 125 outputs a selection signal S_sw to the receiver bit time adjustment circuit 15. This is described in more detail with reference to FIG.

The voltage divider 1221 is connected to the bus 40 in the receiving circuit 15 . During operation of the bus system 1, the voltage divider generates

1221 and the downstream input filter 1223 from the signals CAN_H, CAN_L signals S_l, S_2. The input filter 1223 forwards the signals S_1, S_2 to the reception comparator 1224. The reception comparator 1224 generates a digital comparator output signal CA from the signals S_1, S_2. The signal CA is output to the output filter 1225. The output filter 1225 generates a signal S_3 for the circuit 15. The receiver bit time adjustment circuit 15 generates an output signal S8 which has been adjusted with respect to the bit time from the signal S_3. The driver 1226 generates the digital reception signal RxD from the signal S8. The driver 1221 drives or sends the digital reception signal RxD to the communication control device 11.

Thus, the receiver bit time adjustment circuit 15 is connected between the bus 40 and the driver 1226. The comparator output signal CA depends on the communication mode in which the transceiver 12, for example the comparator 1224 or another component of the transceiver 12, is switched.

As shown in FIG. 6 as an example, the voltage divider 1221 is a resistive voltage divider or resistance voltage divider.

The voltage divider 1221 is powered by the bus biasing source (bus biasing)

1222 supplied with electrical voltage. The bus bias source 1222 typically supplies a voltage CAN_SUPPLY/2 to the receiving circuit 15, more specifically the voltage divider 1221. Typically, CAN_SUPPLY applies = 5V. In this case, the bus bias source 1222 provides a voltage of 2.5V to the receiving circuit 15. Specifically, the voltage from the bus bias source 1222 may be set to about 2.5V for the recessive state 402 (FIG. 3).

The voltage divider 1221 has a first and a second resistor R_CH1, R_CH2 for the bus signal CAN_H. In addition, the voltage divider 1533 has a third and fourth resistor R_CL1, R_CL2 for the bus signal CAN_L. The voltage divider 1221 divides the bus voltages generated by the signals CAN_H, CAN_L down to values which can be processed by the comparator 1224 . The divider factor k for differential signals, such as the CAN_H, CAN_L signals, is k = (R_CH1 + RCH2) / R_CH2 or k = (R_CL1 + RCL2)/R_CL2.

The connection of the resistors in the resistor network of the voltage divider 1224 is constructed symmetrically.

The first resistor R_CH1 is connected at one end to the bus core 41 (CANH). At its other end, the first resistor R_CH1 is connected in series with the second resistor R_CH2. The third resistor R_CL1 is connected to the bus wire 42 (CANL) at one end. At its other end, the third resistor R_CL1 is connected in series with the fourth resistor R_CL2. At the junction of resistors R_CH2, R_CL2, bus bias source 1222 is connected.

A resistor R_filt_CH of the input filter 1223 and a resistor R_filt_CH of the input filter 1223 for a CAN_H signal path are connected to the connection between the resistors R_CH1, R_CH2. A resistor R_filt_CL of the input filter 1223 and a resistor R_filt_CL of the input filter 1223 for a CAN_L signal path are connected to the connection between the resistors R_CL1, R_CL2. The input filter 1223 for the comparator 1224 has a first RC element for the CAN_H signal path and a second RC element for the CAN_L signal path.

In addition to the resistor R_filt_CH, the first RC element has a capacitor or a capacitance C_filt_CH. In addition to the resistor R_filt_CL, the second RC element has a capacitor or a capacitance C_filt_CL. Capacitors C_filt_CH, C_filt_CL are each connected at one end to ground or to connection 44 for CAN_GND. The input filter 1223 filters out high-frequency common-mode voltages and differential-mode voltages at the input of the comparator 1224 from the signal received from the voltage divider 1221 . The input filter 1223 passes on to the comparator 1224 the signals S_1, S_2, which have been correspondingly cleaned of the common-mode voltages and differential-mode voltages. The high-frequency common mode voltages are also referred to as common mode interference and the high-frequency differential mode voltages as differential mode interference.

The comparator 1224 compares the divided and filtered CANH voltage with the divided and filtered CANL voltage and outputs the result in the form of a digital signal, the comparator output signal CA. The comparator 1224 thus compares the signals S_1, S_2 and outputs the result in the form of the comparator output signal CA.

In particular, the receiving circuit 15 uses the comparator 1224 to evaluate the receiving thresholds TI, T2 in the arbitration phase 451 at the same time or simultaneously. In this case, the transceiver 12 is switched to the SLOW operating mode. After switching over the reception threshold for the evaluation with the comparator 1224, the reception thresholds TI, T3 in the data phase 452 are evaluated at the same time or simultaneously. In this case, the transceiver 12 is switched to one of the operating modes FAST_TX, FAST_RX.

The digital output signal CA of the comparator 1224 is further processed by the output filter 1225. From the output signal CA of the receiving comparator 1224, the output filter 1225 only allows pulses of a certain length to pass. The signal S_3 therefore does not contain any glitches. the Evaluation of short interference peaks in the following circuit 15 is thus prevented.

The receiver bit time adjustment circuit 15 of Fig. 5 has a first changing stage 151, a second changing stage 152, a logic circuit 153 and logic modules. Only the logic module 154 is shown in FIG. The receiver bit time adjustment circuit 15 can compensate for any receiver bit time distortion that may be present in the digital signal S_3, so that the limit values for the delta_trec parameter are observed. For this purpose, the receiver bit time adjustment circuit 15 adjusts the time length of a recessive bit of the signal S_3, so that the signal S8 satisfies the parameter delta_trec for the “receiver timing symmetry”.

The driver 1226 drives the signal S8 as the reception signal RxD to the communication controller 11 as described above.

FIGS. 7 to 10 illustrate the function of the receiver bit time adjustment circuit 15 using two examples. FIG. 7 and FIG. 9 each show a digital signal S3 in which a recessive bit has the value H1 (high=high) and a dominant bit has the value LW (low=low). The signal S8 resulting from circuit 15 is shown in FIG. 8 for a first example and in FIG. 10 for a second example.

In both examples, the receiver bit time adjustment circuit 15 adopts an edge of the signal S3 “immediately” into the signal S8. In contrast, the circuit 15 delays the respective other edge of the signal S3.

In the first example of FIG. 7 and FIG. 8 the falling edge of the signal S3 is taken over into the signal S8 and the rising edge was delayed. Thus, in the first example, the receiver bit time adjustment circuit 15 causes the bit time duration tl of the signal S3 of FIG. 7 to be shortened.

The bit time t2 of the signal S8 from FIG. 8 is shorter than the bit time t1 of the signal S3 from FIG. 7. Thus t2<t1 applies. In the second example of FIG. 9 and FIG. 10 the rising edge of the signal S3 is taken over into the signal S8 and the falling edge was delayed. Thus, in the second example, the receiver bit time adjustment circuit 15 causes the bit time length of the signal S3 of FIG. 9 to be lengthened. The bit time t4 of the signal S8 of FIG t4 > t3 holds.

For this purpose, the receiver bit time adjustment circuit 15 can be configured as shown in FIG.

According to FIG. 11, the receiver bit time adjustment circuit 15 is a two-stage circuit with an input connection 150 for the signal S_3 and an output connection 158 for the signal S_8. In addition to the change stages 151, 152, the logic circuit 153 and the logic module 154, the receiver bit time adjustment circuit 15 also has the logic modules 155, 156.

The signal S_3 is input into the first change stage 151 . Signal S_3 has a bit time t_bit for a recessive bit, which corresponds to state 402 (FIG. 3) on bus 40. The inverted signal S_3 is input to the second change stage 152 .

The first modification stage 151 of the circuit 15 has a first current mirror with a first and second transistor T_P_1, T_N_1. An adjustable resistor R_1 and an adjustable capacitor C_1 are connected to the output of the current mirror. The resistor R_1 is connected between the two transistors T_P_1, T_N_1 of the current mirror. The capacitor C_1 is connected in parallel to the resistor R_1 and the second transistor T_N_1. The first transistor T_P_1 is connected to the connection 43 for the voltage supply with CAN supply. The second transistor T_N_1 is connected to ground or to connection 44 for CAN_GND. The transistors T_P_1, T_N_1 can be field effect transistors. In particular, the first transistor T_P_1 is a PMOS transistor, in particular a normally blocking p-channel MOSFET (metal oxide semiconductor field effect transistor). In particular, the second transistor T_N_1 is an NMOS transistor, in particular a normally blocking n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Alternatively, the transistors T_P_1, T_N_1 are bipolar transistors.

The second modification stage 152 of circuit 15 has a first current mirror with first and second transistors T_P_2, T_N_2. An adjustable resistor R_2 and an adjustable capacitor C_2 are connected to the output of the current mirror. The resistor R_2 is connected between the two transistors T_P_2, T_N_2 of the current mirror. The capacitor C_2 is connected in parallel to the resistor R_2 and the second transistor T_N_2. The first transistor T_P_2 is connected to the connection 43 for the voltage supply with CAN supply. The second transistor T_N_2 is connected to ground or to connection 44 for CAN_GND. The transistors T_P_2, T_N_2 can be field effect transistors. In particular, the first transistor T_P_2 is a PMOS transistor, in particular a normally blocking p-channel MOSFET (metal oxide semiconductor field effect transistor). In particular, the second transistor T_N_2 is an NMOS transistor, in particular a normally blocking n-channel MOSFET (metal oxide semiconductor field effect transistor). Alternatively, the transistors T_P_1, T_N_1 are bipolar transistors.

First change stage 151 outputs a signal S_4 to second logic module 155 . The signal S_4 has slowly falling edges and clearly steeper rising edges. In the case of signal S_4, the rising edges therefore have a steeper edge than the falling edges. The second logic module 155 inverts the signal S_4 and outputs a digital signal S_6. All edges of signal S_6 have the same edge steepness. The signal S_6 is a square-wave signal. In this case, the previous bit time t_bit of the signal S_3 is shortened to the pulse duration or bit time t_bit1 of the signal S_6.

The second change stage 152 outputs a signal S_5 to the second logic component 155 . The signal S_5 has slowly falling edges and clearly steeper rising edges. In the case of signal S_5, the rising edges therefore have a steeper edge than the falling edges. The third logic module 155 inverts the signal S_5 and outputs a digital signal S_7. All edges of signal S_7 have the same edge steepness. The signal S_7 is a square-wave signal. In this case, the previous bit time t_bit of the signal S_3 is extended to the pulse duration or bit time t_bit2 of the signal S_6.

As a result, in the first change stage 151, an incoming pulse of the signal S_3 is delayed at the rising edge. The falling edge remains unchanged in time. As a result, the pulse duration or bit time t_bit of the signal S_3 in the resulting digital signal S_6 is reduced to the bit time t_bit1.

In contrast to this, in the second change stage 152 an incoming pulse of the signal S_3 is delayed at the falling edge. The rising edge remains unchanged in time. As a result, the pulse duration or bit time t_bit of the signal S_3 in the resulting digital signal S_7 increases to the bit time t_bit2.

The reduction of the pulse duration or bit time t_bit of the signal S_3 in the pulse duration or bit time t_bitl of the signal S_6 and the increase of the pulse duration or bit time t_bit of the signal S_3 in the pulse duration or bit time t_bit2 of the signal S_7 is due to the adjustability of the elements R_l, R_2, C_1 and C_2 of change levels 151, 152 are reached.

In general, the rising or falling edge of a bit in the signal S3 can be changed independently of one another. Each of the change levels 151, 152 can be set separately. For this, each of the elements R_1, R_2, C_1, C_2 is set as desired. With this, the delay time constants of the respective change stages 151, 152 are changed. As a result, the change in the pulse duration or bit time t_bit of the signal S_3 in FIG. 11 is also set differently. Thus, the amount of the difference t_bit - t_bit1 can be unequal to the amount of the difference t_bit - t_bit2. However, it is possible that the amount of the difference t_bit - t_bit1 is equal to the amount of the difference t_bit - t_bit2.

Signals S_6, S_7 are input to logic circuit 153. In addition, the logic circuit 153 is controlled by the selection signal S_sw. The selection signal S_sw is generated by the control device 125 of the transmission / Receiving device 12 output, as previously mentioned in FIG. The logic circuit 153 can be designed as a multiplexer.

The control device 125 sets the selection signal S_sw to Iw (low=low), for example, if the control device 125 determines by comparison with the parameter 162 stored in the memory that the value for delta_trec is too small. In particular, according to the standard, delta_trec should be a minimum of -20 ns and a maximum of 15 ns. As a result, logic circuit 153 outputs signal S_7 as signal S_8 at terminal 158 .

Otherwise, ie when control device 125 determines that the value for delta_trec is not too small, logic circuit 153 outputs signal S_6 as signal S_8 at connection 158 .

It is of course possible for the control device 125 to set the selection signal S_sw to other values or for the logic circuit 153 to interpret the values of the selection signal S_sw differently.

In the circuit 15 of FIG. 11, the values of the elements R_1, R_2,

C_l, C_2 fixed. Thus, the compensation of the bit time distortion of the receiving module 122 is fixed. The bit time t_bit1 generated by the first change stage 151 is thus fixed. In addition, the bit time t_bit2 generated by the second change stage 152 is thus permanently set. The fixed setting is made based on at least one simulation result and/or laboratory measurement result. This setting can be made as a function of the application-specific integrated circuit (ASIC) 16 in which the receiving module 122 is installed, in particular integrated. The setting determined, in particular at least one configuration value 161, is stored in a memory, in particular in the memory 160 of the ASIC 16, as described above with reference to FIG. The configuration value 16 can thus be chosen to be identical for all parts of the ASIC 16 and the device 12 .

Alternatively, according to a second setting for the change stages 151, 152, a comparison in the series test (trimming) for each of the Elements R_l, R_2, C_l, C_2 take place. First the parameter delta_trec is measured, then the circuit 15 is adjusted accordingly until the parameter delta_trec meets the required specification.

As an alternative to this, according to a third setting possibility for the change stages 151, 152, an additional circuit can be provided. In particular, the additional circuit is at least partially provided in control device 125 . The additional circuit, in particular the control device 125, can set the necessary compensation value or configuration value 161 during operation of the transceiver 12 and/or the application-specific integrated circuit (ASIC) 16. For this purpose, the additional circuit captures the value of delta_trec and determines the compensation variable, so that the configuration value 161 can be stored and/or used, as previously described.

As an alternative to the third setting option for the change stages 151, 152, the following fourth setting option can be used. According to the fourth setting option, the additional circuit, in particular the control device 125, detects the level of the differential voltage VDIFF of the dominant states (401) on the bus 40. The value 161 for the bit time compensation can then be set in such a way that the parameter 162, in particular the parameter delta_trec, is complied with.

According to a first modification of the circuit of Fig. 6 and Fig. 11, the receiver bit time adjustment circuit 15 has only the changing stage 151 or the changing stage 152. If there is only one changing stage, the logic circuit 153 and one of the logic modules 155, 156 can be omitted will.

In addition, the logic module 154 can optionally be omitted. This refinement of the circuit 15 is possible in particular if the compensation value is determined during operation, as described for the third or fourth setting option for the change stages 151, 152 described above.

According to a second modification of the circuit of Fig. 6 and Fig. 11, the receiver bit time adjustment circuit 15 has more than two changing stages 151, 152. Corresponding logic modules 154, 155, 156 are also available. In this case, more than one lengthening and/or shortening of the bit time t_bit can be made and a choice can be made between them. In this way, too, the logic circuit 153 can adjust the bit time distortion variably and thus as required.

12 shows a transceiver 120 according to a second exemplary embodiment. The transceiver 120 can be used instead of a transceiver 12 in the bus system 1 of FIG.

The transmission/reception device 120 has a transmission module 1210 and a reception module 122. The transmission module 1210 is constructed in many parts in the same way as the transmission module 121 according to the first exemplary embodiment. Therefore, only the differences from the first exemplary embodiment are described below.

In contrast to the first exemplary embodiment, the transmission module 1210 generates the signals CAN_H, CAN_L for the two communication phases on the bus 40, as described below with reference to FIGS. 13 to 16.

13 shows an example of a part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451 and generates the signals CAN_H, CAN_L for the bus 40 therefrom. In FIG. 13, the transmission signal TxD changes from a state LW (low=low) to a state HI (high=high) and back to the state LW (low=low).

In the ideal case, the reception signal RxD is identical to the transmission signal TxD. In such an ideal case, there is no transmission delay/delay, particularly over the bus 40, and no reception error, if any.

As shown in more detail in FIG. 14, the transmission module 121 for the transmission signal TxD from FIG. 13 can generate the signals CAN_H, CAN_L from FIG. In contrast to Fig. 3, there is an additional state 403 (sic) in the signals of FIG. State 403 (sic) can have different lengths, as shown with state 403_0 (sic) when transitioning from state 402 (rec) to state 401 (dom) and state 403_1 (sic) when transitioning from state 401 ( dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic). In order to generate signals according to FIG. 10, the transmission module 1210 is switched to a SIC operating mode (SIC mode).

Going through the short sic state 403_0 is not required according to the standard CiA610-3 for CAN XL and the state depends on the type of implementation. The duration of the "long" state 403_1 (sic) is specified for CAN-SIC as well as for the SIC operating mode in CAN-XL as t_sic < 530ns, beginning with the rising edge on the transmit signal TxD of Fig. 13.

In the “long” state 403_1 (sic), the transmission module 121 should match the impedance between the bus cores 41 (CANH) and 42 (CANL) as well as possible to the characteristic wave impedance Zw of the bus line used. Zw=1000hm or 1200hm applies here. This adjustment prevents reflections and thus allows operation at higher bit rates. For the sake of simplicity, the term 403 (sic) or sic state 403 is always used below.

FIG. 15 shows an example of another part of the digital transmit signal TxD, which transmit module 1210 receives from communication control device 11 (FIG. 1) in data phase 452, and uses it to generate signals CAN_H, CAN_L for bus 40. In FIG. 11, the transmission signal TxD changes several times from state HI (high=high) to state LW (low=low) and again to state HI (high=high) and so on.

As shown in more detail in FIG. 16, the transmission module 1210 generates the signals CAN_H, CAN_L for the bus cores 41,

42 such that the state L0 forms for a state LW (low=low). In addition, the state LI forms for a state H1 (high=high). It is possible that no dominant and recessive bus state is used for the two bus states LO, LI, at least temporarily, but instead a first bus state and a second bus state are used, both of which are driven. An example of such a bus system is a CAN XL bus system.

The receiving module 122 can also receive the signals according to FIG. 14 and FIG. 16 in the two different communication phases, namely the SIC operating mode or arbitration phase 451 and the data phase 452. For this purpose, the receiving module 122 switches the receiving thresholds T2, T3 for the respective operating modes, as previously described in relation to the previous exemplary embodiment.

In addition, control circuit 125 outputs an additional signal S_B to circuit 15 . The signal S_B is used to configure the circuit 15 depending on the operating mode of the transceiver 12 and thus on the communication phase 451, 452. The signal S_B is generated, for example, from the information which the transceiver 12 receives when its operating mode changes. The information can be derived, for example, from the transmission signal TxD, in particular the coding of the TxD data.

If the transceiver 12 is switched from the SIC mode to the fast RX mode or to the fast TX mode, the value of the signal S_B changes. This change indicates that the configuration of the bit time compensation circuit 15 is to be changed, as previously described. Changing the configuration of the bit time compensation of the circuit 15 causes the bit times t_bit1, t_bit2 to be approximately equal to the bit time t_bit of FIG.

Such a configuration is usable in the data phase 452 since the receive threshold T3 is chosen to be around 0V. This is an approximately "symmetrical" position of the receiving threshold T3 in relation to the levels of the differential voltage VDIFF of +1V and -IV in the data phase 452. As a result, the previously described effect of bit time distortion is almost non-existent. Alternatively, the circuit 15 can be bypassed when the transceiver 12 is switched to the fast RX mode or to the fast TX mode. As a result, the output signal S_3 of the output filter 1225 is used directly as an input signal for the driver 1226.

If the transceiver 12 is switched from the fast RX mode or the fast TX mode back to the SIC mode, the value of the signal S_B changes.

The control circuit 125 thus indicates that the configuration of the circuit 15 is to be changed according to the currently required operating mode (SIC, FAST_TX, FAST_RX) of the transceiver 120 . In addition, the control circuit 125 can set the configuration of the circuit 15 according to the currently required operating mode (SIC, FAST_TX, FAST_RX) of the transceiver 120 .

Optionally, the control circuit 125 also sets the reception thresholds T2, T3 according to the currently required operating mode (SIC, FAST_TX, FAST_RX) of the transceiver 120.

All previously described configurations of the transmitter module 121, 1210, the receiver module 122, the transmitter/receiver devices 12, 22, 120, the subscriber stations 10, 20, 30, the bus system 1 and the method carried out therein according to the first and second exemplary embodiment and their modifications can be used individually or in any combination. In addition, the following modifications in particular are conceivable.

The previously described bus system 1 according to the first and second exemplary embodiment is described using a bus system based on the CAN protocol. However, the bus system 1 according to the first and/or second exemplary embodiment can alternatively be another type of communication network in which the signals are transmitted as differential signals. It is advantageous, but not essential, that in the bus system 1, exclusive, collision-free access by a subscriber station 10, 20, 30 to the bus 40 is guaranteed at least for certain periods of time. The bus system 1 according to the first and/or second exemplary embodiment and modifications thereof is in particular a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 can be another communication network in which the signals are transmitted as differential signals and serially via the bus 40 .

Thus, the functionality of the exemplary embodiments described above can be used, for example, in transceiver devices 12, 22, 120 that are in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL -Bus system are operable. In addition, the functionality of the exemplary embodiments described above can be used with Flexray or LVDS (Low Voltage Differential Signaling). The number and arrangement of the subscriber stations 10, 20, 30 in the

Bus system 1 according to the first and second exemplary embodiment and modifications thereof is arbitrary. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first or second exemplary embodiment.

Claims

Expectations

1) receiving module (122) for receiving differential signals in a serial bus system (1), with a comparator (1224) for evaluating the differential signals (CAN_H) received from a bus (40) of the bus system (1),

CAN_L) with a receiving threshold (TI; T3), a voltage divider (1221), which is connected to the bus (40), for providing the bus (40) received differential signals (CAN_H, CAN_L) for the comparator (1224) , and a receiver bit time adjustment circuit (15) for compensating for bit time distortion in a signal (CA) output by the comparator (1224), the receiver bit time adjustment circuit (15) having at least one change stage (151) for shifting an edge in time in the signal (CA) output by the comparator (1224).

2) receiving module (122) according to claim 1, wherein the at least one change stage (151) has a resistor (R_l) and a capacitor (C_l), which are adjustable for adjusting the time shift of the edge.

3) receiving module (122) according to claim 2, wherein the at least one change stage (151) also has a current mirror with a first and a second transistor (T_P_1, T_N_1), wherein the resistor (R_l) between the first and second transistor (T_P_1, T_N_1) is connected, the capacitor (C_l) being connected in series with the first transistor (T_P_1), and wherein the capacitor (C_l) is connected in parallel to a series connection of the resistor (R_l) and the second transistor (T_N_1).

4) receiving module (122) according to claim 3, wherein the first transistor (T_P_1) is a PMOS transistor and the second transistor (T_N_1) is an NMOS transistor.

5) receiving module (122) according to any one of the preceding claims, wherein the receiver bit time adjustment circuit (15) also has a logic module (154) which is designed as an inverter, wherein the receiver bit time adjustment circuit (15) has a first change stage ( 151) and a second change stage (152), wherein the logic module (154) before the second change stage

(152) so that the first changing stage (151) is input with the inverted signal (CA) output from the comparator (1224).

6) receiving module (122) according to any one of the preceding claims, wherein the receiver bit time adjustment circuit (15) also includes a logic circuit

(153) for outputting a signal (S_6) processed by at least a first change stage (151) or a signal (S_7) processed by at least a second change stage (152) in response to a selection signal (S_sw).

7) receiving module (122) according to one of the preceding claims, wherein the amount of the change over time in the bit time (t_bit1) of a first change stage (151) can be set differently from the amount of the change over time in the bit time (t_bit2) of a second change stage (152).

8) Receiver module (122) according to one of the preceding claims, also having a control circuit (125) for controlling the receiver bit time adjustment circuit (15) in such a way that the circuit (15) sends a signal (S_8) with an extended bit time (t_bit2) or a signal (S_8) with shortened bit time (t_bitl) for a recessive bit of a bus (40) of the bus system (1) received differential signals (CAN_H, CAN_L) outputs.

9) receiving module (122) according to claim 8, wherein the control circuit (125) is designed to switch over the receiving threshold (TI; T3) for evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) depending on an operating mode of the Receiving module (122), in which the receiving module (122) for a first or second communication phase (451, 452) of a communication on the bus (40) is to be switched.

10) receiving module (122) according to any one of the preceding claims, wherein the configuration of the receiver bit time adjustment circuit (15) depending on an operating mode of the receiving module (122) can be set differently.

11) receiving module (122) according to any one of the preceding claims, wherein the amount of the temporal change in the bit time (t_bitl) of the at least one change stage (151) depending on an operating mode of the receiving module (122) can be set differently.

12) receiving module (122) according to any one of the preceding claims, wherein the receiver bit time adjustment circuit (15) depending on an operating mode of the receiving module (122) can be bypassed.

13) receiving module (122) according to any one of the preceding claims, wherein the voltage divider (1221) has a circuit of resistors to which an input filter (1223) for the comparator (1224) is connected.

14) receiving module (122) according to any one of the preceding claims, also with an input filter (1223) which is connected between the voltage divider (1221) and the comparator (1224), wherein the input filter (1223) has an RC element for a first signal (CAN_H) of the differential signals (CAN_H, CAN_L) and an RC element for a second signal (CAN_L) of the differential signals (CAN_H,

CAN_L), and wherein the voltage divider (1221) has a circuit of resistors to which the input filter (1223) is connected.

15) Transmitting/receiving device (12; 22; 120) for a subscriber station (10, 20, 30) for a serial bus system (1), with a transmitting module (121; 1210) for transmitting signals onto a bus (40) of the Bus system (1), and a receiving module (122) according to any one of the preceding claims.

16) Subscriber station (10; 20; 30) for a serial bus system (1), with a transmitting/receiving device (12; 22) according to claim 15, and a communication control device (11; 21) for controlling the communication in the bus system (1 ) and for generating a digital transmission signal (TxD) for the transmission module (121; 1210).

17) Subscriber station (10; 20; 30) according to claim 16, wherein the subscriber station (10; 20; 30) is designed for communication in a bus system (1) in which at least temporarily an exclusive, collision-free access of a subscriber station (10, 20, 30) on the bus (40) of the bus system (1) is guaranteed.

18) Method for receiving differential signals in a serial bus system (1), the method having the steps,

Receiving, with a receiving module (122), of differential signals (CAN_H, CAN_L) from a bus (40) of the bus system (1), the receiving module (122) being connected to the bus (40) with a voltage divider (1221), Providing the differential signals (CAN_H, CAN_L) with the voltage divider (1221) for a comparator (1224),

Evaluating the differential signals (CAN_H, CAN_L) with the comparator (1224) with a reception threshold (TI; T3), and compensating for a bit time distortion in a signal output by the comparator (1224) with a receiver bit time adjustment circuit (15). (CA), wherein the receiver bit time adjustment circuit (15) has at least one change stage (151) for shifting in time an edge in the signal (CA) output by the comparator (1224).