WO2023280473A1

WO2023280473A1 - Receiving module and method for receiving differential signals in a serial bus system

Info

Publication number: WO2023280473A1
Application number: PCT/EP2022/064762
Authority: WO
Inventors: Steffen Walker; Felix Lang
Original assignee: Robert Bosch Gmbh
Priority date: 2021-07-08
Filing date: 2022-05-31
Publication date: 2023-01-12
Also published as: DE102021207196A1

Abstract

The invention relates to a receiving module (122) and a method for transmitting differential signals in a serial bus system (1). The receiving module (122) has a first comparator (151; 152) for analyzing the differential signals (CAN_H, CAN_L) received by a bus (40) of the bus system (1) using a first receiving threshold (T1; T2), a second comparator (152; 151) for analyzing the differential signals (CAN_H, CAN_L) received by the bus (40) using a second receiving threshold (T2; T1) or a third receiving threshold (T3), wherein the first to third receiving thresholds (T1; T2, T3) are different, a voltage divider (1533) which is connected to the bus (40) for providing the differential signals (CAN_H, CAN_L) received by the bus (40) to the first comparator (151; 152) and the second comparator (152; 151), and an actuation circuit (158) for switching the second comparator (152; 151) between the second and third receiving threshold (T2, T3; T1, T3) on the basis of the receiving module (122) operating mode to which the receiving module (122) is switched for a first or second communication phase (451, 452) of a communication on the bus (40).

Description

description

title

Receiving module and method for receiving differential signals in a serial bus system

The present invention relates to a receiving module and a method for receiving differential signals in a serial bus system, which can be used in a transceiver.

State of the art

Serial bus systems are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control devices in a vehicle or a technical production facility, etc. There are various standards or data transmission protocols for data transmission. In particular, a CAN bus system, an LVDS bus system (LVDS=Low Voltage Differential Signaling), an MSC bus system (MSC=Micro Second Channel), and a 10BASE-T1S Ethernet are known.

In a CAN bus system, messages are transmitted using the CAN and/or CAN FD protocol, as described in the ISO-11898-1:2015 standard as a CAN protocol specification with CAN FD. With CAN FD, during transmission on the bus, there is a switch back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). With a CAN FD bus system, a data transmission rate of more than 1 MBit per second (1Mbps) is possible in the second communication phase. CAN FD will used by most manufacturers in the first step with 500kbit/s arbitration bit rate and 2Mbit/s data bit rate in the vehicle.

In order to enable even higher data rates in the second communication phase, there are successor bus systems for CAN FD, such as CANSIC and CAN XL. With CANSIC according to the CiA601-4 standard, a data rate of around 5 to 8 Mbit/s can be achieved in the second communication phase. With CAN XL, a data rate of > 10 Mbit/s is required in the second communication phase, whereby the standard (CiA610-3) for this is currently being defined by the CAN in Automation (CiA) organization. In addition to pure data transport via the CAN bus, CAN XL should also support other functions such as functional safety (safety), data security (security) and quality of service (QoS = Quality of Service). These are elementary properties that are required in an autonomously driving vehicle.

In all of the above-mentioned CAN-based bus systems, a bus signal CAN_H and ideally a bus signal CAN_L are driven onto a bus separately for a transmission signal TxD. In this case, at least in the first communication phase, a bus state is actively driven in the bus signals CAN_H, CAN_L. The other bus state is not driven and is set due to a terminating resistor for bus lines or bus cores of the bus.

In order to send and receive the bus signals, transceivers, which are also referred to as CAN transceivers or CAN FD transceivers, etc., are usually used in a CAN bus system for the individual communication participants. With CAN XL, the transmitting/receiving devices must be able to send the bus signals CAN_H, CAN_L to the bus in the second communication phase with a different physical layer than in the first communication phase. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).

This means that the data can be sent to the bus at a significantly higher data rate in the second communication phase than in the first communication phase. In addition, the bus levels of the bus signals can change with it CAN_H, CAN_L differ for the first communication phase from the bus levels of the second communication phase. In order to keep the error rate low, it is important that a subscriber station that is newly added to the communication on the bus recognizes the communication phase in which communication on the bus is currently taking place.

It must therefore be ensured for all operating phases of communication on the bus that a receiving subscriber station of the bus system can correctly identify and evaluate the levels of the bus signals CAN_H, CAN_L.

Disclosure of Invention

It is therefore the object of the present invention to provide a receiving module and a method for receiving differential signals in a serial bus system which solve the aforementioned problems. In particular, the receiving module and the method for receiving differential signals in a serial bus system should enable reliable and uncomplicated detection of bus signals, even if the physical layer is switched between two communication phases during communication on the bus.

The object is achieved by a receiving module for receiving differential signals in a serial bus system having the features of claim 1. The receiving module has a first comparator for evaluating the differential signals received from a bus of the bus system with a first receiving threshold, a second comparator for evaluating the differential signals received from the bus with a second receiving threshold or a third receiving threshold, the first to third receiving thresholds being different are, a voltage divider, which is connected to the bus, for providing the differential signals received from the bus for the first comparator and for the second comparator, and a control circuit for switching the second comparator between the second and third receiving threshold depending on an operating mode of the receiving module in which the Receiving module is to be switched for a first or second communication phase of a communication on the bus.

The receiving module described is designed in such a way that bus signals are recognized reliably and without any effort during operation of the bus system. This also applies in particular to such communication in which the physical layer is switched between two communication phases for communication on the bus. The receiving module can reliably differentiate between the respective bus statuses of the individual communication phases and thus the individual communication phases during communication on the bus.

In this case, the receiver module described enables the requirements for communication to be met in accordance with the requirements of CAN XL, which are specified in particular in the CiA610-3 standard.

In addition, the receiving module described is designed in such a way that the signal levels of the bus signals can be converted into a digital received signal with simultaneous evaluation of two receiving thresholds. The two reception thresholds used in the individual communication phases can be different for each communication phase.

In this way, the receiving module ensures that a subscriber station that is connected and tries to integrate into the communication on the bus does not interfere with the communication on the bus. The subscriber station can use the receiving module to reliably identify whether the bus is free of data traffic. Since the receiving module reliably assigns the current bus states, the newly added subscriber station will only send data to the bus itself when the bus is free. This means that switching on a subscriber station that, for example, is initially started or tries to reintegrate itself into the communication on the bus after an error in the bus communication does not lead to a disruption in communication on the bus. As a result, the receive module enables the functionality to use different receive thresholds for arbitration and data phase. This means that not only is communication in the bus system implemented with higher bit rates, but also that the transmittable bit rate is not reduced by communication errors.

Advantageous further configurations of the receiving module are described in the dependent claims.

The first and second comparator can be connected to the voltage divider in such a way that the first and second comparator simultaneously evaluate the differential signals received from the bus.

Possibly the second comparator has a resistor, an input differential pair with two transistors between which the resistor is connected, a first current source connected to one end of the resistor and a second current source connected to the other end of the resistor. In this case, the first and second current sources can be arranged for setting an operating point of the two transistors.

The first and second current sources and the resistor can be arranged to adjust the second or third receiving threshold depending on the actuation by the actuation circuit.

The voltage divider can have a circuit of resistors to which the first and second comparators are connected.

In one configuration, the number of resistors in a first resistive path of the voltage divider for a first signal of the differential signals is equal to the number of resistors in a second resistive path of the voltage divider for a second signal of the differential signals.

In one embodiment, the receiving module also has a first input filter, which is connected between the voltage divider and the first comparator, and a second input filter, which is connected between the voltage divider and the second comparator is connected, each input filter having an RC element for a first signal of the differential signals and an RC element for a second signal of the differential signals.

The second comparator can have at least a single-stage circuit with transistors.

It is conceivable that the receiving module also has a driver for driving a digital received signal to a communication control device of a subscriber station of the bus system) and a logic circuit for forwarding an output signal of the first comparator and an output signal of the second comparator to the driver when the control circuit sets the second receiving threshold has, and for forwarding only the output signal of the second comparator to the driver when the drive circuit has set the third receiving threshold.

According to one option, the first comparator is designed to evaluate the differential signals received from the bus with the first reception threshold or the second reception threshold.

The reception module described above can be part of a transmission/reception device for a subscriber station for a serial bus system. The transceiver can also have a transmission module for sending signals to a bus of the bus system.

The transmitting/receiving device described above can be part of a subscriber station for a serial bus system. The subscriber station can also have a communication control device for controlling the communication in the bus system and for generating a digital transmission signal for the transmission module.

Optionally, the subscriber station is designed for communication in a bus system in which exclusive, collision-free access of a subscriber station to the bus of the bus system is guaranteed at least temporarily. The aforementioned object is also achieved by a method for receiving differential signals in a serial bus system having the features of claim 15. The method is carried out with a receiving module, the method having the steps of receiving, with a receiving module, differential signals from a bus of the bus system, the receiving module being connected to the bus with a voltage divider, providing the differential signals with the voltage divider for a first comparator and for a second comparator, evaluating the differential signals with the first comparator with a first receiving threshold and with the second comparator with a second or third receiving threshold, the first to third receiving thresholds being different, and driving, with a driving circuit, the second comparator to switch the second comparator between the second and third receiving thresholds depending on an operating mode of the receiving module (122) into which the receiving module is to be switched for a first or second communication phase of a communication on the bus.

The method offers the same advantages as previously mentioned in relation to the receiving module.

Further possible implementations of the invention also include combinations of features or embodiments described above or below with regard to the exemplary embodiments that are not explicitly mentioned. The person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

drawings

The invention is described in more detail below with reference to the attached drawing and using exemplary embodiments. Show it:

1 shows a simplified block diagram of a bus system according to a first exemplary embodiment; 2 shows a diagram to illustrate the structure of a message that can be sent by a subscriber station of the bus system according to the first exemplary embodiment;

FIG. 3 shows an example of the ideal time profile of bus signals CAN_H, CAN_L in the bus system of FIG. 1;

FIG. 4 shows the time profile of a differential voltage VDIFF which forms on the bus of the bus system as a result of the bus signals from FIG. 4;

5 shows a simplified block diagram of a transceiver with a receiver module for a subscriber station of the bus system according to the first exemplary embodiment;

6 is a circuit diagram of the receiving module according to the first embodiment;

7 is a circuit diagram of a comparator of the receiving module according to the first embodiment;

8 shows a simplified block diagram of a transceiver with a receiver module for a subscriber station of the bus system according to a second exemplary embodiment;

9 shows an example of a time curve of a digital transmission signal which, according to the second exemplary embodiment, is to be converted into bus signals CAN_H, CAN_L for a bus of the bus system from FIG. 1 in the arbitration phase (SIC operating mode);

10 shows the time course of the bus signals CAN_H, CAN_L when changing from a recessive bus state to a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase (SIC operating mode) on the basis of the transmission signal from FIG. 9; 11 shows an example of a time profile of a digital transmission signal which, according to the second exemplary embodiment, is to be converted in the data phase into bus signals CAN_H, CAN_L for the bus of the bus system from FIG. 1; and

FIG. 12 shows the time course of the bus signals CAN_H, CAN_L, which are sent to the bus in the data phase on the basis of the transmission signal from FIG.

In the figures, elements that are the same or have the same function are provided with the same reference symbols unless otherwise stated.

Description of the exemplary embodiments

1 shows a bus system 1 which, for example, can be a CAN bus system, a CAN FD bus system, etc., at least in sections. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an airplane, etc., or in a hospital, etc.

In FIG. 1, the bus system 1 has a large number of subscriber stations 10, 20, 30, which are each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus cores 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46, 47 in the form of signals can be transmitted between the individual subscriber stations 10, 20, 30 via the bus 40. The subscriber stations 10, 20, 30 can be, for example, control devices or display devices of a motor vehicle.

As shown in Fig. 1, the subscriber stations 10, 30 each have a communication control device 11 and a transceiver 12. The transceiver 12 has a transmit module 121 and a receive module 122. Subscriber station 20 has a communication control device 21 and a transceiver 22. Transceiver 22 has a transmit module 221 and a receive module 222.

The transmitting/receiving devices 12 of the subscriber stations 10, 30 and the transmitting/receiving device 22 of the subscriber station 20 are each connected directly to the bus 40, even if this is not shown in FIG.

The communication control devices 11, 21 are each used to control communication between the respective subscriber station 10, 20, 30 via the bus 40 and at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

The communication control devices 11 create and read first messages 45, 47, which are modified CAN messages 45, 47, for example. In this case, the modified CAN messages 45, 47 are constructed, for example, on the basis of the CAN XL format. Transmitting/receiving device 12 is used to send and receive messages 45, 47 from bus 40. Transmitting module 121 receives a digital transmission signal TxD created by communication control device 11 for one of messages 45, 47 and converts this into signals on bus 40 around. The reception module 121 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them. The reception module 122 sends the reception signal RxD to the communication control device 11.

The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, ie like a CAN FD tolerant classic CAN controller or a CAN FD controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages 46. The transceiver 22 is used to send and receive the messages 46 from the bus 40. The transmission module 221 receives a digital transmission signal TxD and created by the communication control device 21 converts this into signals for a message 46 on the bus 40. The receiving module 221 receives signals sent on the bus 40 corresponding to the messages 45 to 47 and generates from this a digital reception signal RxD. Otherwise, the transceiver 22 can be designed like a conventional CAN transceiver.

For sending the messages 45, 47 with CAN SIC or CAN XL, proven properties are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular frame structure with identifier and arbitration according to the known CSMA/CR method. The consequence of the CSMA/CR method is that there must be so-called recessive states on the bus 40 which can be overwritten by other subscriber stations 10, 20, 30 with dominant levels or dominant states on the bus 40.

With the two subscriber stations 10, 30, a formation and then transmission of messages 45 with different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, and the receipt of such messages 45 can be implemented, as described in more detail below .

2 shows a frame 450 for the message 45, which is in particular a CAN XL frame, as is provided by the communication control device 11 for the transceiver 12 for transmission onto the bus 40. Here, in the present exemplary embodiment, the communication control device 11 creates the frame 450 as compatible with CAN FD. Alternatively, the frame 450 is compatible with CAN SIC.

According to FIG. 2, the frame 450 for the CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a data field 455, a checksum field 456 and a frame termination field 457.

In the arbitration phase 451, an identifier (ID) with, for example, bits ID28 to ID18 in the arbitration field 453 is used to negotiate bit by bit between the subscriber stations 10, 20, 30 as to which subscriber station 10, 20, 30 is sending the message 45, 46 with the highest priority want and therefore gets exclusive access to the bus 40 of the bus system 1 for the next time for sending in the subsequent data phase 452 . In the arbitration phase 451, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).

An important point during phase 451 is that the known CSMA/CR method is used, which allows subscriber stations 10, 20, 30 to access the bus 40 simultaneously without the higher-priority message 45, 46 being destroyed. As a result, further bus subscriber stations 10, 20, 30 can be added to the bus system 1 relatively easily, which is very advantageous.

The consequence of the CSMA/CR method is that there must be so-called recessive states on the bus 40 which are detected by other subscriber stations 10, 20,

30 can be overwritten with dominant levels or dominant states on the bus 40. In the recessive state, the individual subscriber stations 10, 20, 30 have high-impedance conditions, which, in combination with the parasites of the bus wiring, results in longer time constants. This leads to a limitation of the maximum bit rate of today's CAN FD physical layer to around 2 megabits per second in real vehicle use.

In the data phase 452, in addition to part of the control field 454, the user data of the CAN-XL frame 450 or the message 45 from the data field 455 and the checksum field 456 are sent. A checksum over the data of the data phase 452 including the stuff bits can be contained in the checksum field 456, which the sender of the message 45 inserts as an inverse bit after a predetermined number of identical bits, in particular 10 identical bits. At the end of the data phase 452, the arbitration phase 451 is switched back to.

At least one acknowledge bit may be included in an end field in the frame completion phase 457 . There may also be a sequence of 11 equal bits indicating the end of the CAN XL frame 450. With the at least one acknowledge bit can be used to indicate whether or not a receiver has discovered an error in the received CAN XL frame 450 or message 45.

A sender of the message 45 does not start sending bits of the data phase 452 to the bus 40 until the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending .

Thus, in the arbitration phase 451, the subscriber stations 10, 30 partially use a format known from CAN/CAN-FD in accordance with ISO11898-1:2015 as the first communication phase, in particular up to the FDF bit (inclusive). However, compared to CAN or CAN FD in the data phase 452 as the second communication phase, the net data transmission rate can be increased, in particular to more than 10 megabits per second. In addition, it is possible to increase the size of the user data per frame, in particular to around 2 kbyte or any other value.

3 shows on the left side that the subscriber stations 10, 20, 30 send signals CAN_H, CAN_L to the bus 40 in the arbitration phase 451, which alternately have at least one dominant state 401 or at least one recessive state 402. After the arbitration in the arbitration phase 451, one of the subscriber stations 10, 20, 30 is the winner. Assume that subscriber station 10 has won the arbitration. Then the transceiver 12 of the subscriber station 10 switches its physical layer at the end of the arbitration phase 451 from a first operating mode (SLOW) to a second operating mode (FAST_TX), since the subscriber station 10 is the sender of the message 45 in the data phase 452. The transmission module 121 then generates in the data phase 452 or in the second operating mode (FAST_TX) depending on a transmission signal TxD successively and thus serially the states L0 or LI for the signals CAN_H, CAN_L on the bus 40. The frequency of the signals CAN_H, CAN_L may be increased in the data phase 452 as shown on the right in FIG. Thus, the net data transfer rate in the data phase 452 is increased compared to the arbitration phase 451. In contrast, the transceiver switches 12 of the subscriber station 30 changes its physical layer at the end of the arbitration phase 451 from the first operating mode (SLOW) to a third operating mode (FAST_RX), since the subscriber station 30 in the data phase 452 is only a receiver, i.e. not a transmitter, of the frame 450. After the end of the arbitration phase 451, all transmitting/receiving devices 12 of the subscriber stations 10, 30 switch their operating mode to the first operating mode (SLOW). Thus, all transceivers 12 also switch their physical layer.

4 forms in the arbitration phase 451 in the ideal case on the bus 40, a difference signal VDIFF = CAN_H - CAN_L with values of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402. This is on the left side in 4 shown. In contrast, a differential signal VDIFF=CAN_H−CAN_L with states L0, LI is formed on bus 40 in data phase 452, as shown on the right-hand side in FIG. State L0 has a value VDIFF = IV. State LI has a value VDIFF = -IV.

The receiving module 122 can distinguish the states 401, 402 with two of the receiving thresholds TI, T2, T3, which are in the ranges TH_T1, TH_T2, TH_T3. For this purpose, the receiving module 122 samples the signals from FIG. 3 or FIG. 4 at times t_A. To evaluate the scanning result, receiving module 122 uses receiving threshold TI of 0.7 V, for example, and receiving threshold T2, for example -0.35 V, in arbitration phase 451. In contrast, receiving module 122 in data phase 452 only uses signals that match receiving threshold T3 were evaluated. When switching between the first to third operating modes (SLOW, FAST_TX, FAST_RX), which were previously described with reference to FIG. 3, the receiving module 122 switches the receiving thresholds T2, T3, as described below.

The receiving threshold T2 is used to identify whether the bus 40 is free when the subscriber station 12 is newly added to the communication on the bus 40 and tries to integrate into the communication on the bus 40. In the standard for CAN, the receiving threshold T2 is called OOB for short (= Out-of- Boundary = outside the limit value). The conditions for a traffic-free CAN-XL bus are that no dominant state 401 occurs, which typically has the differential voltage VDIFF = 2 V. Thus, the reception threshold TI of 0.7 V, for example, must not be exceeded. In addition, no levels according to the LI state may occur, which typically has the differential voltage VDIFF = 2V -IV. This means that the reception threshold T2, for example -0.35 V, must not be undershot.

Each subscriber station 10, 30 switches the operating mode of the transceiver 12 to the operating mode of the arbitration phase 451 when the subscriber station 12 is newly added to the communication on the bus 40.

On the one hand, it may be necessary to connect the subscriber station 10 if the subscriber station 10 is initially started and is to be integrated into the communication on the bus 40 . On the other hand, it may be necessary for the subscriber station 10 to be connected if the subscriber station 10 attempts to reintegrate itself into the communication on the bus 40 after an error in the bus communication. Only when it is recognized that the bus is free is the subscriber station 10 itself allowed to send data, in particular messages 45, 47, to the bus 40 in the cases mentioned.

Table 1 below shows the values that can be set for the individual reception thresholds on bus 40. In this case, VDIFF_min specifies the lower limit for the individual areas TH_T1, TH_T2, TH_T3, which minimum may be set in V for the corresponding receive threshold TI, T2, T3. VDIFF_typ indicates the value that is typically or usually set in V for the corresponding reception threshold TI, T2, T3. VDIFF_max specifies the upper limit for the individual areas TH_T1, TH_T2, TH_T3, which maximum may be set in V for the corresponding receive threshold TI, T2, T3.

Table 1: Tolerance ranges of the reception thresholds TI, T2, T3 5 shows the basic structure of the transmitter/receiver device 12 of the subscriber station 10. The transmitter module 121 is only shown in a very simplified form. The transmission module 121 is connected directly to the bus 40 in order to be able to transmit the transmission signal TxD from the communication control device 11 to the bus 40 in order to generate signals on the bus 40 in accordance with FIG.

The reception module 122 has a driver 1221 for the digital reception signal RxD, a logic circuit 1222 and a reception circuit 15. The reception circuit 15 has a first reception comparator 151, a second reception comparator 152, a reception stage 153 and a bus biasing source (bus biasing) 154, connections 155 , 156 and a driving circuit 158. The receiving comparators 151, 152 are low-voltage comparators, respectively.

The receiving circuit 15 is connected between the bus 40 and the logic circuit 1222 . The driver 1221 is connected to the output of the logic circuit 1222. The driver 1221 drives or sends the digital reception signal RxD to the communication control device 11.

In the receiving circuit 15, the receiving stage 153 is connected to the bus 40. During operation of the bus system 1, the receiving stage 153 generates signals S_1, S_2 from the signals CAN_H, CAN_L to the first receiving comparator 151. The first reception comparator 151 generates a comparator output signal CA1 from the signals S_1, S_2. The CA1 signal is output at terminal 155 to logic circuit 1222 .

In addition, the receiving stage 153 also generates signals S_3, S_4 from the signals CAN_H, CAN_L during operation of the bus system 1 and forwards these to the second receiving comparator 152. The second reception comparator 151 generates a comparator output signal CA2 from the signals S_3, S_4.

Signal CA2 is output to logic circuit 1222 at terminal 156 . The comparator output signal CA2 depends on the operating mode in which the transceiver 12, more precisely the second comparator 152, is switched. For this purpose, the reception circuit 15 has a control circuit 158 which controls the setting of the reception threshold T2 (FIG. 4) or the reception threshold T3 (FIG. 4) in the reception comparator 152. This is described in more detail with reference to FIGS. 6 and 7 .

The logic circuit 1222 is designed to output the signal CA1 and the signal CA2 to the driver 1221 or only to output the signal CA2 to the driver 1221 depending on the operating mode of the transceiver 12 . For this purpose, the logic circuit 1222 can have at least one AND gate. Alternatively, the logic circuit 1222 has other logic components in order to fulfill the function of the receiving module 122 described below.

As shown in FIG. 6, the receiving stage 153 also has a first input filter 1531 for the first comparator 151, a second input filter 1532 for the second comparator 152, and a voltage divider 1533. The voltage divider 1533 is a resistive voltage divider or resistance voltage divider.

Voltage divider 1533 is supplied with electrical voltage from bus biasing source 154 . Bus bias source 154 typically provides a voltage CAN_SUPPLY/2 to receive stage 153, more specifically voltage divider 1533. Typically CAN_SUPPLY=5V Specifically, bus bias source 154 may be set to 2.5V for recessive state 402 (FIG. 3).

The voltage divider 1533 has a first and a second resistor R_CH1, R_CH2 for the bus signal CAN_H. In addition, the voltage divider 1533 has a third and fourth resistor R_CL1, R_CL2 for the bus signal CAN_L. The voltage divider 1533 divides the bus voltages generated by the signals CAN_H, CAN_L down to values which can be processed by the comparators 151, 152. The circuit of Resistors in the resistor network of the voltage divider 1533 is constructed symmetrically.

The first resistor R_CH1 is connected at one end to the bus core 41 (CANH). At its other end, the first resistor R_CH1 is connected in series with the second resistor R_CH2. The third resistor R_CL1 is connected to the bus wire 42 (CANL) at one end. At its other end, the third resistor R_CL1 is connected in series with the fourth resistor R_CL2. At the junction of resistors R_CH2, R_CL2, bus bias source 154 is connected.

A resistor R_filt_CH_A of the input filter 1531 and a resistor R_filt_CH_B of the input filter 1532 for a CAN_H signal path are connected to the connection between the resistors R_CH1, R_CH2. A resistor R_filt_CL_A of the input filter 1531 and a resistor R_filt_CL_B of the input filter 1532 for a CAN_L signal path are connected to the connection between the resistors R_CL1, R_CL2.

The first input filter 1531 for the first comparator 151 has a first RC element for the CAN_H signal path and a second RC element for the CAN_L signal path. In addition to the resistance R_filt_CH_A, the first RC element has a capacitance C_filt_CH_A. In addition to the resistance R_filt_CL_A, the second RC element has a capacitance C_filt_CL_A. The capacitances C_filt_CH_A, C_filt_CL_A are each connected at one end to ground or to connection 44 for CAN_GND.

The second input filter 1532 for the second comparator 152 has a first RC element for the CAN_H signal path and a second RC element for the CAN_L signal path. In addition to the resistance R_filt_CH_B, the first RC element has a capacitance C_filt_CH_B. In addition to the resistance R_filt_CL_B, the second RC element has a capacitance C_filt_CL_B. Capacitors C_filt_CH_B, C_filt_CL_B are each connected at one end to ground or to connection 44 for CAN GND. Thus both comparators 151, 152 use the same voltage divider 1533. The joint use of the voltage divider 1533 enables the simultaneous evaluation of two reception thresholds. The drive circuit 158 enables the reception thresholds T2, T3 in the second comparator 152 to be switched over with the aid of a signal sw_th. This is shown in Table 2 as the assignment of the output signals CA1, CA2 of the comparators 151, 152 to the reception thresholds TI, T2, T3.

Table 2: First example for an assignment of the output signals CA1, CA2 of the comparators 151, 152 and the reception thresholds TI, T2, T3

The receiving circuit 15 thus evaluates the receiving thresholds TI, T2 in the arbitration phase 451 at the same time or simultaneously, for which the transceiver 12 is switched to the SLOW operating mode. After switching the reception threshold in the second comparator 152, as described below, the reception thresholds TI, T3 are evaluated simultaneously in the data phase 452, for which the transceiver 12 is switched to one of the operating modes FAST_TX, FAST_RX.

According to Fig. 7, the second comparator 152 has a mode setting unit 1520, a two-stage circuit having a first input differential pair 1521, a second input differential pair 1522 and first to third current mirrors 1525, 1526, 1527, and an output buffer 1528. The output buffer 1528 drives the Output signal CA2. The operating mode setting unit 1520 is controlled by the control circuit 158 with the switching signal sw_th. The switching signal sw_th switches the comparator 152 according to the operating mode with which the receiving stage 153 has to receive, more precisely to interpret, the signals CAN_H, CAN_L, as described above.

The two-stage circuit of Fig. 7 has the following elements, namely first through fifth current sources II, 12, 13, 14, 15, first and second transistors TRI, TR2 forming the first input differential pair 1521, a resistor Rdiff, a first and second collector resistor RC1, RC2, a third and fourth transistor TR5, TR6 as an emitter follower, a fifth and sixth transistor TR7, TR8 as a level switch (level shifter), a seventh and eighth transistor TR9, TRIO, which form the second input differential pair 1522, the first current mirror 1525 comprising transistors TR11, TR12, the second current mirror 1526 comprising transistors TR13, TR14, the third current mirror 1527 comprising transistors TR15, TR16. The transistors TRI, TR2, TR5, TR5, TR7, TR8 are npn bipolar transistors in the example of FIG. The transistors TR9, TRIO are pnp bipolar transistors in the example of FIG. The transistors TR11, TR12, TR13, TR14, TR15, TR16 are field effect transistors in the example of FIG. In the example of FIG. 7, the transistors TR11, TR12, TR13, TR14 of the first and second current mirrors 1525, 1526 are NMOS transistors, in particular normally blocking n-channel MOSFETS (metal-oxide-semiconductor field-effect transistors). In the example of FIG. 7, the transistors TR15, TR16 of the third current mirror 1527 are PMOS transistors, in particular normally blocking p-channel MOSFETS (metal oxide semiconductor field effect transistors).

The two-stage circuit of FIG. 7 is supplied with the voltage CAN_SUPPLY via the connection 43 . Each of the collector resistors RC1, RC2 is connected to the terminal 43 at one of its ends. In addition, the collectors of the transistors TR5, TR6 are connected to the terminal 43. In addition, the fifth current source 15 and the third current mirror 1527 are connected to the terminal 43 with the transistors TR15, TR16. The fifth current source 15 feeds the second input differential pair 1522 from the seventh and eighth transistors TR9, TRIO. The first current source II is connected to ground and at its other end to the emitter of the first transistor TRI and to one end of the resistor Rdiff. The second current source 12 is connected to ground and at its other end to the emitter of the second transistor TR2 and to the other end of the resistor Rdiff. The current sources II, 12 set the operating point for the transistors TRI, TR2. The reception threshold T2 or the reception threshold T3 is adjusted according to the value of the switching signal sw_th via the current sources II, I2 and the resistor Rdiff, as indicated in table 2 above.

The base of the third transistor TR5 is connected to the junction between the first transistor TRI and the first collector resistor RC1. The base of the fourth transistor TR6 is connected to the junction between the second transistor TR2 and the second collector resistor RC2. The collector and base of the fifth transistor TR7 are connected to the emitter of the third transistor TR5. The collector and base of the sixth transistor TR8 are connected to the emitter of the fourth transistor TR6. The emitter of the third transistor TR5 is connected to the current source I3. The fourth transistor TR6 has its emitter connected to the current source 14 .

The base of the seventh transistor TR9 is connected to the junction between the fifth transistor TR7 and the third current source I3. The base of the eighth transistor TRIO is connected to the junction between the sixth transistor TR8 and the fourth current source 14 . The emitters of the transistors TR9, TRIO are connected to the current source 15. The transistor TU of the first current mirror is connected to the collector of the seventh transistor TR9. The transistor T13 of the second current mirror is connected to the collector of the eighth transistor TRIO.

The transistor T12 of the first current mirror 1525 is connected between the transistor T15 of the third current mirror 1527 and ground. The transistor T14 of the second current mirror 1526 is connected between the transistor T16 of the third current mirror 1527 and ground. The output buffer 1522 is on its input connected to the transistor TR14 of the second current mirror and the transistor TR16 of the third current mirror.

In the example of FIGS. 5 to 7, the drive circuit 158 is in the form of a transistor or has at least one transistor. The transistor is in particular an NMOS transistor. The abbreviation "NMOS" denotes an n-channel MOSFET, where the abbreviation "MOSFET" stands for metal-oxide field effect transistor. If the control circuit 158 controls the operating mode setting unit 1520 with a signal sw_th with the value “high”, the operating mode setting unit 1520 sets the receiving threshold T2 from FIG. 4 as previously described.

In other words, according to FIGS. 5 to 7, the first comparator 151 supplies a signal CA1 in all operating modes of the transceiver 12, in which the signals S_1, S_2 were evaluated using the reception threshold TI. In contrast, for the second comparator 152, the signal CA1 was evaluated in the two communication phases of a message 45 with different reception thresholds. If the sw_th signal with the value “high” is present at the operating mode setting unit 1520, the second comparator 152 supplies a signal CA2 in which the signals S_3, S_4 were evaluated using the receiving threshold T2. In contrast, the first comparator 151 supplies a signal CA1, independently of the signal sw_th, in which the signals S_1, S_2 were evaluated using the reception threshold TI. In other words, the first comparator 151 provides the detection of threshold TI and the second comparator 152 provides the detection of threshold T2.

If, on the other hand, the sw_th signal at the operating mode setting unit 1520 has the value “low”, the second comparator 152 supplies a signal CA2 in which the signals S_3, S_4 were evaluated using the reception threshold T3. In contrast, the first comparator 151 again supplies a signal CA1, independently of the signal sw_th, in which the signals S_1, S_2 were evaluated using the reception threshold TI. In other words, the first comparator 151 provides the detection of threshold TI and the second comparator 152 provides the detection of threshold T3. The configuration of the receiving stage 15 described allows two different receiving thresholds of the receiving thresholds TI, T2, T3 to be tested independently of one another and thus also at the same time or simultaneously. In addition to this, the control circuit 158 can be used to switch between two reception thresholds of the reception thresholds TI, T2, T3. As a result, either the reception thresholds TI, T2 according to FIG. 4 can be checked independently of one another and simultaneously, or the reception thresholds TI, T3 according to FIG. 4 can be checked independently of one another and simultaneously. So there are two of the three reception thresholds TI,

T2, T3 can be switched to the third reception threshold as required.

The operating mode setting unit 1520 thus sets the reception thresholds T2, T3 according to the currently required operating mode (SLOW, FAST_TX, FAST_RX) of the transceiver 12.

According to a modification of the previous embodiment, a signal sw_th at the mode setting unit 1520 with the value "low" sets the reception threshold T2 in the comparator 152 and a signal sw_th with the value "high" sets the reception threshold T3 in the comparator 152 .

According to a second modification of the previous embodiment, the first comparator 151 always sets the reception threshold T2, and the second comparator 152 can switch between the thresholds TI and T3.

According to a third modification of the foregoing embodiment, the first comparator 151 may be the switchable comparator as described for the second comparator 152 above. The second comparator 152 cannot be switched over. In this modification, the assignment of the output signals CA1, CA2 of the comparators 151, 152 to the reception thresholds TI, T2, T3 is shown in Table 3.

Table 3: Second example for an assignment of the output signals CA1, CA2 of the comparators 151, 152 and the reception thresholds TI, T2, T3

8 shows a transceiver 120 according to a second exemplary embodiment. The transceiver 120 can be used instead of a transceiver 12 in the bus system 1 of FIG.

The transmission/reception device 120 has a transmission module 1210 and a reception module 122. The transmission module 1210 is constructed in many parts in the same way as the transmission module 121 according to the first exemplary embodiment. Therefore, only the differences from the first exemplary embodiment are described below

In contrast to the first exemplary embodiment, the transmission module 1210 generates the signals CAN_H, CAN_L for the two communication phases on the bus 40, as described below with reference to FIGS. 9 to 12.

9 shows an example of a part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451 and generates the signals CAN_H, CAN_L for the bus 40 therefrom. In FIG. 9, the transmission signal TxD changes from a state LW (low=low) to a state HI (high=high) and back to the state LW (low=low). In the ideal case, the reception signal RxD is identical to the transmission signal TxD. In such an ideal case, there is no transmission delay/delay, particularly over the bus 40, and no reception error, if any.

As shown in more detail in FIG. 10, the transmission module 121 for the transmission signal TxD from FIG. 9 can generate the signals CAN_H, CAN_L from FIG. 10 for the bus cores 41, 42 in the CAN SIC or CAN XL operating mode. In contrast to FIG. 3, the signals from FIG. 10 also have a state 403 (sic). State 403 (sic) can have different lengths, as shown with state 403_0 (sic) when transitioning from state 402 (rec) to state 401 (dom) and state 403_1 (sic) when transitioning from state 401 ( dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic). In order to generate signals according to FIG. 10, the transmission module 1210 is switched to a SIC operating mode (SIC mode).

Going through the short sic state 403_0 is not required according to the standard CiA610-3 for CAN XL and the state depends on the type of implementation. The duration of the "long" state 403_1 (sic) is specified for CAN-SIC as well as for the SIC operating mode in CAN-XL as t_sic < 530ns, beginning with the rising edge on the transmit signal TxD of Fig.

9.

In the “long” state 403_1 (sic), the transmission module 121 should match the impedance between the bus cores 41 (CANH) and 42 (CANL) as well as possible to the characteristic wave impedance Zw of the bus line used. Zw=1000hm or 1200hm applies here. This adjustment prevents reflections and thus allows operation at higher bit rates. For the sake of simplicity, the term 403 (sic) or sic state 403 is always used below.

FIG. 11 shows an example of another part of the digital transmission signal TxD, which the transmission module 1210 receives in the data phase 452 from the communication control device 11 (FIG. 1), and generates the signals CAN_H, CAN_L for the bus 40 therefrom. In Fig. 11 the transmission signal changes TxD several times from HI (High = High) state to an LW (Low = Low) state and back to an HI (High = High) state and so on.

As shown in more detail in FIG. 12, the transmission module 1210 generates the signals CAN_H, CAN_L for the bus cores 41, 42 for the transmission signal TxD from FIG. 11 in such a way that the state L0 is formed for a state LW (low=low). In addition, the state LI forms for a state H1 (high=high).

It is possible that no dominant and recessive bus state is used for the two bus states LO, LI, at least temporarily, but instead a first bus state and a second bus state are used, both of which are driven. An example of such a bus system is a CAN XL bus system.

The receiving module 122 can also receive the signals according to FIG. 10 and FIG. 12 in the two different communication phases, namely the SIC operating mode or arbitration phase 451 and the data phase 452. For this purpose, the receiving module 122 switches the receiving thresholds T2, T3 for the respective operating modes, as previously described in relation to the previous exemplary embodiment.

The operating mode setting unit 1520 thus sets the reception thresholds T2, T3 according to the currently required operating mode (SIC, FAST_TX, FAST_RX) of the transceiver 120.

According to a third embodiment, the first comparator 151 is also a comparator that can set two different reception thresholds, as previously described for the second comparator 152 in relation to the first embodiment. In particular, the first comparator 151 can be switched over between the first and second receiving thresholds TI, T2.

In this case, the logic circuit 1222 is designed in such a way that both comparator signals CA1, CA2 are always forwarded to the driver 1221. That Reception module 122 always evaluates the signals CAN_H, CAN_L with two reception thresholds at the same time or simultaneously, namely either with reception thresholds TI, T2 or with reception thresholds T2, T3. In addition, the two reception thresholds are evaluated independently of one another.

This circuit can be advantageous if the reception threshold T2 is also to be used in the data phase 452, as shown in FIG.

According to a fourth embodiment, the two-stage circuit of Fig.

7 built only with bipolar transistors.

According to a fifth embodiment, the two-stage circuit of FIG. 7 is constructed only with MOSFET transistors.

According to a sixth exemplary embodiment, the two-stage circuit of FIG. 7 described above is configured in one stage.

According to a seventh exemplary embodiment, the two-stage circuit of FIG. 7 described above has a multi-stage design.

According to an eighth exemplary embodiment, the previously described two-stage circuit of FIG. 7, depending on the levels, is inverted or flipped with a PMOS input pair. In particular, the transistors TRI, TR2, TR9, TRIO can be PMOS transistors or p-channel bipolar transistors or pnp bipolar transistors.

In this case, the control circuit 158 can have at least one transistor, in particular a MOS transistor. The control circuit 158 controls the operating mode setting unit 1520 with the sw_th signal with the appropriate values in order to set either the reception threshold T2 or the reception threshold T3 of FIG. 4 , as previously described.

All previously described configurations of the transmitter module 121, 1210, the receiver module 122, the transmitter/receiver devices 12, 22, 120, the subscriber stations 10, 20, 30, the bus system 1 and the one implemented therein Methods according to the first and second exemplary embodiment and their modifications can be used individually or in all possible combinations. In addition, the following modifications in particular are conceivable.

The previously described bus system 1 according to the first and second exemplary embodiment is described using a bus system based on the CAN protocol. However, the bus system 1 according to the first and/or second exemplary embodiment can alternatively be another type of communication network in which the signals are transmitted as differential signals. It is advantageous, but not an essential requirement, that in the bus system 1 exclusive, collision-free access by a subscriber station 10, 20, 30 to the bus 40 is guaranteed at least for certain periods of time.

The bus system 1 according to the first and/or second exemplary embodiment and modifications thereof is in particular a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 can be another communication network in which the signals are transmitted as differential signals and serially via the bus 40 .

Thus, the functionality of the exemplary embodiments described above can be used, for example, in transceiver devices 12, 22, 120 that are in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL -Bus system are operable.

The number and arrangement of the subscriber stations 10, 20, 30 in the bus system 1 according to the first and second exemplary embodiment and their modifications is arbitrary. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first or second exemplary embodiment.

Claims

Expectations

1) receiving module (122) for receiving differential signals in a serial bus system (1), with a first comparator (151; 152) for evaluating the differential signals (CAN_H, CAN_L) received from a bus (40) of the bus system (1) with a first reception threshold (TI; T2), a second comparator (152; 151) for evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) with a second reception threshold (T2; TI) or a third reception threshold (T3 ), wherein the first to third reception thresholds (TI; T2, T3) are different, a voltage divider (1533) which is connected to the bus (40) for providing the differential signals (CAN_H, CAN_L ) for the first comparator (151; 152) and for the second comparator (152; 151), and a drive circuit (158) for switching the second comparator (152; 151) between the second and third reception thresholds (T2, T3; TI T3 ) depending on a company Type of receiving module (122) into which the receiving module (122) is to be switched for a first or second communication phase (451, 452) of a communication on the bus (40).

2) receiving module (122) according to claim 1, wherein the first and second comparator (151, 152) are connected to the voltage divider (1533) such that the first and second comparator (151, 152) from the bus (40) received differential Evaluate signals (CAN_H, CAN_L) simultaneously.

3) receiving module (122) according to claim 1 or 2, wherein the second comparator (152; 151). a resistor (Rdiff), an input differential pair (1521) having two transistors (TRI, TR2) between which the resistor (Rdiff) is connected, a first current source (II) connected to one end of the resistor (Rdiff), and a second current source (12) connected to the other end of the resistor (Rdiff).

4) receiving module (122) according to claim 3, wherein the first and second current source (II, 12) for setting an operating point of the two transistors (TRI, TR2) are arranged.

5) receiving module (122) according to claim 3 or 4, wherein the first and second current source (II, 12) and the resistor (Rdiff) for setting the second or third receiving threshold (T2, T3; TI, T3) depending on the control arranged by the drive circuit (158).

6) receiving module (122) according to any one of the preceding claims, wherein the voltage divider (1533) comprise a circuit of resistors to which the first and second comparator (151, 152) is connected.

7) receiving module (122) according to claim 6, wherein the number of resistors (R_CH1, R_CH2) in a first resistance path of the voltage divider (1533) for a first signal (CAN_H) of the differential signals (CAN_H, CAN_L) equal to the number of resistors ( R_CL1, R_CL2) in a second resistive path of the voltage divider (1533) for a second signal (CAN_L) of the differential signals (CAN_H, CAN_L).

8) receiving module (122) according to any one of the preceding claims, further comprising a first input filter (1531) connected between the voltage divider (1533) and the first comparator (151; 152), and a second input filter (1532) connected between the voltage divider (1533) and the second comparator (152; 151), each input filter (1532) having an RC element for a first signal (CAN_H) of the differential signals (CAN_H, CAN_L ) and an RC element for a second signal (CAN_L) of the differential signals (CAN_H, CAN_L).

9) receiving module (122) according to any one of the preceding claims, wherein the second comparator (152; 151) has an at least single-stage circuit with transistors (TRI, TR2, TR5 to TR16).

10) receiving module (122) according to any one of the preceding claims, also with a driver (1222) for driving a digital received signal (RxD) to a communication control device (11) of a subscriber station (10; 30) of the bus system (1), and a logic circuit ( 1222) for forwarding an output signal (CA1) of the first comparator (151; 152) and an output signal (CA2) of the second comparator (152; 151) to the driver (1222) when the drive circuit (158) exceeds the second receiving threshold (T2; TI) and for forwarding only the output signal (CA2) of the second comparator (152; 151) to the driver (1222) when the drive circuit (158) has set the third receiving threshold (T3).

11) receiving module (122) according to any one of the preceding claims, wherein the first comparator (151; 152) for evaluating the from the bus (40) received differential signals (CAN_H, CAN_L) with the first receiving threshold (TI; T2) or the second Reception threshold (T2; TI) is designed.

12) transmitting/receiving device (12; 22; 120) for a subscriber station (10, 20, 30) for a serial bus system (1), with a transmission module (121; 1210) for transmitting signals onto a bus (40) of the bus system (1), and a reception module (122) according to one of the preceding claims.

13) Subscriber station (10; 20; 30) for a serial bus system (1), with a transmitting/receiving device (12; 22) according to claim 12, and a communication control device (11; 21) for controlling the communication in the bus system (1 ) and for generating a digital transmission signal (TxD) for the transmission module (121; 1210).

14) Subscriber station (10; 20; 30) according to claim 13, wherein the subscriber station (10; 20; 30) is designed for communication in a bus system (1) in which at least temporarily an exclusive, collision-free access of a subscriber station (10, 20, 30) on the bus (40) of the bus system (1) is guaranteed.

15) Method for receiving differential signals in a serial bus system (1), the method having the steps with

Receiving, with a receiving module (122), of differential signals (CAN_H, CAN_L) from a bus (40) of the bus system (1), the receiving module (122) being connected to the bus (40) with a voltage divider (1533),

Providing the differential signals (CAN_H, CAN_L) with the voltage divider (1533) for a first comparator (151; 152) and for a second comparator (152; 151),

Evaluation of the differential signals (CAN_H, CAN_L) with the first comparator (151; 152) with a first reception threshold (TI; T2) and with the second comparator (152; 151) with a second or third reception threshold (T2, T3; TI; T3), wherein the first to third reception thresholds (TI; T2, T3) are different, and

Controlling, with a control circuit (158), the second comparator (152; 151) to move the second comparator (152; 151) between the second and third receiving thresholds (T2, T3; TI; T3) in To switch depending on an operating mode of the receiving module (122), in which the receiving module (122) for a first or second communication phase (451, 452) of a communication on the bus (40) is to be switched.