WO2023276333A1

WO2023276333A1 - Composite electronic component

Info

Publication number: WO2023276333A1
Application number: PCT/JP2022/013415
Authority: WO
Inventors: 敏之阿部; 和俊露谷; 武史奥村; 啓太古橋; 満三浦; 祐樹橋本
Original assignee: Tdk株式会社
Priority date: 2021-06-30
Filing date: 2022-03-23
Publication date: 2023-01-05
Also published as: JP2023006519A

Abstract

[Problem] To ensure sufficient inductance and suppress the occurrence of warpage in a composite electronic component comprising an insulation layer in which an electronic component is embedded. [Solution] A composite electronic component 1 comprises: an insulation layer 11; coil patterns C1, C2 that are provided on the side of one surface 11a of the insulation layer 11 and that are magnetically coupled to each other; coil patterns C3, C4 that are provided on the side of another surface 11b of the insulation layer 11 and that are magnetically coupled to each other; and an ESD protection component 2 that is embedded in the insulation layer 11 and is connected at least to the coil patterns C1, C2. This ensures sufficient inductance because the coil patterns are arranged on both sides of the insulation layer 11 in which the ESD protection component 2 is embedded. In addition, the occurrence of warpage is suppressed because the symmetry in the lamination direction is enhanced.

Description

composite electronic components

The present invention relates to a composite electronic component, and more particularly to a composite electronic component comprising an insulating layer in which an electronic component is embedded and a coil pattern.

Patent Document 1 discloses a composite electronic component comprising an insulating layer in which an electronic component is embedded and a coil pattern. For example, FIG. 3 of Patent Document 1 discloses a configuration in which two coil patterns are laminated on an insulating layer in which electronic components are embedded. FIG. 7 of Patent Document 1 discloses a configuration in which two coil patterns are arranged side by side on an insulating layer in which electronic components are embedded.

WO2013/105397

However, in the composite electronic component described in Patent Document 1, since the coil pattern is arranged only on one side of the insulating layer in which the electronic component is embedded, it is difficult to ensure sufficient inductance, and the insulation There is a problem that the entire composite electronic component tends to warp due to the difference in thermal expansion coefficient between the layers and the electronic component.

Accordingly, it is an object of the present invention to ensure sufficient inductance and suppress the occurrence of warping in a composite electronic component including an insulating layer in which electronic components are embedded.

A composite electronic component according to the present invention comprises an insulating layer, first and second coil patterns provided on one surface of the insulating layer and magnetically coupled to each other, and magnetically coupled patterns provided on the other surface of the insulating layer. It is characterized by comprising third and fourth coil patterns, and an electronic component embedded in an insulating layer and connected to at least the first and second coil patterns.

According to the present invention, since the coil patterns are arranged on both sides of the insulating layer in which the electronic components are embedded, sufficient inductance can be secured. Moreover, since the symmetry in the stacking direction is enhanced, the occurrence of warping is also suppressed.

The composite electronic component according to the present invention further comprises first, second, third and fourth signal terminals and a ground terminal, the electronic component being connected between the first and second signal terminals and the ground terminal. An ESD protection component, one ends of the first and second coil patterns are connected to the first and second signal terminals, respectively, and one ends of the third and fourth coil patterns are connected to the third and fourth signal terminals, respectively. The other ends of the first and second coil patterns may be connected to the other ends of the third and fourth coil patterns, respectively. According to this, it becomes possible to provide a common mode filter with an ESD protection function. In this case, the first coil pattern and the second coil pattern overlap each other, the third coil pattern and the fourth coil pattern overlap each other, and the first and second coil patterns have a diameter or number of turns. It doesn't matter if it's different. This facilitates design changes for characteristic adjustment.

The composite electronic component according to the present invention includes fifth and sixth coil patterns provided on one surface side of the insulating layer and magnetically coupled to each other, and seventh and sixth coil patterns provided on the other surface side of the insulating layer and magnetically coupled to each other. 8 coil patterns and fifth, sixth, seventh and eighth signal terminals, the ESD protection component is further connected between the fifth and sixth signal terminals and the ground terminal; and sixth coil patterns are connected to the fifth and sixth signal terminals, respectively; one ends of the seventh and eighth coil patterns are connected to the seventh and eighth signal terminals, respectively; and the other ends of the sixth coil patterns may be connected to the other ends of the seventh and eighth coil patterns, respectively. According to this, it is possible to provide an array product with two built-in common mode filters.

In this case, the first coil pattern and the fifth coil pattern are formed on the same wiring layer and are symmetrical in plan view, and the second coil pattern and the sixth coil pattern are formed on the same wiring layer. and is symmetrical in plan view, the third coil pattern and the seventh coil pattern are formed in the same wiring layer, and are symmetrical in plan view, and the fourth coil pattern and the eighth coil The patterns may be formed in the same wiring layer and may be symmetrical in plan view. According to this, the characteristics of the two common mode filters can be matched, and the pattern design can be facilitated.

As described above, according to the present invention, it is possible to secure sufficient inductance and suppress the occurrence of warpage in a composite electronic component having an insulating layer in which an electronic component is embedded.

FIG. 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to one embodiment of the invention. 2(a) is a schematic cross-sectional view taken along line AA shown in FIG. 1, and FIG. 2(b) is a schematic cross-sectional view taken along line BB shown in FIG. FIG. 3 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer L1. FIG. 4 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer L2. FIG. 5 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer L3. FIG. 6 is a schematic plan view showing the shape of a conductor pattern provided on the conductor layer LESD. FIG. 7 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer L4. FIG. 8 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer L5. FIG. 9 is an equivalent circuit diagram of the composite electronic component 1. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to one embodiment of the present invention.

A composite electronic component 1 according to this embodiment is a surface-mounted chip component, and as shown in FIG. and

2(a) is a schematic cross-sectional view taken along line AA shown in FIG. 1, and FIG. 2(b) is a schematic cross-sectional view taken along line BB shown in FIG.

As shown in FIG. 2, the element body 10 has a structure in which insulating layers 11 to 14 made of resin or the like are laminated. Among them, the insulating layer 14 is provided on one surface 11a side of the insulating layer 11, and the

insulating layers

12 and 13 are provided on the other surface 11b side of the insulating layer 11. As shown in FIG. A conductor layer L4 is formed on one surface 11a of the insulating layer 11 . Conductive layer L4 is covered with insulating layer 14 . A conductor layer L5 is formed on the surface of the insulating layer 14 . Conductive layer L5 is covered with solder resist 32 . A conductor layer L3 is formed on the other surface 11b of the insulating layer 11 . Conductive layer L3 is covered with insulating layer 12 . A conductor layer L2 is formed on the surface of the insulating layer 12 . Conductive layer L2 is covered with insulating layer 13 . A conductor layer L<b>1 is formed on the surface of the insulating layer 13 . Conductive layer L1 is covered with solder resist 31 .

An ESD protection component 2 is embedded in the insulating layer 11 . Since the ESD protection component 2 is composed of a semiconductor substrate, its coefficient of thermal expansion is significantly different from that of the insulating layers 11-14. However, in the present embodiment, the ESD protection component 2 is embedded substantially in the central portion in the stacking direction, and the insulating layers 12 to 14 are provided on both sides thereof. Warpage of the entire composite electronic component 1 caused by this is less likely to occur. The ESD protection component 2 is embedded in the insulating layer 11 in a face-down manner, and terminal electrodes of the ESD protection component 2 are connected to conductor patterns provided on the conductor layer LESD.

3 to 8 are schematic plan views showing shapes of conductor patterns provided on conductor layers L1, L2, L3, LESD, L4 and L5, respectively.

As shown in FIG. 3, conductor patterns 41 to 49 are provided on the conductor layer L1. The conductor patterns 41-49 are connected to the signal terminals 21-28 and the ground terminal 29, respectively.

As shown in FIG. 4, the conductor layer L2 is provided with coil patterns C3 and C7 and conductor patterns 51 to 59, 53a and 57a. The conductor patterns 51-59 are connected to the conductor patterns 41-49 through vias provided in the insulating layer 13, respectively. Further, the outer peripheral end and the inner peripheral end of the coil pattern C3 are connected to the

conductor patterns

53, 53a, respectively. The outer peripheral end and the inner peripheral end of the coil pattern C7 are connected to the

conductor patterns

57, 57a, respectively.

As shown in FIG. 5, the conductor layer L3 is provided with coil patterns C4 and C8 and conductor patterns 61 to 69, 64a and 68a. The conductor patterns 61 to 69 are connected to the

conductor patterns

51, 52, 53a, 54 to 56, 57a, 58, 59 through vias provided in the insulating layer 12, respectively. Further, the outer peripheral end and the inner peripheral end of the coil pattern C4 are connected to the

conductor patterns

64, 64a, respectively. The outer peripheral end and the inner peripheral end of the coil pattern C8 are connected to the

conductor patterns

68, 68a, respectively.

Each of the coil patterns C3, C4, C7, and C8 has a configuration in which a conductor pattern is wound for about 3 turns. The coil pattern C3 and the coil pattern C4 are overlapped in the stacking direction, and the pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Similarly, the coil pattern C7 and the coil pattern C8 overlap in the stacking direction, and their pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Furthermore, the pattern shapes of the coil pattern C3 and the coil pattern C7 are symmetrical in plan view, and the pattern shapes of the coil pattern C4 and the coil pattern C8 are symmetrical in plan view.

As shown in FIG. 6, conductor patterns 71 to 78 and

terminal electrodes

81, 82, 85, 86, 89 of the ESD protection component 2 are provided on the conductor layer LESD. The conductor patterns 71-78 and the terminal electrode 89 are connected to the conductor patterns 61-63, 64a, 65-67, 68a and 69 through vias provided in the insulating layer 11, respectively.

Terminal electrodes

81 , 82 , 85 and 86 are connected to

conductor patterns

61 , 62 , 65 and 66 through vias provided in insulating layer 11 .

As shown in FIG. 7, the conductor layer L4 is provided with coil patterns C1 and C5 and conductor patterns 91-98. The conductor patterns 91-98 are connected to the conductor patterns 71-78 through vias provided in the insulating layer 11, respectively. Further, the outer peripheral end and the inner peripheral end of the coil pattern C1 are connected to the

conductor patterns

91 and 93, respectively. The outer and inner ends of the coil pattern C5 are connected to

conductor patterns

95 and 97, respectively.

As shown in FIG. 8, coil patterns C2 and C6 and

conductor patterns

102, 104, 106 and 108 are provided on the conductor layer L5.

Conductive patterns

102 , 104 , 106 and 108 are connected to

conductive patterns

92 , 94 , 96 and 98 through vias provided in insulating layer 14 . In addition, the outer peripheral end and the inner peripheral end of the coil pattern C2 are connected to the

conductor patterns

102 and 104, respectively. The outer and inner peripheral ends of the coil pattern C6 are connected to

conductor patterns

106 and 108, respectively.

Each of the coil patterns C1, C2, C5, and C6 has a configuration in which a conductor pattern is wound about four turns. The coil pattern C1 and the coil pattern C2 overlap in the stacking direction, and their pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Similarly, the coil pattern C5 and the coil pattern C6 are overlapped in the stacking direction, and the pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Furthermore, the pattern shapes of the coil pattern C1 and the coil pattern C5 are symmetrical in plan view, and the pattern shapes of the coil pattern C2 and the coil pattern C6 are symmetrical in plan view.

FIG. 9 is an equivalent circuit diagram of the composite electronic component 1 according to this embodiment.

As shown in FIG. 9, in the composite electronic component 1 according to the present embodiment, coil patterns C1 and C3 are connected in series between

signal terminals

21 and 23, and coil patterns C2 and C4 are connected in series between

signal terminals

22 and 24. , the coil patterns C5 and C7 are connected in series between the

signal terminals

25 and 27, and the coil patterns C6 and C8 are connected in series between the signal terminals 26 and . Coil patterns C1 and C2 are magnetically coupled, coil patterns C3 and C4 are magnetically coupled, coil patterns C5 and C6 are magnetically coupled, and coil patterns C7 and C8 are magnetically coupled. Furthermore, between the

signal terminals

21 , 22 , 25 , 26 and the ground terminal 29 , protection elements integrated in the ESD protection component 2 are inserted.

As a result, the composite electronic component 1 according to this embodiment constitutes an array of common mode filters with an ESD protection function. Coil patterns C1, C2, C5, and C6 are arranged on one surface 11a of the insulating layer 11 in which the ESD protection component 2 is embedded, and coil patterns C3, C4, C7, and C8 are arranged on the other surface 11b. As a result, the inductance of each common mode filter can be sufficiently increased, and the warpage of the composite electronic component 1 caused by the difference in thermal expansion coefficient between the insulating layers 11 to 14 and the ESD protection component 2 can be reduced. It becomes possible.

In addition, the coil patterns C1, C2, C5, C6 and the coil patterns C3, C4, C7, C8 are sufficiently separated in the stacking direction, and the pattern shapes of both, specifically, the diameter and the number of turns, are different from each other. Therefore, the magnetic coupling between them is suppressed. Therefore, even if the pattern shapes of the coil patterns C1, C2, C5, and C6 are changed for the purpose of adjusting the characteristics, the characteristics of the coil patterns C3, C4, C7, and C8 hardly change, so design changes are easy. becomes. Moreover, since the two coil patterns located on the same conductor layer are symmetrical in plan view, there is almost no characteristic difference between the two common mode filters, and pattern design is easy.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included within the scope.

For example, in the above embodiment, the ESD protection component 2 is embedded in the insulating layer 11, but the electronic component embedded in the insulating layer 11 is not limited to this. Moreover, although the composite electronic component 1 according to the above embodiment is an array product containing two common mode filters, the present invention is not limited to this.

1 composite electronic component 2 ESD protection component 10 base body 11-14 insulating layer 11a one surface 11b of insulating layer other surface 21-28 of insulating layer signal terminal 29

ground terminals

31, 32 solder resist 41-49, 51-57 , 53a, 57a, 61 to 69, 64a, 68a, 71 to 78, 91 to 98, 102, 104, 106, 108

conductor patterns

81, 82, 85, 86, 89 terminal electrodes C1 to C8 coil patterns L1 to L5, LESD conductor layer

Claims

an insulating layer;
first and second coil patterns provided on one surface side of the insulating layer and magnetically coupled to each other;
third and fourth coil patterns provided on the other surface side of the insulating layer and magnetically coupled to each other;
and an electronic component embedded in the insulating layer and connected to at least the first and second coil patterns.
further comprising first, second, third and fourth signal terminals and a ground terminal;
the electronic component is an ESD protection component connected between the first and second signal terminals and the ground terminal;
one ends of the first and second coil patterns are connected to the first and second signal terminals, respectively;
one ends of the third and fourth coil patterns are connected to the third and fourth signal terminals, respectively;
2. The composite electronic component according to claim 1, wherein the other ends of said first and second coil patterns are connected to the other ends of said third and fourth coil patterns, respectively.
the first coil pattern and the second coil pattern overlap each other;
3. The composite electronic component according to claim 2, wherein the third coil pattern and the fourth coil pattern overlap each other, and are different in diameter or number of turns from the first and second coil patterns. .
fifth and sixth coil patterns provided on the one surface side of the insulating layer and magnetically coupled to each other;
seventh and eighth coil patterns provided on the other surface side of the insulating layer and magnetically coupled to each other;
further comprising fifth, sixth, seventh and eighth signal terminals;
the ESD protection component is further connected between the fifth and sixth signal terminals and the ground terminal;
one ends of the fifth and sixth coil patterns are connected to the fifth and sixth signal terminals, respectively;
one ends of the seventh and eighth coil patterns are connected to the seventh and eighth signal terminals, respectively;
4. The composite electronic component according to claim 2, wherein the other ends of said fifth and sixth coil patterns are connected to the other ends of said seventh and eighth coil patterns, respectively.
the first coil pattern and the fifth coil pattern are formed on the same wiring layer and are symmetrical in plan view;
the second coil pattern and the sixth coil pattern are formed on the same wiring layer and are symmetrical in plan view;
the third coil pattern and the seventh coil pattern are formed on the same wiring layer and are symmetrical in plan view;
5. The composite electronic component according to claim 4, wherein said fourth coil pattern and said eighth coil pattern are formed on the same wiring layer and are symmetrical in plan view.