WO2024024160A1 - Composite electronic component - Google Patents

Abstract

[Problem] To enhance freedom of design and prevent the joining of two coil patterns, in a composite electronic component having a structure in which an electronic component is embedded. [Solution] A composite electronic component 1 comprises: coil patterns 41, 42 that are provided to a conductor layer C3 and are arranged with a gap G1 therebetween, without having a ground pattern interposed therebetween; a ground pattern GP that is provided to a conductor layer C4 and overlaps with the gap G1 in plan view; an electronic component 2 that is embedded in an insulation layer 12; and a plurality of external terminals.

Description

composite electronic components

The present disclosure relates to a composite electronic component, and particularly relates to a composite electronic component including an insulating layer in which an electronic component is embedded and a coil pattern provided on the insulating layer.

FIG. 1 of Patent Document 1 and FIG. 12 of Patent Document 2 disclose a structure in which coupling between the coil patterns is suppressed by arranging a ground pattern between two coil patterns arranged on the same conductor layer. There is.

JP2002-280218A Japanese Patent Application Publication No. 9-205018 International Publication No. 2015/194373

However, when a ground pattern is placed between two coil patterns, the area in which the coil pattern can be formed is reduced, resulting in a problem in that the degree of freedom in design is reduced. Such a problem becomes more noticeable in a composite electronic component having a structure in which electronic components are embedded, as described in Patent Document 3. This is because the flatness of the base of the coil pattern deteriorates in areas where it overlaps with electronic components, so it is necessary to design the coil pattern in a position that does not overlap with electronic components as much as possible, further reducing the degree of freedom in design. .

In the present disclosure, a composite electronic component that has a structure in which an electronic component is embedded and has increased design freedom while suppressing coupling between two coil patterns is described.

A composite electronic component according to an aspect of the present disclosure includes an insulating layer and a first conductor layer located on one surface side of the insulating layer, and is arranged through a first gap without using a ground pattern. The first and second coil patterns, the ground pattern provided on the second conductor layer located on one surface side of the insulating layer and overlapping the first gap in plan view, and the first ground pattern embedded in the insulating layer and a second coil pattern and an electronic component connected to the ground pattern, and a plurality of external terminals, the plurality of external terminals are connected to the first and second signals respectively connected to both ends of the first coil pattern. a terminal, third and fourth signal terminals respectively connected to both ends of the second coil pattern, and first and second ground terminals respectively connected to both ends of the ground pattern.

According to the present disclosure, the ground pattern overlapping the first gap is arranged not in the first conductor layer provided with the first and second coil patterns but in the second conductor layer different from the first conductor layer. Therefore, even if flatness deteriorates due to electronic components being embedded in the insulating layer, it is possible to suppress coupling between the first and second coil patterns and ensure sufficient design freedom. becomes possible.

A composite electronic component according to one aspect of the present disclosure further includes third and fourth coil patterns provided on a third conductor layer located on one surface side of the insulating layer and connected to the electronic component, and further includes third and fourth coil patterns connected to the electronic component. The third coil pattern is arranged at a position overlapping with the first coil pattern in a plan view, the fourth coil pattern is arranged at a position overlapping with the second coil pattern in a plan view, and the plurality of external terminals are arranged at a position overlapping with the first coil pattern in a plan view. The present invention further includes fifth and sixth signal terminals connected to both ends of the third coil pattern, respectively, and seventh and eighth signal terminals connected to both ends of the fourth coil pattern, respectively. I do not care. According to this, the first and third coil patterns are magnetically coupled while suppressing coupling between the first and third coil patterns and the second and fourth coil patterns, and the second and fourth coil patterns are coupled to each other. Magnetic coupling becomes possible.

A composite electronic component according to one aspect of the present disclosure includes fifth and sixth coil patterns provided on a fourth conductor layer located on the other surface side of the insulating layer; It is also possible to further include seventh and eighth coil patterns that are provided on the fifth conductor layer and overlap the fifth and sixth coil patterns, respectively, in plan view. According to this, it becomes possible to provide a more highly functional composite electronic component.

In the present disclosure, the first and fifth coil patterns are connected in series between the first and second signal terminals, and the second and sixth coil patterns are connected in series between the third and fourth signal terminals. The third and seventh coil patterns are connected in series between the fifth and sixth signal terminals, and the fourth and eighth coil patterns are connected in series between the seventh and eighth signal terminals. It doesn't matter if it is connected to According to this, it is possible to provide an array product incorporating two common mode filters.

In the present disclosure, the fifth, sixth, seventh, and eighth coil patterns may have longer wiring lengths than the first, second, third, and fourth coil patterns, respectively. According to this, it becomes possible to further improve the characteristics of the common mode filter consisting of the fifth and seventh coil patterns and the common mode filter consisting of the sixth and eighth coil patterns.

In the present disclosure, the second gap between the fifth and sixth coil patterns may be narrower than the first gap. According to this, it becomes possible to further increase the number of turns of the fifth and sixth coil patterns.

In the present disclosure, the second ground terminal may be connected to the electronic component via a ground pattern. According to this, there is no need to provide a dedicated via conductor for the second ground terminal, so the degree of freedom in designing the first and second coil patterns is further increased.

In the present disclosure, all of the plurality of external terminals may be located on the second conductor layer. According to this, there is no need to add a dedicated conductor layer for providing a ground pattern.

As described above, according to the present disclosure, there is provided a composite electronic component that has a structure in which electronic components are embedded, and has increased design freedom while suppressing coupling between two coil patterns.

FIG. 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to an embodiment of the technology according to the present disclosure. FIG. 2(a) is a schematic cross-sectional view of the cross section taken along the line AA shown in FIG. 1, viewed from one direction, and FIG. It is a schematic sectional view seen from the opposite direction side. FIG. 3 is a schematic exploded perspective view of the composite electronic component 1. FIG. 4 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C4. FIG. 5 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C3. FIG. 6 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C2. FIG. 7 is a schematic plan view of the layer in which the ESD protection component 2 is embedded. FIG. 8 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C1. FIG. 9 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C0. FIG. 10 is an equivalent circuit diagram of the composite electronic component 1. FIG. 11 is a diagram for explaining the positional relationship between the coil patterns 43 and 44 and the ESD protection component 2. FIG. 12 is a diagram for explaining the positional relationship between the coil patterns 41 and 42 and the ground pattern GP. FIG. 13 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 14 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 15 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 16 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 17 is a process diagram for explaining the manufacturing method of the composite electronic component 1. FIG. 18 is a process diagram for explaining the method for manufacturing the composite electronic component 1. FIG. 19 is a process diagram for explaining the method for manufacturing the composite electronic component 1. FIG. 20 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 21 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 22 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 23 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 24 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG. FIG. 25 is a process diagram for explaining the method for manufacturing the composite electronic component 1. As shown in FIG.

Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to an embodiment of the technology according to the present disclosure.

The composite electronic component 1 according to the present embodiment is a surface-mounted chip component, and includes an element body 10 and a plurality of external terminals arranged in an array on the surface of the element body 10, as shown in FIG. There is. The plurality of external terminals consists of eight signal terminals 20 to 27 and two ground terminals 28 and 29.

FIG. 2(a) is a schematic cross-sectional view of the cross section taken along the line AA shown in FIG. 1, viewed from one direction, and FIG. It is a schematic sectional view seen from the opposite direction side.

As shown in FIGS. 2(a) and 2(b), the element body 10 has a structure in which insulating layers 11 to 14 made of resin or the like are laminated in this order. Of these, the insulating layers 13 and 14 are provided on the one surface 12a side of the insulating layer 12, and the insulating layer 11 is provided on the other surface 12b side of the insulating layer 12. A conductor layer C1 is formed on the other surface 12b side of the insulating layer 12. The conductor layer C1 is covered with an insulating layer 11. A conductor layer C0 is formed on the surface of the insulating layer 11. The conductor layer C0 is covered with a solder resist 31. A conductor layer C2 is formed on one surface 12a side of the insulating layer 12. The conductor layer C2 is covered with an insulating layer 13. A conductor layer C3 is formed on the surface of the insulating layer 13. The conductor layer C3 is covered with an insulating layer 14. A conductor layer C4 is formed on the surface of the insulating layer 14. The conductor layer C4 is covered with a solder resist 32.

An ESD protection component 2 is embedded in the insulating layer 12. Since the ESD protection component 2 is constituted by a semiconductor substrate, it has a thermal expansion coefficient significantly different from that of the insulating layers 11 to 14. However, in this embodiment, since the ESD protection component 2 is embedded approximately at the center in the stacking direction, and the insulating layers 11, 13, and 14 are provided on both sides, the symmetry in the stacking direction can be adjusted by adjusting the thickness. The degree of freedom in adjustment is high, and the entire composite electronic component 1 is less likely to warp due to temperature changes.

FIG. 3 is a schematic exploded perspective view of the composite electronic component 1.

As shown in FIG. 3, coil patterns 41 to 48 are embedded in the composite electronic component 1. Of these, coil patterns 41 and 42 are arranged on the conductor layer C3, coil patterns 43 and 44 are arranged on the conductor layer C2, coil patterns 45 and 46 are arranged on the conductor layer C1, and coil patterns 47 and 48 are arranged on the conductor layer C2. It is located at C0. The coil patterns 41 and 43 overlap each other in a plan view with the insulating layer 13 in between, and the coil patterns 42 and 44 overlap in a plan view with the insulating layer 13 in between. Further, the coil patterns 45 and 47 overlap each other in a plan view with the insulating layer 11 interposed therebetween, and the coil patterns 46 and 48 overlap each other in a plan view with the insulating layer 11 interposed therebetween.

4 to 6, FIG. 8, and FIG. 9 are schematic plan views showing the shapes of conductor patterns provided in conductor layers C4, C3, C2, C1, and C0, respectively. Moreover, FIG. 7 is a schematic plan view of a layer in which the ESD protection component 2 is embedded. Here, the line AA shown in FIGS. 4 to 9 corresponds to the cross section shown in FIGS. 2(a) and 2(b).

As shown in FIG. 4, the conductor layer C4 is provided with conductor patterns 50 to 59 and a ground pattern GP. The portions of the conductive patterns 50 to 57 exposed from the solder resist 32 are surface-treated and used as signal terminals 20 to 27, respectively. Portions of the conductive patterns 58 and 59 exposed from the solder resist 32 are surface-treated and used as ground terminals 28 and 29, respectively. Further, the conductor patterns 58 and 59 are connected to each other via a ground pattern GP. The ground pattern GP is a conductor pattern extending linearly, and its width is narrower than the width of the conductor patterns 58 and 59. In this way, since the ground pattern GP, the signal terminals 20 to 27, and the conductor patterns 58 and 59 are arranged on the same conductor layer C4, there is no need to add a dedicated conductor layer for providing the ground pattern GP. do not have.

As shown in FIG. 5, the conductor layer C3 is provided with coil patterns 41, 42 and conductor patterns 60, 61, 63-66. The outer peripheral end of the coil pattern 41 is connected to a conductor pattern 52 via a via conductor 102. The outer peripheral end of the coil pattern 42 is connected to a conductor pattern 57 via a via conductor 107. Furthermore, the conductor patterns 60, 61, 63-66 are connected to the conductor patterns 50, 51, 53-56, respectively, via via conductors 100, 101, 103-106 provided in the insulating layer 14. The coil pattern 41 and the coil pattern 42 are adjacent to each other with a gap G1 in between. In the conductor layer C3, a ground pattern or the like is not provided in the gap G1, and the coil pattern 41 and the coil pattern 42 are directly adjacent to each other with the insulating layer 14 in between.

As shown in FIG. 6, the conductor layer C2 is provided with coil patterns 43 and 44 and conductor patterns 70 to 76. The outer peripheral end of the coil pattern 43 is connected to the conductor pattern 63 via a via conductor 113. The outer peripheral end of the coil pattern 44 is connected to the conductor pattern 66 via the via conductor 116. Further, conductor patterns 70 to 74 are connected to conductor patterns 60, 61, 64, 65, and 68 via via conductors 110, 111, 114, 115, and 118, respectively. The conductor patterns 75 and 76 are connected to the inner peripheral ends of the coil patterns 41 and 42 via via conductors 112 and 117, respectively. The coil pattern 43 and the coil pattern 44 are adjacent to each other with a gap G1 in between. In the conductor layer C2, a ground pattern or the like is not provided in the gap G1, and the coil pattern 43 and the coil pattern 44 are directly adjacent to each other with the insulating layer 13 in between.

Each of the coil patterns 41 to 44 has a configuration in which a conductor pattern is wound around four turns. The coil pattern 41 and the coil pattern 43 overlap in the stacking direction, and their pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Similarly, the coil pattern 42 and the coil pattern 44 overlap in the stacking direction, and their pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Further, the pattern shapes of the coil pattern 41 and the coil pattern 42 are symmetrical in plan view, and the pattern shapes of the coil pattern 43 and coil pattern 44 are symmetrical in plan view.

As shown in FIG. 7, terminal electrodes 80 to 87 are provided on the surface of the ESD protection component 2. Terminal electrodes 80 to 83 are connected to conductor patterns 70 to 73, respectively, via via conductors 120 to 123 provided in insulating layer 12. Furthermore, the terminal electrodes 84 to 87 are commonly connected to the conductor pattern 74 via via conductors 124 to 127 provided in the insulating layer 12.

As shown in FIG. 8, the conductor layer C1 is provided with coil patterns 45, 46 and conductor patterns 91, 93, 94, 97. The outer peripheral end of the coil pattern 45 is connected to the conductor pattern 70 via a via conductor 130. The outer peripheral end of the coil pattern 46 is connected to the conductor pattern 73 via a via conductor 135. The inner peripheral end of the coil pattern 45 is connected to the conductor pattern 75 via the via conductor 132. The inner peripheral end of the coil pattern 46 is connected to the conductor pattern 76 via a via conductor 136. Furthermore, conductor patterns 91 and 94 are connected to conductor patterns 71 and 72 via via conductors 131 and 134, respectively. Furthermore, conductor patterns 93 and 97 are connected to inner peripheral ends of coil patterns 43 and 44 via via conductors 133 and 137, respectively. The coil pattern 45 and the coil pattern 46 are adjacent to each other with a gap G2 in between. In the conductor layer C1, a ground pattern or the like is not provided in the gap G2, and the coil pattern 45 and the coil pattern 46 are directly adjacent to each other with the insulating layer 12 in between.

As shown in FIG. 9, coil patterns 47 and 48 are provided on the conductor layer C0. The outer peripheral end and inner peripheral end of the coil pattern 47 are connected to conductor patterns 91 and 93 via via conductors 141 and 143, respectively. The outer peripheral end and inner peripheral end of the coil pattern 48 are connected to conductor patterns 94 and 97 via via conductors 144 and 147, respectively. The coil pattern 47 and the coil pattern 48 are adjacent to each other with a gap G2 in between. In the conductor layer C0, a ground pattern or the like is not provided in the gap G2, and the coil pattern 47 and the coil pattern 48 are directly adjacent to each other with the insulating layer 11 in between.

Each of the coil patterns 45 to 48 has a structure in which a conductor pattern is wound around 5 turns. The coil pattern 45 and the coil pattern 47 overlap in the stacking direction, and their pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Similarly, the coil pattern 46 and the coil pattern 48 overlap in the stacking direction, and their pattern shapes are substantially the same except for the positions of the outer peripheral end and the inner peripheral end. Furthermore, the pattern shapes of the coil pattern 45 and the coil pattern 46 are symmetrical in a plan view, and the pattern shapes of the coil pattern 47 and the coil pattern 48 are symmetrical in a plan view.

FIG. 10 is an equivalent circuit diagram of the composite electronic component 1 according to this embodiment.

As shown in FIG. 10, in the composite electronic component 1 according to the present embodiment, coil patterns 45 and 41 are connected in series between the signal terminals 20 and 22, and coil patterns 47 and 43 are connected in series between the signal terminals 21 and 23. Coil patterns 48 and 44 are connected in series between the signal terminals 24 and 26, and coil patterns 46 and 42 are connected in series between the signal terminals 25 and 27. The common mode filter CMF1 is configured by magnetically coupling the coil patterns 41 and 43, the common mode filter CMF2 is configured by magnetically coupling the coil patterns 42 and 44, and the coil patterns 45 and 47 are magnetically coupled. A common mode filter CMF3 is configured by this, and a common mode filter CMF4 is configured by magnetically coupling the coil patterns 46 and 48. Further, a protection element integrated in the ESD protection component 2 is inserted between the signal terminals 20, 21, 24, 25 and the ground terminals 28, 29. Thereby, the composite electronic component 1 according to this embodiment constitutes an array of common mode filters with an ESD protection function. The ground terminal 29 is connected to the ESD protection component 2 via the ground pattern GP.

FIG. 11 is a diagram for explaining the positional relationship between the coil patterns 43 and 44 and the ESD protection component 2.

As shown in FIG. 11, the coil patterns 43 and 44 are arranged avoiding the ESD protection component 2 so as not to overlap the ESD protection component 2 as much as possible in plan view. This is because the flatness of the insulating layer 12 deteriorates in the portion overlapping with the ESD protection component 2. In the example shown in FIG. 11, part of the coil patterns 43 and 44 overlaps with the ESD protection component 2 in plan view, but the coil patterns 43 and 44 may be designed so that they do not overlap. Note that the coil patterns 41 and 42 have the same planar shape as the coil patterns 43 and 44, respectively, and are disposed at the same planar position as the coil patterns 43 and 44, so that the coil patterns 41 and 42 are different from each other. The positional relationship between the ESD protection component 2 is the same as that between the coil patterns 43 and 44 and the ESD protection component 2.

FIG. 12 is a diagram for explaining the positional relationship between the coil patterns 41 and 42 and the ground pattern GP.

As shown in FIG. 12, the ground pattern GP is arranged along the outermost turn of the coil patterns 41, 42 so as to overlap the gap G1 between the coil patterns 41, 42 in plan view. Although the ground pattern GP is provided on a conductor layer C4 different from the coil patterns 41 to 44, by arranging it so as to overlap the gap G1 in a plan view, the connection between the coil patterns 41 and 42 and the coil It plays a role of suppressing the coupling between the pattern 43 and the coil pattern 44. By minimizing the overlap between the ground pattern GP and the coil patterns 41 to 44, stray capacitance components occurring in the coil patterns 41 to 44 can be reduced. In the example shown in FIG. 12, the width of the ground pattern GP is designed to be approximately the same width as the gap G1, so that each turn of the coil patterns 41 to 44 except for at least the outermost turn is connected to the ground pattern GP. There is no overlap.

The ground pattern GP plays the role of connecting the ground terminal 28 and the ground terminal 29 by connecting the conductive pattern 58 and the conductive pattern 59. Here, the conductor pattern 59 is not provided with a corresponding via conductor, and therefore, the ground potential applied to the ground terminal 29 is supplied to the conductor pattern 58 via the conductor pattern 59 and the ground pattern GP. . In other words, the ground terminal 29 is used as a so-called dummy terminal. The reason why such a ground terminal 29 is provided is to ensure sufficient mounting strength when the composite electronic component 1 according to this embodiment is mounted on a circuit board. Further, since a via conductor is not provided at a position overlapping with the conductor pattern 59 in plan view, the conductor pattern 59 is likely to peel off, but in this embodiment, the conductor pattern 59 is connected to the conductor pattern via the ground pattern GP. Since it is connected to the pattern 58, peeling of the conductive pattern 59 is also prevented.

As described above, in the composite electronic component 1 according to the present embodiment, a ground pattern or the like is not provided between the coil pattern 41 and the coil pattern 42, and a ground pattern or the like is provided between the coil pattern 43 and the coil pattern 44. Since the conductor layers C2 and C3 are not provided, the degree of freedom in designing the conductor layers C2 and C3 is increased. Moreover, since the ground pattern GP is provided on the conductor layer C4 so as to overlap with the gap G1 in plan view, the coupling between the coil pattern 41 and the coil pattern 42 and the coupling between the coil pattern 43 and the coil pattern 44 are reduced. It also becomes possible to suppress binding.

Furthermore, when the composite electronic component 1 is mounted on a circuit board, the coil patterns 45 to 44 whose distance from the circuit board is farther than the number of turns, wiring length, and coil diameter of the coil patterns 41 to 44 which are close to the circuit board. Since the number of turns, wiring length, and coil diameter of 48 are increased, the coil patterns 45 to 48, which have larger inductance, are less affected by the circuit board.

Furthermore, since the coil patterns 41 to 44 are arranged on one surface 12a side of the insulating layer 12 in which the ESD protection component 2 is embedded, and the coil patterns 45 to 48 are arranged on the other surface 12b side, each common In addition to being able to sufficiently increase the inductance of the mode filter, it is also possible to reduce warping of the composite electronic component 1 due to the difference in thermal expansion coefficients between the insulating layers 11 to 14 and the ESD protection component 2.

In addition, since the coil patterns 41 to 44 and the coil patterns 45 to 48 are sufficiently separated in the stacking direction and their pattern shapes, specifically diameters and number of turns, are different from each other, magnetic coupling occurs between them. can be suppressed. Therefore, even if the pattern shapes of the coil patterns 41 to 44 are changed in order to adjust the characteristics, for example, the characteristics of the coil patterns 45 to 48 hardly change, making it easy to change the design. Moreover, since the two coil patterns located on the same conductor layer are symmetrical in plan view, there is almost no difference in characteristics between the two common mode filters, and pattern design is also facilitated.

Next, a method for manufacturing the composite electronic component 1 according to this embodiment will be described.

13 to 25 are process diagrams for explaining the method for manufacturing the composite electronic component 1 according to this embodiment.

First, a copper foil 200 with a carrier is prepared, and a resist pattern 201 is formed on its surface (FIG. 13). The carrier-attached copper foil 200 has a structure in which a release layer is provided between two layers of copper foil. The resist pattern 201 is a negative pattern of the conductor layer C0. In this state, electrolytic plating is performed and the resist pattern 201 is removed to form a conductor layer C0 (FIG. 14). Next, an insulating layer 11 is formed on the surface of the carrier-attached copper foil 200 so that the conductor layer C0 is embedded (FIG. 15). As a result, the side and top surfaces of the conductor pattern located on the conductor layer C0 are covered with the insulating layer 11.

Next, a portion of the conductor layer C0 is exposed by forming a via 202 at a location where a via conductor is to be formed, and then a seed layer 203 is formed on the surface of the insulating layer 11 by electroless plating (FIG. 16). . Next, after forming a resist pattern 204 on the surface of the seed layer 203, electrolytic plating is performed to form a conductor layer C1 (FIG. 17). Next, after removing the resist pattern 204 (FIG. 18), an insulating layer 12A is formed on the surface of the insulating layer 11 so that the conductor layer C1 is embedded, and the ESD protection component 2 is mounted on the surface (FIG. 19). . As a result, the side and top surfaces of the conductor pattern located on the conductor layer C1 are covered with the insulating layer 12A. Next, an insulating layer 12B is formed on the surface of the insulating layer 12A so that the ESD protection component 2 is embedded (FIG. 20). Thereby, the ESD protection component 2 has the insulating layer 12A. It is embedded in the insulating layer 12 made of 12B.

Next, by repeating the process described using FIGS. 16 to 18, a conductor layer C2 is formed on the surface of the insulating layer 12, and then an insulating layer 13 is formed on the surface of the insulating layer 12 so that the conductor layer C2 is embedded. (Figure 21). By repeating this process, a conductor layer C3 is formed on the surface of the insulating layer 13, and then an insulating layer 14 is formed on the surface of the insulating layer 13 so that the conductor layer C3 is embedded (FIG. 22). Next, after forming the conductor layer C4 on the surface of the insulating layer 14, one layer of the copper foil is peeled off via the peeling layer provided on the carrier-attached copper foil 200 (FIG. 23), and the carrier-attached copper foil 200 is separated. The remaining copper foil is removed by etching (FIG. 24). This etching also removes the seed layer used to form the conductor layer C4. After forming solder resists 31 and 32 on the outermost surfaces of the insulating layers 11 and 14, respectively (FIG. 25), the signal terminals 21 to 27 and the ground terminals 28 and 29 are formed by surface treatment. Electronic component 1 is completed.

As described above, in the manufacturing process of the composite electronic component 1 according to the present embodiment, the conductor layers C0 to C4 are laminated in this order. For this reason, since the conductor layers C0 and C1 formed before the ESD protection component 2 are embedded have high flatness as a base, the conductor patterns are formed at a fine pitch even at positions overlapping with the ESD protection component 2 in plan view. can do. On the other hand, since the conductor layers C2 to C4 are formed after the ESD protection component 2 is embedded, the flatness decreases at the positions where they overlap with the ESD protection component 2 in plan view. Taking this point into consideration, in this embodiment, the coil patterns 41 to 48 formed on the conductor layers C2 and C3 are set to be The design is such that the area where the ESD protection component 2 and the ESD protection component 2 overlap is shortened. This makes it possible to ensure a sufficient number of turns and coil diameter of the coil patterns 45 to 48 formed on the conductor layers C0 and C1.

On the other hand, since the coil patterns 41 to 44 formed in the conductor layers C2 and C3 need to be designed so as not to overlap with the ESD protection component 2 as much as possible in plan view, the degree of freedom in design is reduced accordingly. However, in this embodiment, a ground pattern located between the coil patterns 41 and 42 or between the coil patterns 43 and 44 is not provided on the conductor layers C2 and C3, but a ground pattern GP that overlaps with the gap G1 is provided on the conductor layer C4. Therefore, it is possible to increase the degree of freedom in designing the conductor layers C2 and C3 while suppressing the coupling between the coil pattern 41 and the coil pattern 42 and the coupling between the coil pattern 43 and the coil pattern 44.

Although the embodiments of the technology according to the present disclosure have been described above, the technology according to the present disclosure is not limited to the above embodiments, and various changes can be made without departing from the spirit thereof. It goes without saying that this is included within the scope of the technology according to the present disclosure.

For example, in the above embodiment, the ESD protection component 2 is embedded in the insulating layer 12, but the electronic component embedded in the insulating layer 12 is not limited to this.

This application claims the benefit of Japanese Patent Application No. 2022-121464, filed on July 29, 2022, the entire disclosure of which is incorporated herein by reference.

1 Composite electronic components 2 ESD protection components (electronic components)
10 Element bodies 11-14, 12A, 12B Insulating layers 12a, 12b Insulating layer surfaces 20-27 Signal terminals 28, 29 Ground terminals 31, 32 Solder resists 41-48 Coil patterns 50-59 Conductor patterns 60, 61, 63- 66, 68 Conductor patterns 70-76 Conductor patterns 80-87 Terminal electrodes 91, 93, 94, 97 Conductor patterns 100-107, 110-118, 120-127, 130-137, 141, 143, 144, 147 Via conductor 200 Copper foil with carrier 201 Resist pattern 202 Via 203 Seed layer 204 Resist pattern C0 to C4 Conductor layer CMF1 to CMF4 Common mode filters G1, G2 Gap GP Ground pattern

Claims (8)

1. an insulating layer;
   first and second coil patterns provided on a first conductor layer located on one surface side of the insulating layer and arranged through a first gap without a ground pattern;
   a ground pattern provided on a second conductor layer located on the one surface side of the insulating layer and overlapping with the first gap in plan view;
   an electronic component embedded in the insulating layer and connected to the first and second coil patterns and the ground pattern;
   Equipped with multiple external terminals,
   The plurality of external terminals include first and second signal terminals connected to both ends of the first coil pattern, and third and fourth signal terminals connected to both ends of the second coil pattern, respectively. A composite electronic component including a terminal and first and second ground terminals respectively connected to both ends of the ground pattern.
2. Further comprising third and fourth coil patterns provided on a third conductor layer located on the one surface side of the insulating layer and connected to the electronic component,
   The third coil pattern is arranged at a position overlapping the first coil pattern in a plan view,
   The fourth coil pattern is arranged at a position overlapping with the second coil pattern in plan view,
   The plurality of external terminals include fifth and sixth signal terminals connected to both ends of the third coil pattern, respectively, and seventh and eighth signal terminals connected to both ends of the fourth coil pattern, respectively. The composite electronic component according to claim 1, further comprising a terminal.
3. fifth and sixth coil patterns provided on a fourth conductor layer located on the other surface side of the insulating layer;
   Further comprising seventh and eighth coil patterns provided on a fifth conductor layer located on the other surface side of the insulating layer and respectively overlapping the fifth and sixth coil patterns in plan view. The composite electronic component according to claim 2.
4. the first and fifth coil patterns are connected in series between the first and second signal terminals,
   the second and sixth coil patterns are connected in series between the third and fourth signal terminals,
   the third and seventh coil patterns are connected in series between the fifth and sixth signal terminals,
   The composite electronic component according to claim 3, wherein the fourth and eighth coil patterns are connected in series between the seventh and eighth signal terminals.
5. The composite electronic component according to claim 3, wherein the fifth, sixth, seventh, and eighth coil patterns have longer wiring lengths than the first, second, third, and fourth coil patterns, respectively.
6. The composite electronic component according to claim 3, wherein the second gap between the fifth and sixth coil patterns is narrower than the first gap.
7. The composite electronic component according to claim 1, wherein the second ground terminal is connected to the electronic component via the ground pattern.
8. The composite electronic component according to any one of claims 1 to 7, wherein the plurality of external terminals are all located on the second conductor layer.

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