WO2023273377A1 - 时钟接收电路和电子设备 - Google Patents

时钟接收电路和电子设备 Download PDF

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Publication number
WO2023273377A1
WO2023273377A1 PCT/CN2022/078778 CN2022078778W WO2023273377A1 WO 2023273377 A1 WO2023273377 A1 WO 2023273377A1 CN 2022078778 W CN2022078778 W CN 2022078778W WO 2023273377 A1 WO2023273377 A1 WO 2023273377A1
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Prior art keywords
type
transistor
electrically connected
pole
level
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PCT/CN2022/078778
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English (en)
French (fr)
Inventor
朱文涛
常云峰
罗豪
陈玉虎
朱海鹏
刁玉梅
Original Assignee
深圳市中兴微电子技术有限公司
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Application filed by 深圳市中兴微电子技术有限公司 filed Critical 深圳市中兴微电子技术有限公司
Priority to JP2023579856A priority Critical patent/JP2024523605A/ja
Priority to KR1020237044763A priority patent/KR20240013214A/ko
Priority to EP22831208.8A priority patent/EP4350991A1/en
Publication of WO2023273377A1 publication Critical patent/WO2023273377A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of integrated circuits, and in particular, relate to a clock receiving circuit and an electronic device including the clock receiving circuit.
  • the operating frequency of integrated circuits is getting higher and higher, and the high-speed clock is attenuated more seriously during transmission, and is more susceptible to interference from non-ideal factors such as noise and mismatch. , causing clock performance degradation. Therefore, in high-speed circuits, the clock receiving circuit is particularly important.
  • the clock receiving circuit adopts a current mode logic (CML, Current Mode Logic) structure to receive and amplify an input clock.
  • CML Current Mode Logic
  • the phase noise of this kind of clock receiving circuit is relatively large, and the power consumption is also relatively large.
  • the present disclosure provides a clock receiving circuit and an electronic device including the clock receiving circuit.
  • an embodiment of the present disclosure provides a clock receiving circuit, the clock receiving circuit includes a common-mode voltage adjustment module, an amplitude amplification module, and a level conversion module, wherein,
  • the common-mode voltage adjustment module includes an n-type signal conversion unit, a high-level n-type signal output terminal, a low-level n-type signal output terminal, a p-type signal conversion unit, a high-level p-type signal output terminal, a low-level
  • the p-type signal output terminal, the n-type signal conversion unit is used to convert the input n-type signal into a high-level n-type signal and output through the high-level n-type signal output terminal, the n-type signal conversion unit It is also used to convert the input n-type signal into a low-level n-type signal and output through the low-level n-type signal, and the p-type signal conversion unit is used to convert the input p-type signal into a high-level p
  • the p-type signal is output through the high-level p-type signal output terminal, and the p-type signal conversion unit is also used to convert the input p-type signal into a low-level p-type
  • the amplitude amplification module includes a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair, and a bias control unit;
  • the bias control unit is used to control the p-type current source transistor and the n-type current source transistor to work in a saturation region;
  • the first pole of the p-type current source transistor is electrically connected to the high-level signal terminal, and the second pole of the p-type current source transistor is electrically connected to the two first ends of the differential pair of p-type transistors;
  • the two second ends of the p-type transistor differential pair are respectively electrically connected to the two first ends of the n-type transistor differential pair, and the two input ends of the p-type transistor differential pair are respectively connected to the low level
  • the p-type signal output terminal and the low-level n-type signal output terminal are electrically connected, so that the two p-type transistors in the differential pair of p-type transistors both work in the amplification region;
  • the two second ends of the n-type transistor differential pair are electrically connected to the first pole of the n-type current source transistor, and the two input ends of the n-type transistor differential pair are respectively connected to the high-level p-type signal
  • the output terminal and the high-level n-type signal output terminal are electrically connected, so that both n-type transistors in the differential pair of n-type transistors work in the amplification region;
  • the level conversion module is configured to convert the CML level signal output by the amplitude amplification circuit into a CMOS level signal.
  • the differential pair of p-type transistors includes a first p-type transistor and a second p-type transistor, the first pole of the first p-type transistor is electrically connected to the first pole of the second p-type transistor,
  • the first pole of the first p-type transistor and the first pole of the second p-type transistor are respectively formed as two first ends of the p-type differential pair, and the second pole of the first p-type transistor Pole and the second pole of the second p-type transistor are respectively formed as two second ends of the p-type differential pair, the gate of the first p-type transistor and the gate of the second p-type transistor
  • the poles are respectively formed as two input ends of the differential pair of p-type transistors, the gate of the first p-type transistor is electrically connected with the low-level n-type signal output end, and the gate of the second p-type transistor The pole is electrically connected to the low-level p-type signal output terminal.
  • the differential pair of n-type transistors includes a first n-type crystal and a second n-type transistor, and the first pole of the first n-type transistor and the first pole of the second n-type transistor are respectively formed as The two first ends of the differential pair of n-type transistors, the first pole of the first n-type transistor is electrically connected to the second pole of the first p-type transistor, and the first pole of the second n-type transistor The pole is electrically connected to the second pole of the second p-type transistor;
  • the second pole of the first n-type transistor and the second pole of the second n-type transistor are respectively formed as two second ends of the n-type differential pair, and the second pole of the first n-type transistor The pole is electrically connected to the second pole of the second n-type transistor;
  • the gate of the first n-type transistor and the gate of the second n-type transistor are respectively formed as two input terminals of the differential pair of n-type transistors, and the gate of the first n-type transistor is connected to the gate of the second n-type transistor.
  • the high-level n-type signal output end is electrically connected, and the gate of the second n-type transistor is electrically connected to the high-level p-type signal output end.
  • the bias control unit includes a first n-type current mirror transistor, a second n-type current mirror transistor, a third n-type current mirror transistor, a fourth n-type current mirror transistor, a first p-type current mirror transistor and a second p-type current mirror transistor;
  • the first pole of the first n-type current mirror transistor is configured to be electrically connected to a current source, and the first pole of the first n-type current mirror transistor is electrically connected to the gate of the first n-type current mirror transistor , the second pole of the first n-type current mirror transistor is electrically connected to the first pole of the second n-type current mirror transistor, the second pole of the second n-type current mirror transistor is grounded, and the second The gate of the n-type current mirror transistor is electrically connected to the gate of the third n-type current mirror transistor and the gate of the n-type current source transistor;
  • the first pole of the third n-type current mirror transistor is grounded, and the second pole of the third n-type current mirror transistor is electrically connected to the first pole of the fourth n-type current mirror transistor;
  • the second pole of the fourth n-type current mirror transistor is electrically connected to the first pole of the first p-type current mirror transistor, and the gate of the fourth n-type current mirror transistor is connected to the first n-type current mirror transistor.
  • the gate of the mirror transistor is electrically connected;
  • the gate of the first p-type current mirror transistor is electrically connected to the first pole of the first p-type current mirror transistor, and the second pole of the first p-type current mirror transistor is electrically connected to the second p-type current mirror transistor.
  • the first electrode of the mirror transistor is electrically connected;
  • the second pole of the second p-type current mirror transistor is configured to be electrically connected to the high-level signal terminal, and the gate of the second p-type current mirror transistor is electrically connected to the gate of the p-type current source transistor .
  • the common-mode voltage adjustment module further includes an impedance matching resistor, a first voltage dividing resistor and a second voltage dividing resistor, and the impedance matching resistor is connected between the p-port and the n-port of the common-mode voltage adjusting module Between, one end of the first voltage dividing resistor is electrically connected to the high-level signal end;
  • the p-type signal conversion unit includes a first coupling capacitor, a third coupling capacitor, and a third resistor, a fifth resistor, a seventh resistor, and a ninth resistor connected in series in sequence, and one end of the third coupling capacitor is connected to the first The other end of the voltage dividing resistor is electrically connected, the ninth resistor is electrically connected to one end of the second voltage dividing resistor, the second end of the second voltage dividing resistor is grounded, and the first coupling capacitor is connected to the first coupling capacitor.
  • the high-level p-type signal output terminal is electrically connected to the junction of the third resistor and the fifth resistor
  • the third coupling capacitor is connected in parallel to the seventh resistor
  • the The low-level p-type signal output terminal is electrically connected to the junction of the seventh resistor and the ninth resistor
  • the p port is electrically connected to the junction of the fifth resistor and the seventh resistor;
  • the n-type signal conversion unit includes a second coupling capacitor, a fourth coupling capacitor and a fourth resistor, a sixth resistor, an eighth resistor and a tenth resistor connected in series in sequence, one end of the fourth coupling capacitor is connected to the first The other end of the voltage dividing resistor is electrically connected, the tenth resistor is electrically connected to one end of the second voltage dividing resistor, the second coupling capacitor is connected in parallel with the sixth resistor, and the high-level n-type signal
  • the output terminal is electrically connected to the junction of the fourth resistor and the sixth resistor, the fourth coupling capacitor is connected in parallel with the eighth resistor, and the low-level n-type signal output terminal is connected to the eighth resistor.
  • the resistor is electrically connected to the junction of the tenth resistor, and the n port is electrically connected to the junction of the sixth resistor and the eighth resistor.
  • the level conversion module includes a first inverter, a second inverter, a first feedback component, and a second feedback component;
  • the input end of the first inverter is electrically connected to the p-type signal output end of the amplitude amplification module, and the output end of the first inverter is formed as the n-type signal output end of the clock receiving circuit;
  • the first feedback component is configured to collect the current output by the first inverter, and feed back the collected current to the input terminal of the first inverter;
  • the input end of the second inverter is electrically connected to the n-type signal output end of the amplitude amplification module, and the output end of the second inverter is formed as the p-type signal output end of the clock receiving circuit;
  • the second feedback component is configured to collect the current output by the second inverter, and feed back the collected current to the input terminal of the second inverter.
  • the first feedback component includes a first n-type feedback transistor and a first p-type feedback transistor;
  • the gate of the first n-type feedback transistor is electrically connected to the output terminal of the first inverter, the first pole of the first n-type feedback transistor is electrically connected to the high-level signal terminal, and the first The second pole of the n-type feedback transistor is electrically connected to the input terminal of the first inverter;
  • the gate of the first p-type feedback transistor is electrically connected to the output terminal of the first inverter, the first pole of the first p-type feedback transistor is grounded, and the second pole of the first p-type feedback transistor is grounded.
  • the pole is electrically connected to the input end of the first inverter.
  • the second feedback component includes a second n-type feedback transistor and a second p-type feedback transistor;
  • the gate of the second n-type feedback transistor is electrically connected to the output end of the second inverter, the first pole of the second n-type feedback transistor is electrically connected to the high-level signal end, and the second The second pole of the n-type transistor is electrically connected to the input terminal of the second inverter;
  • the gate of the second p-type feedback transistor is electrically connected to the output terminal of the second inverter, the first pole of the second p-type feedback transistor is grounded, and the second pole of the second p-type transistor It is electrically connected with the input terminal of the second inverter.
  • an electronic device includes a clock receiving circuit and a core module, the clock signal input end of the core module is electrically connected to the output end of the clock receiving circuit, the The clock receiving circuit is the clock receiving circuit provided in the first aspect of the present disclosure.
  • the core module is any one of the following devices: an analog-to-digital converter, a digital-to-analog converter, and a phase-locked loop module.
  • the core component of the clock receiving circuit provided by the embodiment of the present disclosure is the amplitude amplification module.
  • the p-type transistor differential pair and the n-type transistor differential pair of the amplitude amplification module are mutually input and load, forming a push-pull structure, increasing The equivalent transconductance of the entire amplitude amplification module.
  • the amplitude amplifying module can provide a relatively large clock output swing under low power supply voltage.
  • the output clock establishment process of the core module of the subsequent stage is correspondingly faster, reducing or even avoiding the process of establishing the clock.
  • the noise influence of the electronic equipment makes the output phase noise of the electronic equipment smaller, reduces the power consumption of the electronic equipment, and improves the performance of the electronic equipment.
  • FIG. 1 is a schematic circuit diagram of a clock signal receiving circuit in the related art
  • FIG. 2 is a schematic diagram of an implementation manner of a clock receiving circuit provided by the present disclosure
  • FIG. 3 is a schematic diagram of an implementation manner of a common-mode voltage adjustment module in the clock receiving circuit provided by the present disclosure
  • FIG. 4 is a schematic diagram of an embodiment of an amplitude amplification module in the clock receiving circuit provided by the present disclosure
  • FIG. 5 is a schematic diagram of an implementation manner of a level conversion module in the clock receiving circuit provided by the present disclosure
  • Fig. 6 is a schematic diagram that the core module of the electronic device is a digital-to-analog converter or an analog-to-digital converter;
  • FIG. 7 is a schematic diagram of a phase-locked loop circuit as a core module of an electronic device.
  • a clock receiving circuit As one aspect of the present disclosure, a clock receiving circuit is provided. As shown in FIG. 2 , the clock receiving circuit includes a common-mode voltage adjustment module 100 , an amplitude amplification module 200 and a level conversion module 300 .
  • the common-mode voltage adjustment module 100 includes an n-type signal conversion unit 110, a high-level n-type signal output terminal von_n, a low-level n-type signal output terminal vop_n, a p-type signal conversion unit 120, a high-level p-type signal output terminal von_p, low-level p-type signal output terminal vop_p.
  • the n-type signal conversion unit 110 is configured to convert the input n-type signal into a high-level n-type signal and output it through the high-level n-type signal output terminal von_n, and the n-type signal conversion unit 110 is also used to convert the input n-type The signal is converted into a low-level n-type signal and output vop_n through the low-level n-type signal terminal.
  • the p-type signal conversion unit 120 is configured to convert the input p-type signal into a high-level p-type signal and output it through the high-level p-type signal von_p output terminal, and the p-type signal conversion unit 120 is also used to convert the input p-type The signal is converted into a low-level p-type signal and output through the low-level p-type signal output terminal vop_p.
  • the amplitude amplification module 200 includes a p-type current source transistor M6 , an n-type current source transistor M5 , a p-type transistor differential pair 210 , an n-type transistor differential pair 220 and a bias control unit 230 .
  • the bias control unit 230 is configured to control the p-type current source transistor M6 and the n-type current source transistor M6 to work in a saturation region.
  • a first pole of the p-type current source transistor M6 is electrically connected to the high-level signal terminal, and a second pole of the p-type current source transistor M6 is electrically connected to two first ends of the p-type transistor differential pair 210 .
  • the two second ends of the p-type transistor differential pair 210 are respectively electrically connected to the two first ends of the n-type transistor differential pair 220, and the two input ends of the p-type transistor differential pair 210 are respectively connected to the low-level p-type signal output end vop_p and the low-level n-type signal output terminal vop_n are electrically connected, so that the two p-type transistors in the differential pair of p-type transistors both work in the amplifying region.
  • the two second terminals of the n-type transistor differential pair 220 are electrically connected to the first pole of the n-type current source transistor M5, and the two input terminals of the n-type transistor differential pair 220 are respectively connected to the high-level p-type signal output terminal von_p, and The high-level n-type signal output terminal von_n is electrically connected, so that both n-type transistors in the differential pair of n-type transistors work in the amplification region.
  • the level conversion module 300 is configured to convert the CML level signal output by the amplitude amplification circuit into a CMOS level signal.
  • the core component of the clock receiving circuit provided in the present disclosure is the amplitude amplification module 200, and the p-type transistor differential pair 210 and the n-type transistor differential pair 220 of the amplitude amplification module 200 are mutually input and load, forming a push-pull structure.
  • the equivalent transconductance of the entire amplitude amplifying module 200 is increased, and the amplitude amplifying module 200 can provide a relatively large clock output swing under low power supply voltage.
  • the p-type transistor differential pair 210 and the n-type transistor differential pair 220 have two connection nodes, where the two connection nodes are respectively formed as the n-type signal output terminal voutn and the p-type signal output terminal of the amplitude amplification module 200 voup.
  • the main function of the common-mode voltage adjustment module 100 is to adjust the differential signal received by the clock receiving circuit, and output the transistors that can make the p-type transistor differential pair 210 and the n-type transistor differential pair 220 of the amplitude amplification module 200 work at zoom area.
  • the function of the P-type current source transistor M6 and the N-type current source transistor M5 is to provide driving current for the amplitude amplification module under the control of the bias control unit.
  • the differential pair of p-type transistors includes a first p-type transistor M4 and a second p-type transistor M3, and the first pole of the first p-type transistor M4 is connected to the second p-type transistor M3.
  • the first pole of the first p-type transistor M4 and the first pole of the second p-type transistor M3 are respectively formed as the two first ends of the p-type differential pair, and the first p-type transistor
  • the second pole of M4 and the second pole of the second p-type transistor M3 are respectively formed as the two second ends of the p-type differential pair, the gate of the first p-type transistor M4 and the gate of the second p-type transistor M3
  • the gates are respectively formed as two input terminals of the p-type transistor differential pair, the gate of the first p-type transistor M4 (vin_p in FIG.
  • the second pole of the first p-type transistor M4 is formed as the n-type signal output terminal of the amplitude amplification module 200
  • the second pole of the second p-type transistor M3 is formed as the p-type signal output terminal of the amplitude amplification module 200 output.
  • the differential pair of n-type transistors includes a first n-type crystal M2 and a second n-type transistor M1, and the first pole of the first n-type transistor M2 and the first pole of the second n-type transistor M1 are respectively Formed as the two first ends of the differential pair of n-type transistors, the first pole of the first n-type transistor M2 is electrically connected to the second pole of the first p-type transistor M4, and the first pole of the second n-type transistor M1 It is electrically connected with the second pole of the second p-type transistor M3.
  • the second pole of the first n-type transistor M2 and the second pole of the second n-type transistor M1 are respectively formed as two second ends of the n-type differential pair, and the second pole of the first n-type transistor M2 is connected to the second pole of the first n-type transistor M2.
  • the second poles of the two n-type transistors M1 are electrically connected, and both are electrically connected to the first poles of the n-type current transistor M5.
  • the gate of the first n-type transistor M2 and the gate of the second n-type transistor M1 are respectively formed as two input terminals of the differential pair of n-type transistors (in FIG. 4, respectively vin_n and vip_n), the first n
  • the gate of the second n-type transistor M2 is electrically connected to the high-level n-type signal output end
  • the gate of the second n-type transistor M1 is electrically connected to the high-level p-type signal output end.
  • the specific structure of the bias control unit 230 is not particularly limited, as long as it can provide bias for the gates of the p-type current transistor M6 and the gate of the n-type current transistor M5, so that the p-type current transistor M6 and the gates of the n-type current transistor M5 The n-type current transistor M5 only needs to work in the saturation region.
  • the bias control unit includes a first n-type current mirror transistor M9, a second n-type current mirror transistor M7, a third n-type current mirror transistor M8, a fourth n-type current mirror transistor The mirror transistor M10, the first p-type current mirror transistor M11 and the second p-type current mirror transistor M12.
  • the first pole of the first n-type current mirror transistor M9 is used to be electrically connected to the current source (the current source provides a reference circuit IREF), and the first pole of the first n-type current mirror transistor M9 is connected to the first n-type current mirror transistor M9.
  • the gate of the first n-type current mirror transistor M9 is electrically connected to the first pole of the second n-type current mirror transistor M7, and the second pole of the second n-type current mirror transistor M7 is grounded.
  • the gate of the n-type current mirror transistor M7 is electrically connected to the gate of the third n-type current mirror transistor M8 and the gate of the n-type current source transistor M5.
  • the first pole of the third n-type current mirror transistor M8 is grounded, and the second pole of the third n-type current mirror transistor M8 is electrically connected to the first pole of the fourth n-type current mirror transistor M10.
  • the second pole of the fourth n-type current mirror transistor M10 is electrically connected to the first pole of the first p-type current mirror transistor M111, and the gate of the fourth n-type current mirror transistor M10 is connected to the first n-type current mirror transistor M11.
  • the grid is electrically connected.
  • the gate of the first p-type current mirror transistor M11 is electrically connected to the first pole of the first p-type current mirror transistor M11, and the second pole of the first p-type current mirror transistor M11 is connected to the first pole of the second p-type current mirror transistor M12. One-pole electrical connection.
  • the second pole of the second p-type current mirror transistor M12 is electrically connected to the high-level signal terminal, and the gate of the second p-type current mirror transistor M12 is electrically connected to the gate of the p-type current source transistor M6.
  • the gate of the n-type current source transistor M5 is electrically connected to the gate of the second n-type current mirror transistor M7, therefore, the gate voltage of the n-type current source transistor M5 is connected to the gate voltage of the second n-type current mirror transistor M7
  • the gate voltage is the same.
  • the gate of the p-type current source transistor M6 is electrically connected to the gate of the second p-type current mirror transistor M12, therefore, the gate voltage of the p-type current source transistor M6 is connected to the gate voltage of the second p-type current mirror transistor M12. Pole voltage is the same.
  • the first n-type current mirror transistor M9 , the second n-type current mirror transistor M7 , the third n-type current mirror transistor M8 , and the fourth n-type current mirror transistor M10 form a current mirror.
  • the current of the fourth n-type current mirror transistor M10 is proportional to the current of the first n-type current mirror transistor M9, and the current received by the first p-type current mirror transistor M11 is the same as the current of the fourth n-type current mirror transistor M10 , and is proportional to the current received by the first electrode of the first n-type current mirror transistor M9.
  • the gate voltage for making the p-type current source transistor M6 work in a saturation region can be obtained.
  • the common mode voltage adjustment module also includes an impedance matching resistor R11, a first voltage dividing resistor R1 and a second voltage dividing resistor R2, and the impedance matching resistor R11 is connected to the p port of the common mode voltage adjusting module Between vip and the n-port vin, one end of the first voltage dividing resistor R1 is electrically connected to the high-level signal end.
  • the p-type signal conversion unit 120 includes a first coupling capacitor C1, a third coupling capacitor C3, and a third resistor R3, a fifth resistor R5, a seventh resistor R7 and a ninth resistor R9 connected in series in sequence.
  • One end of the third coupling capacitor C3 is electrically connected to the other end of the first voltage dividing resistor R1
  • the ninth resistor R9 is electrically connected to one end of the second voltage dividing resistor R2
  • the second end of the second voltage dividing resistor R2 is grounded.
  • the coupling capacitor C1 is connected in parallel with the fifth resistor R5, and the high-level p-type signal output terminal von_p is electrically connected with the junction of the third resistor R3 and the fifth resistor R5, the third coupling capacitor C3 is connected in parallel with the seventh resistor R7, and the low
  • the level p-type signal output terminal vop_p is electrically connected to the junction of the seventh resistor R7 and the ninth resistor R9, and the p-port vip is electrically connected to the junction of the fifth resistor R5 and the seventh resistor R7.
  • the n-type signal conversion unit 110 includes a second coupling capacitor C2, a fourth coupling capacitor C4, and a fourth resistor R4, a sixth resistor R6, an eighth resistor R8 and a tenth resistor R10 connected in series in sequence.
  • One end of the fourth coupling capacitor C4 is electrically connected to the other end of the first voltage dividing resistor R1, the tenth resistor R10 is electrically connected to one end of the second voltage dividing resistor R2, the second coupling capacitor C2 is connected in parallel with the sixth resistor R6, and the high
  • the level n-type signal output terminal von_n is electrically connected to the junction of the fourth resistor R4 and the sixth resistor R6, the fourth coupling capacitor C4 is connected in parallel with the eighth resistor R8, and the low-level n-type signal output terminal vop_n is connected to the eighth resistor R8 is electrically connected to the junction of the tenth resistor R10, and the n-port vin is electrically connected to the junction of the sixth resistor
  • the resistance chain is used to adjust the common-mode voltage, and the resistance value can be flexibly adjusted according to the application scenario, thereby changing the common-mode voltage and improving the flexibility of the circuit.
  • the specific structure of the level conversion module 300 is not specifically limited.
  • the level conversion module includes a first inverter 310 , a second inverter 320 , a first feedback component 330 , and a second feedback component 340 .
  • the input terminal vip1 of the first inverter 310 is electrically connected to the p-type signal output terminal of the amplitude amplification module 200, and the output terminal of the first inverter 310 is formed as the n-type signal output terminal voutn1 of the clock receiving circuit.
  • the first feedback component 330 is configured to collect the output signal of the first inverter 310, and feed back the collected signal to the input terminal of the first inverter 310, so as to perform an output of the first inverter 310 A rough calibration.
  • the input terminal vin1 of the second inverter 320 is electrically connected to the n-type signal output terminal of the amplitude amplification module 200, and the output terminal of the second inverter 320 is formed as the p-type signal output terminal voutn2 of the clock receiving circuit;
  • the second feedback component 340 is configured to collect the output signal of the second inverter 320, and feed back the collected signal to the input terminal of the second inverter 320, so as to perform an output of the second inverter 320.
  • a rough calibration is configured to collect the output signal of the second inverter 320, and feed back the collected signal to the input terminal of the second inverter 320, so as to perform an output of the second inverter 320.
  • the first inverter 310 includes a first p-type transistor M13 and a first n-type transistor M14.
  • the first pole of the first p-type transistor M13 is electrically connected to the high-level signal terminal
  • the gate of the first p-type transistor M13 is electrically connected to the input terminal vip1 of the first inverter 310
  • the first electrode of the first p-type transistor M13 The two poles are electrically connected to the first pole of the first n-type transistor M14, and are electrically connected to the output end of the first inverter 310, the second pole of the first n-type transistor is grounded, and the gate of the first n-type transistor is connected to the ground.
  • the input end vip1 of the first inverter 310 is electrically connected.
  • the second inverter 320 includes a second p-type transistor M15 and a second n-type transistor M16.
  • the first pole of the second p-type transistor M15 is electrically connected to the high-level signal terminal
  • the gate of the second p-type transistor M15 is electrically connected to the input terminal vin1 of the second inverter 320
  • the first electrode of the second p-type transistor M15 The two poles are electrically connected to the first pole of the second n-type transistor M16, and are electrically connected to the output terminal of the second inverter 320
  • the second pole of the second n-type transistor M16 is grounded, and the gate of the second n-type transistor M16
  • the pole is electrically connected to the input terminal vin1 of the second inverter 320 .
  • the specific structure of the first feedback component 330 is not specifically limited. As shown in FIG. 5 , the first feedback component 330 includes a first n-type feedback transistor M17 and a first p-type feedback transistor M18 .
  • the gate of the first n-type feedback transistor M17 is electrically connected to the output end of the first inverter 310, the first pole of the first n-type feedback transistor M17 is electrically connected to the high-level signal end, and the first n-type transistor M17 The second pole is electrically connected to the input terminal of the first inverter 330 .
  • the gate of the first p-type feedback transistor M18 is electrically connected to the output terminal of the first inverter 310, the first pole of the first p-type feedback transistor M18 is grounded, and the second pole of the first p-type transistor M18 is connected to the first inverter 310.
  • the input terminals of the phase converter 330 are electrically connected.
  • Both the first n-type feedback transistor M17 and the first p-type feedback transistor M18 are voltage-controlled turn-on elements, and will not generate power consumption if the turn-on condition is not met. Therefore, the first feedback component including the first n-type feedback transistor M17 and the first p-type feedback transistor M18 can reduce the overall power consumption of the clock receiving circuit.
  • the specific structure of the second feedback component 340 is not specifically limited.
  • the second feedback component 340 may include a second n-type feedback transistor M19 and a second p-type feedback transistor M20 .
  • the gate of the second n-type feedback transistor M19 is electrically connected to the output end of the second inverter 320, the first pole of the second n-type feedback transistor M19 is electrically connected to the high-level signal end, and the second n-type feedback transistor M19 The second pole of is electrically connected to the input terminal of the second inverter.
  • the gate of the second p-type feedback transistor M20 is electrically connected to the output terminal of the second inverter 320, the first pole of the second p-type feedback transistor M20 is grounded, and the second pole of the second p-type feedback transistor M20 is connected to the The input terminals of the second inverter 320 are electrically connected.
  • Both the second n-type feedback transistor M19 and the second p-type feedback transistor M29 are voltage-controlled turn-on elements, and will not generate power consumption if the turn-on condition is not met. Therefore, the first feedback component including the second n-type feedback transistor M19 and the second p-type feedback transistor M20 can reduce the overall power consumption of the clock receiving circuit.
  • Adopting the first feedback assembly 330 including the first n-type feedback transistor M17 and the first p-type feedback transistor M18 and the second feedback assembly 340 including the second n-type feedback transistor M19 and the second p-type feedback transistor M20 can not only reduce The overall power consumption, and its layout layout is simpler, and the occupied area is smaller, which can improve the overall integration of the clock receiving circuit.
  • an electronic device includes a clock receiving circuit and a core module, and a clock signal input terminal of the core module is electrically connected to an output terminal of the clock receiving circuit.
  • the output clock establishment process of the core module of the subsequent stage is correspondingly faster, reducing or even avoiding the process of establishing the clock.
  • the noise influence of the electronic equipment makes the output phase noise of the electronic equipment smaller, reduces the power consumption of the electronic equipment, and improves the performance of the electronic equipment.
  • the core module is any one of the following devices: an analog-to-digital converter, a digital-to-analog converter, and a phase-locked loop module.
  • Figure 6 shows the case where the core module is a digital-to-analog converter or an analog-to-digital converter
  • Figure 7 shows the case where the core module is a phase-locked loop module.

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Abstract

本公开提供一种时钟接收电路，时钟接收电路包括共模电压调整模块、幅值放大模块和电平转换模块。共模电压调整模块包括n型信号转换单元、高电平n型信号输出端、低电平n型信号输出端、p型信号转换单元、高电平p型信号输出端、低电平p型信号输出端，幅值放大模块包括p型电流源晶体管、n型电流源晶体管、p型晶体管差分对、n型晶体管差分对和偏置控制单元；p型晶体管差分对的两个第二端分别与n型晶体管差分对的两个第一端电连接；n型晶体管差分对的两个第二端与n型电流源晶体管的第一极电连接；电平转换模块用于将幅值放大电路输出的CML电平信号转换为CMOS电平信号。本公开还提供一种包括上述时钟接收电路的电子设备。

Description

时钟接收电路和电子设备
相关申请的交叉引用
本公开要求在2021年6月30日提交国家知识产权局、申请号为202110738327.9、发明名称为“时钟接收电路和电子设备”的中国专利申请的优先权，该申请的全部内容通过引用结合在本公开中。
技术领域
本公开的实施例涉及但不限于集成电路领域，具体地，涉及一种时钟接收电路和一种包括该时钟接收电路的电子设备。
背景技术
随着CMOS制造工艺的演进和设计水平的提高，集成电路的工作频率越来越高，而高速率的时钟在传输过程中衰减更加严重，且更容易受到噪声、失配等非理想因素的干扰，造成时钟性能下降。因此，在高速电路中，时钟接收电路尤为重要。
图1中所示的是相关技术中的一种时钟接收电路，该时钟接收电路采用电流模逻辑(CML，Current Mode Logic)结构对输入时钟进行接收和放大。这种时钟接收电路的相位噪声较大、且功耗也较大。
发明内容
本公开提供一种时钟接收电路和一种包括该时钟接收电路的电子设备。
作为本公开的第一个方面，本公开的实施例提供一种时钟接收电路，所述时钟接收电路包括共模电压调整模块、幅值放大模块和电平转换模块，其中，
所述共模电压调整模块包括n型信号转换单元、高电平n型信号输出端、低电平n型信号输出端、p型信号转换单元、高电平p型信号输出端、低电平p型信号输出端，所述n型信号转换单元用于将输入的n型信号转换为高电平n型信号并通过所述高电平n型信号输出端输出，所述n型信号转换单元还用于将输入的n型信号转换为低电平n型信号并通过所述低电平n型信号输出，所述p型信号转换单元用于将输入的p型信号转换为高电平p型信号并通过高电平p型信号输出端输出，所述p型信号转换单元还用于将输入的p型信号转换为低电平p型信号并通过低电平p型信号输出端输出；
所述幅值放大模块包括p型电流源晶体管、n型电流源晶体管、p型晶体管差分对、n型晶体管差分对和偏置控制单元；
所述偏置控制单元用于控制所述p型电流源晶体管和所述n型电流源晶体管工作在饱和区；
所述p型电流源晶体管的第一极与高电平信号端电连接，所述p型电流源晶体管的第二极与所述p型晶体管差分对的两个第一端电连接；
所述p型晶体管差分对的两个第二端分别与所述n型晶体管差分对的两个第一端电连接，所述p型晶体管差分对的两个输入端分别与所述低电平p型信号输出端、以及所述低电平n型信号输出端电连接，以使得所述p型晶体管差分对中的两个p型晶体管均工作在放大区；
所述n型晶体管差分对的两个第二端与所述n型电流源晶体管的第一极电连接，所述n型晶体管差分对的两个输入端分别与所述高电平p型信号输出端、以及所述高电平n型信号输出端电连接，以使得所述n型晶体管差分对中的两个n型晶体管均工作放大区；
所述电平转换模块被配置成将所述幅值放大电路输出的CML电平信号转换为CMOS电平信号。
可选地，所述p型晶体管差分对包括第一p型晶体管和第二p型晶体管，所述第一p型晶体管的第一极与所述第二p型晶体管的第一极电连接，所述第一p型晶体管的第一极、以及所述第二p型晶体管的第一极分别形 成为所述p型差分对的两个第一端，所述第一p型晶体管的第二极、以及所述第二p型晶体管的第二极分别形成为所述p型差分对的两个第二端，所述第一p型晶体管的栅极和所述第二p型晶体管的栅极分别形成为所述p型晶体管差分对的两个输入端，所述第一p型晶体管的栅极与所述低电平n型信号输出端电连接，所述第二p型晶体管的栅极与所述低电平p型信号输出端电连接。
可选地，所述n型晶体管差分对包括第一n型晶体和第二n型晶体管，所述第一n型晶体管的第一极与所述第二n型晶体管的第一极分别形成为所述n型晶体管差分对的两个第一端，所述第一n型晶体管的第一极与所述第一p型晶体管的第二极电连接，所述第二n型晶体管的第一极与所述第二p型晶体管的第二极电连接；
所述第一n型晶体管的第二极、以及所述第二n型晶体管的第二极分别形成为所述n型差分对的两个第二端，所述第一n型晶体管的第二极与所述第二n型晶体管的第二极电连接；
所述第一n型晶体管的栅极和所述第二n型晶体管的栅极分别形成为所述n型晶体管差分对的两个输入端，所述第一n型晶体管的栅极与所述高电平n型信号输出端电连接，所述第二n型晶体管的栅极与所述高电平p型信号输出端电连接。
可选地，所述偏置控制单元包括第一n型电流镜晶体管、第二n型电流镜晶体管、第三n型电流镜晶体管、第四n型电流镜晶体管、第一p型电流镜晶体管和第二p型电流镜晶体管；
所述第一n型电流镜晶体管的第一极被构造成与电流源电连接，所述第一n型电流镜晶体管的第一极与所述第一n型电流镜晶体管的栅极电连接，所述第一n型电流镜晶体管的第二极与所述第二n型电流镜晶体管的第一极电连接，所述第二n型电流镜晶体管的第二极接地，所述第二n型电流镜晶体管的栅极与所述第三n型电流镜晶体管的栅极、以及所述n型电流源晶体管的栅极电连接；
所述第三n型电流镜晶体管的第一极接地，所述第三n型电流镜晶体 管的第二极与所述第四n型电流镜晶体管的第一极电连接；
所述第四n型电流镜晶体管的第二极与所述第一p型电流镜晶体管的第一极电连接，所述第四n型电流镜晶体管的栅极与所述第一n型电流镜晶体管的栅极电连接；
所述第一p型电流镜晶体管的栅极与所述第一p型电流镜晶体管的第一极电连接，所述第一p型电流镜晶体管的第二极与所述第二p型电流镜晶体管的第一极电连接；
所述第二p型电流镜晶体管的第二极被构造成与高电平信号端电连接，所述第二p型电流镜晶体管的栅极与所述p型电流源晶体管的栅极电连接。
可选地，所述共模电压调整模块还包括阻抗匹配电阻、第一分压电阻和第二分压电阻，所述阻抗匹配电阻连接在所述共模电压调整模块的p端口和n端口之间，所述第一分压电阻的一端与高电平信号端电连接；
所述p型信号转换单元包括第一耦合电容、第三耦合电容和依次串联的第三电阻、第五电阻、第七电阻和第九电阻，所述第三耦合电容的一端与所述第一分压电阻的另一端电连接，所述第九电阻与所述第二分压电阻的一端电连接，所述第二分压电阻的第二端接地，所述第一耦合电容与所述第五电阻并联，且所述高电平p型信号输出端与所述第三电阻以及所述第五电阻的连接处电连接，所述第三耦合电容与所述第七电阻并联，且所述低电平p型信号输出端与所述第七电阻和所述第九电阻的连接处电连接，所述p端口与所述第五电阻和所述第七电阻的连接处电连接；
所述n型信号转换单元包括第二耦合电容、第四耦合电容和依次串联的第四电阻、第六电阻、第八电阻和第十电阻，所述第四耦合电容的一端与所述第一分压电阻的另一端电连接，所述第十电阻与所述第二分压电阻的一端电连接，所述第二耦合电容与所述第六电阻并联，且所述高电平n型信号输出端与所述第四电阻以及所述第六电阻的连接处电连接，所述第四耦合电容与所述第八电阻并联，且所述低电平n型信号输出端与所述第八电阻和所述第十电阻的连接处电连接，所述n端口与所述第六电阻和所述第八电阻的连接处电连接。
可选地，所述电平转换模块包括第一反相器、第二反相器、第一反馈组件、第二反馈组件；
所述第一反相器的输入端与所述幅值放大模块的p型信号输出端电连接，所述第一反相器的输出端形成为所述时钟接收电路的n型信号输出端；
所述第一反馈组件被构造成采集所述第一反相器输出的电流，并将采集到的电流反馈至所述第一反相器的输入端；
所述第二反相器的输入端与所述幅值放大模块的n型信号输出端电连接，所述第二反相器的输出端形成为所述时钟接收电路的p型信号输出端；
所述第二反馈组件被构造成采集所述第二反相器输出的电流，并将采集到的电流反馈至所述第二反相器的输入端。
可选地，所述第一反馈组件包括第一n型反馈晶体管和第一p型反馈晶体管；
所述第一n型反馈晶体管的栅极与所述第一反相器的输出端电连接，所述第一n型反馈晶体管的第一极与高电平信号端电连接，所述第一n型反馈晶体管的第二极与所述第一反相器的输入端电连接；
所述第一p型反馈晶体管的栅极与所述第一反相器的输出端电连接，所述第一p型反馈晶体管的第一极接地，所述第一p型反馈晶体管的第二极与所述第一反相器的输入端电连接。
可选地，所述第二反馈组件包括第二n型反馈晶体管和第二p型反馈晶体管；
所述第二n型反馈晶体管的栅极与所述第二反相器的输出端电连接，所述第二n型反馈晶体管的第一极与高电平信号端电连接，所述第二n型晶体管的第二极与所述第二反相器的输入端电连接；
所述第二p型反馈晶体管的栅极与所述第二反相器的输出端电连接，所述第二p型反馈晶体管的第一极接地，所述第二p型晶体管的第二极与所述第二反相器的输入端电连接。
作为本公开的第二个方面，提供一种电子设备，所述电子设备包括时钟接收电路和核心模块，所述核心模块的时钟信号输入端与所述时钟接收电路的输出端电连接，所述时钟接收电路为本公开第一个方面所提供的时钟接收电路。
可选地，所述核心模块为以下设备中的任意一者：模数转换器、数模转换器、锁相环模块。
本公开实施例所提供的时钟接收电路的核心部件为幅值放大模块，该幅值放大模块的p型晶体管差分对和n型晶体管差分对互为输入和负载，构成了推挽结构，增加了整个幅值放大模块的等效跨导。该幅值放大模块能够在低电源电压下提供相对较大的时钟输出摆幅。
由于所述时钟接收电路可以在低电源电压下提供足够的增益，获得较大的输出摆幅，后级的核心模块的输出时钟建立过程也相应较快，减轻甚至避免了建立时钟的过程中受到的噪声影响，使得电子设备的输出相位噪声较小、降低了电子设备功耗，并提高了电子设备的性能。
附图说明
图1是相关技术中的时钟信号接收电路的电路示意图；
图2是本公开所提供的时钟接收电路的一种实施方式的示意图；
图3是本公开所提供的时钟接收电路中，共模电压调整模块的一种实施方式的示意图；
图4是本公开所提供的时钟接收电路中，幅值放大模块的一种实施方式的示意图；
图5是本公开所提供的时钟接收电路中，电平转换模块的一种实施方式的示意图；
图6是电子设备的核心模块为数模转换器或者模数转换器的示意图；
图7是电子设备的核心模块为锁相环电路的示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的时钟接收电路和电子设备进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
作为本公开的一个方面，提供一种时钟接收电路，如图2所示，所述时钟接收电路包括共模电压调整模块100、幅值放大模块200和电平转换模块300。
如图3所示，共模电压调整模块100包括n型信号转换单元110、高电平n型信号输出端von_n、低电平n型信号输出端vop_n、p型信号转换单元120、高电平p型信号输出端von_p、低电平p型信号输出端vop_p。
n型信号转换单元110被配置为将输入的n型信号转换为高电平n型信号并通过高电平n型信号输出端von_n输出，n型信号转换单元110还用于将输入的n型信号转换为低电平n型信号并通过低电平n型信号端输出vop_n。
p型信号转换单元120被配置为将输入的p型信号转换为高电平p型信号并通过高电平p型信号von_p输出端输出，p型信号转换单元120还用于将输入的p型信号转换为低电平p型信号并通过低电平p型信号输出端vop_p输出。
幅值放大模块200包括p型电流源晶体管M6、n型电流源晶体管M5、p型晶体管差分对210、n型晶体管差分对220和偏置控制单元230。
偏置控制单元230被配置为控制p型电流源晶体管M6和n型电流源晶体管M6工作在饱和区。
p型电流源晶体管M6的第一极与高电平信号端电连接，p型电流源晶体管M6的第二极与p型晶体管差分对210的两个第一端电连接。
p型晶体管差分对210的两个第二端分别与n型晶体管差分对220的两个第一端电连接，p型晶体管差分对210的两个输入端分别与低电平p型信号输出端vop_p、以及低电平n型信号输出端vop_n电连接，以使得所述p型晶体管差分对中的两个p型晶体管均工作在放大区。
n型晶体管差分对220的两个第二端与n型电流源晶体管M5的第一极电连接，n型晶体管差分对220的两个输入端分别与高电平p型信号输出端von_p、以及高电平n型信号输出端von_n电连接，以使得所述n型晶体管差分对中的两个n型晶体管均工作放大区。
电平转换模块300被配置为将所述幅值放大电路输出的CML电平信号转换为CMOS电平信号。
本公开所提供的时钟接收电路的核心部件为幅值放大模块200，该幅值放大模块200的p型晶体管差分对210和n型晶体管差分对220互为输入和负载，构成了推挽结构，增加了整个幅值放大模块200的等效跨导，该幅值放大模块200能够在低电源电压下提供相对较大的时钟输出摆幅。 需要指出的是，p型晶体管差分对210和n型晶体管差分对220具有两个连接节点，这里两个连接节点分别形成为幅值放大模块200的n型信号输出端voutn和p型信号输出端voup。
共模电压调整模块100的主要作用是对该时钟接收电路接收到的差分信号进行调整，并输出能够使得幅值放大模块200的p型晶体管差分对210和n型晶体管差分对220的晶体管工作在放大区。
P型电流源晶体管M6和N型电流源晶体管M5的作用是在偏置控制单元的控制下，为幅值放大模块提供驱动电流。
在本公开中，对p型晶体管差分对的具体结构不做特殊的限定。在图4中所示的实施方式中，所述p型晶体管差分对包括第一p型晶体管M4和第二p型晶体管M3，第一p型晶体管M4的第一极与第二p型晶体管M3的第一极电连接，第一p型晶体管M4的第一极、以及第二p型晶体管M3的第一极分别形成为所述p型差分对的两个第一端，第一p型晶体管M4的第二极、以及第二p型晶体管M3的第二极分别形成为所述p型差分对的两个第二端，第一p型晶体管M4的栅极和第二p型晶体管M3的栅极分别形成为所述p型晶体管差分对的两个输入端，第一p型晶体管M4的栅极(在图4中为vin_p)与低电平n型信号输出端vop_p电连接，第二p型晶体管M3的栅极(在图4中为vip_p)与低电平p型信号输出端电连接。
需要指出的是，第一p型晶体管M4的第二极形成为幅值放大模块200的n型信号输出端，第二p型晶体管M3的第二极形成为幅值放大模块200的p型信号输出端。
在本公开中，对n型晶体管差分对的具体结构也不做特殊的限定。如图4所示，所述n型晶体管差分对包括第一n型晶体M2和第二n型晶体管M1，第一n型晶体管M2的第一极与第二n型晶体管M1的第一极分别形成为所述n型晶体管差分对的两个第一端，第一n型晶体管M2的第一极与第一p型晶体管M4的第二极电连接，第二n型晶体管M1的第一极与第二p型晶体管M3的第二极电连接。
第一n型晶体管M2的第二极、以及第二n型晶体管M1的第二极分别形成为所述n型差分对的两个第二端，第一n型晶体管M2的第二极与第二n型晶体管M1的第二极电连接，且均与n型电流晶体管M5的第一极电连接。
第一n型晶体管M2的栅极和第二n型晶体管M1的栅极分别形成为所述n型晶体管差分对的两个输入端(在图4中，分别为vin_n和vip_n)，第一n型晶体管M2的栅极与所述高电平n型信号输出端电连接，第二n型晶体管M1的栅极与所述高电平p型信号输出端电连接。
在本公开中，对偏置控制单元230的具体结构不做特殊的限定，只要能够为p型电流晶体管M6、以及n型电流晶体管M5的栅极提供偏置、使p型电流晶体管M6、以及n型电流晶体管M5工作在饱和区即可。
在图4中所示的实施方式中，所述偏置控制单元包括第一n型电流镜晶体管M9、第二n型电流镜晶体管M7、第三n型电流镜晶体管M8、第四n型电流镜晶体管M10、第一p型电流镜晶体管M11和第二p型电流镜晶体管M12。
第一n型电流镜晶体管M9的第一极用于与电流源(该电流源提供参考电路IREF)电连接，第一n型电流镜晶体管M9的第一极与第一n型电流镜晶体管M9的栅极电连接，第一n型电流镜晶体管M9的第二极与第二n型电流镜晶体管M7的第一极电连接，第二n型电流镜晶体管M7的第二极接地，第二n型电流镜晶体管M7的栅极与第三n型电流镜晶体管M8的栅极、以及n型电流源晶体管M5的栅极电连接。
第三n型电流镜晶体管M8的第一极接地，第三n型电流镜晶体管M8的第二极与第四n型电流镜晶体管M10的第一极电连接。
第四n型电流镜晶体管M10的第二极与所述第一p型电流镜晶体管M111的第一极电连接，第四n型电流镜晶体管M10的栅极与第一n型电流镜晶体管M11的栅极电连接。
第一p型电流镜晶体管M11的栅极与第一p型电流镜晶体管M11的第一极电连接，第一p型电流镜晶体管M11的第二极与第二p型电流镜晶 体管M12的第一极电连接。
第二p型电流镜晶体管M12的第二极用于与高电平信号端电连接，第二p型电流镜晶体管M12的栅极与p型电流源晶体管M6的栅极电连接。
在本公开中，n型电流源晶体管M5的栅极与第二n型电流镜晶体管M7的栅极电连接，因此，n型电流源晶体管M5的栅极电压与第二n型电流镜晶体管M7的栅极电压相同。通过控制第一n型电流镜晶体管M5和第二n型电流镜晶体管M7的尺寸，可以获得使的n型电流源晶体管M5工作在饱和区的栅极电压。
同样地，p型电流源晶体管M6的栅极与第二p型电流镜晶体管M12的栅极电连接，因此，p型电流源晶体管M6的栅极电压与第二p型电流镜晶体管M12的栅极电压相同。在本公开中，第一n型电流镜晶体管M9、第二n型电流镜晶体管M7、第三n型电流镜晶体管M8、第四n型电流镜晶体管M10组成一个电流镜。因此，第四n型电流镜晶体管M10的电流与第一n型电流镜晶体管M9的电流成比例，第一p型电流镜晶体管M11接收到的电流与第四n型电流镜晶体管M10的电流相同，并与第一n型电流镜晶体管M9的第一极接收到的电流成比例相同。通过控制第一p型电流镜晶体管M11和第二p型电流镜晶体管M12的尺寸，可以获得使得p型电流源晶体管M6工作在饱和区的栅极电压。
在本公开中，对共模电压调整模块100的具体结构不做特殊的限定。如图3所示，所述共模电压调整模块还包括阻抗匹配电阻R11、第一分压电阻R1和第二分压电阻R2，阻抗匹配电阻连接R11在所述共模电压调整模块的p端口vip和n端口vin之间，第一分压电阻R1的一端与高电平信号端电连接。
p型信号转换单元120包括第一耦合电容C1、第三耦合电容C3和依次串联的第三电阻R3、第五电阻R5、第七电阻R7和第九电阻R9。第三耦合电容C3的一端与第一分压电阻R1的另一端电连接，第九电阻R9与第二分压电阻R2的一端电连接，第二分压电阻R2的第二端接地，第一耦合电容C1与第五电阻R5并联，且高电平p型信号输出端von_p与第三电阻R3以及第五电阻R5的连接处电连接，第三耦合电容C3与第七电阻R7 并联，且低电平p型信号输出端vop_p与第七电阻R7和第九电阻R9的连接处电连接，p端口vip与第五电阻R5和第七电阻R7的连接处电连接。
n型信号转换单元110包括第二耦合电容C2、第四耦合电容C4和依次串联的第四电阻R4、第六电阻R6、第八电阻R8和第十电阻R10。第四耦合电容C4的一端与第一分压电阻R1的另一端电连接，第十电阻R10与第二分压电阻R2的一端电连接，第二耦合电容C2与第六电阻R6并联，且高电平n型信号输出端von_n与第四电阻R4以及第六电阻R6的连接处电连接，第四耦合电容C4与第八电阻R8并联，且低电平n型信号输出端vop_n与第八电阻R8和第十电阻R10的连接处电连接，n端口vin与第六电阻R6和第八电阻R8的连接处电连接。
在本公开中，采用电阻链进行共模电压的调整，可以根据应用场景灵活调整电阻值，进而改变共模电压，提高了电路的灵活性。
在本公开中，对电平转换模块300的具体结构不做特殊的限定。例如，如图5所示，所述电平转换模块包括第一反相器310、第二反相器320、第一反馈组件330、第二反馈组件340。
第一反相器310的输入端vip1与幅值放大模块200的p型信号输出端电连接，第一反相器310的输出端形成为所述时钟接收电路的n型信号输出端voutn1。
第一反馈组件330被配置为对第一反相器310的输出信号进行采集、并将采集到的信号反馈至第一反相器310的输入端，以对第一反相器310的输出进行一次粗校准。
第二反相器320的输入端vin1与幅值放大模块200的n型信号输出端电连接，第二反相器320的输出端形成为所述时钟接收电路的p型信号输出端voutn2；
第二反馈组件340被配置为对第二反相器320的输出信号进行采集、并将采集到的信号反馈至第二反相器320的输入端，以对第二反相器320的输出进行一次粗校准。
在图5中所示的实施方式中，第一反相器310包括第一p型晶体管 M13和第一n型晶体管M14。第一p型晶体管M13的第一极与高电平信号端电连接，第一p型晶体管M13的栅极与第一反相器310的输入端vip1电连接，第一p型晶体管M13的第二极与第一n型晶体管M14的第一极电连接，且与第一反相器310的输出端电连接，第一n型晶体管的第二极接地，第一n型晶体管的栅极与第一反相器310的输入端vip1电连接。
在图5中所示的实施方式中，第二反相器320包括第二p型晶体管M15和第二n型晶体管M16。第二p型晶体管M15的第一极与高电平信号端电连接，第二p型晶体管M15的栅极与第二反相器320的输入端vin1电连接，第二p型晶体管M15的第二极与第二n型晶体管M16的第一极电连接，且与第二反相器320的输出端电连接，第二n型晶体管M16的第二极接地，第二n型晶体管M16的栅极与第二反相器320的输入端vin1电连接。
在本公开中，对第一反馈组件330的具体结构不做特殊限定。如图5所示，第一反馈组件330包括第一n型反馈晶体管M17和第一p型反馈晶体管M18。
第一n型反馈晶体管M17的栅极与第一反相器310的输出端电连接，第一n型反馈晶体管M17的第一极与高电平信号端电连接，第一n型晶体管M17的第二极与第一反相器330的输入端电连接。
第一p型反馈晶体管M18的栅极与第一反相器310的输出端电连接，第一p型反馈晶体管M18的第一极接地，第一p型晶体管M18的第二极与第一反相器330的输入端电连接。
第一n型反馈晶体管M17和第一p型反馈晶体管M18均为电压控制导通的元件，在不满足导通条件的情况下不会产生功耗。因此，包括第一n型反馈晶体管M17和第一p型反馈晶体管M18的第一反馈组件可以降低所述时钟接收电路的总体功耗。
在本公开中，对第二反馈组件340的具体结构不做特殊限定。如图5所示，可选地，所述第二反馈组件340可以包括第二n型反馈晶体管M19和第二p型反馈晶体管M20。
第二n型反馈晶体管M19的栅极与第二反相器320的输出端电连接，第二n型反馈晶体管M19的第一极与高电平信号端电连接，第二n型反馈晶体管M19的第二极与所述第二反相器的输入端电连接。
所述第二p型反馈晶体管M20的栅极与第二反相器320的输出端电连接，第二p型反馈晶体管M20的第一极接地，第二p反馈型晶体管M20的第二极与第二反相器320的输入端电连接。
第二n型反馈晶体管M19和第二p型反馈晶体管M29均为电压控制导通的元件，在不满足导通条件的情况下不会产生功耗。因此，包括第二n型反馈晶体管M19和第二p型反馈晶体管M20的第一反馈组件可以降低所述时钟接收电路的总体功耗。
采用包括第一n型反馈晶体管M17和第一p型反馈晶体管M18的第一反馈组件330和包括第二n型反馈晶体管M19和第二p型反馈晶体管M20的第二反馈组件340，不仅可以降低总体功耗，且其版图排线更简单，占用面积更小，可以提高时钟接收电路的总体集成度。
作为本公开的第二个方面，提供一种电子设备，所述电子设备包括时钟接收电路和核心模块，该核心模块的时钟信号输入端与所述时钟接收电路的输出端电连接。
由于所述时钟接收电路可以在低电源电压下提供足够的增益，获得较大的输出摆幅，后级的核心模块的输出时钟建立过程也相应较快，减轻甚至避免了建立时钟的过程中受到的噪声影响，使得电子设备的输出相位噪声较小、降低了电子设备功耗，并提高了电子设备的性能。
在本公开中，对核心模块不做特殊的限定。可选地，所述核心模块为以下设备中的任意一者：模数转换器、数模转换器、锁相环模块。
图6中所示的是核心模块为数模转换器或者模数转换器的情况，图7所示的是核心模块为锁相环模块的情况。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独 使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (10)

  1. 一种时钟接收电路，所述时钟接收电路包括共模电压调整模块、幅值放大模块和电平转换模块，其中
    所述共模电压调整模块包括n型信号转换单元、高电平n型信号输出端、低电平n型信号输出端、p型信号转换单元、高电平p型信号输出端、低电平p型信号输出端，所述n型信号转换单元被配置成将输入的n型信号转换为高电平n型信号并通过所述高电平n型信号输出端输出，所述n型信号转换单元还被配置成将输入的n型信号转换为低电平n型信号并通过所述低电平n型信号输出，所述p型信号转换单元被配置成将输入的p型信号转换为高电平p型信号并通过高电平p型信号输出端输出，所述p型信号转换单元还被配置成将输入的p型信号转换为低电平p型信号并通过低电平p型信号输出端输出；
    所述幅值放大模块包括p型电流源晶体管、n型电流源晶体管、p型晶体管差分对、n型晶体管差分对和偏置控制单元；
    所述偏置控制单元被配置成控制所述p型电流源晶体管和所述n型电流源晶体管工作在饱和区；
    所述p型电流源晶体管的第一极与高电平信号端电连接，所述p型电流源晶体管的第二极与所述p型晶体管差分对的两个第一端电连接；
    所述p型晶体管差分对的两个第二端分别与所述n型晶体管差分对的两个第一端电连接，所述p型晶体管差分对的两个输入端分别与所述低电平p型信号输出端、以及所述低电平n型信号输出端电连接，以使得所述p型晶体管差分对中的两个p型晶体管均工作在放大区；
    所述n型晶体管差分对的两个第二端与所述n型电流源晶体管的第一极电连接，所述n型晶体管差分对的两个输入端分别与所述高电平p型信号输出端、以及所述高电平n型信号输出端电连接，以使得所述n型晶体管差分对中的两个n型晶体管均工作放大区；
    所述电平转换模块被配置成将所述幅值放大电路输出的CML电平信号转换为CMOS电平信号。
  2. 根据权利要求1所述的时钟接收电路，其中，所述p型晶体管差分对包括第一p型晶体管和第二p型晶体管，所述第一p型晶体管的第一极与所述第二p型晶体管的第一极电连接，所述第一p型晶体管的第一极、以及所述第二p型晶体管的第一极分别形成为所述p型差分对的两个第一端，所述第一p型晶体管的第二极、以及所述第二p型晶体管的第二极分别形成为所述p型差分对的两个第二端，所述第一p型晶体管的栅极和所述第二p型晶体管的栅极分别形成为所述p型晶体管差分对的两个输入端，所述第一p型晶体管的栅极与所述低电平n型信号输出端电连接，所述第二p型晶体管的栅极与所述低电平p型信号输出端电连接。
  3. 根据权利要求2所述的时钟接收电路，其中，所述n型晶体管差分对包括第一n型晶体和第二n型晶体管，所述第一n型晶体管的第一极与所述第二n型晶体管的第一极分别形成为所述n型晶体管差分对的两个第一端，所述第一n型晶体管的第一极与所述第一p型晶体管的第二极电连接，所述第二n型晶体管的第一极与所述第二p型晶体管的第二极电连接；
    所述第一n型晶体管的第二极、以及所述第二n型晶体管的第二极分别形成为所述n型差分对的两个第二端，所述第一n型晶体管的第二极与所述第二n型晶体管的第二极电连接；
    所述第一n型晶体管的栅极和所述第二n型晶体管的栅极分别形成为所述n型晶体管差分对的两个输入端，所述第一n型晶体管的栅极与所述高电平n型信号输出端电连接，所述第二n型晶体管的栅极与所述高电平p型信号输出端电连接。
  4. 根据权利要求1至3中任意一项所述的时钟接收电路，其中，所述偏置控制单元包括第一n型电流镜晶体管、第二n型电流镜晶体管、第三n型电流镜晶体管、第四n型电流镜晶体管、第一p型电流镜晶体管和 第二p型电流镜晶体管；
    所述第一n型电流镜晶体管的第一极被构造成与电流源电连接，所述第一n型电流镜晶体管的第一极与所述第一n型电流镜晶体管的栅极电连接，所述第一n型电流镜晶体管的第二极与所述第二n型电流镜晶体管的第一极电连接，所述第二n型电流镜晶体管的第二极接地，所述第二n型电流镜晶体管的栅极与所述第三n型电流镜晶体管的栅极、以及所述n型电流源晶体管的栅极电连接；
    所述第三n型电流镜晶体管的第一极接地，所述第三n型电流镜晶体管的第二极与所述第四n型电流镜晶体管的第一极电连接；
    所述第四n型电流镜晶体管的第二极与所述第一p型电流镜晶体管的第一极电连接，所述第四n型电流镜晶体管的栅极与所述第一n型电流镜晶体管的栅极电连接；
    所述第一p型电流镜晶体管的栅极与所述第一p型电流镜晶体管的第一极电连接，所述第一p型电流镜晶体管的第二极与所述第二p型电流镜晶体管的第一极电连接；
    所述第二p型电流镜晶体管的第二极被构造成与高电平信号端电连接，所述第二p型电流镜晶体管的栅极与所述p型电流源晶体管的栅极电连接。
  5. 根据权利要求1至3中任意一项所述的时钟接收电路，其中，所述共模电压调整模块还包括阻抗匹配电阻、第一分压电阻和第二分压电阻，所述阻抗匹配电阻连接在所述共模电压调整模块的p端口和n端口之间，所述第一分压电阻的一端与高电平信号端电连接；
    所述p型信号转换单元包括第一耦合电容、第三耦合电容和依次串联的第三电阻、第五电阻、第七电阻和第九电阻，所述第三耦合电容的一端与所述第一分压电阻的另一端电连接，所述第九电阻与所述第二分压电阻的一端电连接，所述第二分压电阻的第二端接地，所述第一耦合电容与所述第五电阻并联，且所述高电平p型信号输出端与所述第三电阻以及所述第五电阻的连接处电连接，所述第三耦合电容与所述第七电阻并联，且所 述低电平p型信号输出端与所述第七电阻和所述第九电阻的连接处电连接，所述p端口与所述第五电阻和所述第七电阻的连接处电连接；
    所述n型信号转换单元包括第二耦合电容、第四耦合电容和依次串联的第四电阻、第六电阻、第八电阻和第十电阻，所述第四耦合电容的一端与所述第一分压电阻的另一端电连接，所述第十电阻与所述第二分压电阻的一端电连接，所述第二耦合电容与所述第六电阻并联，且所述高电平n型信号输出端与所述第四电阻以及所述第六电阻的连接处电连接，所述第四耦合电容与所述第八电阻并联，且所述低电平n型信号输出端与所述第八电阻和所述第十电阻的连接处电连接，所述n端口与所述第六电阻和所述第八电阻的连接处电连接。
  6. 根据权利要求1至3中任意一项所述的时钟接收电路，其中，所述电平转换模块包括第一反相器、第二反相器、第一反馈组件、第二反馈组件；
    所述第一反相器的输入端与所述幅值放大模块的p型信号输出端电连接，所述第一反相器的输出端形成为所述时钟接收电路的n型信号输出端；
    所述第一反馈组件被构造成采集所述第一反相器输出的电流，并将采集到的电流反馈至所述第一反相器的输入端；
    所述第二反相器的输入端与所述幅值放大模块的n型信号输出端电连接，所述第二反相器的输出端形成为所述时钟接收电路的p型信号输出端；
    所述第二反馈组件被构造成采集所述第二反相器输出的电流，并将采集到的电流反馈至所述第二反相器的输入端。
  7. 根据权利要求6所述的时钟接收电路，其中，所述第一反馈组件包括第一n型反馈晶体管和第一p型反馈晶体管；
    所述第一n型反馈晶体管的栅极与所述第一反相器的输出端电连接，所述第一n型反馈晶体管的第一极与高电平信号端电连接，所述第一n型 反馈晶体管的第二极与所述第一反相器的输入端电连接；
    所述第一p型反馈晶体管的栅极与所述第一反相器的输出端电连接，所述第一p型反馈晶体管的第一极接地，所述第一p型反馈晶体管的第二极与所述第一反相器的输入端电连接。
  8. 根据权利要求6所述的时钟接收电路，其中，所述第二反馈组件包括第二n型反馈晶体管和第二p型反馈晶体管；
    所述第二n型反馈晶体管的栅极与所述第二反相器的输出端电连接，所述第二n型反馈晶体管的第一极与高电平信号端电连接，所述第二n型晶体管的第二极与所述第二反相器的输入端电连接；
    所述第二p型反馈晶体管的栅极与所述第二反相器的输出端电连接，所述第二p型反馈晶体管的第一极接地，所述第二p型晶体管的第二极与所述第二反相器的输入端电连接。
  9. 一种电子设备，所述电子设备包括时钟接收电路和核心模块，所述核心模块的时钟信号输入端与所述时钟接收电路的输出端电连接，所述时钟接收电路为权利要求1至8中任意一项所述的时钟接收电路。
  10. 根据权利要求9所述的电子设备，其特征在于，所述核心模块为以下设备中的任意一者：
    模数转换器、数模转换器、锁相环模块。
PCT/CN2022/078778 2021-06-30 2022-03-02 时钟接收电路和电子设备 WO2023273377A1 (zh)

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