WO2023246410A1 - 一种模数转换电路、控制方法、芯片及电子设备 - Google Patents

一种模数转换电路、控制方法、芯片及电子设备 Download PDF

Info

Publication number
WO2023246410A1
WO2023246410A1 PCT/CN2023/096038 CN2023096038W WO2023246410A1 WO 2023246410 A1 WO2023246410 A1 WO 2023246410A1 CN 2023096038 W CN2023096038 W CN 2023096038W WO 2023246410 A1 WO2023246410 A1 WO 2023246410A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital
analog
conversion
module
digital signal
Prior art date
Application number
PCT/CN2023/096038
Other languages
English (en)
French (fr)
Inventor
席望
Original Assignee
西安芯海微电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 西安芯海微电子科技有限公司 filed Critical 西安芯海微电子科技有限公司
Publication of WO2023246410A1 publication Critical patent/WO2023246410A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values

Definitions

  • the present application relates to the field of electronic technology, and in particular to an analog-to-digital conversion circuit, a control method, a chip and an electronic device.
  • ADC Analog Digital Convertor
  • ADC Analog Digital Convertor
  • quantization is generally implemented based on a reference voltage signal.
  • noise and interference in the reference voltage signal, it may cause errors in the quantization results and reduce the conversion accuracy of the ADC.
  • embodiments of the present application provide an analog-to-digital conversion circuit, a control method, a chip and an electronic device, which can improve the conversion accuracy of the analog-to-digital conversion circuit.
  • the technical solution is as follows:
  • an analog-to-digital conversion circuit includes a main digital-to-analog conversion module, an auxiliary digital-to-analog conversion module, a comparison module and a logic module, wherein the auxiliary digital-to-analog conversion module The same circuit type as the main digital-to-analog conversion module;
  • the main digital-to-analog conversion module is configured to receive an input signal, convert the input signal based on a reference voltage signal, and obtain a first conversion voltage;
  • the auxiliary digital-to-analog conversion module is configured to receive a reference digital signal, process the reference digital signal based on the reference voltage signal, and obtain a second conversion voltage;
  • the comparison module and the logic module are configured to determine a target digital signal code value based on the first conversion voltage and the second conversion voltage, and the target digital signal code value is the conversion result of the input signal. .
  • the analog-to-digital conversion circuit includes a main digital-to-analog conversion module, an auxiliary digital-to-analog conversion module, a comparison module and a logic module, wherein the auxiliary
  • the digital-to-analog conversion module has the same circuit type as the main digital-to-analog conversion module, and the method includes:
  • the input signal is converted based on a reference voltage signal to obtain a first conversion voltage
  • the reference digital signal is processed based on the reference voltage signal to obtain a second conversion voltage
  • a target digital signal code value is determined based on the first conversion voltage and the second conversion voltage, and the target digital signal code value is the conversion result of the input signal.
  • a chip which chip includes the above-mentioned analog-to-digital conversion circuit.
  • an electronic device which electronic device includes the above-mentioned analog-to-digital conversion circuit.
  • the analog-to-digital conversion circuit may include an auxiliary digital-to-analog conversion module for canceling interference.
  • the reference digital signal is converted into a corresponding second conversion voltage through the auxiliary digital-to-analog conversion module, and the input signal is converted through the main digital-to-analog conversion module. is the corresponding first conversion voltage.
  • the crosstalk generated by the reference voltage signal in the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module is similar, so the second conversion voltage can be used to A conversion voltage is used for compensation to offset the noise or interference of the reference voltage signal in the first conversion voltage, thereby improving the accuracy in the process of determining the digital signal value by the comparison module and the logic module, and improving the conversion accuracy of the analog-to-digital conversion circuit.
  • Figure 1 shows a schematic diagram of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application
  • Figure 2 shows a schematic diagram of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application
  • Figure 3 shows a schematic diagram of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application
  • Figure 4 shows a flow chart of a control method of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application
  • Figure 5 shows a schematic diagram of the analog-to-digital conversion workflow provided according to an exemplary embodiment of the present application
  • Figure 6 shows a schematic diagram of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application.
  • Main digital-to-analog conversion module 11. First main digital-to-analog conversion module; 12. Second main digital-to-analog conversion module; 2. Auxiliary digital-to-analog conversion module; 21. First auxiliary digital-to-analog conversion module; 22. Second Auxiliary digital-to-analog conversion module; 3. Comparison module; 4. logic module.
  • the term “include” and its variations are open-ended, ie, “including but not limited to.”
  • the term “based on” means “based at least in part on.”
  • the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one additional embodiment”; and the term “some embodiments” means “at least some embodiments”.
  • Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as “first” and “second” mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units. Or interdependence.
  • the embodiment of the present application provides an analog-to-digital conversion circuit.
  • the analog-to-digital conversion circuit can be integrated in a chip or provided in an electronic device.
  • the analog-to-digital conversion circuit may include a main digital-to-analog conversion module 1, an auxiliary digital-to-analog conversion module 2, a comparison module 3 and a logic module 4, wherein the main digital-to-analog conversion module 1 and the auxiliary digital-to-analog conversion module 2 are respectively connected to the comparison module 3 input terminal.
  • the circuit structure can be as follows:
  • the first input end of the main digital-to-analog conversion module 1 is set to receive the input signal, the second input end is set to receive the reference voltage signal, the third input end is set to receive the digital signal code value fed back by the logic module 4, and the output end is connected to the comparison module 3's first input connection.
  • the first input terminal of the auxiliary digital-to-analog conversion module 2 is configured to receive the reference voltage signal, the second input terminal is configured to receive the reference digital signal, and the output terminal is connected to the second input terminal of the comparison module 3 .
  • the first input terminal of the comparison module 3 is connected to the output terminal of the main digital-to-analog conversion module 1 , the second input terminal is connected to the output terminal of the auxiliary digital-to-analog conversion module 2 , and the output terminal is connected to the input terminal of the logic module 4 .
  • the input end of the logic module 4 is connected to the output end of the comparison module 3, and the corresponding digital signal code value can be fed back to the main digital-to-analog conversion module 1 during the conversion process. After a conversion cycle, the final digital signal code value can be output ,also That is, the target digital signal code value of the current conversion cycle.
  • the main digital-to-analog conversion module 1 may include a first main digital-to-analog conversion module 11 and a second main digital-to-analog conversion module 12.
  • the digital-to-analog conversion module 2 may include a first auxiliary digital-to-analog conversion module 21 and a second auxiliary digital-to-analog conversion module 22, and the circuit structure may be as follows:
  • the first input terminal of the first main digital-to-analog conversion module 11 is configured to receive the first signal of the input signal
  • the second input terminal is configured to receive the reference voltage signal
  • the third input terminal is configured to receive the first digital signal fed back by the logic module 4
  • the output terminal of the number value is connected to the first input terminal of the comparison module 3.
  • the first digital signal code value is used to quantize the above-mentioned first signal.
  • the first input terminal of the first auxiliary digital-to-analog conversion module 21 is configured to receive the reference voltage signal, the second input terminal is configured to receive the corresponding reference digital signal, and the output terminal is connected to the second input terminal of the comparison module 3 .
  • the first input terminal of the second main digital-to-analog conversion module 12 is configured to receive the second signal of the input signal, the second input terminal is configured to receive the reference voltage signal, and the third input terminal is configured to receive the second digital signal fed back by the logic module 4
  • the output terminal of the number value is connected to the second input terminal of the comparison module 3.
  • the second digital signal code value is used to quantize the above-mentioned second signal.
  • the first input terminal of the second auxiliary digital-to-analog conversion module 22 is configured to receive the reference voltage signal, the second input terminal is configured to receive the corresponding reference digital signal, and the output terminal is connected to the first input terminal of the comparison module 3 .
  • the output terminal of the comparison module 3 is connected to the input terminal of the logic module 4 .
  • the main digital-to-analog conversion module 1 and the auxiliary digital-to-analog conversion module 2 have the same circuit type and the same or similar circuit structure. On this basis, it can be ensured that the conversion voltages output by the two are unified, that is, when the same digital signal is input When the number value is specified, the same or similar conversion voltage can be output.
  • the circuit structure of the digital-to-analog conversion module is adapted to the input digital signal code value.
  • the main digital-to-analog conversion module 1 and the auxiliary digital-to-analog conversion can be the same; when the reference digital signal and the digital signal value output by the analog-to-digital conversion circuit have different number of digits, the main digital-to-analog conversion module 1 and the auxiliary digital-to-analog conversion module 2 can belong to the same circuit type, using Suitable for circuit structures with different digits.
  • the main digital-to-analog conversion module 1 can adopt a circuit type such as capacitive type, resistive type or capacitor-resistive type
  • the auxiliary digital-to-analog conversion module 2 adopts the same circuit type as the main digital-to-analog conversion module, that is, the main digital-to-analog conversion module Module 1 and the auxiliary digital-to-analog conversion module 2 are both capacitive digital-to-analog conversion circuits, or both are resistive digital-to-analog conversion circuits, or both are capacitive-resistive digital-to-analog conversion circuits, etc.
  • the main digital-to-analog conversion module 1 is a capacitive digital-to-analog conversion circuit
  • the auxiliary digital-to-analog conversion module 2 is also a capacitive digital-to-analog conversion circuit.
  • the circuit structure of the main digital-to-analog conversion module 1 and the auxiliary digital-to-analog conversion module 2 is the same, and both can include a 12-bit capacitor array; if the number of digits of the digital signal value output by the analog-to-digital conversion circuit is 12 , the number of digits of the reference digital signal is 6, then the main number
  • the analog-to-analog conversion module 1 may include a 12-bit capacitor array
  • the auxiliary digital-to-analog conversion module 2 may include a 6-bit capacitor array.
  • the analog-to-digital conversion circuit may be a successive approximation analog-to-digital conversion circuit (SAR ADC, Successive Approximation Register Analog-to-Digital Converter), Among them, DAC (Digital-to-Analog Converter, analog-to-digital converter) corresponds to the above-mentioned main digital-to-analog conversion module 1, and auxDAC (Auxiliary Digital-to-Analog Converter, auxiliary analog-to-digital converter) corresponds to the above-mentioned auxiliary digital-to-analog conversion module 2.
  • the comparator CMP corresponds to the above-mentioned comparison module 3
  • the logic circuit Logic corresponds to the above-mentioned logic module 4.
  • two switches sw connected in series can be set between the two input terminals of the comparator CMP, and the common mode signal Vcm is connected between the two switches.
  • the two switches sw are turned on and the common mode signal Vcm is connected to the main digital-to-analog conversion module and the auxiliary digital-to-analog conversion module; during the conversion period, the two switches sw are turned off.
  • the analog-to-digital conversion circuit can also be a hybrid structure ADC based on SAR ADC and other ADCs, such as Pipeline-SAR ADC (a combination of pipeline type and successive approximation type), Incremental-SAR ADC (a combination of incremental type and successive approximation type) ), Delta-Sigma-SAR ADC (combination of ⁇ - ⁇ type and successive approximation type), Flash-SAR ADC (combination of parallel comparison type and successive approximation type), etc.
  • Pipeline-SAR ADC a combination of pipeline type and successive approximation type
  • Incremental-SAR ADC a combination of incremental type and successive approximation type
  • Delta-Sigma-SAR ADC combination of ⁇ - ⁇ type and successive approximation type
  • Flash-SAR ADC combination of parallel comparison type and successive approximation type
  • Step 401 Obtain the input signal.
  • the input signal is an analog signal.
  • the input end of the analog-to-digital conversion circuit can receive a corresponding input signal, so that the analog-to-digital conversion circuit can convert the input signal into a corresponding target number in each conversion cycle. signal, and after the end of a conversion cycle, the corresponding target digital signal code value is output.
  • the analog-to-digital conversion circuit is a 12-bit SAR ADC
  • the input signal can be converted into a 12-bit digital signal in each conversion cycle and the corresponding 12-bit digital signal value can be output.
  • the input signal can be a single-ended signal or a differential signal.
  • the analog-to-digital conversion circuit can adopt a circuit structure suitable for single-ended signals, or a circuit structure suitable for differential signals, or a circuit structure suitable for both single-ended signals and differential signals. This embodiment does not limit this.
  • Step 402 Obtain the reference digital signal.
  • the role of the reference digital signal in the auxiliary digital-to-analog conversion module is the same as the role of the digital signal value in the main digital-to-analog conversion module, that is, it is converted into an analog voltage through the digital-to-analog conversion module. Since the circuit types of the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module are the same, and the module input includes both reference voltage signals and digital signals, on this basis, the second conversion voltage (output by the auxiliary digital-to-analog conversion module) can carry The noise or interference of equal or similar reference voltage signals present in the first conversion voltage (output by the main digital-to-analog conversion module) can be achieved in the subsequent conversion process. mutually canceling effects.
  • this embodiment provides different ways of obtaining the reference digital signal.
  • the analog-to-digital conversion method provided in this embodiment may include multiple conversion cycles. The following will take one conversion cycle as an example to introduce the method of obtaining a reference digital signal for this conversion cycle.
  • Method 1 Determine the reference digital signal to be the first preset value.
  • the first preset value can be set based on the digital signal code value determined by the analog-to-digital conversion circuit for the same or similar input signal, so that the reference digital signal can meet the regularity, voltage, etc. of the input signal. scope and other properties.
  • the reference digital signal obtained in this way is fixed, which can reduce the difficulty of circuit design and improve the stability of the auxiliary digital-to-analog conversion module.
  • Method 2 In the current conversion cycle, determine the reference digital signal based on the target digital signal code value of the previous conversion cycle.
  • the target digital signal code value output by the logic module in the previous conversion cycle can be fed back to the auxiliary digital-to-analog conversion module, and the reference digital signal can be processed along with the target digital signal code value in the previous conversion cycle. Adjustment.
  • This method is suitable for applications where the input signal bandwidth is small or channels are not cut.
  • the second method can have the following two situations:
  • Case 1 If the number of bits i of the reference digital signal is equal to the number of bits n of the target digital signal code value of the previous conversion cycle, then the reference digital signal is determined to be the target digital signal code value of the previous conversion cycle;
  • Case 2 If the number of bits i of the reference digital signal is less than the number of bits n of the target digital signal code value in the previous conversion cycle, then the reference digital signal is determined to be the high i-bit of the target digital signal code value in the previous conversion cycle.
  • i and n are integers greater than 1.
  • the reference digital signal can be expressed as Din[i-1:0]
  • the target digital signal code value of the previous conversion cycle can be expressed as Dt -1 [n-1:0]
  • the subscript t is used to represent The current conversion cycle, correspondingly, the subscript t-1 is used to indicate the previous conversion cycle.
  • Method 3 Determine the reference digital signal based on the digital signal code value of the current conversion cycle.
  • Method 3 can include two stages:
  • a first reference digital signal is obtained, which is used to input the auxiliary digital-to-analog conversion module when determining the high k bits of the digital signal code value of the current conversion cycle;
  • At least one second reference digital signal is obtained based on the high k bits.
  • the second reference digital signal is used to determine the digital signal value of the current conversion cycle.
  • the remaining digits of the number value are input into the auxiliary digital-to-analog conversion module.
  • k is an integer greater than 1.
  • This method is suitable for applications where the input signal bandwidth is small or channels are not cut. It is also suitable for applications where the input signal bandwidth is large or channels are cut. Compared with the above-mentioned method 2, the scope of application is expanded.
  • the above-mentioned first reference digital signal can be determined using the above-mentioned method one or two, that is, the first reference digital signal is determined to be the second preset value, or based on the target digital signal of the previous conversion cycle.
  • the number value determines the first reference digital signal.
  • the second preset value is the same as the above-mentioned first preset value, and may be equal to the above-mentioned first preset value, or may not be equal.
  • the above second stage is executed after determining the high k bits of the digital signal code value of the current conversion cycle. That is to say, when the conversion of the high k bits of the digital signal code value is completed, the code of the currently determined high k bit part can be value as a reference digital signal.
  • a second reference digital signal can be determined.
  • the value of k is less than n, the number of bits of the digital signal code value, and equal to the number of bits, i, of the reference digital signal, then it can be determined that the second reference digital signal is the code value of the currently determined high-k bit part. If the value of k is less than n, the number of bits of the target digital signal code value, and greater than the number of bits, i, of the reference digital signal, then the second reference digital signal can be determined to be the code value of the currently determined high i-bit part.
  • the reference digital signal can be expressed as Din[i-1:0]
  • the digital signal code value of the current conversion cycle can be expressed as Dt [n-1:0]
  • the subscript t is used to represent the current conversion cycle.
  • a plurality of second reference digital signals may also be determined in the second stage.
  • the value of k is less than n, the number of digits of the digital signal code value, and equal to the number of digits of the reference digital signal, i, then it can be determined that the first and second reference digital signal is the digital signal code value of the current conversion cycle. High k bit. If the value of k is less than n, the number of bits of the digital signal code value, and greater than the number of bits, i, of the reference digital signal, then it can be determined that the first second reference digital signal is the high i-bit of the digital signal code value in the current conversion cycle. Thereafter, whenever one or more digits of the digital signal code value are determined, the latest determined One or more bits of the second reference digital signal are updated.
  • the reference digital signal can be expressed as Din[i-1:0], and the digital signal code value of the current conversion cycle can be expressed as Dt [n-1:0].
  • the number of bits of the reference digital signal i is equal to k. .
  • Step 403 In the main digital-to-analog conversion module, the input signal is converted based on the reference voltage signal to obtain the first conversion voltage.
  • the main digital-to-analog conversion module can be used to sample and hold the input signal. Then the main digital-to-analog conversion module, the comparison module and the logic module form a loop. The main digital-to-analog conversion module can be based on the reference voltage signal.
  • the intermediate digital signal code value fed back by the logic module is converted into a corresponding analog voltage, that is, the first conversion voltage.
  • the intermediate digital signal code value is the digital signal code value determined during the conversion process. Taking the SAR ADC as an example, the intermediate digital signal code value fed back by the logic module can refer to the digital signal code value determined through the principle of successive approximation in each clock cycle. Since the digital signal code value has not yet been completely determined, it has not yet been used as an analog signal.
  • the output signal of the digital conversion circuit is called the intermediate digital signal code value in this embodiment.
  • the working principle of the main digital-to-analog conversion module is introduced with reference to the analog-to-digital conversion circuit shown in Figure 3 and the analog-to-digital conversion workflow shown in Figure 5.
  • the switch sw is turned on, connecting the common mode signal Vcm to the main digital-to-analog conversion module, and the input signal is sampled and held by the DAC.
  • the two switches sw are turned off.
  • the intermediate digital signal code value D[n-1:0] can be the initial value.
  • the output voltage Vdac can be adjusted in the above manner until the end of the conversion cycle. When there is noise or interference in Vref, Vdac includes interference from the reference voltage signal Vref.
  • analog-to-digital conversion workflow and the formulas involved shown in Figure 5 are only mathematical modeling of the working principle of the analog-to-digital conversion circuit, and do not mean that the execution process and formula calculations are based on software.
  • Step 404 In the auxiliary digital-to-analog conversion module, the reference digital signal is processed based on the reference voltage signal to obtain the second conversion voltage.
  • the auxiliary digital-to-analog conversion module can convert the accessed reference digital signal into a corresponding analog voltage, that is, the second conversion voltage, based on the reference voltage signal.
  • the conversion principle is the same as that used by the main digital-to-analog conversion module to convert digital signal code values.
  • the circuit types of the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module are the same, and the inputs of the modules are similar.
  • the second conversion voltage output by the auxiliary digital-to-analog conversion module can be generated to be the same as the reference voltage signal in the main digital-to-analog conversion The same or similar crosstalk in the module, thereby canceling the interference caused by the reference voltage signal in the main digital-to-analog conversion module.
  • the second conversion voltage output by the auxiliary digital-to-analog conversion module can be fixed, and the analog-to-digital conversion circuit used in each conversion cycle
  • the second switching voltage can be the same.
  • the auxiliary digital-to-analog conversion module may be fixed, but the second conversion voltage used by the analog-to-digital conversion circuit in each conversion cycle may be adjusted according to the target digital signal code value of the previous conversion cycle.
  • the auxiliary digital-to-analog conversion module in the first stage, can convert the first reference digital signal into a second conversion voltage, and in the second stage, the auxiliary digital-to-analog conversion module can convert at least A second reference digital signal is converted into a corresponding second converted voltage. It can be seen that in one conversion cycle, the second conversion voltage can be dynamically adjusted according to the digital signal code value determined in the current conversion cycle.
  • the working principle of the auxiliary digital-to-analog conversion module is introduced with reference to the analog-to-digital conversion circuit shown in Figure 3 and the analog-to-digital conversion workflow shown in Figure 5.
  • the switch sw is turned on and the common mode signal Vcm is connected to the auxiliary digital-to-analog conversion module.
  • the two switches sw are turned off.
  • the auxDAC can adjust the switches in the auxDAC based on Din, and the auxDAC can output the voltage Vaux.
  • the output voltage Vaux is equivalent to interference including the common mode signal Vcm and the reference voltage signal Vref.
  • Step 405 In the comparison module and the logic module, the target digital signal code value is determined based on the first conversion voltage and the second conversion voltage, and the target digital signal code value is the conversion result of the input signal.
  • the comparison module can compare the first conversion voltage and the second conversion voltage it receives, output a corresponding comparison result, and connect the comparison result to the logic module.
  • the logic module can determine whether the current bit of the digital signal code value is "0" or "1" based on the comparison result, that is, it quantizes the sampled input signal to obtain the corresponding quantization result. After a conversion cycle, the final quantization result can be obtained. At this time, the module The digital conversion circuit can output the target digital signal code value of the current conversion cycle.
  • the working principle of each conversion cycle is the same and will not be listed one by one in this embodiment.
  • the non-inverting input end of the comparator CMP is set to receive Vaux, and the inverting input end is set to receive Vdac. Then the comparator CMP is set to compare whether Vaux is greater than Vdac. If so, it indicates the current digital signal code value D[n-1 :0] is less than the digital signal code value that should be output, then the comparator CMP can output a high level; if not, it means that the current digital signal code value D[n-1:0] is greater than the digital signal code value that should be output, Then the comparator CMP can output a low level.
  • the logic circuit Logic can set D[n-1:0] to the initial value "100...00", that is, the highest bit is set to "1" and the remaining bits are set to "0". Moreover, the initial D[n-1:0] is connected to the main digital-to-analog conversion module, so that the main digital-to-analog conversion module can output the corresponding Vdac, and the above comparison result is determined through the comparator CMP.
  • the main digital-to-analog conversion module When the main digital-to-analog conversion module receives the high level output by the comparator CMP, that is, the current digital signal code value D[n-1:0] is less than the digital signal code value that should be output, the highest bit can be retained as "1 "And you can set the next bit to "1” and increase the digital signal code value D[n-1:0]; when the main digital-to-analog conversion module receives the low level output by the comparator CMP, it is the current digital If the signal code value D[n-1:0] is greater than the digital signal code value that should be output, the highest bit can be changed to "0” and the next bit can be set to "1", reducing the digital signal code value D[n -1:0].
  • the digital signal code value D[n-1:0] is determined bit by bit from high to low. That is to say, through the "dichotomy" search, the DAC output signal Vdac successively approaches the common mode signal Vcm. After n times of approximation, the digital signal code value D[n-1:0] is the final quantization result, and is used as Target digital signal code value output.
  • the above uses the single-ended structure as an example to introduce the working principles of a set of main digital-to-analog conversion modules and auxiliary digital-to-analog conversion modules.
  • the first main digital-to-analog conversion module and the first auxiliary digital-to-analog conversion module can be used as a set of modules, respectively connected to the input terminals of the comparison module; the second main digital-to-analog conversion module and the second auxiliary digital-to-analog conversion module
  • the modules are also connected to the input terminals of the comparison module.
  • the working principle of each group of modules is the same as above and will not be described again here.
  • the conversion voltage output by the first auxiliary digital-to-analog conversion module can produce the same or similar crosstalk as the reference voltage signal in the first main digital-to-analog conversion module, which is used to convert the output of the first main digital-to-analog conversion module.
  • the voltage is compensated to offset the interference caused by the reference voltage signal in the first main digital-to-analog conversion module; the conversion voltage output by the second auxiliary digital-to-analog conversion module can be the same as the reference voltage signal in the second main digital-to-analog conversion module or Similar crosstalk is used to compensate the conversion voltage output by the second main digital-to-analog conversion module to offset the interference generated by the reference voltage signal in the second main digital-to-analog conversion module.
  • the analog-to-digital conversion circuit may be a fully differential SAR ADC, where Vip is the positive input signal of the SAR ADC, and Vin is the SAR ADC
  • the negative terminal input signal is, DACp is the positive terminal DAC inside the SAR ADC, DACn is the negative terminal DAC inside the SAR ADC, auxDACp is the positive terminal auxiliary DAC, and auxDACn is the negative terminal auxiliary DAC.
  • the input of DACp includes Vip, reference voltage The signal Vref and the positive digital signal code value Dp[n-1:0] fed back by the logic circuit Logic, the input of auxDACn includes Vref and the corresponding reference digital signal Din_n, Din_n is related to the above Dp[n-1:0], auxDACn Used to offset the interference generated by Vref in DACp.
  • the input of DACn includes Vin, Vref and the negative terminal digital signal value Dn[n-1:0] fed back by the logic circuit Logic.
  • the input of auxDACp includes Vref and the corresponding reference digital signal Din_p. Din_p and the above-mentioned Dn[n-1: 0] related, auxDACp is used to offset the interference caused by Vref in DACn.
  • the analog-to-digital conversion circuit may include an auxiliary digital-to-analog conversion module for canceling interference.
  • the reference digital signal is converted into the corresponding second conversion voltage through the auxiliary digital-to-analog conversion module, and the input signal is converted into corresponding first conversion voltage.
  • the crosstalk generated by the reference voltage signal in the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module is similar, so the second conversion voltage can be used to A conversion voltage is used for compensation to offset the noise or interference of the reference voltage signal in the first conversion voltage, thereby improving the accuracy in the process of determining the digital signal value by the comparison module and the logic module, and improving the conversion accuracy of the analog-to-digital conversion circuit.
  • the embodiment of the present application also provides an analog-to-digital conversion circuit, which can be used to implement the above analog-to-digital conversion method.
  • the implementation principle of the analog-to-digital conversion circuit has been introduced above and will not be described again in this embodiment.
  • the analog-to-digital conversion circuit may include a main digital-to-analog conversion module, an auxiliary digital-to-analog conversion module, a comparison module and a logic module.
  • the main digital-to-analog conversion module and the auxiliary digital-to-analog conversion module are respectively connected to the input terminals of the comparison module.
  • the circuit type of the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module is the same.
  • the main digital-to-analog conversion module is configured to receive an input signal, convert the input signal based on a reference voltage signal, and obtain a first conversion voltage;
  • the auxiliary digital-to-analog conversion module is configured to receive a reference digital signal, process the reference digital signal based on the reference voltage signal, and obtain a second conversion voltage;
  • the comparison module and the logic module are configured to determine a target digital signal code value based on the first conversion voltage and the second conversion voltage, and the target digital signal code value is the conversion result of the input signal. .
  • the output terminal of the main digital-to-analog conversion module is connected to the first input terminal of the comparison module, and the output terminal of the auxiliary digital-to-analog conversion module is connected to the second input terminal of the comparison module.
  • the main digital-to-analog conversion module includes a first main digital-to-analog conversion module and a second main digital-to-analog conversion module
  • the auxiliary digital-to-analog conversion module includes a first auxiliary digital-to-analog conversion module and a second auxiliary digital-to-analog conversion module.
  • module wherein the first main digital-to-analog conversion module and the first auxiliary digital-to-analog conversion module are respectively connected to the input end of the comparison module, and the second main digital-to-analog conversion module and the second auxiliary digital-to-analog conversion module
  • the analog conversion modules are respectively connected to the input terminals of the comparison modules.
  • the output end of the first main digital-to-analog conversion module is connected to the first input end of the comparison module, and the The output end of an auxiliary digital-to-analog conversion module is connected to the second input end of the comparison module;
  • the output terminal of the second main digital-to-analog conversion module is connected to the second input terminal of the comparison module, and the output terminal of the second auxiliary digital-to-analog conversion module is connected to the first input terminal of the comparison module.
  • the reference digital signal is configured as a first preset value.
  • the reference digital signal is determined based on the target digital signal code value of the previous conversion cycle in the current conversion cycle.
  • the reference digital signal is configured as the target digital signal code value of the previous conversion cycle. value, where i and n are integers greater than 1;
  • the reference digital signal is configured to be the number of bits of the target digital signal code value of the previous conversion cycle. High i bit.
  • the auxiliary digital-to-analog conversion module is configured to receive a first reference digital signal, based on the reference voltage signal and the first Process the reference digital signal to obtain the second conversion voltage, where k is an integer greater than 1;
  • the auxiliary digital-to-analog conversion module is configured to receive at least one second reference digital signal based on the reference voltage signal and the at least one second reference The digital signal is processed to obtain a second conversion voltage, wherein the at least one second reference digital signal is determined based on the determined high-k bits.
  • the first reference digital signal is configured as a second preset value
  • the first reference digital signal is determined based on the target digital signal code value of the previous conversion cycle.
  • the analog-to-digital conversion circuit may include an auxiliary digital-to-analog conversion module for canceling interference.
  • the auxiliary digital-to-analog conversion module converts the reference digital signal into a corresponding second conversion voltage
  • the main digital-to-analog conversion module converts the input signal into a corresponding second conversion voltage. The signal is converted into a corresponding first conversion voltage.
  • the circuit types of the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module are the same, so that the reference voltage signal is transmitted between the auxiliary digital-to-analog conversion module and the main digital-to-analog conversion module.
  • the crosstalk generated in the conversion module is similar, so the second conversion voltage can be used to compensate the first conversion voltage, offset the noise or interference of the reference voltage signal in the first conversion voltage, and then perform digital signal coding in the comparison module and logic module. In the process of determining the value, the accuracy can be improved and the conversion accuracy of the analog-to-digital conversion circuit can be improved.
  • An embodiment of the present application also provides a chip, including the analog-to-digital conversion circuit provided by the embodiment of the present application.
  • Chip Integrated Circuit, IC
  • the chip can be but is not limited to a SOC (System on Chip, chip-level system) chip or a SIP (system in package, system-level packaging) chip.
  • SOC System on Chip, chip-level system
  • SIP system in package, system-level packaging
  • An embodiment of the present application also provides an electronic device.
  • the electronic device includes a device main body and a device provided in the device body.
  • Electronic devices may be, but are not limited to, weight scales, body fat scales, nutrition scales, infrared electronic thermometers, pulse oximeters, body composition analyzers, mobile power supplies, wireless chargers, fast charge chargers, car chargers, adapters, and displays.
  • USB Universal Serial Bus, Universal Serial Bus
  • stylus true wireless headphones
  • car central control screen automobile
  • smart wearable devices mobile terminals, smart home equipment.
  • Smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical massagers.
  • Mobile terminals include but are not limited to smartphones, laptops, tablets, and POS (point of sales terminal) machines.
  • Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本申请提供一种模数转换电路、控制方法、芯片及电子设备，属于电子技术领域。模数转换电路包括主数模转换模块、辅助数模转换模块，辅助数模转换模块与主数模转换模块的电路类型相同；所述主数模转换模块，设置为接收输入信号，基于参考电压信号对所述输入信号进行转换，得到第一转换电压；所述辅助数模转换模块，设置为接收参考数字信号，基于所述参考电压信号对所述参考数字信号进行处理，得到第二转换电压；所述比较模块和所述逻辑模块，设置为基于所述第一转换电压和所述第二转换电压，确定目标数字信号码值，所述目标数字信号码值为对所述输入信号的转换结果。采用本申请，可以提高模数转换电路的转换精度。

Description

一种模数转换电路、控制方法、芯片及电子设备
相关申请的交叉引用
本申请要求于2022年06月21日提交的申请号为202210706874.3的中国申请的优先权，其在此处于所有目的通过引用将其全部内容并入本文。
技术领域
本申请涉及电子技术领域，尤其涉及一种模数转换电路、控制方法、芯片及电子设备。
背景技术
模数转换器(ADC：Analog Digital Convertor)电路的主要作用是将电信号(如电压、电流)转换为数字信号，实现对电信号的量化。ADC是通信、仪器测量、传感控制系统的重要功能模块，广泛应用于模拟集成电路和数模混合集成电路领域。
在转换过程中，一般基于参考电压信号实现量化。当参考电压信号存在噪声、干扰时，可能导致量化结果出现错误，降低ADC的转换精度。
发明内容
为了解决现有技术的问题，本申请实施例提供了一种模数转换电路、控制方法、芯片及电子设备，可以提高模数转换电路的转换精度。技术方案如下：
根据本申请的一方面，提供了一种模数转换电路，所述模数转换电路包括主数模转换模块、辅助数模转换模块、比较模块和逻辑模块，其中，所述辅助数模转换模块与所述主数模转换模块的电路类型相同；
所述主数模转换模块，设置为接收输入信号，基于参考电压信号对所述输入信号进行转换，得到第一转换电压；
所述辅助数模转换模块，设置为接收参考数字信号，基于所述参考电压信号对所述参考数字信号进行处理，得到第二转换电压；
所述比较模块和所述逻辑模块，设置为基于所述第一转换电压和所述第二转换电压，确定目标数字信号码值，所述目标数字信号码值为对所述输入信号的转换结果。
根据本申请的另一方面，提供了一种模数转换电路的控制方法，所述模数转换电路包括主数模转换模块、辅助数模转换模块、比较模块和逻辑模块，其中，所述辅助数模转换模块与所述主数模转换模块的电路类型相同，所述方法包括：
获取输入信号及参考数字信号；
在所述主数模转换模块中，基于参考电压信号对所述输入信号进行转换，得到第一转换电压；
在所述辅助数模转换模块中，基于所述参考电压信号对所述参考数字信号进行处理，得到第二转换电压；
在所述比较模块和所述逻辑模块中，基于所述第一转换电压和所述第二转换电压，确定目标数字信号码值，所述目标数字信号码值为对所述输入信号的转换结果。
根据本申请的另一方面，提供了一种芯片，所述芯片包括上述模数转换电路。
根据本申请的另一方面，提供了一种电子设备，所述电子设备包括上述模数转换电路。
本申请中，模数转换电路可以包括用于抵消干扰的辅助数模转换模块，通过辅助数模转换模块将参考数字信号转换为相应的第二转换电压，通过主数模转换模块将输入信号转换为相应的第一转换电压。由于辅助数模转换模块和主数模转换模块的电路类型相同，使得参考电压信号在辅助数模转换模块和主数模转换模块中产生的串扰相似，因此可以将第二转换电压用于对第一转换电压进行补偿，抵消第一转换电压中参考电压信号的噪声或干扰，进而在比较模块和逻辑模块进行数字信号码值的确定过程中可以提高正确率，提高模数转换电路的转换精度。
附图说明
在下面结合附图对于示例性实施例的描述中，本申请的更多细节、特征和优点被公开，在附图中：
图1示出了根据本申请示例性实施例提供的模数转换电路示意图；
图2示出了根据本申请示例性实施例提供的模数转换电路示意图；
图3示出了根据本申请示例性实施例提供的模数转换电路示意图；
图4示出了根据本申请示例性实施例提供的模数转换电路的控制方法流程图；
图5示出了根据本申请示例性实施例提供的模数转换工作流程示意图；
图6示出了根据本申请示例性实施例提供的模数转换电路示意图。
图中，
1、主数模转换模块；11、第一主数模转换模块；12、第二主数模转换模块；2、辅助数模转换模块；21、第一辅助数模转换模块；22、第二辅助数模转换模块；3、比较模块；4、 逻辑模块。
具体实施方式
下面将参照附图更详细地描述本申请的实施例。虽然附图中显示了本申请的某些实施例，然而应当理解的是，本申请可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本申请。应当理解的是，本申请的附图及实施例仅用于示例性作用，并非用于限制本申请的保护范围。
本文使用的术语“包括”及其变形是开放性包括，即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”；术语“另一实施例”表示“至少一个另外的实施例”；术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。需要注意，本申请中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分，并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意，本申请中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
本申请实施方式中的多个装置之间所交互的消息或者信息的名称仅用于说明性的目的，而并不是用于对这些消息或信息的范围进行限制。
本申请实施例提供了一种模数转换电路。该模数转换电路可以集成在芯片中，或者设置在电子设备中。
首先对模数转换电路进行介绍。该模数转换电路可以包括主数模转换模块1、辅助数模转换模块2、比较模块3和逻辑模块4，其中，主数模转换模块1和辅助数模转换模块2分别连接于比较模块3的输入端。参照图1所示的模数转换电路示意图，当上述模数转换电路采用单端结构时，电路结构可以如下：
主数模转换模块1的第一输入端设置为接收输入信号，第二输入端设置为接收参考电压信号，第三输入端设置为接收逻辑模块4反馈的数字信号码值，输出端与比较模块3的第一输入端连接。
辅助数模转换模块2的第一输入端设置为接收参考电压信号，第二输入端设置为接收参考数字信号，输出端与比较模块3的第二输入端连接。
比较模块3的第一输入端与主数模转换模块1的输出端连接，第二输入端与辅助数模转换模块2的输出端连接，输出端与逻辑模块4的输入端连接。
逻辑模块4的输入端与比较模块3的输出端连接，可以在转换过程中将相应的数字信号码值反馈至主数模转换模块1，经过一个转换周期后，可以输出最终的数字信号码值，也 即是当前转换周期的目标数字信号码值。
参照图2所示的模数转换电路示意图，当上述模数转换电路采用差分结构时，主数模转换模块1可以包括第一主数模转换模块11和第二主数模转换模块12，辅助数模转换模块2可以包括第一辅助数模转换模块21和第二辅助数模转换模块22，电路结构可以如下：
第一主数模转换模块11的第一输入端设置为接收输入信号的第一信号，第二输入端设置为接收参考电压信号，第三输入端设置为接收逻辑模块4反馈的第一数字信号码值，输出端与比较模块3的第一输入端连接。其中，第一数字信号码值用于对上述第一信号进行量化。
第一辅助数模转换模块21的第一输入端设置为接收参考电压信号，第二输入端设置为接收对应的参考数字信号，输出端与比较模块3的第二输入端连接。
第二主数模转换模块12的第一输入端设置为接收输入信号的第二信号，第二输入端设置为接收参考电压信号，第三输入端设置为接收逻辑模块4反馈的第二数字信号码值，输出端与比较模块3的第二输入端连接。其中，第二数字信号码值用于对上述第二信号进行量化。
第二辅助数模转换模块22的第一输入端设置为接收参考电压信号，第二输入端设置为接收对应的参考数字信号，输出端与比较模块3的第一输入端连接。
比较模块3的输出端与逻辑模块4的输入端连接。
主数模转换模块1和辅助数模转换模块2的电路类型相同，电路结构相同或相似，在此基础上，可以保证两者输出的转换电压具有统一性，也即是当输入相同的数字信号码值时，可以输出相同或相近的转换电压。数模转换模块的电路结构与输入的数字信号码值相适配，当参考数字信号与模数转换电路输出的数字信号码值的位数相同时，主数模转换模块1和辅助数模转换模块2的电路结构可以相同；当参考数字信号与模数转换电路输出的数字信号码值的位数不同时，主数模转换模块1和辅助数模转换模块2可以属于同一电路类型下，用于适应不同位数的电路结构。
本实施例对主数模转换模块1和辅助数模转换模块2的具体电路类型不作限定。例如，主数模转换模块1可以采用电容型、电阻型或电容-电阻型等电路类型，辅助数模转换模块2采用与主数模转换模块相同的电路类型，也即是，主数模转换模块1和辅助数模转换模块2均为电容型数模转换电路，或均为电阻型数模转换电路，或均为电容-电阻型数模转换电路等。示例性的，设主数模转换模块1为电容型数模转换电路，则辅助数模转换模块2同样为电容型数模转换电路，若参考数字信号与模数转换电路输出的数字信号码值的位数均为12，则主数模转换模块1和辅助数模转换模块2的电路结构相同，可以均包括12位的电容阵列；若模数转换电路输出的数字信号码值的位数位12，参考数字信号的位数为6，则主数 模转换模块1可以包括12位的电容阵列，辅助数模转换模块2可以包括6位的电容阵列。
在一种具体的实施方式中，参照图3所示的模数转换电路示意图，该模数转换电路可以是逐次逼近型模拟数字转换电路(SAR ADC，Successive Approximation Register Analog-to-Digital Converter)，其中，DAC(Digital-to-Analog Converter，模拟数字转换器)对应于上述主数模转换模块1，auxDAC(Auxiliary Digital-to-Analog Converter，辅助模拟数字转换器)对应于上述辅助数模转换模块2，比较器CMP对应于上述比较模块3，逻辑电路Logic对应于上述逻辑模块4。
此外，在比较器CMP的两个输入端之间可以设置两个串联的开关sw，并在两个开关之间接入共模信号Vcm。在采样期间，两个开关sw导通，将共模信号Vcm接入主数模转换模块和辅助数模转换模块；在转换期间，两个开关sw关断。
该模数转换电路还可以是基于SAR ADC与其他ADC组成的混合结构ADC，例如Pipeline-SAR ADC(流水线型和逐次逼近型相结合)，Incremental-SAR ADC(增量型和逐次逼近型相结合)，Delta-Sigma-SAR ADC(∑-Δ型和逐次逼近型相结合)，Flash-SAR ADC(并联比较型和逐次逼近型相结合)等。本实施例对此不作限定。
下面将参照图4所示的模数转换电路的控制方法流程图，在步骤401-405中对该模数转换电路的实现原理进行介绍。
步骤401，获取输入信号。
其中，输入信号为模拟信号。
在一种可能的实施方式中，上电后，模数转换电路的输入端可以接收到相应的输入信号，使得模数转换电路可以在每个转换周期中将该输入信号转换为相应的目标数字信号，并在一个转换周期结束后，输出相应的目标数字信号码值。例如，当模数转换电路为12位的SAR ADC时，可以在每个转换周期将输入信号转换为12位的数字信号，输出相应的12位数字信号码值。
输入信号可以是单端信号，也可以是差分信号。相对应的，模数转换电路可以采用适用于单端信号的电路结构，或者，采用适用于差分信号的电路结构，又或者，采用同时适用于单端信号和差分信号的电路结构。本实施例对此不作限定。
步骤402，获取参考数字信号。
参考数字信号在辅助数模转换模块中的作用，与数字信号码值在主数模转换模块中的作用同理，也即是通过数模转换模块将其转换成一个模拟电压。由于辅助数模转换模块和主数模转换模块的电路类型相同，且模块输入同时包括参考电压信号和数字信号，在此基础上，第二转换电压(由辅助数模转换模块输出)可以携带与第一转换电压(由主数模转换模块输出)中存在的相等或相近的参考电压信号的噪声或干扰，在后续的转换过程中可以达到 相互抵消的效果。
为了适应不同的应用场景，本实施例提供了不同的获取参考数字信号的方式。本实施例提供的模数转换方法可以包括多个转换周期，下面将以一个转换周期为例，对该转换周期获取参考数字信号的方式进行介绍。
方式一：确定参考数字信号为第一预设值。
在一种可能的实施方式中，第一预设值可以基于模数转换电路对相同或相近的输入信号确定的数字信号码值进行设定，使得参考数字信号可以满足输入信号的规律性、电压范围等性质。
此方式获取的参考数字信号固定，可以降低电路设计的难度，并且可以提高辅助数模转换模块的稳定性。
方式二：在当前转换周期中，基于上一转换周期的目标数字信号码值确定参考数字信号。
在一种可能的实施方式中，可以将逻辑模块在上一转换周期输出的目标数字信号码值反馈至辅助数模转换模块，参考数字信号可以随着上一转换周期的目标数字信号码值进行调整。
此方式适用于输入信号带宽较小或不切通道的应用。
具体的，根据参考数字信号的位数不同，方式二可以有如下两种情况：
情况一，若参考数字信号的位数i等于上一转换周期的目标数字信号码值的位数n，则确定参考数字信号为上一转换周期的目标数字信号码值；
情况二，若参考数字信号的位数i小于上一转换周期的目标数字信号码值的位数n，则确定参考数字信号为上一转换周期的目标数字信号码值的高i位。
其中，i、n为大于1的整数。
示例性的，参考数字信号可以表示为Din[i-1：0]，上一转换周期的目标数字信号码值可以表示为Dt-1[n-1：0]，下标t用于表示当前转换周期，相应的，下标t-1用于表示上一转换周期。当参考数字信号的位数i等于目标数字信号码值的位数n时，可以令Din[i-1：0]＝Dt-1[i-1：0]。当参考数字信号的位数i小于目标数字信号码值的位数n时，可以令Din[i-1：0]＝Dt-1[n-1：n-i]。
例如，设模数转换电路输出的目标数字信号码值为12位，在上一转换周期输出Dt- 1[11：0]＝001101010101，若i＝12，则Din[11：0]＝001101010101；若i＝6，则Din[5：0]＝Dt-1[11：6]＝001101。
方式三：基于当前转换周期的数字信号码值确定参考数字信号。
当前转换周期的数字信号码值是从高到低逐位确定的，方式三可以包括两个阶段：
第一阶段，在当前转换周期中，获取第一参考数字信号，该第一参考数字信号用于在确定当前转换周期的数字信号码值的高k位时输入辅助数模转换模块；
第二阶段，在确定当前转换周期的数字信号码值的高k位后，基于上述高k位，获取至少一个第二参考数字信号，第二参考数字信号用于在确定当前转换周期的数字信号码值的剩余位时输入辅助数模转换模块。
其中，k为大于1的整数。
此方式适用于输入信号带宽较小或不切通道的应用，同时也适用于输入信号带宽较大或切通道的应用，相对于上述方式二扩展了应用范围。
在第一阶段，上述第一参考数字信号可以采用上述方式一或方式二确定，也即是说，确定第一参考数字信号为第二预设值，或，基于上一转换周期的目标数字信号码值确定第一参考数字信号。其中，第二预设值与上述第一预设值同理，可以等于上述第一预设值，也可以不相等。
上述第二阶段执行在确定当前转换周期的数字信号码值的高k位之后，也即是说，当数字信号码值高k位转换完成时，可以将当前已确定的高k位部分的码值作为参考数字信号。
在第二阶段可以确定一个第二参考数字信号。在此情况下，若k的取值小于数字信号码值的位数n，等于参考数字信号的位数i，则可以确定第二参考数字信号为当前已确定的高k位部分的码值。若k的取值小于目标数字信号码值的位数n，大于参考数字信号的位数i，则可以确定第二参考数字信号为当前已确定的高i位部分的码值。
示例性的，参考数字信号可以表示为Din[i-1：0]，当前转换周期的数字信号码值可以表示为Dt[n-1：0]，下标t用于表示当前转换周期。在确定Dt[n-1：n-k]后，如果参考数字信号的位数i等于k，则可以令Din[i-1：0]＝Dt[n-1：n-k]；如果参考数字信号的位数i小于k时，则令Din[i-1：0]＝Dt[n-1：n-i]。
例如，设模数转换电路输出的目标数字信号码值为12位，在上述第一阶段确定高6位部分的码值，在当前转换周期中，经过6个时钟周期后确定当前的高6位部分的码值Dt[11：6]＝001101，若参考数字信号的位数i＝6，则可以得到Din[5：0]＝Dt[11：6]＝001101；若参考数字信号的位数i＝3，则可以得到Din[2：0]＝Dt[11：9]＝001。
在一些实施方式中，在第二阶段还可以确定多个第二参考数字信号。在此情况下，若k的取值小于数字信号码值的位数n，等于参考数字信号的位数i，则可以确定第一个第二参考数字信号为当前转换周期的数字信号码值的高k位。若k的取值小于数字信号码值的位数n，大于参考数字信号的位数i，则可以确定第一个第二参考数字信号为当前转换周期的数字信号码值的高i位。此后，每当数字信号码值确定一位或多位时，可以基于最新确定 的一位或多位对第二参考数字信号进行更新。
示例性的，参考数字信号可以表示为Din[i-1：0]，当前转换周期的数字信号码值可以表示为Dt[n-1：0]，设参考数字信号的位数i等于k。在确定Dt[n-1：n-k]后，可以令Din[i-1：0]＝Dt[n-1：n-k]。此后，在确定Dt[n-1：n-k-1]时，可以令Din[i-1：0]＝Dt[n-2：n-k-1]；在确定Dt[n-1：n-k-2]时，可以令Din[i-1：0]＝Dt[n-3：n-k-2]，依此类推。
例如，设模数转换电路输出的目标数字信号码值为12位，在上述第一阶段确定高6位部分的码值，参考数字信号的位数i＝6，在当前转换周期中，经过6个时钟周期后逻辑模块确定当前数字信号码值的高6位部分的码值Dt[11：6]＝001101，则此时可以得到第一个参考数字信号Din1[5：0]＝Dt[11：6]＝001101，并在第7个时钟周期将Din1[5：0]输入辅助数模转换模块；第7个时钟周期结束后，逻辑模块可以确定当前数字信号码值的高7位部分的码值Dt[11：5]＝0011010，此时可以得到第二个参考数字信号Din2[5：0]＝Dt[10：5]＝011010，并在第8个时钟周期将Din2[5：0]输入辅助数模转换模块，依此类推。
步骤403，在主数模转换模块中，基于参考电压信号对输入信号进行转换，得到第一转换电压。
在一种可能的实施方式中，主数模转换模块可以用于对输入信号进行采样保持，然后主数模转换模块、比较模块和逻辑模块形成环路，主数模转换模块可以基于参考电压信号将逻辑模块反馈的中间数字信号码值转换为相应的模拟电压，即第一转换电压。其中，中间数字信号码值为转换过程中确定的数字信号码值。以SAR ADC为例，逻辑模块反馈的中间数字信号码值可以是指在每个时钟周期通过逐次逼近的原理确定的数字信号码值，由于该数字信号码值还未完全确定，还未作为模数转换电路的输出信号，本实施例中将其称为中间数字信号码值。
具体的，以单端结构的SAR ADC为例，参照图3所示的模数转换电路和图5所示的模数转换工作流程对主数模转换模块的工作原理进行介绍。首先，开关sw导通，将共模信号Vcm接入主数模转换模块，输入信号被DAC采样并保持。其次，两个开关sw关断，此时中间数字信号码值D[n-1：0]可以为初始值，DAC的输出电压Vdac＝Vref/2-Vin+Vcm，接入比较器CMP的反相输入端。在下一个时钟周期，DAC可以基于当前接收到的中间数字信号码值D[n-1：0]对DAC中的开关进行调整，使得输出电压更新为Vdac+(2*D[j]-1)Vref/2(n- j+1)，j为当前确定的数字信号码值的位，此时，j＝n-1，即最高位。在之后的每个时钟周期，均可以采用上述方式调整输出电压Vdac，直至转换周期结束。当Vref存在噪声或干扰时，Vdac包括参考电压信号Vref的干扰。
需要说明的是，图5所示的模数转换工作流程以及涉及的公式仅仅是对模数转换电路的工作原理进行的数学建模，并不意味着基于软件实现执行流程以及公式的计算。
步骤404，在辅助数模转换模块中，基于参考电压信号对参考数字信号进行处理，得到第二转换电压。
在一种可能的实施方式中，辅助数模转换模块可以基于参考电压信号将接入的参考数字信号转换为相应的模拟电压，即第二转换电压。转换原理与主数模转换模块转换数字信号码值的原理相同。
并且，辅助数模转换模块和主数模转换模块的电路类型相同，模块的输入相似，在此基础上，辅助数模转换模块输出的第二转换电压可以产生与参考电压信号在主数模转换模块中相同或相似的串扰，进而抵消参考电压信号在主数模转换模块中产生的干扰。
下面将分别针对上述获取参考数字信号的方式，对辅助数模转换模块的工作原理进行介绍。
对应于上述方式一，参考数字信号为第一预设值，则在一个转换周期中，辅助数模转换模块输出的第二转换电压可以是固定的，且每个转换周期模数转换电路所采用的第二转换电压可以相同。
对应于上述方式二，参考数字信号为上一转换周期的目标数字信号码值，或，上一转换周期的目标数字信号码值的高i位，则在一个转换周期中，辅助数模转换模块输出的第二转换电压可以是固定的，但每个转换周期模数转换电路所采用的第二转换电压可以随着上一转换周期的目标数字信号码值进行调整。
对应于上述方式三，在一个转换周期中，在第一阶段，辅助数模转换模块可以将第一参考数字信号转换为一个第二转换电压，在第二阶段，辅助数模转换模块可以将至少一个第二参考数字信号转换为相应的第二转换电压。由此可见，在一个转换周期中，第二转换电压可以随着当前转换周期确定的数字信号码值动态调整。
具体的，以单端结构的SAR ADC为例，参照图3所示的模数转换电路和图5所示的模数转换工作流程对辅助数模转换模块的工作原理进行介绍。首先，开关sw导通，将共模信号Vcm接入辅助数模转换模块。其次，两个开关sw关断，此时auxDAC可以基于Din对auxDAC中的开关进行调整，auxDAC可以输出电压Vaux。输出电压Vaux相当于包括共模信号Vcm和参考电压信号Vref的干扰。
步骤405，在比较模块和逻辑模块中，基于第一转换电压和第二转换电压，确定目标数字信号码值，目标数字信号码值为对输入信号的转换结果。
在一种可能的实施方式中，比较模块可以对其接收的第一转换电压和第二转换电压进行比较，并输出相应的比较结果，将比较结果接入逻辑模块。逻辑模块接收到比较结果后，可以基于该比较结果确定数字信号码值的当前位为“0”或“1”，也即是对采样的输入信号进行量化，得到相应的量化结果。经过一个转换周期后，可以得到最终的量化结果，此时模 数转换电路可以输出当前转换周期的目标数字信号码值。每个转换周期的工作原理相同，本实施例不再一一列举。
具体的，以单端结构的SAR ADC为例，参照图3所示的模数转换电路和图5所示的模数转换工作流程对比较模块和逻辑模块的工作原理进行介绍。
比较器CMP的正相输入端设置为接收Vaux，反相输入端设置为接收Vdac，则比较器CMP设置为比较Vaux是否大于Vdac，如果是，则表明当前的数字信号码值D[n-1：0]小于应当输出的数字信号码值，则比较器CMP可以输出高电平；如果否，则表明当前的数字信号码值D[n-1：0]大于应当输出的数字信号码值，则比较器CMP可以输出低电平。
逻辑电路Logic可以将D[n-1：0]设置为初始值“100...00”，也即是最高位设置为“1”，其余位设置为“0”。并且，将该初始的D[n-1：0]接入主数模转换模块，使得主数模转换模块可以输出相应的Vdac，并通过比较器CMP确定上述比较结果。当主数模转换模块接收到比较器CMP输出的高电平时，也即是当前的数字信号码值D[n-1：0]小于应当输出的数字信号码值，则可以保留最高位为“1”并且可以将下一位设置为“1”，加大数字信号码值D[n-1：0]；当主数模转换模块接收到比较器CMP输出的低电平时，也即是当前的数字信号码值D[n-1：0]大于应当输出的数字信号码值，则可以更改最高位为“0”并且可以将下一位设置为“1”，减小数字信号码值D[n-1：0]。依此类推，从高到低逐位确定数字信号码值D[n-1：0]。也即是实现了通过“二分法”搜索，DAC输出信号Vdac逐次逼近共模信号Vcm，经过n次逼近后，数字信号码值D[n-1：0]即为最终的量化结果，并作为目标数字信号码值输出。
上文以单端结构为例，对一组主数模转换模块和辅助数模转换模块的工作原理进行了介绍。对于差分结构，可以将第一主数模转换模块和第一辅助数模转换模块作为一组模块，分别连接于比较模块的输入端；将第二主数模转换模块和第二辅助数模转换模块作为另一组模块，同样分别连接于比较模块的输入端。其中，每组模块的工作原理与上文同理，此处不再赘述。也即是说，第一辅助数模转换模块输出的转换电压可以产生与参考电压信号在第一主数模转换模块中相同或相似的串扰，用于对第一主数模转换模块输出的转换电压进行补偿，以抵消参考电压信号在第一主数模转换模块中产生的干扰；第二辅助数模转换模块输出的转换电压可以产生与参考电压信号在第二主数模转换模块中相同或相似的串扰，用于对第二主数模转换模块输出的转换电压进行补偿，以抵消参考电压信号在第二主数模转换模块中产生的干扰。
在一种具体的实施方式中，参照图6所示的模数转换电路示意图，该模数转换电路可以是全差分型SAR ADC，其中，Vip为SAR ADC的正端输入信号，Vin为SAR ADC的负端输入信号，DACp为SAR ADC内部的正端DAC，DACn为SAR ADC内部的负端DAC，auxDACp为正端辅助DAC，auxDACn为负端辅助DAC。DACp的输入包括Vip、参考电压 信号Vref和逻辑电路Logic反馈的正端数字信号码值Dp[n-1：0]，auxDACn的输入包括Vref和对应的参考数字信号Din_n，Din_n与上述Dp[n-1：0]相关，auxDACn用于抵消DACp中Vref产生的干扰。DACn的输入包括Vin、Vref和逻辑电路Logic反馈的负端数字信号码值Dn[n-1：0]，auxDACp的输入包括Vref和对应的参考数字信号Din_p，Din_p与上述Dn[n-1：0]相关，auxDACp用于抵消DACn中Vref产生的干扰。
本申请实施例可以获得如下有益效果：
(1)模数转换电路可以包括用于抵消干扰的辅助数模转换模块，通过辅助数模转换模块将参考数字信号转换为相应的第二转换电压，通过主数模转换模块将输入信号转换为相应的第一转换电压。由于辅助数模转换模块和主数模转换模块的电路类型相同，使得参考电压信号在辅助数模转换模块和主数模转换模块中产生的串扰相似，因此可以将第二转换电压用于对第一转换电压进行补偿，抵消第一转换电压中参考电压信号的噪声或干扰，进而在比较模块和逻辑模块进行数字信号码值的确定过程中可以提高正确率，提高模数转换电路的转换精度。
(2)提供了多种获取参考数字信号的方式，可以适应多种应用场景。
本申请实施例还提供了一种模数转换电路，可以用于实现上述模数转换方法。该模数转换电路的实现原理在上文中已经介绍，本实施例中不再赘述。
该模数转换电路可以包括主数模转换模块、辅助数模转换模块、比较模块和逻辑模块，所述主数模转换模块和所述辅助数模转换模块分别连接于所述比较模块的输入端，所述辅助数模转换模块与所述主数模转换模块的电路类型相同。
所述主数模转换模块，设置为接收输入信号，基于参考电压信号对所述输入信号进行转换，得到第一转换电压；
所述辅助数模转换模块，设置为接收参考数字信号，基于所述参考电压信号对所述参考数字信号进行处理，得到第二转换电压；
所述比较模块和所述逻辑模块，设置为基于所述第一转换电压和所述第二转换电压，确定目标数字信号码值，所述目标数字信号码值为对所述输入信号的转换结果。
可选的，所述主数模转换模块的输出端与所述比较模块的第一输入端连接，所述辅助数模转换模块的输出端与所述比较模块的第二输入端连接。
可选的，所述主数模转换模块包括第一主数模转换模块和第二主数模转换模块，所述辅助数模转换模块包括第一辅助数模转换模块和第二辅助数模转换模块，其中，所述第一主数模转换模块和所述第一辅助数模转换模块分别连接于所述比较模块的输入端，所述第二主数模转换模块和所述第二辅助数模转换模块分别连接于所述比较模块的输入端。
可选的，所述第一主数模转换模块的输出端与所述比较模块的第一输入端连接，所述第 一辅助数模转换模块的输出端与所述比较模块的第二输入端连接；
所述第二主数模转换模块的输出端与所述比较模块的第二输入端连接，所述第二辅助数模转换模块的输出端与所述比较模块的第一输入端连接。
可选的，所述参考数字信号被配置为第一预设值。
可选的，所述参考数字信号在当前转换周期中，基于上一转换周期的目标数字信号码值确定。
可选的，若所述参考数字信号的位数i等于所述上一转换周期的目标数字信号码值的位数n，则所述参考数字信号被配置为上一转换周期的目标数字信号码值，其中，i、n为大于1的整数；
若所述参考数字信号的位数i小于所述上一转换周期的目标数字信号码值的位数n，则所述参考数字信号被配置为所述上一转换周期的目标数字信号码值的高i位。
可选的，在确定所述当前转换周期的数字信号码值的高k位时，所述辅助数模转换模块，设置为接收第一参考数字信号，基于所述参考电压信号和所述第一参考数字信号进行处理，得到第二转换电压，其中，k为大于1的整数；
在确定所述当前转换周期的数字信号码值的剩余位时，所述辅助数模转换模块，设置为接收至少一个第二参考数字信号，基于所述参考电压信号和所述至少一个第二参考数字信号进行处理，得到第二转换电压，其中，所述至少一个第二参考数字信号基于已确定的所述高k位确定。
可选的，所述第一参考数字信号被配置为第二预设值；或
所述第一参考数字信号基于上一转换周期的目标数字信号码值确定。
本申请实施例中，模数转换电路可以包括用于抵消干扰的辅助数模转换模块，通过辅助数模转换模块将参考数字信号转换为相应的第二转换电压，通过主数模转换模块将输入信号转换为相应的第一转换电压。由于参考数字信号与主数模转换模块可以接收到的数字信号码值相关，辅助数模转换模块和主数模转换模块的电路类型相同，使得参考电压信号在辅助数模转换模块和主数模转换模块中产生的串扰相似，因此可以将第二转换电压用于对第一转换电压进行补偿，抵消第一转换电压中参考电压信号的噪声或干扰，进而在比较模块和逻辑模块进行数字信号码值的确定过程中可以提高正确率，提高模数转换电路的转换精度。
本申请实施例还提供一种芯片，包括本申请实施例提供的模数转换电路。芯片(Integrated Circuit，IC)也称芯片，该芯片可以是但不限于是SOC(System on Chip，芯片级系统)芯片、SIP(system in package，系统级封装)芯片。该芯片通过配置上述模数转换电路，使得模数转换电路的转换精度提高，进而芯片性能也相应提高。
本申请实施例还提供一种电子设备，该电子设备包括设备主体以及设于设备主题内的 如上述的芯片。电子设备可以是但不限于体重秤、体脂秤、营养秤、红外电子体温计、脉搏血氧仪、人体成分分析仪、移动电源、无线充电器、快充充电器、车载充电器、适配器、显示器、USB(Universal Serial Bus，通用串行总线)扩展坞、触控笔、真无线耳机、汽车中控屏、汽车、智能穿戴设备、移动终端、智能家居设备。智能穿戴设备包括但不限于智能手表、智能手环、颈椎按摩仪。移动终端包括但不限于智能手机、笔记本电脑、平板电脑、POS(point of sales terminal，销售点终端)机。智能家居设备包括但不限于智能插座、智能电饭煲、智能扫地机、智能灯。该电子设备通过配置上述模数转换电路，使得模数转换电路的转换精度提高，进而电子设备性能也相应提高。
以上，仅是本申请的较佳实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以较佳实施例揭示如上，然而并非用以限定本申请，任何本领域技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案内容，依据本申请的技术实质对以上实施例所作的任何简介修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (12)

  1. 一种模数转换电路，其中，所述模数转换电路包括主数模转换模块、辅助数模转换模块、比较模块和逻辑模块，其中，所述辅助数模转换模块与所述主数模转换模块的电路类型相同；
    所述主数模转换模块，设置为接收输入信号，基于参考电压信号对所述输入信号进行转换，得到第一转换电压；
    所述辅助数模转换模块，设置为接收参考数字信号，基于所述参考电压信号对所述参考数字信号进行处理，得到第二转换电压；
    所述比较模块和所述逻辑模块，设置为基于所述第一转换电压和所述第二转换电压，确定目标数字信号码值，所述目标数字信号码值为对所述输入信号的转换结果。
  2. 根据权利要求1所述的模数转换电路，其中，所述参考数字信号被配置为第一预设值。
  3. 根据权利要求1所述的模数转换电路，其中，所述参考数字信号在当前转换周期中，基于上一转换周期的目标数字信号码值确定。
  4. 根据权利要求3所述的模数转换电路，其中，若所述参考数字信号的位数i等于所述上一转换周期的目标数字信号码值的位数n，则所述参考数字信号被配置为上一转换周期的目标数字信号码值，其中，i、n为大于1的整数；
    若所述参考数字信号的位数i小于所述上一转换周期的目标数字信号码值的位数n，则所述参考数字信号被配置为所述上一转换周期的目标数字信号码值的高i位。
  5. 根据权利要求1所述的模数转换电路，其中，在确定所述当前转换周期的数字信号码值的高k位时，所述辅助数模转换模块设置为接收第一参考数字信号，基于所述参考电压信号对所述第一参考数字信号进行处理，得到第二转换电压，其中，k为大于1的整数；
    在确定所述当前转换周期的数字信号码值的剩余位时，所述辅助数模转换模块设置为接收至少一个第二参考数字信号，基于所述参考电压信号对所述至少一个第二参考数字信号进行处理，得到第二转换电压，其中，所述至少一个第二参考数字信号基于已确定的所述高k位确定。
  6. 根据权利要求5所述的模数转换电路，其中，所述第一参考数字信号被配置为第二预设值；或
    所述第一参考数字信号基于上一转换周期的目标数字信号码值确定。
  7. 根据权利要求1所述的模数转换电路，其中，所述主数模转换模块的输出端与所述比较模块的第一输入端连接，所述辅助数模转换模块的输出端与所述比较模块的第二输入端连接。
  8. 根据权利要求1所述的模数转换电路，其中，所述主数模转换模块包括第一主数模转换模块和第二主数模转换模块，所述辅助数模转换模块包括第一辅助数模转换模块和第二辅助数模转换模块，其中，所述第一主数模转换模块和所述第一辅助数模转换模块分别连接于所述比较模块的输入端，所述第二主数模转换模块和所述第二辅助数模转换模块分别连接于所述比较模块的输入端。
  9. 根据权利要求8所述的模数转换电路，其中，所述第一主数模转换模块的输出端与所述比较模块的第一输入端连接，所述第一辅助数模转换模块的输出端与所述比较模块的第二输入端连接；
    所述第二主数模转换模块的输出端与所述比较模块的第二输入端连接，所述第二辅助数模转换模块的输出端与所述比较模块的第一输入端连接。
  10. 一种模数转换电路的控制方法，其中，所述模数转换电路包括主数模转换模块、辅助数模转换模块、比较模块和逻辑模块，其中，所述辅助数模转换模块与所述主数模转换模块的电路类型相同，所述方法包括：
    获取输入信号及参考数字信号；
    在所述主数模转换模块中，基于参考电压信号对所述输入信号进行转换，得到第一转换电压；
    在所述辅助数模转换模块中，基于所述参考电压信号对所述参考数字信号进行处理，得到第二转换电压；
    在所述比较模块和所述逻辑模块中，基于所述第一转换电压和所述第二转换电压，确定目标数字信号码值，所述目标数字信号码值为对所述输入信号的转换结果。
  11. 一种芯片，其中，所述芯片包括如权利要求1-9中任一项所述的模数转换电路。
  12. 一种电子设备，其中，所述电子设备包括如权利要求1-9中任一项所述的模数转换电路。
PCT/CN2023/096038 2022-06-21 2023-05-24 一种模数转换电路、控制方法、芯片及电子设备 WO2023246410A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210706874.3 2022-06-21
CN202210706874.3A CN114978172A (zh) 2022-06-21 2022-06-21 一种模数转换电路、控制方法、芯片及电子设备

Publications (1)

Publication Number Publication Date
WO2023246410A1 true WO2023246410A1 (zh) 2023-12-28

Family

ID=82965186

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/096038 WO2023246410A1 (zh) 2022-06-21 2023-05-24 一种模数转换电路、控制方法、芯片及电子设备

Country Status (2)

Country Link
CN (1) CN114978172A (zh)
WO (1) WO2023246410A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114978172A (zh) * 2022-06-21 2022-08-30 西安芯海微电子科技有限公司 一种模数转换电路、控制方法、芯片及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103873059A (zh) * 2014-03-10 2014-06-18 天津大学 一种应用于高精度逐次逼近模数转换器的数字校准方法
CN104518798A (zh) * 2013-10-04 2015-04-15 瑞昱半导体股份有限公司 模拟数字转换装置及其方法
CN113517891A (zh) * 2021-09-13 2021-10-19 成都爱旗科技有限公司 一种应用于数模转换器的线性校准系统和方法
CN114503437A (zh) * 2019-09-24 2022-05-13 美国亚德诺半导体公司 提高△-σ模数转换器中过量环路延迟补偿的效率
CN114978172A (zh) * 2022-06-21 2022-08-30 西安芯海微电子科技有限公司 一种模数转换电路、控制方法、芯片及电子设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102103933B1 (ko) * 2013-09-04 2020-04-24 삼성전자주식회사 연속 접근 방식 아날로그-디지털 변환기 및 아날로그-디지털 변환 방법
US8957802B1 (en) * 2013-09-13 2015-02-17 Cadence Design Systems, Inc. Metastability error detection and correction system and method for successive approximation analog-to-digital converters
US10298871B2 (en) * 2017-08-07 2019-05-21 Semiconductor Components Industries, Llc Imaging systems with analog-to-digital converters
CN114499520A (zh) * 2022-02-10 2022-05-13 芯海科技（深圳）股份有限公司 一种adc电路及其控制方法
CN114614821B (zh) * 2022-03-30 2023-10-20 广东齐芯半导体有限公司 基于差分结构的sar adc失调误差校正方法及电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104518798A (zh) * 2013-10-04 2015-04-15 瑞昱半导体股份有限公司 模拟数字转换装置及其方法
CN103873059A (zh) * 2014-03-10 2014-06-18 天津大学 一种应用于高精度逐次逼近模数转换器的数字校准方法
CN114503437A (zh) * 2019-09-24 2022-05-13 美国亚德诺半导体公司 提高△-σ模数转换器中过量环路延迟补偿的效率
CN113517891A (zh) * 2021-09-13 2021-10-19 成都爱旗科技有限公司 一种应用于数模转换器的线性校准系统和方法
CN114978172A (zh) * 2022-06-21 2022-08-30 西安芯海微电子科技有限公司 一种模数转换电路、控制方法、芯片及电子设备

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114978172A (zh) * 2022-06-21 2022-08-30 西安芯海微电子科技有限公司 一种模数转换电路、控制方法、芯片及电子设备

Also Published As

Publication number Publication date
CN114978172A (zh) 2022-08-30

Similar Documents

Publication Publication Date Title
CN102045067B (zh) 提高逐次逼近adc输出信噪比的转换和校准算法及adc
TWI434517B (zh) 數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存器類比數位轉換器
KR20060052937A (ko) 공간 효율적 저전력 주기적 ａ／ｄ 변환기
CN110880934A (zh) 一种逐次逼近型模数转换器及校准方法
CN109889199B (zh) 一种带斩波稳定的σδ型和sar型混合型adc
WO2016055613A1 (en) Passive analog sample and hold in analog-to-digital converters
WO2023246410A1 (zh) 一种模数转换电路、控制方法、芯片及电子设备
TWI736430B (zh) 雜訊整形類比到數位轉換器、方法及裝置
CN109644002B (zh) 可扩展的随机逐次逼近寄存器模数转换器
CN104682958B (zh) 一种带噪声整形的并行逐次逼近模数转换器
Gao et al. An amplifier-free pipeline-SAR ADC architecture with enhanced speed and energy efficiency
US20060092069A1 (en) Domino asynchronous successive approximation adc
US9197231B1 (en) Systems and methods for data conversion
CN105071811B (zh) 一种提高逐次逼近模数转换器dnl/inl的位循环方法
CN112187265A (zh) 用于电力专用通信网的混合型模数转换器及信号收发装置
US11509320B2 (en) Signal converting apparatus and related method
CN112994699B (zh) 失调校准装置、逐次逼近型模数转换装置及失调校准方法
CN115021756A (zh) 模数转换电路、芯片、模数转换方法和电子设备
TWI703830B (zh) 類比數位轉換裝置及其電容調整方法
US11522556B1 (en) Noise-shaping successive approximation register (SAR) analog-to-digital converter
CN217824933U (zh) 一种模数转换电路、芯片和电子设备
Gu et al. Power efficient SAR ADC with optimized settling technique
Fan et al. A bit cycling method for improving the DNL/INL in successive approximation register (SAR) analog-to-digital converter (ADC)
CN116938248A (zh) 一种模拟数字转换器和提高模拟数字转换器的带宽方法
JP2001168715A (ja) アナログデジタルコンバータ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23826059

Country of ref document: EP

Kind code of ref document: A1