WO2023245667A1 - 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 Download PDF

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Publication number
WO2023245667A1
WO2023245667A1 PCT/CN2022/101292 CN2022101292W WO2023245667A1 WO 2023245667 A1 WO2023245667 A1 WO 2023245667A1 CN 2022101292 W CN2022101292 W CN 2022101292W WO 2023245667 A1 WO2023245667 A1 WO 2023245667A1
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Prior art keywords
signal
driving
node
transistor
terminal
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PCT/CN2022/101292
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English (en)
French (fr)
Inventor
刘伟星
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京东方科技集团股份有限公司
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Priority to CN202280001870.3A priority Critical patent/CN117642805A/zh
Priority to PCT/CN2022/101292 priority patent/WO2023245667A1/zh
Publication of WO2023245667A1 publication Critical patent/WO2023245667A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, a display device and a driving method.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the drive control circuit is usually composed of multiple cascaded shift register units.
  • the first control circuit is configured to control the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal;
  • a second control circuit configured to control signals of at least two driving nodes according to signals of the first node, the second node and the second clock signal terminal;
  • the cascade output circuit is configured to provide a signal of one of the at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal;
  • the driving output circuit is configured to provide a signal of at least one driving node of the at least two driving nodes to a driving output terminal corresponding to the driving node according to the driving selection signal terminal.
  • the driving nodes include M driving nodes, the second clock signal terminals include M second clock signal terminals, and the driving output terminals include M driving output terminals; M is an integer greater than 1;
  • the second control circuit includes M second control circuits; wherein the m-th second control circuit among the M second control circuits corresponds to the m-th driving node among the M driving nodes, and The m-th second control circuit corresponds to the m-th second clock signal terminal among the M second clock signal terminals; and the m-th second control circuit is configured to respond to the m-th second clock signal terminal.
  • a signal of a node provides the signal of the m-th second clock signal terminal to the m-th driving node, and in response to the signal of the second node, provides the signal of the first reference signal terminal to the The mth driving node; 1 ⁇ m ⁇ M, and m is an integer;
  • the cascade output circuit includes M cascade output circuits, and the cascade selection signal terminal includes M cascade selection signal terminals; wherein, the m-th cascade output circuit among the M cascade output circuits is the same as
  • the m-th driving node corresponds to the m-th cascade output circuit and the m-th cascade selection signal terminal among the M cascade selection signal terminals; the m-th cascade output circuit configured to provide the signal of the m-th drive node to the cascade output terminal in response to the signal of the m-th cascade selection signal terminal;
  • the drive output circuit includes M drive output circuits, and the drive selection signal terminals include M drive selection signal terminals; the mth drive output circuit among the M drive output circuits corresponds to the mth drive node. , and the m-th drive output circuit corresponds to the m-th drive selection signal terminal among the M drive selection signal terminals; the m-th drive output circuit is configured to respond to the m-th drive selection The signal of the signal terminal provides the signal of the m-th driving node to the m-th driving output terminal.
  • the m-th cascade output circuit includes: the m-th first transistor;
  • the control electrode of the mth first transistor is coupled to the mth cascade selection signal terminal, and the first electrode of the mth first transistor is coupled to the mth drive node.
  • the second pole of the mth first transistor is coupled to the cascade output terminal.
  • the m-th driving output circuit includes: the m-th second transistor;
  • the control electrode of the m-th second transistor is coupled to the m-th drive selection signal terminal, the first electrode of the m-th second transistor is coupled to the m-th drive node, and the m-th drive selection signal terminal is coupled to the control electrode of the m-th second transistor.
  • the second poles of the m second transistors are coupled to the driving output terminals.
  • the m-th second control circuit includes: an m-th third transistor, an m-th fourth transistor, and an m-th first capacitor;
  • the control electrode of the m-th third transistor is coupled to the first node, the first electrode of the m-th third transistor is coupled to the m-th second clock signal terminal, and the m-th third transistor is coupled to the first node.
  • the second pole of a third transistor is coupled to the m-th driving node;
  • the control electrode of the mth fourth transistor is coupled to the second node, the first electrode of the mth fourth transistor is coupled to the first reference signal terminal, and the mth fourth transistor is coupled to the first reference signal terminal.
  • the second pole of the transistor is coupled to the m-th driving node;
  • the first electrode plate of the m-th first capacitor is coupled to the first node, and the second electrode plate of the m-th first capacitor is coupled to the m-th driving node.
  • the m-th second control circuit further includes: an m-th fifth transistor; the control electrode of the m-th third transistor passes through the m-th fifth transistor and The first node is coupled; the first pole of the mth fifth transistor is coupled to the first node, and the second pole of the mth fifth transistor is coupled to the mth third transistor.
  • the control electrode of the m-th fifth transistor is coupled to the second reference signal terminal
  • the control electrode of the m-th fifth transistor is coupled to the first clock signal terminal.
  • the first control circuit includes: an input circuit and a node control circuit
  • the input circuit is configured to provide the signal at the input signal terminal to the first node in response to the signal at the first clock signal terminal;
  • the node control circuit is configured to provide a signal from a second reference signal terminal to the second node in response to a signal from the first clock signal terminal, and to provide the first clock signal from the first node in response to a signal from the first node.
  • the signal at the signal terminal is provided to the second node, and in response to the signal at the second node and the first second clock signal terminal, the signal at the first reference signal terminal is provided to the first node.
  • the input circuit includes: a sixth transistor; a control electrode of the sixth transistor is coupled to the first clock signal terminal, and a first electrode of the sixth transistor is coupled to the first clock signal terminal.
  • the input signal terminal is coupled, and the second pole of the sixth transistor is coupled to the first node;
  • the node control circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor; wherein the control electrode of the seventh transistor is coupled to the first clock signal terminal, and the The first electrode of the seventh transistor is coupled to the second reference signal terminal, the second electrode of the seventh transistor is coupled to the second node, and the control electrode of the eighth transistor is coupled to the first node.
  • the control pole of the ninth transistor is coupled to The second node is coupled, the first pole of the ninth transistor is coupled to the first reference signal terminal, and the second pole of the ninth transistor is coupled to the first pole of the tenth transistor;
  • the control electrode of the tenth transistor is coupled to the first second clock signal terminal, and the second electrode of the tenth transistor is coupled to the first node; the first electrode plate of the second capacitor Coupled with the second node, the second electrode plate of the second capacitor is coupled with the first reference signal terminal.
  • Embodiments of the present disclosure also provide a gate drive circuit, including a plurality of the above-mentioned shift register units in cascade;
  • the input signal terminal of the first-stage shift register unit is coupled to the frame start signal line;
  • the input signal terminal of the next-stage shift register unit is coupled to the cascade output terminal of the upper-stage shift register unit.
  • Embodiments of the present disclosure also provide a display device, including a display panel; the display panel includes: multiple gate lines, multiple clock signal lines, multiple cascade selection signal lines, multiple drive selection signal lines, and the above-mentioned gate electrodes. Drive circuit;
  • Each driving output terminal of each shift register unit in the gate driving circuit is coupled to the plurality of gate lines in one-to-one correspondence, and one of the shift registers in the gate driving circuit
  • the unit is coupled to the plurality of clock signal lines
  • the cascade selection signal terminal of the shift register unit in the gate drive circuit is coupled to the cascade selection signal line;
  • the drive selection signal terminal of the shift register unit in the gate drive circuit is coupled to the drive selection signal line.
  • the display panel further includes a plurality of pixel units arranged in an array; one row of the pixel units corresponds to one of the shift register units in the gate driving circuit;
  • the pixel unit includes a plurality of sub-pixels of different colors arranged along the column direction, and one row of the sub-pixels is coupled to one of the gate lines;
  • each shift register unit is coupled to the gate line corresponding to the sub-pixel of the same color.
  • M 3, and the pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel arranged sequentially in the column direction;
  • the plurality of clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; wherein, the first clock signal end, the 4k_2th level shift register unit
  • the 1st second clock signal terminal of the 4k-stage shift register unit, the 2nd second clock signal terminal of the 4k_1-stage shift register unit, and the 3rd second clock signal terminal of the 4k-stage shift register unit are all Coupled with the first clock signal line;
  • the third second clock signal terminal of the register unit and the first clock signal terminal of the 4k-stage shift register unit are both coupled to the second clock signal line;
  • the second clock signal terminal of the 4k_3-stage shift register unit The second clock signal terminal, the third second clock signal terminal of the 4k_2-stage shift register unit, the first clock signal terminal of the 4
  • the plurality of cascade selection signal lines include a first cascade selection signal line, a second cascade selection signal line and a third cascade selection signal line; wherein, the first cascade selection signal of each level of shift register unit The terminal is coupled to the first cascade selection signal line, the second cascade selection signal terminal of the shift register unit at each level is coupled to the second cascade selection signal line, and the second cascade selection signal terminal of the shift register unit at each level is coupled to the first cascade selection signal line.
  • Three cascade selection signal terminals are coupled to the third cascade selection signal line;
  • the plurality of drive selection signal lines include a first drive selection signal line, a second drive selection signal line and a third drive selection signal line; wherein the first drive selection signal terminal of the shift register unit at each level is connected to the first drive selection signal line.
  • a drive selection signal line is coupled, the second drive selection signal end of the shift register unit at each level is coupled to the second drive selection signal line, and the third drive selection signal end of the shift register unit at each level is coupled to the second drive selection signal line.
  • the third driving selection signal line is coupled.
  • Embodiments of the present disclosure also provide the above-mentioned driving method of the shift register unit, including:
  • a display frame In the first driving mode, a display frame includes a first input stage, a first output stage and a first reset stage;
  • the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal;
  • the second control circuit controls the signals of the first node and the second node according to the signals of the first node and the second clock signal terminal.
  • the signal of the node and the second clock signal terminal controls the signals of at least two driving nodes;
  • the cascade output circuit provides the signal of the Mth driving node among the at least two driving nodes to the cascade according to the cascade selection signal terminal.
  • the driving output circuit provides the signal of each driving node of the at least two driving nodes to the driving output terminal corresponding to each of the driving nodes according to the driving selection signal terminal;
  • the second control circuit controls the signals of at least two driving nodes according to the signals of the first node and the second clock signal terminal;
  • the cascade output circuit controls the at least two driving nodes according to the cascade selection signal terminal.
  • the signal of the Mth driving node among the two driving nodes is provided to the cascade output terminal;
  • the driving output circuit provides the signal of each driving node of the at least two driving nodes to the corresponding the driving output end of the driving node;
  • the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls at least two driving nodes according to the signal of the second node. signal; the cascade output circuit provides the signal of the Mth drive node among the at least two drive nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit provides the signal of the Mth drive node among the at least two drive nodes to the cascade output terminal according to the drive selection signal terminal.
  • a signal from each of the at least two driving nodes is provided to a driving output corresponding to each of the driving nodes;
  • one display frame includes a second input stage, a second output stage and a second reset stage;
  • the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal;
  • the second control circuit controls the signals of the first node and the second node according to the signals of the first node and the second clock signal terminal.
  • the signal of the node and the second clock signal terminal controls the signals of at least two driving nodes;
  • the cascade output circuit provides the signal of the m-th driving node among the at least two driving nodes to the cascade according to the cascade selection signal terminal.
  • the driving output circuit provides the signal of the m-th driving node among the at least two driving nodes to the corresponding driving output terminal according to the driving selection signal terminal;
  • the second control circuit controls the signals of at least two driving nodes according to the signals of the first node and the second clock signal terminal; the cascade output circuit controls the at least two driving nodes according to the cascade selection signal terminal.
  • the signal of the m-th driving node among the two driving nodes is provided to the cascade output terminal; the driving output circuit provides the signal of the m-th driving node among the at least two driving nodes to the cascade output terminal according to the driving selection signal terminal.
  • the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls at least two driving nodes according to the signal of the second node. signal; the cascade output circuit provides the signal of the m-th drive node among the at least two drive nodes to the cascade output terminal according to the cascade selection signal terminal; the drive output circuit supplies the signal to the cascade output terminal according to the drive selection signal terminal.
  • the signal of the m-th driving node among at least two driving nodes is provided to the corresponding driving output terminal.
  • Embodiments of the present disclosure also provide a driving method for the above-mentioned display device, including:
  • a different first clock signal is loaded on each of the clock signal lines, a gate conduction signal is loaded on each of the drive selection signal lines, and a gate conduction signal is loaded on each of the M-th drive output circuits.
  • the coupled cascade selection signal line is loaded with a gate-on signal, and the remaining cascade selection signal lines are loaded with a gate-off signal to control each of the shift register units to work sequentially, and the first of the at least two drive nodes is
  • the signals of the M driving nodes are provided to the cascade output terminals, and the signals of each of the at least two driving nodes are provided to the driving output terminals corresponding to each of the driving nodes, and the plurality of gates are Line progressive scan;
  • the second clock signal is loaded on each of the clock signal lines
  • the gate conduction signal is loaded on the drive selection signal line coupled to the m-th cascade output circuit
  • the remaining gate turn-on signals are loaded on the second driving mode.
  • the drive selection signal line is loaded with a gate cut-off signal
  • the cascade selection signal line coupled to the m-th drive output circuit is loaded with a gate turn-on signal
  • the remaining cascade selection signal lines are loaded with a gate cut-off signal to control each of the
  • the shift register unit operates sequentially, providing the signal of the m-th driving node among the at least two driving nodes to the cascade output terminal, and providing the signal of the m-th driving node to the corresponding driving output terminal,
  • the plurality of gate lines are interleavedly scanned; wherein the clock cycle of the second clock signal is different from the clock cycle of the first clock signal.
  • the first clock signal line and the third clock signal line are loaded with the same second clock signal
  • the second clock signal line and the fourth clock signal line are loaded with the same second clock signal. Load the same second clock signal, load the gate-on signal to the first cascade selection signal line, and load the gate-off signal to both the second cascade selection signal line and the third cascade selection signal line, and load the gate-off signal to the first cascade selection signal line.
  • the drive selection signal line is loaded with a gate-on signal, and both the second drive selection signal line and the third drive selection signal line are loaded with a gate-off signal to control each of the shift register units to work sequentially, and the first drive node
  • the signal of the first driving node is provided to the cascade output terminal, and the signal of the first driving node is provided to the first driving output terminal, and the gate line coupled to each first color sub-pixel row is scanned; wherein, The second clock signal loaded on the first clock signal line and the second clock signal terminal is different.
  • the clock period of the second clock signal is no greater than 3/2 of the clock period of the first clock signal.
  • different second clock signals are loaded on the first to fourth clock signal lines respectively, and a gate conductor is loaded on the second cascade selection signal line. pass signal, and load the gate-off signal to both the first cascade selection signal line and the third cascade selection signal line, load the gate-on signal to the second drive selection signal line, and load the first drive selection signal line and
  • the third drive selection signal lines are all loaded with gate cut-off signals to control the sequential operation of each shift register unit, provide the signal of the second drive node to the cascade output terminal, and connect the second drive node
  • the signal is provided to the second driving output terminal to scan the gate line coupled to each second color sub-pixel row; wherein the second clock signal has two different clock cycles.
  • the two different clock cycles include a first clock cycle and a second clock cycle; the first clock cycle is not greater than 3/4 of the clock cycle of the first clock signal. , the second clock period is not greater than 9/4 of the clock period of the first clock signal.
  • different second clock signals are loaded on the first to fourth clock signal lines respectively, and a gate conductor is loaded on the third cascade selection signal line. pass signal, and load the gate-off signal to both the first cascade selection signal line and the second cascade selection signal line, load the gate-on signal to the third drive selection signal line, and load the first drive selection signal line and
  • the second drive selection signal lines are all loaded with gate cut-off signals to control the sequential operation of each shift register unit, provide the signal of the third drive node to the cascade output terminal, and connect the third drive node The signal is provided to the third drive output terminal to scan the gate line coupled to each third color sub-pixel row.
  • the second clock period is no greater than three times the clock period of the first clock signal.
  • the maintenance time of the effective level of the second clock signal within one clock cycle is not less than the maintenance time of the effective level of the first clock signal within one clock cycle.
  • the maintenance time of the effective level of the corresponding second clock signal in one clock cycle is longer than the The maintenance time of the effective level of the first clock signal within one clock cycle
  • the duration of the effective level of the corresponding second clock signal in one clock cycle is equal to the duration of the first clock signal in one clock cycle.
  • the duration of the effective level of the corresponding second clock signal in one clock cycle is equal to the duration of the first clock signal in one clock cycle. The duration of the effective level.
  • Figure 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure
  • Figure 2 is another structural schematic diagram of a shift register unit provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of some specific structures of a shift register unit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic flowchart of the shift register unit in the first driving mode provided by an embodiment of the present disclosure
  • Figure 5a is some signal timing diagrams of the shift register unit provided by the embodiment of the present disclosure in the first driving mode
  • Figure 5b is another signal timing diagram of the shift register unit provided by the embodiment of the present disclosure in the first driving mode
  • Figure 6 is a schematic flowchart of the shift register unit in the second driving mode provided by an embodiment of the present disclosure
  • Figure 7a is some signal timing diagrams of the shift register unit provided by the embodiment of the present disclosure in the second driving mode
  • Figure 7b is another signal timing diagram of the shift register unit provided by the embodiment of the present disclosure in the second driving mode
  • Figure 7c is another signal timing diagram of the shift register unit provided by the embodiment of the present disclosure in the second driving mode
  • Figure 8 is another signal timing diagram of the shift register unit provided by the embodiment of the present disclosure in the second driving mode
  • Figure 9 is some further signal timing diagrams of the shift register unit provided by the embodiment of the present disclosure in the second driving mode
  • Figure 10 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of some display devices provided by embodiments of the present disclosure.
  • Figure 12 is a schematic structural diagram of some display panels provided by embodiments of the present disclosure.
  • Figure 13 is another structural schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic flowchart of some display devices provided by embodiments of the present disclosure.
  • Figure 15 is some signal timing diagrams of the display device in the first driving mode according to the embodiment of the present disclosure.
  • Figure 16a is some signal timing diagrams of the display device in the second driving mode according to the embodiment of the present disclosure.
  • Figure 16b is another signal timing diagram of the display device in the second driving mode according to the embodiment of the present disclosure.
  • Figure 16c is another signal timing diagram of the display device in the second driving mode according to the embodiment of the present disclosure.
  • Figure 17a is another signal timing diagram of the display device in the second driving mode according to the embodiment of the present disclosure.
  • Figure 17b is another signal timing diagram of the display device in the second driving mode according to the embodiment of the present disclosure.
  • Figure 18a is another signal timing diagram of the display device in the second driving mode according to the embodiment of the present disclosure.
  • FIG. 18b is another signal timing diagram of the display device in the second driving mode according to the embodiment of the present disclosure.
  • the shift register unit provided by the embodiment of the present disclosure, as shown in Figure 1, may include:
  • the first control circuit 01 is configured to control the signals of the first node N1 and the second node N2 according to the signals of the input signal terminal INP and the first clock signal terminal CK1;
  • the second control circuit 02 is configured to control signals of at least two driving nodes N0_1 to N0_3 (taking three driving nodes as an example in Figure 1) according to the signals of the first node N1, the second node N2 and the second clock signal terminal. ;
  • the cascade output circuit 03 is configured to drive the signal of at least one of the two drive nodes N0_1 to N0_3 according to the cascade selection signal terminals JX_1 to JX_3 (taking three cascade selection signal terminals as an example in Figure 1). Provided to the cascade output terminal JO;
  • the drive output circuit 04 is configured to drive at least two drive nodes N0_1 to N0_3 (take three drive nodes as an example in Figure 1) according to the drive selection signal terminals GX_1 ⁇ GX_3 (in Figure 1, three drive selection signal terminals are taken as an example).
  • the signal of at least one driving node in the example is provided to the driving output terminals GO_1 ⁇ GO_3 of the corresponding driving node (three driving output terminals are taken as an example in Figure 1).
  • the shift register unit provided by the embodiment of the present disclosure, through the cooperation of the first control circuit, the second control circuit, the cascade output circuit and the drive output circuit, can select the signal of one drive node from the signals of multiple drive nodes to provide Give the cascade output terminal JO as a cascade signal output to input the corresponding signal to the input signal terminal of the next stage shift register unit.
  • the shift register unit in the embodiment of the present disclosure can be coupled to multiple gate lines, so that the signal of at least one driving node is selected from the signals of the multiple driving nodes to provide Give the drive output terminal as a gate scan signal output to input a corresponding gate scan signal to at least one of the coupled gate lines to realize a shift register unit driving the coupled gate lines or Driving one of the coupled gate lines.
  • the shift register unit in the embodiment of the present disclosure can be coupled to multiple gate lines, compared with one gate line connecting one shift register unit, the number of shift register units provided in the display panel can be reduced, thereby Enable the display panel to achieve a narrow bezel design.
  • the driving nodes may include M driving nodes
  • the second clock signal terminals may include M second clock signal terminals
  • the driving output terminals may include M driving output terminals
  • the cascade selection signal terminals may include There are M cascade selection signal terminals
  • the drive selection signal terminals may include M drive selection signal terminals.
  • the second control circuit may include M second control circuits
  • the cascade output circuit may include M cascade output circuits
  • the driving output circuit may include M driving output circuits.
  • the m-th second control circuit among the M second control circuits corresponds to the m-th driving node among the M driving nodes
  • the m-th second control circuit corresponds to the m-th driving node among the M second clock signal terminals.
  • the m second control circuit is configured to respond to the signal of the first node, provide the signal of the m second clock signal terminal to the m th driving node, and, in response to The signal at the second node provides the signal at the first reference signal terminal VREF1 to the m-th driving node.
  • the m-th cascade output circuit among the M cascade output circuits corresponds to the m-th drive node
  • the m-th cascade output circuit corresponds to the m-th cascade selection signal among the M cascade selection signal terminals.
  • the m-th cascade output circuit is configured to provide the signal of the m-th driving node to the cascade output terminal JO in response to the signal of the m-th cascade selection signal terminal.
  • the m-th drive output circuit among the M drive output circuits corresponds to the m-th drive node, and the m-th drive output circuit corresponds to the m-th drive selection signal terminal among the M drive selection signal terminals; the m-th drive output circuit corresponds to the m-th drive selection signal terminal.
  • the driving output circuit is configured to provide the signal of the m-th driving node to the m-th driving output terminal in response to the signal of the m-th driving selection signal terminal.
  • M is an integer greater than 1, 1 ⁇ m ⁇ M, and m is an integer;
  • M 3 as an example for explanation.
  • M can also be set to other values, such as 2, 4, 5, 6 or more, which are not limited here.
  • the driving node may include three driving nodes: the first driving node N0_1, the second driving node N0_2, and the third driving node N0_3.
  • the second clock signal terminal may include three second clock signal terminals: the first second clock signal terminal CK2_1, the second second clock signal terminal CK2_2, and the third second clock signal terminal CK2_3.
  • the driving output terminal may include three driving output terminals: the first driving output terminal GO_1, the second driving output terminal GO_2, and the third driving output terminal GO_3.
  • the cascade selection signal terminal may include three cascade selection signal terminals: the first cascade selection signal terminal JX_1, the second cascade selection signal terminal JX_2, and the third cascade selection signal terminal JX_3.
  • the drive selection signal terminal may include three drive selection signal terminals: the first drive selection signal terminal GX_1, the second drive selection signal terminal GX_2, and the third drive selection signal terminal GX_3.
  • the second control circuit may include three second control circuits: the first second control circuit 02_1, the second second control circuit 02_2, and the third second control circuit 02_3.
  • the cascade output circuit may include three cascade output circuits: the first cascade output circuit 03_1, the second cascade output circuit 03_2, and the third cascade output circuit 03_3.
  • the driving output circuit may include three driving output circuits: the first driving output circuit 04_1, the second driving output circuit 04_2, and the third driving output circuit 04_3.
  • the first second control circuit 02_1 is provided correspondingly to the first drive node N0_1 and the first second clock signal terminal CK2_1, and the first second control circuit 02_1 is configured to provide the signal of the first second clock signal terminal CK2_1 to the first driving node N0_1 in response to the signal of the first node N1, and to provide the first reference signal in response to the signal of the second node N2.
  • the signal at terminal VREF1 is provided to the first drive node N0_1.
  • the first cascade output circuit 03_1 corresponds to the first drive node N0_1 and the first cascade selection signal terminal JX_1, and the first cascade output circuit 03_1 is configured to respond to the first cascade selection signal
  • the signal of terminal JX_1 provides the signal of the first drive node N0_1 to the cascade output terminal JO.
  • the first drive output circuit 04_1 corresponds to the first drive node N0_1 and the first drive selection signal terminal GX_1, and the first drive output circuit 04_1 is configured to respond to the signal of the first drive selection signal terminal GX_1 , providing the signal of the first driving node N0_1 to the first driving output terminal GO_1.
  • the second second control circuit 02_2 is provided correspondingly to the second drive node N0_2 and the second second clock signal terminal CK2_2, and the second second control circuit 02_2 is configured to provide the signal of the second clock signal terminal CK2_2 to the second driving node N0_2 in response to the signal of the first node N1, and to provide the first reference signal in response to the signal of the second node N2.
  • the signal at terminal VREF1 is provided to the second drive node N0_2.
  • the second cascade output circuit 03_2 corresponds to the second drive node N0_2 and the second cascade selection signal terminal JX_2, and the second cascade output circuit 03_2 is configured to respond to the second cascade selection signal
  • the signal of terminal JX_2 provides the signal of the second drive node N0_2 to the cascade output terminal JO.
  • the second drive output circuit 04_2 corresponds to the second drive node N0_2 and the second drive selection signal terminal GX_2, and the second drive output circuit 04_2 is configured to respond to the signal of the second drive selection signal terminal GX_2 , providing the signal of the second drive node N0_2 to the second drive output terminal GO_2.
  • the third second control circuit 02_3 is configured corresponding to the third drive node N0_3 and the third second clock signal terminal CK2_3, and the third second control circuit 02_3 is configured to provide the signal of the third second clock signal terminal CK2_3 to the third driving node N0_3 in response to the signal of the first node N1, and to provide the first reference signal in response to the signal of the second node N2.
  • the signal at terminal VREF1 is provided to the third drive node N0_3.
  • the third cascade output circuit 03_3 corresponds to the third drive node N0_3 and the third cascade selection signal terminal JX_3, and the third cascade output circuit 03_3 is configured to respond to the third cascade selection signal
  • the signal of terminal JX_3 provides the signal of the third drive node N0_3 to the cascade output terminal JO.
  • the third drive output circuit 04_3 corresponds to the third drive node N0_3 and the third drive selection signal terminal GX_3, and the third drive output circuit 04_3 is configured to respond to the signal of the third drive selection signal terminal GX_3 , providing the signal of the third drive node N0_3 to the third drive output terminal GO_3.
  • the first control circuit 01 may include: an input circuit 011 and a node control circuit 012.
  • the input circuit 011 is configured to provide the signal of the input signal terminal INP to the first node N1 in response to the signal of the first clock signal terminal CK1.
  • the node control circuit 012 is configured to provide the signal of the second reference signal terminal VREF2 to the second node N2 in response to the signal of the first clock signal terminal CK1, and to provide the signal of the first clock signal terminal CK1 to the second node N2 in response to the signal of the first node N1.
  • the signal is provided to the second node N2, and in response to the signal of the second node N2 and the first second clock signal terminal CK2_1, the signal of the first reference signal terminal VREF1 is provided to the first node N1.
  • the first cascade output circuit 03_1 may include: the first first transistor M1_1.
  • the control electrode of the first first transistor M1_1 is coupled to the first cascade selection signal terminal JX_1
  • the first electrode of the first first transistor M1_1 is coupled to the first drive node N0_1
  • the first The second pole of a transistor M1_1 is coupled to the cascade output terminal JO.
  • the first first transistor M1_1 may be turned on when the signal of the first cascade selection signal terminal JX_1 is at a valid level, and turned off when the signal of the first cascade selection signal terminal JX_1 is at an inactive level.
  • the first first transistor M1_1 may be an N-type transistor, then the effective level of the signal at the first cascade selection signal terminal JX_1 is high level and the inactive level is low level.
  • the first first transistor M1_1 may be a P-type transistor, so the effective level of the signal at the first cascade selection signal terminal JX_1 is low level and the inactive level is high level.
  • the second cascade output circuit 03_2 may include: a second first transistor M1_2.
  • the control electrode of the second first transistor M1_2 is coupled to the second cascade selection signal terminal JX_2
  • the first electrode of the second first transistor M1_2 is coupled to the second drive node N0_2
  • the second first transistor M1_2 is coupled to the second drive node N0_2.
  • the second pole of a transistor M1_2 is coupled to the cascade output terminal JO.
  • the second first transistor M1_2 may be turned on when the signal of the second cascade selection signal terminal JX_2 is at a valid level, and turned off when the signal of the second cascade selection signal terminal JX_2 is at an inactive level.
  • the second first transistor M1_2 can be an N-type transistor, then the effective level of the signal at the second cascade selection signal terminal JX_2 is high level and the inactive level is low level.
  • the second first transistor M1_2 can be a P-type transistor, then the effective level of the signal at the second cascade selection signal terminal JX_2 is low level and the inactive level is high level.
  • the third cascade output circuit 03_3 may include: a third first transistor M1_3.
  • the control electrode of the third first transistor M1_3 is coupled to the third cascade selection signal terminal JX_3
  • the first electrode of the third first transistor M1_3 is coupled to the third drive node N0_3
  • the third first transistor M1_3 is coupled to the third drive node N0_3.
  • the second pole of a transistor M1_3 is coupled to the cascade output terminal JO.
  • the third first transistor M1_3 may be turned on when the signal of the third cascade selection signal terminal JX_3 is at a valid level, and turned off when the signal of the third cascade selection signal terminal JX_3 is at an inactive level.
  • the third first transistor M1_3 may be an N-type transistor, then the effective level of the signal at the third cascade selection signal terminal JX_3 is high level and the inactive level is low level.
  • the third first transistor M1_3 may be a P-type transistor, then the effective level of the signal at the third cascade selection signal terminal JX_3 is low level and the inactive level is high level.
  • the first driving output circuit 04_1 may include: a first second transistor M2_1.
  • the control electrode of the first second transistor M2_1 is coupled to the first driving selection signal terminal GX_1
  • the first electrode of the first second transistor M2_1 is coupled to the first driving node N0_1
  • the first second transistor M2_1 is coupled to the first driving node N0_1.
  • the second pole of the transistor M2_1 is coupled to the driving output terminal.
  • the first second transistor M2_1 may be turned on when the signal of the first driving selection signal terminal GX_1 is at a valid level, and turned off when the signal of the first driving selection signal terminal GX_1 is at an inactive level.
  • the first second transistor M2_1 can be an N-type transistor, then the effective level of the signal of the first driving selection signal terminal GX_1 is high level and the inactive level is low level.
  • the first second transistor M2_1 may be a P-type transistor, so the effective level of the signal at the first drive selection signal terminal GX_1 is low level and the inactive level is high level.
  • the second driving output circuit 04_2 may include: a second second transistor M2_2.
  • the control electrode of the second second transistor M2_2 is coupled to the second drive selection signal terminal GX_2
  • the first electrode of the second second transistor M2_2 is coupled to the second drive node N0_2
  • the second second transistor M2_2 is coupled to the second drive selection signal terminal GX_2.
  • the second pole of the transistor M2_2 is coupled to the driving output terminal.
  • the second second transistor M2_2 may be turned on when the signal of the second driving selection signal terminal GX_2 is at a valid level, and turned off when the signal of the second driving selection signal terminal GX_2 is at an inactive level.
  • the second second transistor M2_2 can be an N-type transistor, then the effective level of the signal of the second driving selection signal terminal GX_2 is high level and the inactive level is low level.
  • the second second transistor M2_2 may be a P-type transistor, so the effective level of the signal at the second drive selection signal terminal GX_2 is low level and the inactive level is high level.
  • the third driving output circuit 04_3 may include: a third second transistor M2_3.
  • the control electrode of the third second transistor M2_3 is coupled to the third drive selection signal terminal GX_3
  • the first electrode of the third second transistor M2_3 is coupled to the third drive node N0_3
  • the third second transistor M2_3 is coupled to the third drive selection signal terminal GX_3.
  • the second pole of the transistor M2_3 is coupled to the driving output terminal.
  • the third second transistor M2_3 may be turned on when the signal of the third driving selection signal terminal GX_3 is at a valid level, and turned off when the signal of the third driving selection signal terminal GX_3 is at an invalid level.
  • the third second transistor M2_3 can be an N-type transistor, then the effective level of the signal of the third driving selection signal terminal GX_3 is high level and the inactive level is low level.
  • the third second transistor M2_3 may be a P-type transistor, then the effective level of the signal of the third driving selection signal terminal GX_3 is low level and the inactive level is high level.
  • the first second control circuit 02_1 may include: a first third transistor M3_1, a first fourth transistor M4_1, and a first first capacitor C1_1.
  • the control electrode of the first third transistor M3_1 is coupled to the first node N1
  • the first electrode of the first third transistor M3_1 is coupled to the first second clock signal terminal CK2_1
  • the control electrode of the first third transistor M3_1 is coupled to the first second clock signal terminal CK2_1.
  • the second pole of M3_1 is coupled to the first driving node N0_1.
  • the control electrode of the first fourth transistor M4_1 is coupled to the second node N2, the first electrode of the first fourth transistor M4_1 is coupled to the first reference signal terminal VREF1, and the second electrode of the first fourth transistor M4_1 Coupled with the first drive node N0_1.
  • the first electrode plate of the first first capacitor C1_1 is coupled to the first node N1, and the second electrode plate of the first first capacitor C1_1 is coupled to the first driving node N0_1.
  • the first third transistor M3_1 may be turned on when the signal of the first node N1 is at a valid level, and turned off when the signal of the first node N1 is at an inactive level.
  • the first third transistor M3_1 may be an N-type transistor, so the effective level of the signal at the first node N1 is high level and the inactive level is low level.
  • the first third transistor M3_1 may be a P-type transistor, then the effective level of the signal at the first node N1 is low level and the inactive level is high level.
  • the first fourth transistor M4_1 may be turned on when the signal of the second node N2 is at a valid level, and turned off when the signal of the second node N2 is at an inactive level.
  • the first fourth transistor M4_1 may be an N-type transistor, then the effective level of the signal at the second node N2 is high level and the inactive level is low level.
  • the first fourth transistor M4_1 may be a P-type transistor, so the effective level of the signal at the second node N2 is low level and the inactive level is high level. And, the first first capacitor C1_1 can keep the voltage on its two electrode plates stable.
  • the second second control circuit 02_2 may include: a second third transistor M3_2, a second fourth transistor M4_2, and a second first capacitor C1_2.
  • the control electrode of the second third transistor M3_2 is coupled to the first node N1
  • the first electrode of the second third transistor M3_2 is coupled to the second second clock signal terminal CK2_2
  • the second third transistor M3_2 has a control electrode coupled to the first node N1.
  • the second pole of M3_2 is coupled to the second driving node N0_2.
  • the control electrode of the second fourth transistor M4_2 is coupled to the second node N2, the first electrode of the second fourth transistor M4_2 is coupled to the first reference signal terminal VREF1, and the second electrode of the second fourth transistor M4_2 Coupled with the second drive node N0_2.
  • the first electrode plate of the second first capacitor C1_2 is coupled to the first node N1, and the second electrode plate of the second first capacitor C1_2 is coupled to the second driving node N0_2.
  • the second third transistor M3_2 may be turned on when the signal of the first node N1 is at a valid level, and turned off when the signal of the first node N1 is at an inactive level.
  • the second third transistor M3_2 may be an N-type transistor, so the effective level of the signal at the first node N1 is high level and the inactive level is low level.
  • the second third transistor M3_2 may be a P-type transistor, so the effective level of the signal at the first node N1 is low level and the inactive level is high level.
  • the second fourth transistor M4_2 may be turned on when the signal of the second node N2 is at a valid level, and turned off when the signal of the second node N2 is at an inactive level.
  • the second fourth transistor M4_2 may be an N-type transistor, so the effective level of the signal at the second node N2 is high level and the inactive level is low level.
  • the second fourth transistor M4_2 may be a P-type transistor, so the effective level of the signal at the second node N2 is low level and the inactive level is high level. And, the second first capacitor C1_2 can keep the voltage on its two electrode plates stable.
  • the third second control circuit 02_3 may include: a third third transistor M3_3, a third fourth transistor M4_3, and a third first capacitor C1_3.
  • the control electrode of the third third transistor M3_3 is coupled to the first node N1
  • the first electrode of the third third transistor M3_3 is coupled to the third second clock signal terminal CK2_3
  • the third third transistor M3_3 has a control electrode coupled to the first node N1.
  • the second pole of M3_3 is coupled to the third driving node N0_3.
  • the control electrode of the third fourth transistor M4_3 is coupled to the second node N2, the first electrode of the third fourth transistor M4_3 is coupled to the first reference signal terminal VREF1, and the second electrode of the third fourth transistor M4_3 Coupled with the third drive node N0_3.
  • the first electrode plate of the third first capacitor C1_3 is coupled to the first node N1, and the second electrode plate of the third first capacitor C1_3 is coupled to the third driving node N0_3.
  • the third third transistor M3_3 may be turned on when the signal of the first node N1 is at a valid level, and turned off when the signal of the first node N1 is at an inactive level.
  • the third third transistor M3_3 may be an N-type transistor, so the effective level of the signal at the first node N1 is high level and the inactive level is low level.
  • the third third transistor M3_3 may be a P-type transistor, so the effective level of the signal at the first node N1 is low level and the inactive level is high level.
  • the third fourth transistor M4_3 may be turned on when the signal of the second node N2 is at a valid level, and turned off when the signal of the second node N2 is at an inactive level.
  • the third fourth transistor M4_3 may be an N-type transistor, so the effective level of the signal at the second node N2 is high level and the inactive level is low level.
  • the third and fourth transistor M4_3 may be a P-type transistor, so the effective level of the signal at the second node N2 is low level and the inactive level is high level. And, the third first capacitor C1_3 can keep the voltage on its two electrode plates stable.
  • the first second control circuit 02_1 may also include: a first fifth transistor M5_1.
  • the control electrode of the first third transistor M3_1 is coupled to the first node N1 through the first fifth transistor M5_1.
  • the first electrode of the first fifth transistor M5_1 is coupled to the first node N1, and the second electrode of the first fifth transistor M5_1 is coupled to the control electrode of the first third transistor M3_1.
  • the control electrode of the first fifth transistor M5_1 is coupled to the second reference signal terminal VREF2.
  • the first fifth transistor M5_1 may be an N-type transistor, and the signal at the second reference signal terminal VREF2 is a low-level signal to control the first fifth transistor M5_1 to turn on.
  • the first fifth transistor M5_1 may also be a P-type transistor, and the signal at the second reference signal terminal VREF2 is a high-level signal to control the first fifth transistor M5_1 to turn on.
  • the second second control circuit 02_2 may also include: a second fifth transistor M5_2.
  • the control electrode of the second third transistor M3_2 is coupled to the first node N1 through the second fifth transistor M5_2.
  • the first electrode of the second fifth transistor M5_2 is coupled to the first node N1, and the second electrode of the second fifth transistor M5_2 is coupled to the control electrode of the second third transistor M3_2.
  • the control electrode of the second fifth transistor M5_2 is coupled to the first clock signal terminal CK1.
  • the second fifth transistor M5_2 may be turned on when the signal of the first clock signal terminal CK1 is at a valid level, and turned off when the signal of the first clock signal terminal CK1 is at an inactive level.
  • the second fifth transistor M5_2 may be an N-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is high level and the inactive level is low level.
  • the second fifth transistor M5_2 may also be a P-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is low level and the inactive level is high level.
  • the third second control circuit 02_3 may also include: a third fifth transistor M5_3.
  • the control electrode of the third third transistor M3_3 is coupled to the first node N1 through the third fifth transistor M5_3.
  • the first electrode of the third fifth transistor M5_3 is coupled to the first node N1, and the second electrode of the third fifth transistor M5_3 is coupled to the control electrode of the third third transistor M3_3.
  • the control electrode of the third fifth transistor M5_3 is coupled to the first clock signal terminal CK1.
  • the third fifth transistor M5_3 may be turned on when the signal of the first clock signal terminal CK1 is at a valid level, and turned off when the signal of the first clock signal terminal CK1 is at an inactive level.
  • the third fifth transistor M5_3 may be an N-type transistor, then the effective level of the signal at the first clock signal terminal CK1 is high level and the inactive level is low level.
  • the third and fifth transistor M5_3 may also be a P-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is low level and the inactive level is high level.
  • the input circuit 011 may include: a sixth transistor M6.
  • the control electrode of the sixth transistor M6 is coupled to the first clock signal terminal CK1
  • the first electrode of the sixth transistor M6 is coupled to the input signal terminal INP
  • the second electrode of the sixth transistor M6 is coupled to the first node N1.
  • the sixth transistor M6 may be turned on when the signal of the first clock signal terminal CK1 is at a valid level, and turned off when the signal of the first clock signal terminal CK1 is at an inactive level.
  • the sixth transistor M6 may be an N-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is high level and the inactive level is low level.
  • the sixth transistor M6 may also be a P-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is low level and the inactive level is high level.
  • the node control circuit 012 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and a second capacitor C2.
  • the control electrode of the seventh transistor M7 is coupled to the first clock signal terminal CK1
  • the first electrode of the seventh transistor M7 is coupled to the second reference signal terminal VREF2
  • the second electrode of the seventh transistor M7 is coupled to the second node N2.
  • the control electrode of the eighth transistor M8 is coupled to the first node N1, the first electrode of the eighth transistor M8 is coupled to the first clock signal terminal CK1
  • the second electrode of the eighth transistor M8 is coupled to the second node N2.
  • the control electrode of the ninth transistor M9 is coupled to the second node N2, the first electrode of the ninth transistor M9 is coupled to the first reference signal terminal VREF1, and the second electrode of the ninth transistor M9 is coupled to the first electrode of the tenth transistor M10.
  • One pole is coupled; the control pole of the tenth transistor M10 is coupled to the first second clock signal terminal CK2_1, and the second pole of the tenth transistor M10 is coupled to the first node N1; the first electrode plate of the second capacitor C2 Coupled with the second node N2, the second electrode plate of the second capacitor C2 is coupled with the first reference signal terminal VREF1.
  • the seventh transistor M7 may be turned on when the signal of the first clock signal terminal CK1 is at a valid level, and turned off when the signal of the first clock signal terminal CK1 is at an inactive level.
  • the seventh transistor M7 may be an N-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is high level and the inactive level is low level.
  • the seventh transistor M7 may be a P-type transistor, so the effective level of the signal at the first clock signal terminal CK1 is low level and the inactive level is high level.
  • the eighth transistor M8 may be turned on when the signal of the first node N1 is at a valid level, and turned off when the signal of the first node N1 is at an inactive level.
  • the eighth transistor M8 may be an N-type transistor, so the effective level of the signal at the first node N1 is high level and the inactive level is low level.
  • the eighth transistor M8 may be a P-type transistor, so the effective level of the signal at the first node N1 is low level and the inactive level is high level.
  • the ninth transistor M9 may be turned on when the signal of the second node N2 is at a valid level, and turned off when the signal of the second node N2 is at an inactive level.
  • the ninth transistor M9 may be an N-type transistor, so the effective level of the signal at the second node N2 is high level and the inactive level is low level.
  • the ninth transistor M9 may be a P-type transistor, so the effective level of the signal at the second node N2 is low level and the inactive level is high level.
  • the tenth transistor M10 may be turned on when the signal of the first second clock signal terminal CK2_1 is at a valid level, and turned off when the signal of the first second clock signal terminal CK2_1 is at an inactive level.
  • the tenth transistor M10 may be an N-type transistor, so the effective level of the signal at the first second clock signal terminal CK2_1 is high level and the inactive level is low level.
  • the tenth transistor M10 may be a P-type transistor, so the effective level of the signal at the first second clock signal terminal CK2_1 is low level and the inactive level is high level. And, the second capacitor C2 can keep the voltage on its two electrode plates stable.
  • all transistors may be made of the same material.
  • all transistors may be P-type transistors.
  • the signal at the first reference signal terminal VREF1 is a high-level signal
  • the signal at the second reference signal terminal VREF2 is a low-level signal.
  • all transistors can also be N-type transistors, and the signal at the first reference signal terminal VREF1 is a low-level signal, and the signal at the second reference signal terminal VREF2 is a high-level signal, which is not limited here.
  • the transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here.
  • the control electrodes of these transistors serve as their gates.
  • the first electrode and the second electrode of these transistors can be used as the source or drain of the transistor, and the second electrode can be used as the drain or source of the transistor. No limitation is made here.
  • the above-mentioned shift register unit provided by the embodiment of the present disclosure can implement two driving modes: a first driving mode and a second driving mode.
  • the first driving mode the signal of each driving node can be provided to the driving output terminal corresponding to each driving node, so that each driving output terminal outputs a signal.
  • the second driving mode the signal of one driving node among the plurality of driving nodes can be provided to the corresponding driving output terminal, so that only one driving output terminal outputs a signal.
  • the driving method of the above-mentioned shift register unit may include: in the first driving mode, a display frame may include a first input stage T11, a first output stage T12 and a first Reset phase T13;
  • the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal;
  • the second control circuit controls the signals of the first node and the second node according to the signals of the first node, the second node and the first clock signal terminal.
  • the signal of the second clock signal terminal controls the signals of at least two driving nodes;
  • the cascade output circuit provides the signal of the Mth driving node of at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal;
  • the driving output The circuit provides the signal of each driving node of the at least two driving nodes to the driving output terminal corresponding to each driving node according to the driving selection signal terminal;
  • the second control circuit controls the signals of at least two driving nodes according to the signals of the first node and the second clock signal terminal;
  • the cascade output circuit controls the signals of at least two driving nodes according to the cascade selection signal terminal.
  • the signal of the Mth driving node in the node is provided to the cascade output terminal;
  • the driving output circuit provides the signal of each driving node of at least two driving nodes to the driving output corresponding to each driving node according to the driving selection signal terminal. end;
  • the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signal of the second node. signal; the cascade output circuit provides the signal of the Mth drive node among at least two drive nodes to the cascade output end according to the cascade selection signal end; the drive output circuit provides the signal of at least two drive nodes to the cascade output end according to the drive selection signal end.
  • the signal of each driving node is provided to the driving output terminal corresponding to each driving node.
  • the signals at the driving selection signal terminal are all low-level signals. Furthermore, the signal at the cascade selection signal terminal corresponding to the Mth driving node coupled to the cascade output circuit is a low-level signal, and the signals at the other cascade selection signal terminals are all high-level signals.
  • the following takes the structure of the shift register unit shown in Figure 3 as an example, combined with the signal timing diagram shown in Figure 5a, to describe the operation of the above-mentioned shift register unit in the first driving mode provided by the embodiment of the present disclosure.
  • the process is described.
  • the first input stage T11, the first output stage T12 and the first reset stage T13 in the signal timing diagram shown in FIG. 5a are mainly selected.
  • the first output stage T12 may include three stages: T121, T122 and T123.
  • ck1 represents the signal of the first clock signal terminal CK1
  • ck2_1 represents the signal of the first second clock signal terminal CK2_1
  • ck2_2 represents the signal of the second second clock signal terminal CK2_2
  • ck2_3 represents the signal of the third second clock signal terminal CK2_3
  • n0_1 represents the signal of the first driving node N0_1
  • n0_2 represents the signal of the second driving node N0_2
  • n0_3 represents the signal of the third driving node N0_3
  • go_1 represents the signal of the third driving node N0_3.
  • the signal of 1 driver output terminal GO_1, go_2 represents the signal of the second driver output terminal GO_2, go_3 represents the signal of the third driver output terminal GO_3, and jo represents the signal of the cascade output terminal JO.
  • the signals from the first drive selection signal terminal GX_1 to the third drive selection signal terminal GX_3 are all low-level signals.
  • the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the low-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the low-level signal ck1 to the second node N2, so that the signal of the second node N2 is a low-level signal.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, and further makes the signal of the second node N2 a low-level signal to control the first fourth transistor M4_1,
  • the second fourth transistor M4_2 and the third fourth transistor M4_3 are both turned on.
  • the first fourth transistor M4_1 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a high-level signal.
  • the second fourth transistor M4_2 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a high-level signal.
  • the turned-on third fourth transistor M4_3 provides the high-level signal of the first reference signal terminal VREF1 to the third driving node N0_3, so that the signal of the third driving node N0_3 is a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on.
  • the first third transistor M3_1 is turned on to provide the high-level signal of the signal ck2_1 to the first driving node N0_1, further causing the signal of the first driving node N0_1 to be a high-level signal. Since the signal of the first node N1 is a low-level signal and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned on to provide the high-level signal of the signal ck2_2 to the second driving node N0_2, further making the signal of the second driving node N0_2 a high level signal.
  • the third third transistor M3_3 is turned on to provide the high-level signal of the signal ck2_3 to the third driving node N0_3, further making the signal of the third driving node N0_3 a high level signal. Since the signal of the first drive selection signal terminal GX_1 is low level, the first second transistor M2_1 is turned on to provide the high level signal of the first drive node N0_1 to the first drive output terminal GO_1, So that the first drive output terminal GO_1 outputs a high level signal.
  • the second second transistor M2_2 Since the signal of the second driving selection signal terminal GX_2 is low level, the second second transistor M2_2 is turned on to provide the high level signal of the second driving node N0_2 to the second driving output terminal GO_2, So that the second drive output terminal GO_2 outputs a high level signal. Since the signal of the third drive selection signal terminal GX_3 is low level, the third second transistor M2_3 is turned on to provide the high level signal of the third drive node N0_3 to the third drive output terminal GO_3, So that the third drive output terminal GO_3 outputs a high level signal.
  • the third cascade selection signal terminal JX_3 Since the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals, then the third The first transistor M1_3 is turned on, and both the first first transistor M1_1 and the second first transistor M1_2 are turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to be turned off. Therefore, the first node N1 is in a floating state, and due to the action of the first capacitor C1_1, the signal of the first node N1 can be kept as a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal,
  • the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 are controlled to be turned off. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on. Therefore, the first third transistor M3_1 is turned on to provide the low-level signal of the signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a low-level signal.
  • the level of the first node N1 can be further pulled down to completely conduct the first third transistor M3_1 as much as possible, and the low level signal of the signal ck2_1 It can be provided to the first driving node N0_1 with as little voltage loss as possible, so that the signal of the first driving node N0_1 is a low-level signal. Since the signal of the first node N1 is a low-level signal and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned on to provide the high-level signal of the signal ck2_2 to the second driving node N0_2, make the signal of the second driving node N0_2 a high level signal.
  • the third third transistor M3_3 is turned on to provide the high-level signal of the signal ck2_3 to the third driving node N0_3, making the signal of the third drive node N0_3 a high level signal. Since the signal of the first drive selection signal terminal GX_1 is low level, the first second transistor M2_1 is turned on to provide the low level signal of the first drive node N0_1 to the first drive output terminal GO_1, So that the first drive output terminal GO_1 outputs a low level signal.
  • the second second transistor M2_2 Since the signal of the second driving selection signal terminal GX_2 is low level, the second second transistor M2_2 is turned on to provide the high level signal of the second driving node N0_2 to the second driving output terminal GO_2, So that the second drive output terminal GO_2 outputs a high level signal. Since the signal of the third drive selection signal terminal GX_3 is low level, the third second transistor M2_3 is turned on to provide the high level signal of the third drive node N0_3 to the third drive output terminal GO_3, So that the third drive output terminal GO_3 outputs a high level signal.
  • the third cascade selection signal terminal JX_3 Since the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals, then the third The first transistor M1_3 is turned on, and both the first first transistor M1_1 and the second first transistor M1_2 are turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to turn off. Therefore, the first node N1 is in a floating state, and due to the action of the first capacitor C1_1, the signal of the first node N1 can be kept as a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal,
  • the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 are controlled to be turned off. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on. Therefore, the first third transistor M3_1 is turned on to provide the high-level signal of the signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a high-level signal.
  • the signal of the control electrode of the second third transistor M3_2 can be kept as a low-level signal, so that the second third transistor M3_2 It is turned on to provide the low-level signal of the signal ck2_2 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a low-level signal.
  • the level of the control electrode of the second third transistor M3_2 can be further pulled down to turn on the second third transistor M3_2 as completely as possible, and the signal ck2_2
  • the low-level signal can be provided to the second driving node N0_2 with as little voltage loss as possible, so that the signal of the second driving node N0_2 is a low-level signal.
  • the level of the control electrode of the third third transistor M3_3 can be kept at a low level, and then the third third transistor M3_3 is turned on to change the high level of the signal ck2_3.
  • the signal is provided to the third driving node N0_3, so that the signal of the third driving node N0_3 is a high level signal. Since the signal of the first drive selection signal terminal GX_1 is low level, the first second transistor M2_1 is turned on to provide the high level signal of the first drive node N0_1 to the first drive output terminal GO_1, So that the first drive output terminal GO_1 outputs a high level signal. Since the signal of the second drive selection signal terminal GX_2 is low level, the second second transistor M2_2 is turned on to provide the low level signal of the second drive node N0_2 to the second drive output terminal GO_2, So that the second drive output terminal GO_2 outputs a low level signal.
  • the third second transistor M2_3 Since the signal of the third drive selection signal terminal GX_3 is low level, the third second transistor M2_3 is turned on to provide the high level signal of the third drive node N0_3 to the third drive output terminal GO_3, So that the third drive output terminal GO_3 outputs a high level signal. Since the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals, then the third The first transistor M1_3 is turned on, and both the first first transistor M1_1 and the second first transistor M1_2 are turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to turn off. Therefore, the first node N1 is in a floating state, and due to the action of the first capacitor C1_1, the signal of the first node N1 can be kept as a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal,
  • the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 are controlled to be turned off. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on. Therefore, the first third transistor M3_1 is turned on to provide the high-level signal of the signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a high-level signal.
  • the signal of the control electrode of the second third transistor M3_2 can be kept as a low-level signal, so that the second third transistor M3_2 It is turned on to provide the high-level signal of the signal ck2_2 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a high-level signal. Due to the action of the third first capacitor C1_3, the level of the control electrode of the third third transistor M3_3 can be kept at a low level, and then the third third transistor M3_3 is turned on to change the low level of the signal ck2_3.
  • the signal is provided to the third driving node N0_3, so that the signal of the third driving node N0_3 is a low level signal. Due to the bootstrap effect of the third first capacitor C1_3, the level of the control electrode of the third third transistor M3_3 can be further pulled down to completely conduct the third third transistor M3_3 as much as possible, and the signal ck2_3 The low-level signal can be provided to the third driving node N0_3 with as little voltage loss as possible, so that the signal of the third driving node N0_3 is a low-level signal.
  • the first second transistor M2_1 Since the signal of the first drive selection signal terminal GX_1 is low level, the first second transistor M2_1 is turned on to provide the high level signal of the first drive node N0_1 to the first drive output terminal GO_1, So that the first drive output terminal GO_1 outputs a high level signal. Since the signal of the second driving selection signal terminal GX_2 is low level, the second second transistor M2_2 is turned on to provide the high level signal of the second driving node N0_2 to the second driving output terminal GO_2, So that the second drive output terminal GO_2 outputs a high level signal.
  • the third second transistor M2_3 Since the signal of the third drive selection signal terminal GX_3 is low level, the third second transistor M2_3 is turned on to provide the low level signal of the third drive node N0_3 to the third drive output terminal GO_3, So that the third drive output terminal GO_3 outputs a low level signal. Since the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals, then the third The first transistor M1_3 is turned on, and both the first first transistor M1_1 and the second first transistor M1_2 are turned off. The turned-on third first transistor M1_3 provides the low-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a low-level signal.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the high-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a high-level signal.
  • the eighth transistor M8 can be turned off under the control of the high-level signal of the first node N1.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is a low-level signal to control the first fourth transistor M4_1 and the second node N2.
  • Both the two fourth transistors M4_2 and the third fourth transistor M4_3 are turned on.
  • the first fourth transistor M4_1 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a high-level signal.
  • the second fourth transistor M4_2 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a high-level signal.
  • the turned-on third fourth transistor M4_3 provides the high-level signal of the first reference signal terminal VREF1 to the third driving node N0_3, so that the signal of the third driving node N0_3 is a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on. Therefore, the first third transistor M3_1 can be turned off under the control of the high-level signal of the first node N1.
  • the second third transistor M3_2 Since the signal of the first node N1 is a high-level signal and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned off. Since the signal of the first node N1 is a high-level signal and the third fifth transistor M5_3 is turned on, the third third transistor M3_3 is turned off. Since the signal of the first drive selection signal terminal GX_1 is low level, the first second transistor M2_1 is turned on to provide the high level signal of the first drive node N0_1 to the first drive output terminal GO_1, So that the first drive output terminal GO_1 outputs a high level signal.
  • the second second transistor M2_2 Since the signal of the second driving selection signal terminal GX_2 is low level, the second second transistor M2_2 is turned on to provide the high level signal of the second driving node N0_2 to the second driving output terminal GO_2, So that the second drive output terminal GO_2 outputs a high level signal. Since the signal of the third drive selection signal terminal GX_3 is low level, the third second transistor M2_3 is turned on to provide the high level signal of the third drive node N0_3 to the third drive output terminal GO_3, So that the third drive output terminal GO_3 outputs a high level signal.
  • the third cascade selection signal terminal JX_3 Since the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals, then the third The first transistor M1_3 is turned on, and both the first first transistor M1_1 and the second first transistor M1_2 are turned off. The turned-on third first transistor M1_3 provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signals output by the first driving output terminal GO_1 to the third driving output terminal GO_3 are gate scanning signals.
  • the shift register unit can enter the next stage after the signal is stable.
  • the interval length may be 1H.
  • H represents the duration of the low level of a gate-loaded gate scan signal.
  • the first The signals output by the first drive output terminal GO_1 and the third drive output terminal GO_3 have peak voltages.
  • the signal of the third driving output terminal GO_3 changes, due to the coupling effect between the first first capacitor C1_1, the second first capacitor C1_2 and the third first capacitor C1_3, the second driving The signals output by the output terminal GO_2 and the first drive output terminal GO_1 have peak voltages.
  • the embodiment of the present disclosure sets the second fifth transistor M5_2 and the third fifth transistor M5_3, so that the second third fifth transistor M5_2 and the third fifth transistor M5_3 can be set.
  • the control electrode of the transistor M3_2 and the control electrode of the third transistor M3_3 are isolated from other signals, thereby avoiding mutual influence of signals and improving the stability of the output.
  • the following takes the structure of the shift register unit shown in Figure 3 as an example, combined with the signal timing diagram shown in Figure 5b, to analyze the operation of the above-mentioned shift register unit in the first driving mode provided by the embodiment of the present disclosure.
  • the first input stage T11, the first output stage T12 and the first reset stage T13 in the signal timing diagram shown in FIG. 5b are mainly selected.
  • the first output stage T12 may include three stages: T121, T122 and T123.
  • the shift register unit shown in Figure 3 is combined with the first input stages T11, T121, T122 and T123 and the first reset stage T13 when operating with the signal timing diagram shown in Figure 5b.
  • the working processes of the first input stages T11, T121, T122 and T123 and the first reset stage T13 when the signal timing diagram shown in Figure 5a is working are basically the same and will not be described again here.
  • the signals output by the first driving output terminal GO_1 to the third driving output terminal GO_3 are gate scanning signals.
  • the above-mentioned holding phase is not provided between two adjacent phases, so that there is no above-mentioned interval duration between the low levels of the gate scanning signals input into the two adjacent gate lines.
  • the refresh time of the shift register unit when the gate lines are scanned line by line in combination with the signal timing diagram shown in Figure 5b is shorter than the scanning time of the shift register unit when the gate lines are scanned line by line based on the signal timing diagram shown in Figure 5a. time, thereby reducing the scanning time of a display frame and thereby increasing the refresh frequency.
  • the shift register unit shown in Figure 3 works in conjunction with the signal timing diagrams shown in Figures 5a and 5b, it can output a gate scanning signal to each gate line to scan these gate lines row by row.
  • the clock period of the signals ck2_1 to ck2_3 shown in FIG. 5a is 8H
  • the clock period of the signals ck2_1 to ck2_3 shown in FIG. 5b is 4H.
  • the driving method of the above-mentioned shift register unit provided by the embodiment of the present disclosure, as shown in Figure 6, may include: in the second driving mode, a display frame may include a second input stage T21, a second output stage T22 and a second Reset phase T23;
  • the first control circuit controls the signals of the first node and the second node according to the signals of the input signal terminal and the first clock signal terminal; the second control circuit controls the signals of the first node and the second node according to the signals of the first node, the second node and the first clock signal terminal.
  • the signal of the second clock signal terminal controls the signals of at least two driving nodes;
  • the cascade output circuit provides the signal of the m-th driving node of at least two driving nodes to the cascade output terminal according to the cascade selection signal terminal;
  • the driving output The circuit provides the signal of the m-th driving node among at least two driving nodes to the corresponding driving output terminal according to the driving selection signal terminal;
  • the second control circuit controls the signals of at least two driving nodes according to the signals of the first node and the second clock signal terminal;
  • the cascade output circuit controls the signals of at least two driving nodes according to the cascade selection signal terminal.
  • the signal of the m-th driving node in the node is provided to the cascade output terminal;
  • the driving output circuit provides the signal of the m-th driving node in at least two driving nodes to the corresponding driving output terminal according to the driving selection signal terminal;
  • the first control circuit controls the signals of the first node and the second node according to the signal of the first clock signal terminal; the second control circuit controls the signals of at least two driving nodes according to the signal of the second node. signal; the cascade output circuit provides the signal of the m-th drive node among at least two drive nodes to the cascade output end according to the cascade selection signal end; the drive output circuit provides the signal of at least two drive nodes to the cascade output end according to the drive selection signal end.
  • the signal of the m-th driving node in is provided to the corresponding driving output terminal.
  • the signal at the cascade selection signal terminal corresponding to the m-th driving node can be a low-level signal, and the remaining cascaded Select the signal at the signal end as a high level signal. Furthermore, the signal at the drive selection signal terminal corresponding to the m-th drive node is a low-level signal, and the signals at the other drive selection signal terminals are high-level signals.
  • the first driving output terminal GO_1 of each stage of the shift register unit in the second driving mode, can be controlled to output a gate scanning signal to the coupled gate line to achieve interlaced scanning.
  • the following takes the structure of the shift register unit shown in Figure 3 as an example, combined with the signal timing diagram shown in Figure 7a, to describe the operation of the above-mentioned shift register unit in the second driving mode provided by the embodiment of the present disclosure.
  • the process is described.
  • the second input stage T21, the second output stage T22 and the second reset stage T23 in the signal timing diagram shown in FIG. 7a are mainly selected.
  • inp represents the signal of the input signal terminal INP
  • ck1 represents the signal of the first clock signal terminal CK1
  • ck2_1 represents the signal of the first second clock signal terminal CK2_1
  • ck2_2 represents the signal of the second second clock signal terminal CK2_2
  • ck2_3 represents the signal of the third second clock signal terminal CK2_3
  • n0_1 represents the signal of the first driving node N0_1
  • go_1 represents the signal of the first driving output terminal GO_1
  • jo represents the signal of the cascade output terminal JO.
  • the signal of the first drive selection signal terminal GX_1 is a low-level signal
  • the signals of the second drive selection signal terminal GX_2 and the third drive selection signal terminal GX_3 are high-level signals.
  • the signal of the first cascade selection signal terminal JX_1 is a low-level signal
  • the signals of the second cascade selection signal terminal JX_2 and the third cascade selection signal terminal JX_3 are both high-level signals. Since the signals of the second drive selection signal terminal GX_2 and the third drive selection signal terminal GX_3 are both high-level signals, in this embodiment, the second second transistor M2_2 and the third second transistor M2_3 are both turned off. of.
  • the second first transistor M1_2 and the third first transistor M1_3 are all cut-off. Therefore, in this embodiment, only the signal of the first driving node N0_1 can be output to the cascade output terminal JO and the first driving output terminal GO_1, while the signals of the second driving node N0_2 and the third driving node N0_3 All are not output. Therefore, the change process of the signal of the second driving node N0_2 and the third driving node N0_3 has no impact on this embodiment.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the low-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the low-level signal ck1 to the second node N2, so that the signal of the second node N2 is a low-level signal.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, and further makes the signal of the second node N2 a low-level signal to control the first fourth transistor M4_1,
  • the second fourth transistor M4_2 and the third fourth transistor M4_3 are both turned on.
  • the first fourth transistor M4_1 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on.
  • the first third transistor M3_1 is turned on to provide the high-level signal of the signal ck2_1 to the first driving node N0_1, further causing the signal of the first driving node N0_1 to be a high-level signal.
  • the first second transistor M2_1 that is turned on provides the high-level signal of the first driving node N0_1 to the first driving output terminal GO_1, so that the first driving output terminal GO_1 outputs a high-level signal.
  • the first first transistor M1_1 that is turned on provides the high-level signal of the first driving node N0_1 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to be turned off. Therefore, the first node N1 is in a floating state, and due to the action of the first capacitor C1_1, the signal of the first node N1 can be kept as a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal,
  • the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 are controlled to be turned off. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on. Therefore, the first third transistor M3_1 is turned on to provide the low-level signal of the signal ck2_1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a low-level signal.
  • the level of the first node N1 can be further pulled down to completely conduct the first third transistor M3_1 as much as possible, and the low level signal of the signal ck2_1 It can be provided to the first driving node N0_1 with as little voltage loss as possible, so that the signal of the first driving node N0_1 is a low-level signal.
  • the first second transistor M2_1 that is turned on provides the low-level signal of the first driving node N0_1 to the first driving output terminal GO_1, so that the first driving output terminal GO_1 outputs a low-level signal.
  • the first first transistor M1_1 that is turned on provides the low-level signal of the first driving node N0_1 to the cascade output terminal JO, so that the cascade output terminal JO outputs a low-level signal.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the high-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a high-level signal.
  • the eighth transistor M8 can be turned off under the control of the high-level signal of the first node N1.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is a low-level signal to control the first fourth transistor M4_1 and the second node N2.
  • Both the two fourth transistors M4_2 and the third fourth transistor M4_3 are turned on.
  • the first fourth transistor M4_1 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the first driving node N0_1, so that the signal of the first driving node N0_1 is a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on.
  • the first third transistor M3_1 can be turned off under the control of the high level signal of the first node N1. Furthermore, the first second transistor M2_1 that is turned on provides the high-level signal of the first driving node N0_1 to the first driving output terminal GO_1, so that the first driving output terminal GO_1 outputs a high-level signal. And, the first first transistor M1_1 that is turned on provides the high-level signal of the first driving node N0_1 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal output by the first drive output terminal GO_1 is the gate scanning signal.
  • the shift register unit can enter the next stage after the signal is stable. In this way, there is an interval between the low levels of the gate scanning signals output by the first drive output terminal GO_1 of the adjacent two-stage shift register units.
  • the interval length may be 5H.
  • the following takes the structure of the shift register unit shown in Figure 3 as an example, combined with the signal timing diagram shown in Figure 7b, to analyze the operation of the above-mentioned shift register unit in the second driving mode provided by the embodiment of the present disclosure.
  • Other working processes are described.
  • the second input stage T21, the second output stage T22 and the second reset stage T23 in the signal timing diagram shown in FIG. 7b are mainly selected.
  • the shift register unit shown in Figure 3 combines the second input stage T21, the second output stage T22 and the second reset stage T23 when working with the signal timing diagram shown in Figure 7b, and the shift register shown in Figure 3
  • the working processes of the second input stage T21, the second output stage T22 and the second reset stage T23 when the unit operates in conjunction with the signal timing diagram shown in Figure 7a are basically the same and will not be described again here.
  • the signal output by the first drive output terminal GO_1 is the gate scanning signal.
  • the shift register unit can enter the next stage after the signal is stable. In this way, there is an interval between the low levels of the gate scanning signals output by the first drive output terminal GO_1 of the adjacent two-stage shift register units.
  • the interval length may be 1H.
  • the following takes the structure of the shift register unit shown in Figure 3 as an example, combined with the signal timing diagram shown in Figure 7c, to analyze the operation of the above-mentioned shift register unit in the second driving mode provided by the embodiment of the present disclosure.
  • Other working processes are described.
  • the second input stage T21, the second output stage T22 and the second reset stage T23 in the signal timing diagram shown in FIG. 7b are mainly selected.
  • the shift register unit shown in Figure 3 combines the second input stage T21, the second output stage T22 and the second reset stage T23 when working with the signal timing diagram shown in Figure 7c, and the shift register shown in Figure 3
  • the working processes of the second input stage T21, the second output stage T22 and the second reset stage T23 when the unit operates in conjunction with the signal timing diagram shown in Figure 7a are basically the same and will not be described again here.
  • the signal output by the first drive output terminal GO_1 is the gate scanning signal.
  • the above-mentioned holding stage is not set between two adjacent stages, so that there is no gap between the low levels of the gate scanning signal output by the first driving output terminal GO_1 of the adjacent two-stage shift register unit. with the above interval duration.
  • the refresh time of the shift register unit when interlaced scanning of gate lines is smaller than the refresh time of the shift register unit when interlaced scanning of gate lines is combined with the signal timing diagram shown in Figure 7b. This can reduce the scanning time of a display frame and thus increase the refresh frequency.
  • the shift register unit shown in Figure 3 operates in conjunction with the signal timing diagrams shown in Figures 7a to 7c, it is possible to couple the first driving output terminal GO_1 of each stage of the shift register unit.
  • the gate lines output gate scan signals to scan only these gate lines.
  • the clock period of the signals ck2_1 to ck2_3 shown in FIG. 7a is 12H
  • the clock period of the signals ck2_1 to ck2_3 shown in FIG. 7b is 4H
  • the clock period of the signals ck2_1 to ck2_3 shown in FIG. 7c is 2H.
  • the second driving output terminal GO_2 of each stage of the shift register unit in the second driving mode, can be controlled to output a gate scanning signal to the coupled gate line to achieve interlaced scanning.
  • the following takes the structure of the shift register unit shown in FIG. 3 as an example, and combines the signal timing diagram shown in FIG. 8 to describe the operation of the above-mentioned shift register unit in the second driving mode provided by the embodiment of the present disclosure. The process is described.
  • the second input stage T21, the second output stage T22, and the second reset stage T23 in the signal timing diagram shown in FIG. 8 are mainly selected.
  • inp represents the signal of the input signal terminal INP
  • ck1 represents the signal of the first clock signal terminal CK1
  • ck2_1 represents the signal of the first second clock signal terminal CK2_1
  • ck2_2 represents the signal of the second second clock signal terminal CK2_2
  • ck2_3 represents the signal of the third second clock signal terminal CK2_3
  • n0_2 represents the signal of the second driving node N0_2
  • go_2 represents the signal of the second driving output terminal GO_2
  • jo represents the signal of the cascade output terminal JO.
  • the signal of the second drive selection signal terminal GX_2 is a low-level signal, and the signals of the first drive selection signal terminal GX_1 and the third drive selection signal terminal GX_3 are high-level signals.
  • the signal of the second cascade selection signal terminal JX_2 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the third cascade selection signal terminal JX_3 are both high-level signals. Since the signals of the first drive selection signal terminal GX_1 and the third drive selection signal terminal GX_3 are both high-level signals, in this embodiment, the first second transistor M2_1 and the third second transistor M2_3 are both turned off. of.
  • the first first transistor M1_1 and the third first transistor M1_1 M1_3 are all cut-off. Therefore, in this embodiment, only the signal of the second driving node N0_2 can be output to the cascade output terminal JO and the second driving output terminal GO_2, while the signals of the first driving node N0_1 and the third driving node N0_3 All are not output. Therefore, the change process of the signal of the first driving node N0_1 and the third driving node N0_3 has no impact on this embodiment. Therefore, the change of the signal of the second driving node N0_2 will be described below. The changes in the signals of the first driving node N0_1 and the third driving node N0_3 are no longer explained.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the low-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the low-level signal ck1 to the second node N2, so that the signal of the second node N2 is a low-level signal.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, and further makes the signal of the second node N2 a low-level signal to control the first fourth transistor M4_1,
  • the second fourth transistor M4_2 and the third fourth transistor M4_3 are both turned on.
  • the second fourth transistor M4_2 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on.
  • the second fifth transistor M5_2 is also turned on, which can make the level of the control electrode of the second third transistor M3_2 low, so the second third transistor M3_2 is turned on to turn the high level of the signal ck2_2
  • the level signal is provided to the second driving node N0_2, further causing the signal of the second driving node N0_2 to be a high-level signal.
  • the turned-on second second transistor M2_2 provides the high-level signal of the second driving node N0_2 to the second driving output terminal GO_2, so that the second driving output terminal GO_2 outputs a high-level signal.
  • the second first transistor M1_2 that is turned on provides the high-level signal of the second driving node N0_2 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to turn off. Therefore, the first node N1 is in a floating state, and due to the action of the first capacitor C1_1, the signal of the first node N1 can be kept as a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal,
  • the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 are controlled to be turned off. Due to the action of the second first capacitor C1_2, the level of the control electrode of the second third transistor M3_2 can be kept low, so the second third transistor M3_2 is turned on to turn the low level of the signal ck2_2
  • the signal is provided to the second driving node N0_2, so that the signal of the second driving node N0_2 is a low level signal.
  • the level of the control electrode of the second third transistor M3_2 can be further pulled down to completely conduct the second third transistor M3_2 as much as possible, and the signal The low-level signal of ck2_2 can be provided to the second driving node N0_2 with as little voltage loss as possible, so that the signal of the second driving node N0_2 is a low-level signal.
  • the turned-on second second transistor M2_2 provides the low-level signal of the second driving node N0_2 to the second driving output terminal GO_2, so that the second driving output terminal GO_2 outputs a low-level signal.
  • the second first transistor M1_2 that is turned on provides the low-level signal of the second driving node N0_2 to the cascade output terminal JO, so that the cascade output terminal JO outputs a low-level signal.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the high-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a high-level signal.
  • the eighth transistor M8 can be turned off under the control of the high-level signal of the first node N1.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is a low-level signal to control the first fourth transistor M4_1 and the second node N2.
  • the two fourth transistors M4_2 and the third fourth transistor M4_3 are both turned on.
  • the second fourth transistor M4_2 that is turned on provides the high-level signal of the first reference signal terminal VREF1 to the second driving node N0_2, so that the signal of the second driving node N0_2 is a high-level signal. Since the signal of the first node N1 is a high-level signal and the second fifth transistor M5_2 is turned on, the second third transistor M3_2 is turned off.
  • the turned-on second second transistor M2_2 provides the high-level signal of the second driving node N0_2 to the second driving output terminal GO_2, so that the second driving output terminal GO_2 outputs a high-level signal.
  • the second first transistor M1_2 that is turned on provides the high-level signal of the second driving node N0_2 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal output by the second drive output terminal GO_2 is the gate scanning signal.
  • the shift register unit can enter the next stage after the signal is stable. In this way, there is an interval between the low levels of the gate scanning signals output by the second drive output terminal GO_2 of the adjacent two-stage shift register units.
  • the interval length may be 5H.
  • the clock cycles of the signals ck1, ck2_1, ck2_2, and ck2_3 can be reduced so that the second driving output terminal GO_2 of the adjacent two-stage shift register unit
  • the interval duration between the low levels of the gate scanning signals output by the two drive output terminals GO_2 is reduced, or even has no interval duration, thereby reducing the scanning time of a display frame and thereby increasing the refresh frequency.
  • the third driving output terminal GO_3 of each stage of the shift register unit can be controlled to output a gate scanning signal to the coupled gate line to achieve interlaced scanning.
  • the following takes the structure of the shift register unit shown in FIG. 3 as an example, and combines the signal timing diagram shown in FIG. 9 to describe the operation of the above-mentioned shift register unit in the second driving mode provided by the embodiment of the present disclosure. The process is described.
  • the second input stage T21, the second output stage T22 and the second reset stage T23 in the signal timing diagram shown in FIG. 9 are mainly selected.
  • inp represents the signal of the input signal terminal INP
  • ck1 represents the signal of the first clock signal terminal CK1
  • ck2_1 represents the signal of the first second clock signal terminal CK2_1
  • ck2_2 represents the signal of the second second clock signal terminal CK2_2
  • ck2_3 represents the signal of the third second clock signal terminal CK2_3
  • n0_2 represents the signal of the second driving node N0_2
  • go_2 represents the signal of the second driving output terminal GO_2
  • jo represents the signal of the cascade output terminal JO.
  • the signal of the third drive selection signal terminal GX_3 is a low-level signal, and the signals of the first drive selection signal terminal GX_1 and the second drive selection signal terminal GX_2 are high-level signals.
  • the signal of the third cascade selection signal terminal JX_3 is a low-level signal, and the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals. Since the signals of the first drive selection signal terminal GX_1 and the second drive selection signal terminal GX_2 are both high-level signals, in this embodiment, the first second transistor M2_1 and the second second transistor M2_2 are both turned off. of.
  • the signals of the first cascade selection signal terminal JX_1 and the second cascade selection signal terminal JX_2 are both high-level signals, in this embodiment, the first first transistor M1_1 and the second first transistor M1_1 M1_2 are all cut-off. Therefore, in this embodiment, only the signal of the third driving node N0_3 can be output to the cascade output terminal JO and the third driving output terminal GO_3, while the signals of the first driving node N0_1 and the second driving node N0_2 All are not output. Therefore, the change process of the signal of the first driving node N0_1 and the second driving node N0_2 has no impact on this embodiment. Therefore, the change of the signal of the third driving node N0_3 will be described below. The changes in the signals of the first driving node N0_1 and the second driving node N0_2 are no longer explained.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the low-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the low-level signal ck1 to the second node N2, so that the signal of the second node N2 is a low-level signal.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, and further makes the signal of the second node N2 a low-level signal to control the first fourth transistor M4_1,
  • the second fourth transistor M4_2 and the third fourth transistor M4_3 are both turned on.
  • the turned-on third fourth transistor M4_3 provides the high-level signal of the first reference signal terminal VREF1 to the third driving node N0_3, so that the signal of the third driving node N0_3 is a high-level signal. Since the signal at the second reference signal terminal VREF2 is a low-level signal, the first fifth transistor M5_1 can be controlled to be turned on.
  • the third fifth transistor M5_3 is also turned on, which can make the level of the control electrode of the third third transistor M3_3 low. Therefore, the third third transistor M3_3 is turned on to turn the high level of the signal ck2_3
  • the level signal is provided to the third driving node N0_3, further making the signal of the third driving node N0_3 a high-level signal.
  • the turned-on third second transistor M2_3 provides the high-level signal of the third driving node N0_3 to the third driving output terminal GO_3, so that the third driving output terminal GO_3 outputs a high-level signal.
  • the turned-on third first transistor M1_3 provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal ck1 is a high-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to turn off. Therefore, the first node N1 is in a floating state, and due to the action of the first capacitor C1_1, the signal of the first node N1 can be kept as a low-level signal.
  • the eighth transistor M8 is controlled by the low-level signal of the first node N1 and can be turned on to provide the high-level signal ck1 to the second node N2, so that the signal of the second node N2 is a high-level signal,
  • the first fourth transistor M4_1, the second fourth transistor M4_2, and the third fourth transistor M4_3 are controlled to be turned off. Due to the action of the third first capacitor C1_3, the level of the control electrode of the third third transistor M3_3 can be kept low, so the third third transistor M3_3 is turned on to turn the low level of the signal ck2_3
  • the signal is provided to the third driving node N0_3, so that the signal of the third driving node N0_3 is a low level signal.
  • the level of the control electrode of the third third transistor M3_3 can be further pulled down to completely conduct the third third transistor M3_3 as much as possible, and the signal The low-level signal of ck2_3 can be provided to the third driving node N0_3 with as little voltage loss as possible, so that the signal of the third driving node N0_3 is a low-level signal.
  • the turned-on third second transistor M2_3 provides the low-level signal of the third driving node N0_3 to the third driving output terminal GO_3, so that the third driving output terminal GO_3 outputs a low-level signal.
  • the turned-on third first transistor M1_3 provides the low-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a low-level signal.
  • the signal ck1 is a low-level signal, which can control the sixth transistor M6, the seventh transistor M7, the second fifth transistor M5_2 and the third fifth transistor M5_3 to all be turned on.
  • the turned-on sixth transistor M6 provides the high-level signal of the signal inp to the first node N1, so that the signal of the first node N1 is a high-level signal.
  • the eighth transistor M8 can be turned off under the control of the high-level signal of the first node N1.
  • the turned-on seventh transistor M7 provides the low-level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is a low-level signal to control the first fourth transistor M4_1 and the second node N2.
  • the two fourth transistors M4_2 and the third fourth transistor M4_3 are both turned on.
  • the turned-on third fourth transistor M4_3 provides the high-level signal of the first reference signal terminal VREF1 to the third driving node N0_3, so that the signal of the third driving node N0_3 is a high-level signal. Since the signal of the first node N1 is a high-level signal and the third fifth transistor M5_3 is turned on, the third third transistor M3_3 is turned off.
  • the turned-on third second transistor M2_3 provides the high-level signal of the third driving node N0_3 to the third driving output terminal GO_3, so that the third driving output terminal GO_3 outputs a high-level signal.
  • the third first transistor M1_3 that is turned on provides the high-level signal of the third driving node N0_3 to the cascade output terminal JO, so that the cascade output terminal JO outputs a high-level signal.
  • the signal output by the third drive output terminal GO_3 is the gate scanning signal.
  • the shift register unit can enter the next stage after the signal is stable. In this way, there is an interval between the low levels of the gate scanning signals output by the first drive output terminal GO_1 of the adjacent two-stage shift register units.
  • the interval length may be 5H.
  • the clock cycles of the signals ck1, ck2_1, ck2_2, and ck2_3 can be reduced so that the third drive output terminal GO_3 of the adjacent two-stage shift register unit
  • the interval duration between the low levels of the gate scan signals output by the three drive output terminals GO_3 is reduced, or even has no interval duration, which can reduce the scan time of a display frame and thereby increase the refresh frequency.
  • Embodiments of the present disclosure also provide a gate driving circuit, which may include a plurality of the above-mentioned shift register units in cascade.
  • the input signal terminal of the first-stage shift register unit is coupled to the frame start signal line.
  • the input signal terminal of the next-stage shift register unit is coupled to the cascade output terminal of the upper-stage shift register unit.
  • the signal output by the cascade output terminal of the upper stage shift register unit can be input into the input signal terminal of the next stage shift register unit, so that the cascade signal terminal and the driving signal terminal of the next stage shift register unit can be Corresponding signals can be output.
  • the first-stage shift register unit SR1 The input signal terminal INP is coupled with the frame start signal line STV.
  • the input signal terminal INP of the second-stage shift register unit SR2 is coupled to the cascade output terminal JO of the first-stage shift register unit SR1.
  • the input signal terminal INP of the third-stage shift register unit SR3 is coupled to the cascade output terminal JO of the second-stage shift register unit SR2.
  • the input signal terminal INP of the fourth-stage shift register unit SR4 is coupled to the cascade output terminal JO of the third-stage shift register unit SR3.
  • each shift register unit in the above-mentioned gate driving circuit is the same in function and structure as the above-mentioned shift register unit in the present disclosure, and the repeated details will not be repeated.
  • the first reference signal terminals VREF1 of the shift register units at each level are coupled to the same first reference signal line, and the second reference signal terminals VREF2 of the shift register units at each level are coupled to the same first reference signal line.
  • the second reference signal line is coupled.
  • Embodiments of the present disclosure also provide a display device.
  • the display device may include a display panel 100 and a timing controller 200 .
  • the display panel 100 may include: a plurality of pixel units arranged in an array, a plurality of gate lines GA, a plurality of data lines DA insulated and intersecting with the gate lines GA, and gate drivers respectively coupled to each gate line GA. circuit 110, and a source driving circuit 120 coupled to each data line DA.
  • two source driving circuits 120 may be provided, one source driving circuit 120 is coupled to half of the number of data lines, and the other source driving circuit 120 is coupled to the other half of the number of data lines.
  • there can also be three, four, or more source driving circuits 120 which can be designed and determined according to actual application requirements, and are not limited here.
  • each pixel unit may include multiple sub-pixels SPX.
  • a pixel unit may include a plurality of sub-pixels of different colors arranged along a column direction.
  • the pixel unit may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel arranged sequentially in the column direction. This makes a row of subpixels the same color.
  • the rows of first color sub-pixels, second color sub-pixel rows and third color sub-pixel rows may be repeatedly arranged.
  • the first color sub-pixel, the second color sub-pixel and the third color sub-pixel may be selected from red sub-pixels, green sub-pixels and blue sub-pixels.
  • the first color sub-pixel is a red sub-pixel
  • the second color sub-pixel is a green sub-pixel
  • the third color sub-pixel is a blue sub-pixel.
  • a red sub-pixel row, a green sub-pixel row and a blue sub-pixel can be used Rows are arranged repeatedly to achieve color display by mixing red, green, blue and white.
  • the first row of sub-pixels are red sub-pixels R11-R16
  • the second row of sub-pixels are green sub-pixels G11-G16
  • the third row of sub-pixels are blue sub-pixels B11-B16
  • the fourth row of sub-pixels are blue sub-pixels B11-B16.
  • the sub-pixels in the fifth row are red sub-pixels R21 ⁇ R26
  • the sub-pixels in the fifth row are green sub-pixels G21 ⁇ G26
  • the sub-pixels in the sixth row are blue sub-pixels B21 ⁇ B26
  • the sub-pixels in the seventh row are red sub-pixels R31 ⁇ R36.
  • the eighth row of sub-pixels are green sub-pixels G31 ⁇ G36
  • the ninth row of sub-pixels are blue sub-pixels B31 ⁇ B36
  • the tenth row of sub-pixels are red sub-pixels R41 ⁇ R46
  • the eleventh row of sub-pixels are green sub-pixels G41 ⁇ G46
  • the twelfth row of sub-pixels are blue sub-pixels B41 ⁇ B46.
  • the red sub-pixel R11, the green sub-pixel G11 and the blue sub-pixel B11 are one pixel unit
  • the red sub-pixel R12, the green sub-pixel G12 and the blue sub-pixel B12 are one pixel unit
  • the red sub-pixel R13 and the green sub-pixel G13 and blue sub-pixel B13 are one pixel unit
  • red sub-pixel R14, green sub-pixel G14 and blue sub-pixel B14 are one pixel unit
  • red sub-pixel R15, green sub-pixel G15 and blue sub-pixel B15 are one pixel unit
  • the red sub-pixel R16, the green sub-pixel G16 and the blue sub-pixel B16 are one pixel unit.
  • the luminescent color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.
  • each pixel SPX may include a transistor 11 and a pixel electrode 12 .
  • one row of sub-pixels SPX is coupled to one gate line
  • one column of sub-pixels SPX is coupled to one data line.
  • the gate of the transistor 11 is coupled to the corresponding gate line
  • the source of the transistor 11 is coupled to the corresponding data line
  • the drain of the transistor 11 is coupled to the pixel electrode 12 .
  • the pixel array structure of the present disclosure can also be a double gate structure, that is, two gate lines are provided between two adjacent rows of sub-pixels.
  • This arrangement can reduce the number of data lines by half, that is, some adjacent columns of sub-pixels Data lines are included between pixels, and some adjacent columns of sub-pixels cannot include data lines.
  • the specific sub-pixel arrangement structure and data lines, and the arrangement of the scan lines are not limited.
  • the timing controller 200 can obtain the display data of the picture to be displayed in each display frame, and the timing controller 200 can input a clock signal to the gate drive circuit 110 so that the gate drive circuit 110 can operate according to the input clock. signal, and outputs a gate scanning signal to the gate line GA, thereby scanning the gate line GA to control the conduction of the transistors in the coupled sub-pixels. And, the timing controller 200 inputs corresponding display data to the source driving circuit 120, so that the source driving circuit 120 can input the corresponding data voltage to the coupled data line DA according to the input display data, thereby passing through the sub-pixel. The turned-on transistor inputs the voltage on the data line DA into the sub-pixel to charge the sub-pixel, thereby charging each sub-pixel with the corresponding data voltage to realize the screen display function.
  • the display panel in the embodiment of the present disclosure may be a liquid crystal display panel, an OLED display panel, etc., which is not limited here.
  • a liquid crystal display panel may generally include an upper substrate and a lower substrate of a pair of cells, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate.
  • this voltage difference can form an electric field, causing the liquid crystal molecules to deflect under the action of the electric field.
  • electric fields of different strengths cause different degrees of deflection of liquid crystal molecules, the transmittance of the sub-pixels is different, so that the sub-pixel SPX can achieve different gray-scale brightness, thereby achieving screen display.
  • the gate driving circuit may include a plurality of cascaded shift register units. Each driving output terminal of each shift register unit in the gate driving circuit is coupled to a plurality of gate lines in a one-to-one correspondence, so that a gate scanning signal can be output to the coupled gate through the driving output terminal.
  • the first-stage shift register unit SR1 The first drive output terminal GO_1 is coupled to the gate line GA1, the second drive output terminal GO_2 of the first-stage shift register unit SR1 is coupled to the gate line GA2, and the third drive output terminal GO_2 of the first-stage shift register unit SR1 is coupled to the gate line GA2.
  • the driving output terminal GO_3 is coupled to the gate line GA3.
  • the first driving output terminal GO_1 of the second-stage shift register unit SR2 is coupled to the gate line GA4, and the second driving output terminal GO_2 of the second-stage shift register unit SR2 is coupled to the gate line GA5.
  • the third driving output terminal GO_3 of the bit register unit SR2 is coupled to the gate line GA6.
  • the first driving output terminal GO_1 of the third-stage shift register unit SR3 is coupled to the gate line GA7
  • the second driving output terminal GO_2 of the third-stage shift register unit SR3 is coupled to the gate line GA8.
  • the third driving output terminal GO_3 of the bit register unit SR3 is coupled to the gate line GA9.
  • the first driving output terminal GO_1 of the fourth-stage shift register unit SR4 is coupled to the gate line GA10, and the second driving output terminal GO_2 of the fourth-stage shift register unit SR4 is coupled to the gate line GA11.
  • the third driving output terminal GO_3 of the bit register unit SR4 is coupled to the gate line GA12.
  • the effective level of the gate scan signal can control the transistor in the sub-pixel coupled to the corresponding gate line to be turned on, and the inactive level can control the transistor in the sub-pixel coupled to the corresponding gate line to be turned off.
  • the effective level of the gate scanning signal may be low level, and the inactive level may be high level.
  • the effective level of the gate scanning signal can also be set to high level and the inactive level to low level, which is not limited here.
  • the display panel may further include a plurality of clock signal lines and a frame start signal line, and the plurality of clock signal lines and frame start signal lines are respectively coupled to the gate driving circuit.
  • the multiple clock signals are respectively input to the first clock signal terminal CK1 and M second clock signal terminals of the shift register unit, thereby causing the shift The register unit outputs a gate scan signal to the coupled gate line.
  • the display panel may include four clock signals Lines CKS1 to CKS4 and a frame start signal line STVS_1.
  • the four clock signal lines CKS1 ⁇ CKS4 and one frame start signal line STVS_1 are coupled to the gate driving circuit 110 respectively.
  • CKS1 serves as the first clock signal line
  • CKS2 serves as the second clock signal line
  • CKS3 serves as the third clock signal line
  • CKS4 serves as the fourth clock signal line.
  • first clock signal terminal CK1 of the 4k_3rd stage shift register unit the first second clock signal terminal CK2_1 of the 4k_2nd stage shift register unit, and the second second clock signal of the 4k_1th stage shift register unit.
  • Terminal CK2_2 and the third second clock signal terminal CK2_3 of the 4k-th stage shift register unit are both coupled with the first clock signal line;
  • the second second clock signal terminal CK2_2 of the 4k_2-stage shift register unit, the third second clock signal terminal CK2_3 of the 4k_1-stage shift register unit, and the first clock signal terminal CK1 of the 4k-stage shift register unit, Both are coupled to the second clock signal line;
  • the first clock signal terminal CK1 of the bit register unit and the first second clock signal terminal CK2_1 of the 4k-level shift register unit are both coupled to the third clock signal line; the third clock signal terminal of the 4k_3-level shift register unit
  • the two second clock signal terminals CK2_2 are all coupled to the third clock signal line; k is an integer greater than 0.
  • Figure 10 only takes 4 clock signal lines and 1 frame start signal line as an example for illustration.
  • the specific number of clock signal lines and frame start signal lines can be determined according to the actual application. The requirements are determined and are not limited here. For example, it can also be other numbers of clock signal lines and frame start signal lines that are an integer multiple of 2, such as 2, 4, 6, 10, 12, etc. The number of clock signal lines and frame Start signal line.
  • the display panel may further include a plurality of cascade selection signal lines and a plurality of drive selection signal lines, and the cascade selection signal terminal of the shift register unit in the gate drive circuit is connected to the cascade selection signal Line coupling, the drive selection signal end of the shift register unit in the gate drive circuit is coupled with the drive selection signal line.
  • the display panel may include three cascaded Select signal lines JXS1 ⁇ JXS3 and three drive selection signal lines GXS1 ⁇ GXS3.
  • the three cascade selection signal lines JXS1 to JXS3 are respectively coupled to the cascade selection signal terminals of the shift register unit in the gate drive circuit 110 .
  • the three driving selection signal lines GXS1 to GXS3 are respectively coupled to the driving selection signal terminals of the shift register unit in the gate driving circuit 110 .
  • JXS1 serves as the first cascade selection signal line
  • JXS2 serves as the second cascade selection signal line
  • JXS3 serves as the third cascade selection signal line.
  • GXS1 serves as the first drive selection signal line
  • GXS2 serves as the second drive selection signal line
  • GXS3 serves as the third drive selection signal line.
  • the first cascade selection signal terminal JX_1 of the shift register unit at each level is coupled to the first cascade selection signal line
  • the second cascade selection signal terminal JX_2 of the shift register unit at each level is coupled to the second cascade selection signal line.
  • the selection signal line is coupled
  • the third cascade selection signal terminal JX_3 of each stage shift register unit is coupled with the third cascade selection signal line.
  • the first drive selection signal terminal GX_1 of the shift register unit at each stage is coupled to the first drive selection signal line
  • the second drive selection signal terminal GX_2 of the shift register unit at each stage is coupled to the second drive selection signal line.
  • the third drive selection signal terminal GX_3 of the shift register unit at each stage is coupled with the third drive selection signal line.
  • Figure 10 only takes three cascade selection signal lines JXS1 ⁇ JXS3 and three drive selection signal lines GXS1 ⁇ GXS3 as an example for illustration. In actual applications, the cascade selection signal lines and the drive selection signal lines The specific quantity can be determined according to the actual application requirements and is not limited here.
  • one row of pixel units can correspond to one shift register unit in the gate driving circuit.
  • the m-th driving output terminal of each shift register unit is coupled to the gate line corresponding to the sub-pixel of the same color.
  • the first-stage shift The first drive output terminal GO_1 from the register unit to the fourth-stage shift register unit is coupled to the gate lines GA1, GA4, GA7, and GA10 corresponding to the red sub-pixel.
  • the second driving output terminal GO_2 of the first-stage shift register unit to the fourth-stage shift register unit is coupled to the gate lines GA2, GA5, GA8, and GA11 corresponding to the green sub-pixel.
  • the third driving output terminal GO_3 of the first-stage shift register unit to the fourth-stage shift register unit is coupled to the gate lines GA3, GA6, GA9, and GA12 corresponding to the red sub-pixel.
  • the gate driving circuit may be provided only at the first end of the gate line.
  • the gate driving circuit may also be provided only at the second end of the gate line.
  • a gate driving circuit may also be provided at both the first end and the second end of the gate line, so that the shift register unit coupled to the same gate line inputs the effective level of the gate scanning signal to the gate line at the same time.
  • a gate driving circuit is provided on the left side of the plurality of gate lines.
  • a gate driving circuit is provided on the left and right sides of the plurality of gate lines.
  • Embodiments of the present disclosure also provide a control method for a display device, as shown in Figure 14, which may include the following steps:
  • the gate driving circuit outputs a gate scan signal to the coupled gate line by driving the output terminal.
  • the effective level of the gate scan signal can control the conduction of the transistor coupled to the corresponding gate line
  • the inactive level can control the conduction of the transistor coupled to the corresponding gate line. Control the transistor coupled to the corresponding gate line to turn off.
  • the effective level of the gate scanning signal may be high level, and the inactive level may be low level.
  • the effective level of the gate scanning signal can also be low level, and the inactive level can be high level, which is not limited here.
  • the effective level of the first clock signal is used to output the effective level of the gate scanning signal for scanning the gate line.
  • the maintenance durations of the effective levels of the first clock signals are the same.
  • the clock periods of the first clock signals are the same.
  • cks1_1 represents the first clock signal input to the first clock signal line CKS1
  • cks2_1 represents the first clock signal input to the second clock signal line CKS2
  • cks3_1 represents the first clock signal input to the third clock signal line CKS3.
  • the clock signal, cks4_1 represents the first clock signal input to the fourth clock signal line CKS4, and stvs_1 represents the frame start signal input to the frame start signal line STVS_1.
  • the signal ga1_1 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA1
  • the signal ga2_1 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA2
  • the signal ga10_1 represents the gate driving.
  • the circuit 110 outputs a gate scanning signal on the gate line GA10.
  • the signal ga11_1 represents the gate scanning signal output by the gate driving circuit 110 on the gate line GA11.
  • the signal ga12_1 represents the gate scanning signal output by the gate driving circuit 110 on the gate line GA12. Polar scan signal.
  • a low-level gate turn-on signal is applied to the first driving selection signal line to control the first and second transistors M2_1 in the shift register units at each level to be turned on.
  • a low-level gate turn-on signal is applied to the second driving selection signal line to control the second transistor M2_2 in the shift register unit at each level to be turned on.
  • a low-level gate turn-on signal is applied to the third drive selection signal line to control the third second transistor M2_3 in the shift register units at all levels to be turned on.
  • a high-level gate-off signal is applied to the first cascade selection signal line to control the first transistor M1_1 in the shift register unit at each level to be turned off.
  • a high-level gate-off signal is applied to the second driving selection signal line to control the second first transistor M1_2 in the shift register unit at each level to be turned off.
  • a low-level gate turn-on signal is applied to the third drive selection signal line to control the third first transistor M1_3 in the shift register units at all levels to be turned on.
  • the gate-on signal can also be a high-level signal
  • the gate-off signal can also be a low-level signal, which is not limited here.
  • the signal stvs_1 is input to the input signal terminal INP of the shift register unit SR1, and the shift register unit SR1 converts the first low level of the first clock signal cks2_1 , is output to the gate line GA1 through the first driving output terminal GO_1 to generate a low level in the gate scanning signal ga1_1.
  • the shift register unit SR1 outputs the first low level of the first clock signal cks3_1 to the gate line GA2 through the second driving output terminal GO_2 to generate a low level in the gate scanning signal ga2_1.
  • the shift register unit SR1 outputs the first low level of the first clock signal cks4_1 to the gate line GA3 through the third driving output terminal GO_3 to generate a low level in the gate scanning signal ga3_1.
  • the gate scan signal ga3_1 is input to the input signal terminal INP of the shift register unit SR2.
  • the shift register unit SR2 outputs the second low level of the first clock signal cks1_1 to the gate line GA4 through the first drive output terminal GO_1. , to generate a low level in the gate scanning signal ga4_1.
  • the shift register unit SR2 outputs the second low level of the first clock signal cks2_1 to the gate line GA5 through the second driving output terminal GO_2 to generate a low level in the gate scanning signal ga5_1.
  • the shift register unit SR2 outputs the second low level of the first clock signal cks3_1 to the gate line GA6 through the third driving output terminal GO_3 to generate a low level in the gate scanning signal ga6_1.
  • the gate scan signal ga6_1 is input to the input signal terminal INP of the shift register unit SR3.
  • the shift register unit SR3 outputs the second low level of the first clock signal cks4_1 to the gate line GA7 through the first drive output terminal GO_1. , to generate a low level in the gate scanning signal ga7_1.
  • the shift register unit SR3 outputs the third low level of the first clock signal cks1_1 to the gate line GA8 through the second driving output terminal GO_2 to generate a low level in the gate scanning signal ga8_1.
  • the shift register unit SR3 outputs the third low level of the first clock signal cks2_1 to the gate line GA9 through the third driving output terminal GO_3 to generate a low level in the gate scanning signal ga9_1.
  • the gate scan signal ga9_1 is input to the input signal terminal INP of the shift register unit SR4.
  • the shift register unit SR4 outputs the third low level of the first clock signal cks3_1 to the gate line GA10 through the first drive output terminal GO_1. , to generate a low level in the gate scanning signal ga10_1.
  • the shift register unit SR4 outputs the third low level of the first clock signal cks4_1 to the gate line GA11 through the second driving output terminal GO_2 to generate a low level in the gate scanning signal ga11_1.
  • the shift register unit SR4 outputs the fourth low level of the first clock signal cks1_1 to the gate line GA12 through the third driving output terminal GO_3 to generate a low level in the gate scanning signal ga12_
  • the low-level maintenance durations of the first clock signals cks1_1 to cks4_1 are the same, and the clock periods ts11 of the first clock signals cks1_1 to cks4_1 are the same.
  • the low level of the first clock signals cks1_1 to cks4_1 can be their effective level, and the high level can be their inactive level.
  • the shift register unit outputs the high level of the first clock signal to generate a high level signal for controlling the conduction of the transistor in the gate scan signal
  • the high level of the first clock signal can be used as its effective level. flat, low level as its invalid level.
  • the clock period ts11 of each first clock signal cks1_1 to cks4_1 may be 8H.
  • the clock cycle of each first clock signal may be 4H.
  • the specific value of the clock cycle of each first clock signal can be determined according to the requirements of the actual application, and is not limited here.
  • the second driving mode in one display frame, load the second clock signal to each clock signal line, load the gate conduction signal to the driving selection signal line coupled to the m-th cascade output circuit, and load the gate conduction signal to the remaining
  • the drive selection signal line is loaded with a gate-off signal
  • the cascade selection signal line coupled to the m-th drive output circuit is loaded with a gate-on signal
  • the remaining cascade selection signal lines are loaded with a gate-off signal to control each shift.
  • the register unit works sequentially, providing the signal of the m-th driving node among at least two driving nodes to the cascade output terminal, and providing the signal of the m-th driving node to the corresponding driving output terminal, and interlacing multiple gate lines. scanning.
  • the clock period of the second clock signal is different from the clock period of the first clock signal.
  • step S20 may include: in the second driving mode, loading the same second clock signal to the first clock signal line and the third clock signal line, and loading the second clock signal to The same second clock signal is loaded on the first cascade selection signal line and the fourth clock signal line, the gate conduction signal is loaded on the first cascade selection signal line, and the gate conduction signal is loaded on both the second cascade selection signal line and the third cascade selection signal line.
  • the first drive selection signal line is loaded with a gate turn-on signal
  • the second drive selection signal line and the third drive selection signal line are both loaded with gate-off signals to control the sequential operation of each shift register unit.
  • the signal of the first driving node is provided to the cascade output terminal, and the signal of the first driving node is provided to the first driving output terminal, and the gate lines coupled to each first color sub-pixel row are scanned; wherein , the second clock signal loaded on the first clock signal line and the second clock signal terminal is different.
  • the first color sub-pixel row may be a red sub-pixel row, so that in the second driving mode, the same second clock signal is loaded on the first clock signal line and the third clock signal line, and the second clock signal is loaded on the second clock signal line.
  • the signal line and the fourth clock signal line are loaded with the same second clock signal
  • the first cascade selection signal line is loaded with the gate conduction signal
  • the second cascade selection signal line and the third cascade selection signal line are loaded with
  • the gate cutoff signal loads the gate turn-on signal to the first drive selection signal line, and loads the gate cutoff signal to both the second drive selection signal line and the third drive selection signal line to control the sequential operation of each shift register unit
  • the signal of the first driving node is provided to the cascade output terminal, and the signal of the first driving node is provided to the first driving output terminal, and the gate line coupled to each red sub-pixel row is scanned. That is to say, in the second driving mode, in one display frame, the gate scan signal can be output only to the gate coupled to the red sub
  • the clock period of the second clock signal can be made not greater than 3/2 of the clock period of the first clock signal.
  • the clock period of the second clock signal may be equal to 3/2 of the clock period of the first clock signal.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the clock period ts21 of the second clock signals cks1_2 to cks4_2 can be 12H.
  • the clock period of the second clock signal may be equal to 1/2 of the clock period of the first clock signal. For example, as shown in FIG. 15 and FIG.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the clock period ts22 of the second clock signals cks1_2 to cks4_2 can be 4H.
  • the clock period of the first clock signal is 4H
  • the clock period of the second clock signal may be 2H.
  • the clock period of the second clock signal may be equal to 1/4 of the clock period of the first clock signal. For example, as shown in FIG. 15 and FIG.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the clock period ts23 of the second clock signals cks1_2 to cks4_2 can be 2H.
  • the relationship between the clock cycle of the second clock signal and the clock cycle of the first clock signal loaded when only the gate lines coupled to the first color sub-pixel row are scanned in a display frame It can be determined according to the actual application requirements and is not limited here.
  • cks1_2 represents the second clock signal input to the first clock signal line CKS1
  • cks2_2 represents the second clock signal input to the second clock signal line CKS2
  • cks3_2 represents the second clock signal input to the third clock signal line CKS3.
  • the clock signal, cks4_2 represents the second clock signal input to the fourth clock signal line CKS4, and stvs_2 represents the frame start signal input to the frame start signal line STVS_2.
  • the signal ga1_2 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA1
  • the signal ga4_2 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA4
  • the signal ga7_2 represents the gate driving
  • the circuit 110 outputs the gate scanning signal on the gate line GA7
  • the signal ga10_2 represents the gate scanning signal output by the gate driving circuit 110 on the gate line GA10.
  • a low-level gate turn-on signal is applied to the first driving selection signal line to control the first and second transistors M2_1 in the shift register units at each level to be turned on.
  • a high-level gate-off signal is applied to the second driving selection signal line to control the second transistor M2_2 in the shift register unit at each level to be turned off.
  • a high-level gate-off signal is applied to the third driving selection signal line to control the third second transistor M2_3 in the shift register units at all levels to be turned off.
  • a low-level gate turn-on signal is applied to the first cascade selection signal line to control the first first transistor M1_1 in the shift register unit at each level to be turned on.
  • a high-level gate-off signal is applied to the second driving selection signal line to control the second first transistor M1_2 in the shift register unit at each level to be turned off.
  • a high-level gate-off signal is applied to the third driving selection signal line to control the third first transistor M1_3 in the shift register units at each level to be turned off.
  • the gate-on signal can also be a high-level signal, and the gate-off signal can also be a low-level signal, which is not limited here.
  • the signal stvs_2 is input to the input signal terminal INP of the shift register unit SR1, and the shift register unit SR1 converts the first low level of the second clock signal cks2_2 , is output to the gate line GA1 through the first driving output terminal GO_1 to generate a low level in the gate scanning signal ga1_2.
  • the gate scan signal ga1_2 is input to the input signal terminal INP of the shift register unit SR2.
  • the shift register unit SR2 outputs the second low level of the second clock signal cks1_2 to the gate line GA4 through the first drive output terminal GO_1. , to generate a low level in the gate scanning signal ga4_2.
  • the gate scan signal ga4_2 is input to the input signal terminal INP of the shift register unit SR3.
  • the shift register unit SR3 outputs the second low level of the second clock signal cks4_2 to the gate line GA7 through the first drive output terminal GO_1. , to generate a low level in the gate scanning signal ga7_2.
  • the gate scan signal ga7_2 is input to the input signal terminal INP of the shift register unit SR4.
  • the shift register unit SR4 outputs the third low level of the second clock signal cks3_2 to the gate line GA10 through the first drive output terminal GO_1. , to generate a low level in the gate scanning signal ga10_2.
  • the low-level maintenance durations of the second clock signals cks1_2 to cks4_2 are the same, and the clock periods of the second clock signals cks1_2 to cks4_2 are the same.
  • the low level of the second clock signals cks1_2 to cks4_2 can be their effective level, and the high level can be their inactive level.
  • the shift register unit outputs the high level of the second clock signal to generate a high level signal for controlling the conduction of the transistor in the gate scan signal
  • the high level of the second clock signal can be used as its effective level. flat, low level as its invalid level.
  • the clock period ts21 of each second clock signal cks1_2 to cks4_2 may be 12H.
  • the clock period ts22 of each of the second clock signals cks1_2 to cks4_2 may be 4H.
  • the clock period ts23 of each of the second clock signals cks1_2 to cks4_2 may be 2H.
  • step S20 may include: in the second driving mode, loading different second clock signals respectively on the first to fourth clock signal lines, and on the second stage
  • the cascade selection signal line is loaded with a gate-on signal
  • the first cascade selection signal line and the third cascade selection signal line are both loaded with a gate-off signal
  • the second drive selection signal line is loaded with a gate-on signal
  • the first drive selection signal line and the third drive selection signal line are both loaded with gate cut-off signals to control the sequential operation of each shift register unit, provide the signal of the second drive node to the cascade output terminal, and provide the second drive node with a gate cutoff signal.
  • the signal of the driving node is provided to the second driving output terminal to scan the gate line coupled to each second color sub-pixel row; wherein the second clock signal has two different clock cycles.
  • the second color sub-pixel row may be a green sub-pixel row, so that in the second driving mode, different second clock signals are respectively loaded on the first to fourth clock signal lines, and the second cascaded
  • the selection signal line is loaded with a gate-on signal
  • the first cascade selection signal line and the third cascade selection signal line are both loaded with a gate-off signal
  • the second drive selection signal line is loaded with a gate-on signal
  • the first drive selection signal line and the third drive selection signal line are both loaded with gate cut-off signals to control the sequential operation of each shift register unit, provide the signal of the second drive node to the cascade output terminal, and
  • the signal of the node is provided to the second driving output terminal to scan the gate line coupled to each green sub-pixel row. That is to say, in the second driving mode, in one display frame, the gate scanning signal can be output only to the gate coupled to the green subpixel row, so that only the data voltage can be input to the green subpixel.
  • the two different clock cycles may include a first clock cycle and a second clock cycle.
  • the first clock period is not greater than 3/4 of the clock period of the first clock signal
  • the second clock period is not greater than 9/4 of the clock period of the first clock signal.
  • the first clock period may be equal to 3/4 of the clock period of the first clock signal
  • the second clock period may be equal to 9/4 of the clock period of the first clock signal.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the second clock period ts31_2 of the second clock signals cks1_2 to cks4_2 can be 18H
  • the first clock period ts31_1 is 6H.
  • the first clock period may be equal to 2/3 of the clock period of the first clock signal
  • the second clock period may be equal to 3/2 of the clock period of the first clock signal.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the second clock period ts32_2 of the second clock signals cks1_2 to cks4_2 can be 12H
  • the first clock period ts32_1 is 4H.
  • the first clock cycle and the second clock cycle of the loaded second clock signal are different from those of the first clock signal.
  • the relationship between the clock cycles can be determined according to the actual application requirements and is not limited here.
  • cks1_2 represents the second clock signal input to the first clock signal line CKS1
  • cks2_2 represents the second clock signal input to the second clock signal line CKS2
  • cks3_2 represents the second clock signal input to the third clock signal line CKS3.
  • the clock signal, cks4_2 represents the second clock signal input to the fourth clock signal line CKS4, and stvs_2 represents the frame start signal input to the frame start signal line STVS_2.
  • the signal ga2_2 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA2
  • the signal ga5_2 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA5
  • the signal ga8_2 represents the gate driving
  • the circuit 110 outputs the gate scanning signal on the gate line GA8, and the signal ga11_2 represents the gate scanning signal output by the gate driving circuit 110 on the gate line GA11.
  • a low-level gate turn-on signal is applied to the second driving selection signal line to control the second transistor M2_2 in the shift register unit at each level to be turned on.
  • a high-level gate-off signal is applied to the first driving selection signal line to control the first and second transistors M2_1 in the shift register units at each level to be turned off.
  • a high-level gate-off signal is applied to the third driving selection signal line to control the third second transistor M2_3 in the shift register units at all levels to be turned off.
  • a low-level gate turn-on signal is applied to the second cascade selection signal line to control the second first transistor M1_2 in the shift register unit at each level to be turned on.
  • a high-level gate-off signal is applied to the first driving selection signal line to control the first transistor M1_1 in the shift register unit at each level to be turned off.
  • a high-level gate-off signal is applied to the third driving selection signal line to control the third first transistor M1_3 in the shift register units at each level to be turned off.
  • the gate-on signal can also be a high-level signal, and the gate-off signal can also be a low-level signal, which is not limited here.
  • the signal stvs_2 is input to the input signal terminal INP of the shift register unit SR1, and the shift register unit SR1 converts the first low level of the second clock signal cks3_2 , is output to the gate line GA2 through the second driving output terminal GO_2 to generate a low level in the gate scanning signal ga2_2.
  • the gate scan signal ga2_2 is input to the input signal terminal INP of the shift register unit SR2.
  • the shift register unit SR2 outputs the second low level of the second clock signal cks2_2 to the gate line GA5 through the second drive output terminal GO_2. , to generate a low level in the gate scanning signal ga5_2.
  • the gate scan signal ga5_2 is input to the input signal terminal INP of the shift register unit SR3.
  • the shift register unit SR3 outputs the second low level of the second clock signal cks1_2 to the gate line GA8 through the second drive output terminal GO_2. , to generate a low level in the gate scanning signal ga8_2.
  • the gate scan signal ga8_2 is input to the input signal terminal INP of the shift register unit SR4.
  • the shift register unit SR4 outputs the third low level of the second clock signal cks4_2 to the gate line GA11 through the second drive output terminal GO_2. , to generate a low level in the gate scanning signal ga11_2.
  • the low-level maintenance durations of the second clock signals cks1_2 to cks4_2 are the same, the first clock cycles and the second clock cycles of the second clock signals cks1_2 to cks4_2 are the same.
  • the low level of the second clock signals cks1_2 to cks4_2 can be their effective level, and the high level can be their inactive level.
  • the shift register unit outputs the high level of the second clock signal to generate a high level signal for controlling the conduction of the transistor in the gate scan signal
  • the high level of the second clock signal can be used as its effective level. flat, low level as its invalid level.
  • the second clock period ts31_2 of each of the second clock signals cks1_2 to cks4_2 may be 18H, and the first clock period ts31_1 may be 6H.
  • the second clock period ts32_2 of each of the second clock signals cks1_2 to cks4_2 may be 12H, and the first clock period ts32_1 may be 4H.
  • the scanning time of the gate line coupled to the green sub-pixel can be reduced, thereby reducing the scanning time of one display frame, thereby increasing the refresh frequency.
  • step S20 may include: in the second driving mode, loading different second clock signals respectively on the first to fourth clock signal lines, and on the third stage
  • the cascade selection signal line is loaded with a gate-on signal
  • both the first cascade selection signal line and the second cascade selection signal line are loaded with a gate-off signal
  • the third drive selection signal line is loaded with a gate-on signal
  • the first drive selection signal line and the second drive selection signal line are both loaded with gate cut-off signals to control the sequential operation of each shift register unit, provide the signal of the third drive node to the cascade output terminal, and provide the third drive node with a gate cutoff signal.
  • the signal of the driving node is provided to the third driving output terminal, and the gate line coupled to each third color sub-pixel row is scanned.
  • the third color sub-pixel row may be a blue sub-pixel row, so that in the second driving mode, different second clock signals are loaded on the first to fourth clock signal lines respectively, and different second clock signals are loaded on the third clock signal line.
  • the cascade selection signal line is loaded with a gate-on signal
  • the first cascade selection signal line and the second cascade selection signal line are both loaded with a gate-off signal
  • the third drive selection signal line is loaded with a gate-on signal
  • the first drive selection signal line and the second drive selection signal line are both loaded with gate cut-off signals to control the sequential operation of each shift register unit, provide the signal of the third drive node to the cascade output terminal, and provide the third drive node to the cascade output terminal.
  • the signal of the first driving node is provided to the third driving output terminal, and the gate line coupled to each third color sub-pixel row is scanned. That is to say, in the second driving mode, in one display frame, the gate scanning signal may be output only to the gate coupled to the blue sub-pixel row, so that only the data voltage is input to the blue sub-pixel.
  • the second clock period may be made not greater than three times the clock period of the first clock signal.
  • the second clock period may be made equal to three times the clock period of the first clock signal.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the clock period ts41 of the second clock signals cks1_2 to cks4_2 can be 24H.
  • the second clock period may be equal to twice the clock period of the first clock signal.
  • the clock period of the first clock signals cks1_1 to cks4_1 is 8H
  • the clock period of the second clock signals cks1_2 to cks4_2 can be 16H
  • the second clock period may be equal to 1/2 of the clock period of the first clock signal.
  • the clock period ts11 of the first clock signals cks1_1 to cks4_1 is 8H
  • the clock period ts42 of the second clock signals cks1_2 to cks4_2 can be 4H.
  • the relationship between the clock cycle of the second clock signal and the clock cycle of the first clock signal when only the gate line coupled to the third color sub-pixel row is scanned in a display frame It can be determined according to the actual application requirements and is not limited here.
  • cks1_2 represents the second clock signal input to the first clock signal line CKS1
  • cks2_2 represents the second clock signal input to the second clock signal line CKS2
  • cks3_2 represents the second clock signal input to the third clock signal line CKS3.
  • the clock signal, cks4_2 represents the second clock signal input to the fourth clock signal line CKS4, and stvs_2 represents the frame start signal input to the frame start signal line STVS_2.
  • the signal ga3_2 represents the gate scanning signal output by the gate driving circuit 110 to the gate line GA3
  • the signal ga6_2 represents the gate scanning signal outputted by the gate driving circuit 110 to the gate line GA6, ...
  • the signal ga9_2 represents the gate driving.
  • the circuit 110 outputs the gate scanning signal on the gate line GA9
  • the signal ga12_2 represents the gate scanning signal output by the gate driving circuit 110 on the gate line GA12.
  • a low-level gate turn-on signal is applied to the third drive selection signal line to control the third second transistor M2_3 in the shift register units at all levels to be turned on.
  • a high-level gate-off signal is applied to the second drive selection signal line to control the second transistor M2_2 in the shift register unit at each level to be turned off.
  • a high-level gate-off signal is applied to the first driving selection signal line to control the first and second transistors M2_1 in the shift register units at each level to be turned off.
  • a low-level gate turn-on signal is applied to the third cascade selection signal line to control the third first transistor M1_3 in the shift register unit at each level to be turned on.
  • a high-level gate-off signal is applied to the second driving selection signal line to control the second first transistor M1_2 in the shift register unit at each level to be turned off.
  • a high-level gate-off signal is applied to the first driving selection signal line to control the first transistor M1_1 in the shift register unit at each level to be turned off.
  • the gate-on signal can also be a high-level signal, and the gate-off signal can also be a low-level signal, which is not limited here.
  • the signal stvs_2 is input to the input signal terminal INP of the shift register unit SR1, and the shift register unit SR1 converts the first low level of the second clock signal cks4_2 , is output to the gate line GA3 through the third drive output terminal GO_3 to generate a low level in the gate scanning signal ga3_2.
  • the gate scan signal ga3_2 is input to the input signal terminal INP of the shift register unit SR2.
  • the shift register unit SR2 outputs the first low level of the second clock signal cks3_2 to the gate line GA6 through the third drive output terminal GO_3. , to generate a low level in the gate scanning signal ga6_2.
  • the gate scan signal ga6_2 is input to the input signal terminal INP of the shift register unit SR3.
  • the shift register unit SR3 outputs the first low level of the second clock signal cks2_2 to the gate line GA9 through the third drive output terminal GO_3. , to generate a low level in the gate scanning signal ga9_2.
  • the gate scan signal ga9_2 is input to the input signal terminal INP of the shift register unit SR4.
  • the shift register unit SR4 outputs the second low level of the second clock signal cks1_2 to the gate line GA12 through the third drive output terminal GO_3. , to generate a low level in the gate scanning signal ga12_2.
  • the low-level maintenance durations of the second clock signals cks1_2 to cks4_2 are the same, and the clock periods of the second clock signals cks1_2 to cks4_2 are the same.
  • the low level of the second clock signals cks1_2 to cks4_2 can be their effective level, and the high level can be their inactive level.
  • the shift register unit outputs the high level of the second clock signal to generate a high level signal for controlling the conduction of the transistor in the gate scan signal
  • the high level of the second clock signal can be used as its effective level. flat, low level as its invalid level.
  • the clock period ts41 of each second clock signal cks1_2 to cks4_2 may be 24H.
  • the clock period ts42 of each of the second clock signals cks1_2 to cks4_2 may be 4H.
  • the maintenance time of the effective level of the second clock signal within one clock cycle is not less than the maintenance time of the effective level of the first clock signal within one clock cycle.
  • the maintenance time of the effective level of the second clock signal within one clock cycle can be equal to the maintenance time of the effective level of the first clock signal within one clock cycle.
  • the duration of the effective level of the corresponding second clock signal in one clock cycle is equal to the effective level of the first clock signal in one clock cycle.
  • the maintenance time when scanning the gate line coupled to the second color sub-pixel row, the maintenance time of the effective level of the corresponding second clock signal in one clock cycle is equal to the effective level of the first clock signal in one clock cycle.
  • the maintenance time when scanning the gate line coupled to the third color sub-pixel row, the maintenance time of the effective level of the corresponding second clock signal in one clock cycle is equal to the effective level of the first clock signal in one clock cycle.
  • Flat maintenance time when the gate line coupled to the first color sub-pixel row is scanned, the maintenance time of the effective level of the corresponding second clock signal in one clock cycle is longer than the effective level of the first clock signal in one clock cycle.
  • the maintenance time, when scanning the gate line coupled to the second color sub-pixel row, the maintenance time of the effective level of the corresponding second clock signal in one clock cycle is equal to the effective level of the first clock signal in one clock cycle.
  • the maintenance time when scanning the gate line coupled to the third color sub-pixel row, the maintenance time of the effective level of the corresponding second clock signal in one clock cycle is equal to the effective level of the first clock signal in one clock cycle.
  • Flat maintenance time This increases the charging rate for red subpixels.
  • the working process of the second driving mode may be performed for the same color sub-pixel in each of the multiple display frames.
  • a working process of scanning the gate lines coupled to each red sub-pixel row can be performed to charge the red sub-pixels to achieve a red picture. show.
  • a working process of scanning the gate lines coupled to each green sub-pixel row may be performed to charge the green sub-pixels to achieve the display of a green picture.
  • a working process of scanning the gate lines coupled to each blue sub-pixel row may be performed to charge the blue sub-pixels to achieve blue screen display.
  • the working process of the second driving mode can be performed for sub-pixels of different colors in multiple adjacent display frames among multiple display frames.
  • the working process of the second driving mode may be performed in the order of red sub-pixels, green sub-pixels and blue sub-pixels in multiple display frames.
  • the plurality of display frames may include: the q-1th display frame Fq-1, the qth display frame Fq, and the q+1th display frame Fq+1.
  • a process of scanning the gate lines coupled to each red sub-pixel row is performed to charge the red sub-pixels.
  • a process of scanning the gate lines coupled to each green sub-pixel row is performed to charge the green sub-pixels.
  • a process of scanning the gate lines coupled to each blue subpixel row is performed to charge the blue subpixels.
  • embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (which may include, but is not limited to, disk storage, CD-ROMs, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media which may include, but is not limited to, disk storage, CD-ROMs, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture that may include instructing the apparatus, the
  • the instruction means implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

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Abstract

提供了一种移位寄存器单元、栅极驱动电路、显示装置以及驱动方法。其中，移位寄存器单元，包括：第一控制电路（01），被配置为根据输入信号端（INP）和第一时钟信号端（CK1）的信号，控制第一节点（N1）和第二节点（N2）的信号；第二控制电路（02），被配置为根据第一节点（N1）、第二节点（N2）以及第二时钟信号端（CK2）的信号，控制至少两个驱动节点（N0_1，N0_2，N0_3）的信号；级联输出电路（03），被配置为根据级联选择信号端（JX_1，JX_2，JX_3），将至少两个驱动节点（N0_1，N0_2，N0_3）中的一个驱动节点的信号提供给级联输出端（JO）；驱动输出电路（04），被配置为根据驱动选择信号端（GX_1，GX_2，GX_3），将至少两个驱动节点（N0_1，N0_2，N0_3）中的至少一个驱动节点的信号提供给对应驱动节点的驱动输出端（GO_1，GO_2，GO_3）。

Description

移位寄存器单元、栅极驱动电路、显示装置以及驱动方法 技术领域
本公开涉及显示技术领域，特别涉及移位寄存器单元、栅极驱动电路、显示装置以及驱动方法。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极驱动电路集成在显示装置的阵列基板上，以形成对显示装置的驱动。其中，驱动控制电路通常由多个级联的移位寄存器单元构成。
发明内容
本公开实施例提供的移位寄存器单元，包括：
第一控制电路，被配置为根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；
第二控制电路，被配置为根据所述第一节点、所述第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；
级联输出电路，被配置为根据级联选择信号端，将所述至少两个驱动节点中的一个驱动节点的信号提供给级联输出端；
驱动输出电路，被配置为根据驱动选择信号端，将所述至少两个驱动节点中的至少一个驱动节点的信号提供给对应所述驱动节点的驱动输出端。
在本公开一些可能的实施方式中，所述驱动节点包括M个驱动节点，所述第二时钟信号端包括M个第二时钟信号端，所述驱动输出端包括M个驱动输出端；M为大于1的整数；
所述第二控制电路包括M个第二控制电路；其中，所述M个第二控制电 路中的第m个第二控制电路与所述M个驱动节点中的第m个驱动节点对应，且所述第m个第二控制电路与所述M个第二时钟信号端中的第m个第二时钟信号端对应；并且，所述第m个第二控制电路被配置为响应于所述第一节点的信号，将所述第m个第二时钟信号端的信号提供给所述第m个驱动节点，以及，响应于所述第二节点的信号，将第一参考信号端的信号提供给所述第m个驱动节点；1≤m≤M，且m为整数；
所述级联输出电路包括M个级联输出电路，所述级联选择信号端包括M个级联选择信号端；其中，所述M个级联输出电路中的第m个级联输出电路与所述第m个驱动节点对应，且所述第m个级联输出电路与所述M个级联选择信号端中的第m个级联选择信号端对应；所述第m个级联输出电路被配置为响应于所述第m个级联选择信号端的信号，将所述第m个驱动节点的信号提供给所述级联输出端；
所述驱动输出电路包括M个驱动输出电路，所述驱动选择信号端包括M个驱动选择信号端；所述M个驱动输出电路中的第m个驱动输出电路与所述第m个驱动节点对应，且所述第m个驱动输出电路与所述M个驱动选择信号端中的第m个驱动选择信号端对应；所述第m个驱动输出电路被配置为响应于所述第m个驱动选择信号端的信号，将所述第m个驱动节点的信号提供给所述第m个驱动输出端。
在本公开一些可能的实施方式中，所述第m个级联输出电路包括：第m个第一晶体管；
所述第m个第一晶体管的控制极与所述第m个级联选择信号端耦接，所述第m个第一晶体管的第一极与所述第m个驱动节点耦接，所述第m个第一晶体管的第二极与所述级联输出端耦接。
在本公开一些可能的实施方式中，所述第m个驱动输出电路包括：第m个第二晶体管；
所述第m个第二晶体管的控制极与所述第m个驱动选择信号端耦接，所述第m个第二晶体管的第一极与所述第m个驱动节点耦接，所述第m个第二 晶体管的第二极与所述驱动输出端耦接。
在本公开一些可能的实施方式中，所述第m个第二控制电路包括：第m个第三晶体管、第m个第四晶体管以及第m个第一电容；
所述第m个第三晶体管的控制极与所述第一节点耦接，所述第m个第三晶体管的第一极与所述第m个第二时钟信号端耦接，所述第m个第三晶体管的第二极与所述第m个驱动节点耦接；
所述第m个第四晶体管的控制极与所述第二节点耦接，所述第m个第四晶体管的第一极与所述第一参考信号端耦接，所述第m个第四晶体管的第二极与所述第m个驱动节点耦接；
所述第m个第一电容的第一电极板与所述第一节点耦接，所述第m个第一电容的第二电极板与所述第m个驱动节点耦接。
在本公开一些可能的实施方式中，所述第m个第二控制电路还包括：第m个第五晶体管；所述第m个第三晶体管的控制极通过所述第m个第五晶体管与所述第一节点耦接；所述第m个第五晶体管的第一极与所述第一节点耦接，所述第m个第五晶体管的第二极与所述第m个第三晶体管的控制极耦接；
在m＝1时，所述第m个第五晶体管的控制极与第二参考信号端耦接；
在1<m≤M时，所述第m个第五晶体管的控制极与所述第一时钟信号端耦接。
在本公开一些可能的实施方式中，所述第一控制电路包括：输入电路和节点控制电路；
所述输入电路被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点；
所述节点控制电路被配置为响应于所述第一时钟信号端的信号，将第二参考信号端的信号提供给所述第二节点，响应于所述第一节点的信号，将所述第一时钟信号端的信号提供给所述第二节点，以及响应于所述第二节点和第1个第二时钟信号端的信号，将所述第一参考信号端的信号提供给所述第一节点。
在本公开一些可能的实施方式中，所述输入电路包括：第六晶体管；所述第六晶体管的控制极与所述第一时钟信号端耦接，所述第六晶体管的第一极与所述输入信号端耦接，所述第六晶体管的第二极与所述第一节点耦接；
所述节点控制电路包括：第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第二电容；其中，所述第七晶体管的控制极与所述第一时钟信号端耦接，所述第七晶体管的第一极与所述第二参考信号端耦接，所述第七晶体管的第二极与所述第二节点耦接；所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的第一极与所述第一时钟信号端耦接，所述第八晶体管的第二极与所述第二节点耦接；所述第九晶体管的控制极与所述第二节点耦接，所述第九晶体管的第一极与所述第一参考信号端耦接，所述第九晶体管的第二极与所述第十晶体管的第一极耦接；所述第十晶体管的控制极与所述第1个第二时钟信号端耦接，所述第十晶体管的第二极与所述第一节点耦接；所述第二电容的第一电极板与所述第二节点耦接，所述第二电容的第二电极板与所述第一参考信号端耦接。
本公开实施例还提供了栅极驱动电路，包括级联的多个上述的移位寄存器单元；
第一级移位寄存器单元的输入信号端与帧起始信号线耦接；
每相邻两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的级联输出端耦接。
本公开实施例还提供了显示装置，包括显示面板；所述显示面板包括：多条栅线、多条时钟信号线、多条级联选择信号线、多条驱动选择信号线以及上述的栅极驱动电路；
所述栅极驱动电路中的每一个所述移位寄存器单元的每一个驱动输出端与所述多条栅线一一对应耦接，且所述栅极驱动电路中的一个所述移位寄存器单元与所述多条时钟信号线耦接；
所述栅极驱动电路中的所述移位寄存器单元的级联选择信号端与所述级联选择信号线耦接；
所述栅极驱动电路中的所述移位寄存器单元的驱动选择信号端与所述驱动选择信号线耦接。
在本公开一些可能的实施方式中，所述显示面板还包括阵列排布的多个像素单元；一行所述像素单元对应所述栅极驱动电路中的一个所述移位寄存器单元；
所述像素单元包括沿列方向排列的多个不同颜色的子像素，一行所述子像素耦接一条所述栅线；
每一个所述移位寄存器单元的第m个驱动输出端耦接同一颜色子像素对应的栅线。
在本公开一些可能的实施方式中，M＝3，所述像素单元包括列方向依次排列的第一颜色子像素、第二颜色子像素以及第三颜色子像素；
所述多条时钟信号线包括第一时钟信号线、第二时钟信号线、第三时钟信号线以及第四时钟信号线；其中，第4k_3级移位寄存器单元的第一时钟信号端、第4k_2级移位寄存器单元的第1个第二时钟信号端、第4k_1级移位寄存器单元的第2个第二时钟信号端以及第4k级移位寄存器单元的第3个第二时钟信号端，均与所述第一时钟信号线耦接；第4k_3级移位寄存器单元的第1个第二时钟信号端、第4k_2级移位寄存器单元的第2个第二时钟信号端、第4k_1级移位寄存器单元的第3个第二时钟信号端以及第4k级移位寄存器单元的第一时钟信号端，均与所述第二时钟信号线耦接；第4k_3级移位寄存器单元的第2个第二时钟信号端、第4k_2级移位寄存器单元的第3个第二时钟信号端、第4k_1级移位寄存器单元的第一时钟信号端以及第4k级移位寄存器单元的第1个第二时钟信号端，均与所述第三时钟信号线耦接；第4k_3级移位寄存器单元的第3个第二时钟信号端、第4k_2级移位寄存器单元的第一时钟信号端、第4k_1级移位寄存器单元的第1个第二时钟信号端以及第4k级移位寄存器单元的第2个第二时钟信号端，均与所述第三时钟信号线耦接；k为大于0的整数；
所述多条级联选择信号线包括第一级联选择信号线、第二级联选择信号 线以及第三级联选择信号线；其中，各级移位寄存器单元的第1个级联选择信号端与所述第一级联选择信号线耦接，各级移位寄存器单元的第2个级联选择信号端与所述第二级联选择信号线耦接，各级移位寄存器单元的第3个级联选择信号端与所述第三级联选择信号线耦接；
所述多条驱动选择信号线包括第一驱动选择信号线、第二驱动选择信号线以及第三驱动选择信号线；其中，各级移位寄存器单元的第1个驱动选择信号端与所述第一驱动选择信号线耦接，各级移位寄存器单元的第2个驱动选择信号端与所述第二驱动选择信号线耦接，各级移位寄存器单元的第3个驱动选择信号端与所述第三驱动选择信号线耦接。
本公开实施例还提供了上述的移位寄存器单元的驱动方法，包括：
在第一驱动模式时，一个显示帧包括第一输入阶段、第一输出阶段以及第一复位阶段；
在所述第一输入阶段，第一控制电路根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第一节点、所述第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端；
在所述第一输出阶段，第二控制电路根据所述第一节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端；
在所述第一复位阶段，第一控制电路根据第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第二节点的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少 两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端；
在第二驱动模式时，一个显示帧包括第二输入阶段、第二输出阶段以及第二复位阶段；
在所述第二输入阶段，第一控制电路根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第一节点、所述第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的所述第m个驱动节点的信号提供给对应的驱动输出端；
在所述第二输出阶段，第二控制电路根据所述第一节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的所述第m个驱动节点的信号提供给对应的驱动输出端；
在所述第二复位阶段，第一控制电路根据第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第二节点的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的所述第m个驱动节点的信号提供给对应的驱动输出端。
本公开实施例还提供了上述的显示装置的驱动方法，包括：
在第一驱动模式时，在一个显示帧中，对各所述时钟信号线加载不同的第一时钟信号，对各所述驱动选择信号线加载栅极导通信号，对第M个驱动输出电路耦接的级联选择信号线加载栅极导通信号，对其余级联选择信号线 加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端，以及将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端，对所述多条栅线逐行扫描；
在第二驱动模式时，在一个显示帧中，对各所述时钟信号线加载第二时钟信号，对第m个级联输出电路耦接的驱动选择信号线加载栅极导通信号，对其余驱动选择信号线加载栅极截止信号，对第m个驱动输出电路耦接的级联选择信号线加载栅极导通信号，且对其余级联选择信号线加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将所述至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端，以及将所述第m个驱动节点的信号提供给对应的驱动输出端，对所述多条栅线隔行扫描；其中，所述第二时钟信号的时钟周期与所述第一时钟信号的时钟周期不同。
在本公开一些可能的实施方式中，在第二驱动模式时，对第一时钟信号线和第三时钟信号线加载相同的第二时钟信号，且对第二时钟信号线和第四时钟信号线加载相同的第二时钟信号，对第一级联选择信号线加载栅极导通信号，且对第二级联选择信号线和第三级联选择信号线均加载栅极截止信号，对第一驱动选择信号线加载栅极导通信号，且对第二驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将第1个驱动节点的信号提供给所述级联输出端，以及将所述第1个驱动节点的信号提供给第1个驱动输出端，对每一个第一颜色子像素行耦接的栅线进行扫描；其中，对所述第一时钟信号线和所述第二时钟信号端加载的第二时钟信号不同。
在本公开一些可能的实施方式中，所述第二时钟信号的时钟周期不大于所述第一时钟信号的时钟周期的3/2。
在本公开一些可能的实施方式中，在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第二级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第三级联选择信号线均加载 栅极截止信号，对第二驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将第2个驱动节点的信号提供给所述级联输出端，以及将所述第2个驱动节点的信号提供给第2个驱动输出端，对每一个第二颜色子像素行耦接的栅线进行扫描；其中，所述第二时钟信号具有两个不同的时钟周期。
在本公开一些可能的实施方式中，所述两个不同的时钟周期包括第一时钟周期和第二时钟周期；所述第一时钟周期不大于所述第一时钟信号的时钟周期的3/4，所述第二时钟周期不大于所述第一时钟信号的时钟周期的9/4。
在本公开一些可能的实施方式中，在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第三级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第二级联选择信号线均加载栅极截止信号，对第三驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第二驱动选择信号线均加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将第3个驱动节点的信号提供给所述级联输出端，以及将所述第3个驱动节点的信号提供给第3个驱动输出端，对每一个第三颜色子像素行耦接的栅线进行扫描。
在本公开一些可能的实施方式中，所述第二时钟周期不大于所述第一时钟信号的时钟周期的三倍。
在本公开一些可能的实施方式中，所述第二时钟信号在一个时钟周期内的有效电平的维持时长不小于所述第一时钟信号在一个时钟周期内的有效电平的维持时长。
在本公开一些可能的实施方式中，对所述第一颜色子像素行耦接的栅线进行扫描时对应的所述第二时钟信号在一个时钟周期内的有效电平的维持时长大于所述第一时钟信号在一个时钟周期内的有效电平的维持时长；
对所述第二颜色子像素行耦接的栅线进行扫描时对应的所述第二时钟信号在一个时钟周期内的有效电平的维持时长等于所述第一时钟信号在一个时 钟周期内的有效电平的维持时长；
对所述第三颜色子像素行耦接的栅线进行扫描时对应的所述第二时钟信号在一个时钟周期内的有效电平的维持时长等于所述第一时钟信号在一个时钟周期内的有效电平的维持时长。
附图说明
图1为本公开实施例提供的移位寄存器单元的一些结构示意图；
图2为本公开实施例提供的移位寄存器单元的另一些结构示意图；
图3为本公开实施例提供的移位寄存器单元的一些具体结构示意图；
图4为本公开实施例提供的移位寄存器单元在第一驱动模式时的流程示意图；
图5a为本公开实施例提供的移位寄存器单元在第一驱动模式时的一些信号时序图；
图5b为本公开实施例提供的移位寄存器单元在第一驱动模式时的另一些信号时序图；
图6为本公开实施例提供的移位寄存器单元在第二驱动模式时的流程示意图；
图7a为本公开实施例提供的移位寄存器单元在第二驱动模式时的一些信号时序图；
图7b为本公开实施例提供的移位寄存器单元在第二驱动模式时的另一些信号时序图；
图7c为本公开实施例提供的移位寄存器单元在第二驱动模式时的又一些信号时序图；
图8为本公开实施例提供的移位寄存器单元在第二驱动模式时的又一些信号时序图；
图9为本公开实施例提供的移位寄存器单元在第二驱动模式时的又一些信号时序图；
图10为本公开实施例提供的栅极驱动电路的一些结构示意图；
图11为本公开实施例提供的显示装置的一些结构示意图；
图12为本公开实施例提供的显示面板的一些结构示意图；
图13为本公开实施例提供的显示面板的另一些结构示意图；
图14为本公开实施例提供的显示装置的一些流程示意图；
图15为本公开实施例提供的显示装置在第一驱动模式时的一些信号时序图；
图16a为本公开实施例提供的显示装置在第二驱动模式时的一些信号时序图；
图16b为本公开实施例提供的显示装置在第二驱动模式时的另一些信号时序图；
图16c为本公开实施例提供的显示装置在第二驱动模式时的又一些信号时序图；
图17a为本公开实施例提供的显示装置在第二驱动模式时的又一些信号时序图；
图17b为本公开实施例提供的显示装置在第二驱动模式时的又一些信号时序图；
图18a为本公开实施例提供的显示装置在第二驱动模式时的又一些信号时序图；
图18b为本公开实施例提供的显示装置在第二驱动模式时的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所 描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“可以包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的移位寄存器单元，如图1所示，可以包括：
第一控制电路01，被配置为根据输入信号端INP和第一时钟信号端CK1的信号，控制第一节点N1和第二节点N2的信号；
第二控制电路02，被配置为根据第一节点N1、第二节点N2以及第二时钟信号端的信号，控制至少两个驱动节点N0_1～N0_3(图1中以3个驱动节点为例)的信号；
级联输出电路03，被配置为根据级联选择信号端JX_1～JX_3(图1中以3个级联选择信号端为例)，将至少两个驱动节点N0_1～N0_3中的一个驱动节点的信号提供给级联输出端JO；
驱动输出电路04，被配置为根据驱动选择信号端GX_1～GX_3(图1中以3个驱动选择信号端为例)，将至少两个驱动节点N0_1～N0_3(图1中以3个驱动节点为例)中的至少一个驱动节点的信号提供给对应驱动节点的驱动输出端GO_1～GO_3(图1中以3个驱动输出端为例)。
本公开实施例提供的移位寄存器单元，通过第一控制电路、第二控制电路、级联输出电路以及驱动输出电路的相互配合，可以从多个驱动节点的信 号中选取一个驱动节点的信号提供给级联输出端JO，作为级联信号输出，以为下一级移位寄存器单元的输入信号端输入相应的信号。以及，由于一个驱动输出端与一条栅线耦接，本公开实施例中的移位寄存器单元可以与多条栅线耦接，这样从多个驱动节点的信号中选取至少一个驱动节点的信号提供给驱动输出端，作为栅极扫描信号输出，以为耦接的多条栅线中的至少一条栅线输入相应的栅极扫描信号，以实现一个移位寄存器单元驱动耦接的多条栅线或驱动耦接的多条栅线中的一条栅线。并且，由于本公开实施例中的移位寄存器单元可以与多条栅线耦接，这样相比一条栅线连接一个移位寄存器单元，可以降低显示面板中设置的移位寄存器单元的数量，从而使显示面板实现窄边框设计。
在本公开一些实施例中，驱动节点可以包括M个驱动节点，第二时钟信号端可以包括M个第二时钟信号端，驱动输出端可以包括M个驱动输出端，级联选择信号端可以包括M个级联选择信号端，驱动选择信号端可以包括M个驱动选择信号端。第二控制电路可以包括M个第二控制电路，级联输出电路可以包括M个级联输出电路，驱动输出电路可以包括M个驱动输出电路。其中，M个第二控制电路中的第m个第二控制电路与M个驱动节点中的第m个驱动节点对应，且第m个第二控制电路与M个第二时钟信号端中的第m个第二时钟信号端对应；并且，第m个第二控制电路被配置为响应于第一节点的信号，将第m个第二时钟信号端的信号提供给第m个驱动节点，以及，响应于第二节点的信号，将第一参考信号端VREF1的信号提供给第m个驱动节点。以及，M个级联输出电路中的第m个级联输出电路与第m个驱动节点对应，且第m个级联输出电路与M个级联选择信号端中的第m个级联选择信号端对应；第m个级联输出电路被配置为响应于第m个级联选择信号端的信号，将第m个驱动节点的信号提供给级联输出端JO。以及，M个驱动输出电路中的第m个驱动输出电路与第m个驱动节点对应，且第m个驱动输出电路与M个驱动选择信号端中的第m个驱动选择信号端对应；第m个驱动输出电路被配置为响应于第m个驱动选择信号端的信号，将第m个驱动节点的 信号提供给第m个驱动输出端。并且，M为大于1的整数，1≤m≤M，且m为整数；
下面以M＝3为例进行说明。当然，在实际应用中，M还可以设置为其他数值，例如，2、4、5、6或更多，在此不作限定。
在本公开一些实施例中，如图2所示，驱动节点可以包括3个驱动节点：第1个驱动节点N0_1、第2个驱动节点N0_2、第3个驱动节点N0_3。第二时钟信号端可以包括3个第二时钟信号端：第1个第二时钟信号端CK2_1、第2个第二时钟信号端CK2_2、第3个第二时钟信号端CK2_3。驱动输出端可以包括3个驱动输出端：第1个驱动输出端GO_1、第2个驱动输出端GO_2、第3个驱动输出端GO_3。级联选择信号端可以包括3个级联选择信号端：第1个级联选择信号端JX_1、第2个级联选择信号端JX_2、第3个级联选择信号端JX_3。驱动选择信号端可以包括3个驱动选择信号端：第1个驱动选择信号端GX_1、第2个驱动选择信号端GX_2、第3个驱动选择信号端GX_3。第二控制电路可以包括3个第二控制电路：第1个第二控制电路02_1、第2个第二控制电路02_2、第3个第二控制电路02_3。级联输出电路可以包括3个级联输出电路：第1个级联输出电路03_1、第2个级联输出电路03_2、第3个级联输出电路03_3。驱动输出电路可以包括3个驱动输出电路：第1个驱动输出电路04_1、第2个驱动输出电路04_2、第3个驱动输出电路04_3。
在本公开一些实施例中，如图2所示，第1个第二控制电路02_1与第1个驱动节点N0_1、第1个第二时钟信号端CK2_1对应设置，且第1个第二控制电路02_1被配置为响应于第一节点N1的信号，将第1个第二时钟信号端CK2_1的信号提供给第1个驱动节点N0_1，以及，响应于第二节点N2的信号，将第一参考信号端VREF1的信号提供给第1个驱动节点N0_1。以及，第1个级联输出电路03_1与第1个驱动节点N0_1、第1个级联选择信号端JX_1对应，且第1个级联输出电路03_1被配置为响应于第1个级联选择信号端JX_1的信号，将第1个驱动节点N0_1的信号提供给级联输出端JO。以及，第1个驱动输出电路04_1与第1个驱动节点N0_1、第1个驱动选择信号端 GX_1对应，且第1个驱动输出电路04_1被配置为响应于第1个驱动选择信号端GX_1的信号，将第1个驱动节点N0_1的信号提供给第1个驱动输出端GO_1。
在本公开一些实施例中，如图2所示，第2个第二控制电路02_2与第2个驱动节点N0_2、第2个第二时钟信号端CK2_2对应设置，且第2个第二控制电路02_2被配置为响应于第一节点N1的信号，将第2个第二时钟信号端CK2_2的信号提供给第2个驱动节点N0_2，以及，响应于第二节点N2的信号，将第一参考信号端VREF1的信号提供给第2个驱动节点N0_2。以及，第2个级联输出电路03_2与第2个驱动节点N0_2、第2个级联选择信号端JX_2对应，且第2个级联输出电路03_2被配置为响应于第2个级联选择信号端JX_2的信号，将第2个驱动节点N0_2的信号提供给级联输出端JO。以及，第2个驱动输出电路04_2与第2个驱动节点N0_2、第2个驱动选择信号端GX_2对应，且第2个驱动输出电路04_2被配置为响应于第2个驱动选择信号端GX_2的信号，将第2个驱动节点N0_2的信号提供给第2个驱动输出端GO_2。
在本公开一些实施例中，如图2所示，第3个第二控制电路02_3与第3个驱动节点N0_3、第3个第二时钟信号端CK2_3对应设置，且第3个第二控制电路02_3被配置为响应于第一节点N1的信号，将第3个第二时钟信号端CK2_3的信号提供给第3个驱动节点N0_3，以及，响应于第二节点N2的信号，将第一参考信号端VREF1的信号提供给第3个驱动节点N0_3。以及，第3个级联输出电路03_3与第3个驱动节点N0_3、第3个级联选择信号端JX_3对应，且第3个级联输出电路03_3被配置为响应于第3个级联选择信号端JX_3的信号，将第3个驱动节点N0_3的信号提供给级联输出端JO。以及，第3个驱动输出电路04_3与第3个驱动节点N0_3、第3个驱动选择信号端GX_3对应，且第3个驱动输出电路04_3被配置为响应于第3个驱动选择信号端GX_3的信号，将第3个驱动节点N0_3的信号提供给第3个驱动输出端GO_3。
在本公开一些实施例中，如图2所示，第一控制电路01可以包括：输入电路011和节点控制电路012。其中，输入电路011被配置为响应于第一时钟信号端CK1的信号，将输入信号端INP的信号提供给第一节点N1。节点控制电路012被配置为响应于第一时钟信号端CK1的信号，将第二参考信号端VREF2的信号提供给第二节点N2，响应于第一节点N1的信号，将第一时钟信号端CK1的信号提供给第二节点N2，以及响应于第二节点N2和第1个第二时钟信号端CK2_1的信号，将第一参考信号端VREF1的信号提供给第一节点N1。
在本公开一些实施例中，如图3所示，第1个级联输出电路03_1可以包括：第1个第一晶体管M1_1。其中，第1个第一晶体管M1_1的控制极与第1个级联选择信号端JX_1耦接，第1个第一晶体管M1_1的第一极与第1个驱动节点N0_1耦接，第1个第一晶体管M1_1的第二极与级联输出端JO耦接。示例性地，第1个第一晶体管M1_1可以在第1个级联选择信号端JX_1的信号为有效电平时导通，在第1个级联选择信号端JX_1的信号为无效电平时截止。例如，第1个第一晶体管M1_1可以为N型晶体管，则第1个级联选择信号端JX_1的信号的有效电平为高电平，无效电平为低电平。或者，第1个第一晶体管M1_1可以为P型晶体管，则第1个级联选择信号端JX_1的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第2个级联输出电路03_2可以包括：第2个第一晶体管M1_2。其中，第2个第一晶体管M1_2的控制极与第2个级联选择信号端JX_2耦接，第2个第一晶体管M1_2的第一极与第2个驱动节点N0_2耦接，第2个第一晶体管M1_2的第二极与级联输出端JO耦接。示例性地，第2个第一晶体管M1_2可以在第2个级联选择信号端JX_2的信号为有效电平时导通，在第2个级联选择信号端JX_2的信号为无效电平时截止。例如，第2个第一晶体管M1_2可以为N型晶体管，则第2个级联选择信号端JX_2的信号的有效电平为高电平，无效电平为低电平。或者，第2个第一晶体管M1_2可以为P型晶体管，则第2个级联选择信号端JX_2的 信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第3个级联输出电路03_3可以包括：第3个第一晶体管M1_3。其中，第3个第一晶体管M1_3的控制极与第3个级联选择信号端JX_3耦接，第3个第一晶体管M1_3的第一极与第3个驱动节点N0_3耦接，第3个第一晶体管M1_3的第二极与级联输出端JO耦接。示例性地，第3个第一晶体管M1_3可以在第3个级联选择信号端JX_3的信号为有效电平时导通，在第3个级联选择信号端JX_3的信号为无效电平时截止。例如，第3个第一晶体管M1_3可以为N型晶体管，则第3个级联选择信号端JX_3的信号的有效电平为高电平，无效电平为低电平。或者，第3个第一晶体管M1_3可以为P型晶体管，则第3个级联选择信号端JX_3的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第1个驱动输出电路04_1可以包括：第1个第二晶体管M2_1。其中，第1个第二晶体管M2_1的控制极与第1个驱动选择信号端GX_1耦接，第1个第二晶体管M2_1的第一极与第1个驱动节点N0_1耦接，第1个第二晶体管M2_1的第二极与驱动输出端耦接。示例性地，第1个第二晶体管M2_1可以在第1个驱动选择信号端GX_1的信号为有效电平时导通，在第1个驱动选择信号端GX_1的信号为无效电平时截止。例如，第1个第二晶体管M2_1可以为N型晶体管，则第1个驱动选择信号端GX_1的信号的有效电平为高电平，无效电平为低电平。或者，第1个第二晶体管M2_1可以为P型晶体管，则第1个驱动选择信号端GX_1的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第2个驱动输出电路04_2可以包括：第2个第二晶体管M2_2。其中，第2个第二晶体管M2_2的控制极与第2个驱动选择信号端GX_2耦接，第2个第二晶体管M2_2的第一极与第2个驱动节点N0_2耦接，第2个第二晶体管M2_2的第二极与驱动输出端耦接。示例性地，第2个第二晶体管M2_2可以在第2个驱动选择信号端GX_2的信号为有效电平时导通，在第2个驱动选择信号端GX_2的信号为无效电平时 截止。例如，第2个第二晶体管M2_2可以为N型晶体管，则第2个驱动选择信号端GX_2的信号的有效电平为高电平，无效电平为低电平。或者，第2个第二晶体管M2_2可以为P型晶体管，则第2个驱动选择信号端GX_2的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第3个驱动输出电路04_3可以包括：第3个第二晶体管M2_3。其中，第3个第二晶体管M2_3的控制极与第3个驱动选择信号端GX_3耦接，第3个第二晶体管M2_3的第一极与第3个驱动节点N0_3耦接，第3个第二晶体管M2_3的第二极与驱动输出端耦接。示例性地，第3个第二晶体管M2_3可以在第3个驱动选择信号端GX_3的信号为有效电平时导通，在第3个驱动选择信号端GX_3的信号为无效电平时截止。例如，第3个第二晶体管M2_3可以为N型晶体管，则第3个驱动选择信号端GX_3的信号的有效电平为高电平，无效电平为低电平。或者，第3个第二晶体管M2_3可以为P型晶体管，则第3个驱动选择信号端GX_3的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第1个第二控制电路02_1可以包括：第1个第三晶体管M3_1、第1个第四晶体管M4_1以及第1个第一电容C1_1。其中，第1个第三晶体管M3_1的控制极与第一节点N1耦接，第1个第三晶体管M3_1的第一极与第1个第二时钟信号端CK2_1耦接，第1个第三晶体管M3_1的第二极与第1个驱动节点N0_1耦接。第1个第四晶体管M4_1的控制极与第二节点N2耦接，第1个第四晶体管M4_1的第一极与第一参考信号端VREF1耦接，第1个第四晶体管M4_1的第二极与第1个驱动节点N0_1耦接。第1个第一电容C1_1的第一电极板与第一节点N1耦接，第1个第一电容C1_1的第二电极板与第1个驱动节点N0_1耦接。示例性地，第1个第三晶体管M3_1可以在第一节点N1的信号为有效电平时导通，在第一节点N1的信号为无效电平时截止。例如，第1个第三晶体管M3_1可以为N型晶体管，则第一节点N1的信号的有效电平为高电平，无效电平为低电平。或者，第1个第三晶体管M3_1可以为P型晶体管，则第一节点N1的信号的 有效电平为低电平，无效电平为高电平。以及，第1个第四晶体管M4_1可以在第二节点N2的信号为有效电平时导通，在第二节点N2的信号为无效电平时截止。例如，第1个第四晶体管M4_1可以为N型晶体管，则第二节点N2的信号的有效电平为高电平，无效电平为低电平。或者，第1个第四晶体管M4_1可以为P型晶体管，则第二节点N2的信号的有效电平为低电平，无效电平为高电平。以及，第1个第一电容C1_1可以保持其两个电极板上的电压稳定。
在本公开一些实施例中，如图3所示，第2个第二控制电路02_2可以包括：第2个第三晶体管M3_2、第2个第四晶体管M4_2以及第2个第一电容C1_2。其中，第2个第三晶体管M3_2的控制极与第一节点N1耦接，第2个第三晶体管M3_2的第一极与第2个第二时钟信号端CK2_2耦接，第2个第三晶体管M3_2的第二极与第2个驱动节点N0_2耦接。第2个第四晶体管M4_2的控制极与第二节点N2耦接，第2个第四晶体管M4_2的第一极与第一参考信号端VREF1耦接，第2个第四晶体管M4_2的第二极与第2个驱动节点N0_2耦接。第2个第一电容C1_2的第一电极板与第一节点N1耦接，第2个第一电容C1_2的第二电极板与第2个驱动节点N0_2耦接。示例性地，第2个第三晶体管M3_2可以在第一节点N1的信号为有效电平时导通，在第一节点N1的信号为无效电平时截止。例如，第2个第三晶体管M3_2可以为N型晶体管，则第一节点N1的信号的有效电平为高电平，无效电平为低电平。或者，第2个第三晶体管M3_2可以为P型晶体管，则第一节点N1的信号的有效电平为低电平，无效电平为高电平。以及，第2个第四晶体管M4_2可以在第二节点N2的信号为有效电平时导通，在第二节点N2的信号为无效电平时截止。例如，第2个第四晶体管M4_2可以为N型晶体管，则第二节点N2的信号的有效电平为高电平，无效电平为低电平。或者，第2个第四晶体管M4_2可以为P型晶体管，则第二节点N2的信号的有效电平为低电平，无效电平为高电平。以及，第2个第一电容C1_2可以保持其两个电极板上的电压稳定。
在本公开一些实施例中，如图3所示，第3个第二控制电路02_3可以包括：第3个第三晶体管M3_3、第3个第四晶体管M4_3以及第3个第一电容C1_3。其中，第3个第三晶体管M3_3的控制极与第一节点N1耦接，第3个第三晶体管M3_3的第一极与第3个第二时钟信号端CK2_3耦接，第3个第三晶体管M3_3的第二极与第3个驱动节点N0_3耦接。第3个第四晶体管M4_3的控制极与第二节点N2耦接，第3个第四晶体管M4_3的第一极与第一参考信号端VREF1耦接，第3个第四晶体管M4_3的第二极与第3个驱动节点N0_3耦接。第3个第一电容C1_3的第一电极板与第一节点N1耦接，第3个第一电容C1_3的第二电极板与第3个驱动节点N0_3耦接。示例性地，第3个第三晶体管M3_3可以在第一节点N1的信号为有效电平时导通，在第一节点N1的信号为无效电平时截止。例如，第3个第三晶体管M3_3可以为N型晶体管，则第一节点N1的信号的有效电平为高电平，无效电平为低电平。或者，第3个第三晶体管M3_3可以为P型晶体管，则第一节点N1的信号的有效电平为低电平，无效电平为高电平。以及，第3个第四晶体管M4_3可以在第二节点N2的信号为有效电平时导通，在第二节点N2的信号为无效电平时截止。例如，第3个第四晶体管M4_3可以为N型晶体管，则第二节点N2的信号的有效电平为高电平，无效电平为低电平。或者，第3个第四晶体管M4_3可以为P型晶体管，则第二节点N2的信号的有效电平为低电平，无效电平为高电平。以及，第3个第一电容C1_3可以保持其两个电极板上的电压稳定。
在本公开一些实施例中，如图3所示，第1个第二控制电路02_1还可以包括：第1个第五晶体管M5_1。第1个第三晶体管M3_1的控制极通过第1个第五晶体管M5_1与第一节点N1耦接。第1个第五晶体管M5_1的第一极与第一节点N1耦接，第1个第五晶体管M5_1的第二极与第1个第三晶体管M3_1的控制极耦接。并且，第1个第五晶体管M5_1的控制极与第二参考信号端VREF2耦接。示例性地，第1个第五晶体管M5_1可以为N型晶体管，则第二参考信号端VREF2的信号为低电平信号，以控制第1个第五晶体管 M5_1导通。或者，第1个第五晶体管M5_1也可以为P型晶体管，则第二参考信号端VREF2的信号为高电平信号，以控制第1个第五晶体管M5_1导通。
在本公开一些实施例中，如图3所示，第2个第二控制电路02_2还可以包括：第2个第五晶体管M5_2。第2个第三晶体管M3_2的控制极通过第2个第五晶体管M5_2与第一节点N1耦接。第2个第五晶体管M5_2的第一极与第一节点N1耦接，第2个第五晶体管M5_2的第二极与第2个第三晶体管M3_2的控制极耦接。并且，第2个第五晶体管M5_2的控制极与第一时钟信号端CK1耦接。示例性地，第2个第五晶体管M5_2可以在第一时钟信号端CK1的信号为有效电平时导通，在第一时钟信号端CK1的信号为无效电平时截止。例如，第2个第五晶体管M5_2可以为N型晶体管，则第一时钟信号端CK1的信号的有效电平为高电平，无效电平为低电平。或者，第2个第五晶体管M5_2也可以为P型晶体管，则第一时钟信号端CK1的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，第3个第二控制电路02_3还可以包括：第3个第五晶体管M5_3。第3个第三晶体管M3_3的控制极通过第3个第五晶体管M5_3与第一节点N1耦接。第3个第五晶体管M5_3的第一极与第一节点N1耦接，第3个第五晶体管M5_3的第二极与第3个第三晶体管M3_3的控制极耦接。并且，第3个第五晶体管M5_3的控制极与第一时钟信号端CK1耦接。示例性地，第3个第五晶体管M5_3可以在第一时钟信号端CK1的信号为有效电平时导通，在第一时钟信号端CK1的信号为无效电平时截止。例如，第3个第五晶体管M5_3可以为N型晶体管，则第一时钟信号端CK1的信号的有效电平为高电平，无效电平为低电平。或者，第3个第五晶体管M5_3也可以为P型晶体管，则第一时钟信号端CK1的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，输入电路011可以包括：第六晶体管M6。其中，第六晶体管M6的控制极与第一时钟信号端CK1耦接，第六晶体管M6的第一极与输入信号端INP耦接，第六晶体管M6的第二极与第 一节点N1耦接。示例性地，第六晶体管M6可以在第一时钟信号端CK1的信号为有效电平时导通，在第一时钟信号端CK1的信号为无效电平时截止。例如，第六晶体管M6可以为N型晶体管，则第一时钟信号端CK1的信号的有效电平为高电平，无效电平为低电平。或者，第六晶体管M6也可以为P型晶体管，则第一时钟信号端CK1的信号的有效电平为低电平，无效电平为高电平。
在本公开一些实施例中，如图3所示，节点控制电路012可以包括：第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10以及第二电容C2。其中，第七晶体管M7的控制极与第一时钟信号端CK1耦接，第七晶体管M7的第一极与第二参考信号端VREF2耦接，第七晶体管M7的第二极与第二节点N2耦接；第八晶体管M8的控制极与第一节点N1耦接，第八晶体管M8的第一极与第一时钟信号端CK1耦接，第八晶体管M8的第二极与第二节点N2耦接；第九晶体管M9的控制极与第二节点N2耦接，第九晶体管M9的第一极与第一参考信号端VREF1耦接，第九晶体管M9的第二极与第十晶体管M10的第一极耦接；第十晶体管M10的控制极与第1个第二时钟信号端CK2_1耦接，第十晶体管M10的第二极与第一节点N1耦接；第二电容C2的第一电极板与第二节点N2耦接，第二电容C2的第二电极板与第一参考信号端VREF1耦接。示例性地，第七晶体管M7可以在第一时钟信号端CK1的信号为有效电平时导通，在第一时钟信号端CK1的信号为无效电平时截止。例如，第七晶体管M7可以为N型晶体管，则第一时钟信号端CK1的信号的有效电平为高电平，无效电平为低电平。或者，第七晶体管M7可以为P型晶体管，则第一时钟信号端CK1的信号的有效电平为低电平，无效电平为高电平。以及，第八晶体管M8可以在第一节点N1的信号为有效电平时导通，在第一节点N1的信号为无效电平时截止。例如，第八晶体管M8可以为N型晶体管，则第一节点N1的信号的有效电平为高电平，无效电平为低电平。或者，第八晶体管M8可以为P型晶体管，则第一节点N1的信号的有效电平为低电平，无效电平为高电平。以及，第九晶体管M9可以在第二节点 N2的信号为有效电平时导通，在第二节点N2的信号为无效电平时截止。例如，第九晶体管M9可以为N型晶体管，则第二节点N2的信号的有效电平为高电平，无效电平为低电平。或者，第九晶体管M9可以为P型晶体管，则第二节点N2的信号的有效电平为低电平，无效电平为高电平。以及，第十晶体管M10可以在第1个第二时钟信号端CK2_1的信号为有效电平时导通，在第1个第二时钟信号端CK2_1的信号为无效电平时截止。例如，第十晶体管M10可以为N型晶体管，则第1个第二时钟信号端CK2_1的信号的有效电平为高电平，无效电平为低电平。或者，第十晶体管M10可以为P型晶体管，则第1个第二时钟信号端CK2_1的信号的有效电平为低电平，无效电平为高电平。以及，第二电容C2可以保持其两个电极板上的电压稳定。
以上仅是举例说明本公开实施例中提供的移位寄存器单元中各电路的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
可选地，在本公开实施例提供的上述移位寄存器单元中，所有的晶体管可以采用相同材质。在具体实施时，如图3所示，所有晶体管可以均为P型晶体管。并且，第一参考信号端VREF1的信号为高电平信号，第二参考信号端VREF2的信号为低电平信号。当然，所有晶体管也可以均为N型晶体管，并且，第一参考信号端VREF1的信号为低电平信号，第二参考信号端VREF2的信号为高电平信号，在此不作限定。
需要说明的是。本公开上述实施例中提到的晶体管，可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不作限定。在具体实施中，这些晶体管的控制极作为其栅极。并且，这些晶体管的第一极和第二极根据晶体管类型以及信号端的信号的不同，可以将第一极作为晶体管的源极或漏极，以及将第二极作为晶体管的漏极或源极，在此不作限定。
本公开实施例提供的上述移位寄存器单元可以实现两种驱动模式：第一驱动模式和第二驱动模式。在第一驱动模式时，可以使每一个驱动节点的信 号提供给对应每一个驱动节点的驱动输出端，从而使每一个驱动输出端均输出信号。在第二驱动模式时，可以使多个驱动节点中的一个驱动节点的信号提供给对应的驱动输出端，从而仅使一个驱动输出端输出信号。
本公开实施例提供的上述移位寄存器单元的驱动方法，如图4所示，可以包括：在第一驱动模式时，一个显示帧可以包括第一输入阶段T11、第一输出阶段T12以及第一复位阶段T13；
S110、在第一输入阶段T11，第一控制电路根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据第一节点、第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个驱动节点的驱动输出端；
S120、在第一输出阶段T12，第二控制电路根据第一节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个驱动节点的驱动输出端；
S130、在第一复位阶段T13，第一控制电路根据第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据第二节点的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个驱动节点的驱动输出端。
在本公开一些实施例中，以有效电平为低电平为例，在第一驱动模式时，驱动选择信号端的信号均为低电平信号。并且，与第M个驱动节点耦接的级联输出电路对应的级联选择信号端的信号为低电平信号，其余级联选择信号端的信号均为高电平信号。
在一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图5a所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第一驱动模式时的工作过程作以描述。示例性地，主要选取如图5a所示的信号时序图中的第一输入阶段T11、第一输出阶段T12以及第一复位阶段T13。其中，第一输出阶段T12可以包括：T121、T122和T123三个阶段。
并且，inp代表输入信号端INP的信号，ck1代表第一时钟信号端CK1的信号，ck2_1代表第1个第二时钟信号端CK2_1的信号，ck2_2代表第2个第二时钟信号端CK2_2的信号，ck2_3代表第3个第二时钟信号端CK2_3的信号，n0_1代表第1个驱动节点N0_1的信号，n0_2代表第2个驱动节点N0_2的信号，n0_3代表第3个驱动节点N0_3的信号，go_1代表第1个驱动输出端GO_1的信号，go_2代表第2个驱动输出端GO_2的信号，go_3代表第3个驱动输出端GO_3的信号，jo代表级联输出端JO的信号。并且，第1个驱动选择信号端GX_1至第3个驱动选择信号端GX_3的信号均为低电平信号。第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号。
在第一输入阶段T11，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的低电平信号提供给第一节点N1，使第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的低电平提供给第二节点N2，以使第二节点N2的信号为低电平信号。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，进一步使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第1个第四晶体管M4_1将第一参考信号端VREF1的高电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为高电平信号。导通的第2个第四晶体管M4_2将第一参考信号端VREF1的高电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2 的信号为高电平信号。导通的第3个第四晶体管M4_3将第一参考信号端VREF1的高电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为高电平信号。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1导通，以将信号ck2_1的高电平信号提供给第1个驱动节点N0_1，进一步使第1个驱动节点N0_1的信号为高电平信号。由于第一节点N1的信号为低电平信号且第2个第五晶体管M5_2导通，因此第2个第三晶体管M3_2导通，以将信号ck2_2的高电平信号提供给第2个驱动节点N0_2，进一步使第2个驱动节点N0_2的信号为高电平信号。由于第一节点N1的信号为低电平信号且第3个第五晶体管M5_3导通，因此第3个第三晶体管M3_3导通，以将信号ck2_3的高电平信号提供给第3个驱动节点N0_3，进一步使第3个驱动节点N0_3的信号为高电平信号。由于第1个驱动选择信号端GX_1的信号为低电平，则第1个第二晶体管M2_1导通，以将第1个驱动节点N0_1的高电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出高电平信号。由于第2个驱动选择信号端GX_2的信号为低电平，则第2个第二晶体管M2_2导通，以将第2个驱动节点N0_2的高电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出高电平信号。由于第3个驱动选择信号端GX_3的信号为低电平，则第3个第二晶体管M2_3导通，以将第3个驱动节点N0_3的高电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出高电平信号。由于第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号，则第3个第一晶体管M1_3导通，第1个第一晶体管M1_1和第2个第一晶体管M1_2均截止。导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
在第一输出阶段T12中的T121阶段，信号ck1为高电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五 晶体管M5_3均截止。因此第一节点N1处于浮接状态，由于第1个第一电容C1_1的作用，可以保持第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的高电平提供给第二节点N2，以使第二节点N2的信号为高电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均截止。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1导通，以将信号ck2_1的低电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为低电平信号。并由于第1个第一电容C1_1的自举作用，可以将第一节点N1的电平进一步拉低，以将第1个第三晶体管M3_1尽可能导通完全，将信号ck2_1的低电平信号可以尽可能无电压损失的提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为低电平信号。由于第一节点N1的信号为低电平信号且第2个第五晶体管M5_2导通，因此第2个第三晶体管M3_2导通，以将信号ck2_2的高电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为高电平信号。由于第一节点N1的信号为低电平信号且第3个第五晶体管M5_3导通，因此第3个第三晶体管M3_3导通，以将信号ck2_3的高电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为高电平信号。由于第1个驱动选择信号端GX_1的信号为低电平，则第1个第二晶体管M2_1导通，以将第1个驱动节点N0_1的低电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出低电平信号。由于第2个驱动选择信号端GX_2的信号为低电平，则第2个第二晶体管M2_2导通，以将第2个驱动节点N0_2的高电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出高电平信号。由于第3个驱动选择信号端GX_3的信号为低电平，则第3个第二晶体管M2_3导通，以将第3个驱动节点N0_3的高电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出高电平信号。由于第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平 信号，则第3个第一晶体管M1_3导通，第1个第一晶体管M1_1和第2个第一晶体管M1_2均截止。导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
在第一输出阶段T12中的T122阶段，信号ck1为高电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均截止。因此第一节点N1处于浮接状态，由于第1个第一电容C1_1的作用，可以保持第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的高电平提供给第二节点N2，以使第二节点N2的信号为高电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均截止。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1导通，以将信号ck2_1的高电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为高电平信号。由于第2个第五晶体管M5_2截止，并且由于第2个第一电容C1_2的作用，可以保持第2个第三晶体管M3_2的控制极的信号为低电平信号，使第2个第三晶体管M3_2导通，以将信号ck2_2的低电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为低电平信号。由于第2个第一电容C1_2的自举作用，可以将第2个第三晶体管M3_2的控制极的电平进一步拉低，以将第2个第三晶体管M3_2尽可能导通完全，将信号ck2_2的低电平信号可以尽可能无电压损失的提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为低电平信号。由于第3个第一电容C1_3的作用，可以保持第3个第三晶体管M3_3的控制极的电平为低电平，则第3个第三晶体管M3_3导通，以将信号ck2_3的高电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为高电平信号。由于第1个驱动选择信号端GX_1的信号为低电平，则第1个第二晶体管M2_1导通，以将第1个驱动节点N0_1的高电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1 输出高电平信号。由于第2个驱动选择信号端GX_2的信号为低电平，则第2个第二晶体管M2_2导通，以将第2个驱动节点N0_2的低电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出低电平信号。由于第3个驱动选择信号端GX_3的信号为低电平，则第3个第二晶体管M2_3导通，以将第3个驱动节点N0_3的高电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出高电平信号。由于第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号，则第3个第一晶体管M1_3导通，第1个第一晶体管M1_1和第2个第一晶体管M1_2均截止。导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
在第一输出阶段T12中的T123阶段，信号ck1为高电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均截止。因此第一节点N1处于浮接状态，由于第1个第一电容C1_1的作用，可以保持第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的高电平提供给第二节点N2，以使第二节点N2的信号为高电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均截止。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1导通，以将信号ck2_1的高电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为高电平信号。由于第2个第五晶体管M5_2截止，并且由于第2个第一电容C1_2的作用，可以保持第2个第三晶体管M3_2的控制极的信号为低电平信号，使第2个第三晶体管M3_2导通，以将信号ck2_2的高电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为高电平信号。由于第3个第一电容C1_3的作用，可以保持第3个第三晶体管M3_3的控制极的电平为低电平，则第3个第三晶体管M3_3导通，以将信号ck2_3的低电平信号提供给第 3个驱动节点N0_3，使第3个驱动节点N0_3的信号为低电平信号。由于第3个第一电容C1_3的自举作用，可以将第3个第三晶体管M3_3的控制极的电平进一步拉低，以将第3个第三晶体管M3_3尽可能导通完全，将信号ck2_3的低电平信号可以尽可能无电压损失的提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为低电平信号。由于第1个驱动选择信号端GX_1的信号为低电平，则第1个第二晶体管M2_1导通，以将第1个驱动节点N0_1的高电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出高电平信号。由于第2个驱动选择信号端GX_2的信号为低电平，则第2个第二晶体管M2_2导通，以将第2个驱动节点N0_2的高电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出高电平信号。由于第3个驱动选择信号端GX_3的信号为低电平，则第3个第二晶体管M2_3导通，以将第3个驱动节点N0_3的低电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出低电平信号。由于第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号，则第3个第一晶体管M1_3导通，第1个第一晶体管M1_1和第2个第一晶体管M1_2均截止。导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的低电平信号提供给级联输出端JO，以使级联输出端JO输出低电平信号。
在第一复位阶段T13，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的高电平信号提供给第一节点N1，使第一节点N1的信号为高电平信号。第八晶体管M8受第一节点N1的高电平的信号的控制可以截止。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第1个第四晶体管M4_1将第一参考信号端VREF1的高电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为 高电平信号。导通的第2个第四晶体管M4_2将第一参考信号端VREF1的高电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为高电平信号。导通的第3个第四晶体管M4_3将第一参考信号端VREF1的高电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为高电平信号。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1受第一节点N1的高电平信号的控制可以截止。由于第一节点N1的信号为高电平信号且第2个第五晶体管M5_2导通，因此第2个第三晶体管M3_2截止。由于第一节点N1的信号为高电平信号且第3个第五晶体管M5_3导通，因此第3个第三晶体管M3_3截止。由于第1个驱动选择信号端GX_1的信号为低电平，则第1个第二晶体管M2_1导通，以将第1个驱动节点N0_1的高电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出高电平信号。由于第2个驱动选择信号端GX_2的信号为低电平，则第2个第二晶体管M2_2导通，以将第2个驱动节点N0_2的高电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出高电平信号。由于第3个驱动选择信号端GX_3的信号为低电平，则第3个第二晶体管M2_3导通，以将第3个驱动节点N0_3的高电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出高电平信号。由于第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号，则第3个第一晶体管M1_3导通，第1个第一晶体管M1_1和第2个第一晶体管M1_2均截止。导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
需要说明的是，第1个驱动输出端GO_1至第3个驱动输出端GO_3输出的信号即为栅极扫描信号。在图5a中，相邻两个阶段之间具有保持阶段，即信号inp、ck1、ck2_1、ck2_2、ck2_3均为高电平时，可以使移位寄存器单元在信号稳定后进入下一个阶段。这样使得输入相邻两条栅线中的栅极扫描信 号的低电平之间具有间隔时长。示例性地，该间隔时长可以为1H。H代表一条栅极加载的栅极扫描信号的低电平的维持时长。
需要说明的是，由于第1个第一电容C1_1、第2个第一电容C1_2以及第3个第一电容C1_3的存在，若不设置第2个第五晶体管M5_2和第3个第五晶体管M5_3，而是将该位置处换成常规导线，则第1个驱动输出端GO_1的信号变化时，会由于第1个第一电容C1_1、第2个第一电容C1_2以及第3个第一电容C1_3之间的耦合作用，导致第2个驱动输出端GO_2和第3个驱动输出端GO_3输出的信号有尖峰电压存在。同理，在第2个驱动输出端GO_2的信号变化时，会由于第1个第一电容C1_1、第2个第一电容C1_2以及第3个第一电容C1_3之间的耦合作用，导致第1个驱动输出端GO_1和第3个驱动输出端GO_3输出的信号有尖峰电压存在。以及，第3个驱动输出端GO_3的信号变化时，会由于第1个第一电容C1_1、第2个第一电容C1_2以及第3个第一电容C1_3之间的耦合作用，导致第2个驱动输出端GO_2和第1个驱动输出端GO_1输出的信号有尖峰电压存在。基于此，本公开实施例设置了第2个第五晶体管M5_2和第3个第五晶体管M5_3，从而通过设置第2个第五晶体管M5_2和第3个第五晶体管M5_3可以将第2个第三晶体管M3_2的控制极和第3个第三晶体管M3_3的控制极与其他信号隔离开，进而避免信号相互影响，提高输出的稳定性。
在另一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图5b所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第一驱动模式时的另一些工作过程作以描述。示例性地，主要选取如图5b所示的信号时序图中的第一输入阶段T11、第一输出阶段T12以及第一复位阶段T13。其中，第一输出阶段T12可以包括：T121、T122和T123三个阶段。图3所示的移位寄存器单元结合图5b所示的信号时序图工作时的第一输入阶段T11、T121、T122和T123以及第一复位阶段T13，与图3所示的移位寄存器单元结合图5a所示的信号时序图工作时的第一输入阶段T11、T121、T122和T123以及第一复位阶段T13的工作过程基本相同，在此不作赘述。
需要说明的是，第1个驱动输出端GO_1至第3个驱动输出端GO_3输出的信号即为栅极扫描信号。在图5b中，在相邻两个阶段之间不设置上述保持阶段，这样使得输入相邻两条栅线中的栅极扫描信号的低电平之间不具有上述间隔时长。这样可以使移位寄存器单元结合图5b所示的信号时序图对栅线逐行扫描时的刷新时间，小于移位寄存器单元结合图5a所示的信号时序图对栅线逐行扫描时的扫描时间，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
需要说明的是，图3所示的移位寄存器单元结合图5a和图5b所示的信号时序图工作时，可以对每一条栅线输出栅极扫描信号，以对这些栅线进行逐行扫描。并且，图5a所示的信号ck2_1～ck2_3的时钟周期为8H，图5b所示的信号ck2_1～ck2_3的时钟周期为4H。
本公开实施例提供的上述移位寄存器单元的驱动方法，如图6所示，可以包括：在第二驱动模式时，一个显示帧可以包括第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23；
S210、在第二输入阶段T21，第一控制电路根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据第一节点、第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将至少两个驱动节点中的第m个驱动节点的信号提供给对应的驱动输出端；
S220、在第二输出阶段T22，第二控制电路根据第一节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将至少两个驱动节点中的第m个驱动节点的信号提供给对应的驱动输出端；
S230、在第二复位阶段T23，第一控制电路根据第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据第二节点的信号，控制 至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将至少两个驱动节点中的第m个驱动节点的信号提供给对应的驱动输出端。
在本公开一些实施例中，以有效电平为低电平为例，在第二驱动模式时，可以将对应第m个驱动节点的级联选择信号端的信号为低电平信号，其余级联选择信号端的信号为高电平信号。并且，将对应第m个驱动节点的驱动选择信号端的信号为低电平信号，其余驱动选择信号端的信号为高电平信号。
在本公开一些实施例中，可以在第二驱动模式时，控制每一级移位寄存器单元的第1个驱动输出端GO_1对耦接的栅线输出栅极扫描信号，以实现隔行扫描。
在一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图7a所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第二驱动模式时的工作过程作以描述。示例性地，主要选取如图7a所示的信号时序图中的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23。
并且，inp代表输入信号端INP的信号，ck1代表第一时钟信号端CK1的信号，ck2_1代表第1个第二时钟信号端CK2_1的信号，ck2_2代表第2个第二时钟信号端CK2_2的信号，ck2_3代表第3个第二时钟信号端CK2_3的信号，n0_1代表第1个驱动节点N0_1的信号，go_1代表第1个驱动输出端GO_1的信号，jo代表级联输出端JO的信号。并且，第1个驱动选择信号端GX_1的信号为低电平信号，第2个驱动选择信号端GX_2和第3个驱动选择信号端GX_3的信号为高电平信号。第1个级联选择信号端JX_1的信号为低电平信号，第2个级联选择信号端JX_2和第3个级联选择信号端JX_3的信号均为高电平信号。由于第2个驱动选择信号端GX_2和第3个驱动选择信号端GX_3的信号均为高电平信号，在本实施例中第2个第二晶体管M2_2和第3个第二晶体管M2_3均是截止的。以及，由于第2个级联选择信号端JX_2和第3个级联选择信号端JX_3的信号均为高电平信号，在本实施例中第2个第 一晶体管M1_2和第3个第一晶体管M1_3均是截止的。因此，在本实施例中可以仅将第1个驱动节点N0_1的信号输出给级联输出端JO和第1个驱动输出端GO_1，而第2个驱动节点N0_2和第3个驱动节点N0_3的信号均是不输出的。因此，第2个驱动节点N0_2和第3个驱动节点N0_3的信号的变化过程，对本实施例是没有影响的，因此，下面对第1个驱动节点N0_1的信号的变化进行说明，对第2个驱动节点N0_2和第3个驱动节点N0_3的信号的变化不再说明。
在第二输入阶段T21，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的低电平信号提供给第一节点N1，使第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的低电平提供给第二节点N2，以使第二节点N2的信号为低电平信号。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，进一步使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第1个第四晶体管M4_1将第一参考信号端VREF1的高电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为高电平信号。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1导通，以将信号ck2_1的高电平信号提供给第1个驱动节点N0_1，进一步使第1个驱动节点N0_1的信号为高电平信号。并且，导通的第1个第二晶体管M2_1将第1个驱动节点N0_1的高电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出高电平信号。以及，导通的第1个第一晶体管M1_1将第1个驱动节点N0_1的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
在第二输出阶段T22中，信号ck1为高电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3 均截止。因此第一节点N1处于浮接状态，由于第1个第一电容C1_1的作用，可以保持第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的高电平提供给第二节点N2，以使第二节点N2的信号为高电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均截止。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1导通，以将信号ck2_1的低电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为低电平信号。并由于第1个第一电容C1_1的自举作用，可以将第一节点N1的电平进一步拉低，以将第1个第三晶体管M3_1尽可能导通完全，将信号ck2_1的低电平信号可以尽可能无电压损失的提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为低电平信号。并且，导通的第1个第二晶体管M2_1将第1个驱动节点N0_1的低电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出低电平信号。以及，导通的第1个第一晶体管M1_1将第1个驱动节点N0_1的低电平信号提供给级联输出端JO，以使级联输出端JO输出低电平信号。
在第二复位阶段T23，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的高电平信号提供给第一节点N1，使第一节点N1的信号为高电平信号。第八晶体管M8受第一节点N1的高电平的信号的控制可以截止。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第1个第四晶体管M4_1将第一参考信号端VREF1的高电平信号提供给第1个驱动节点N0_1，使第1个驱动节点N0_1的信号为高电平信号。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。因此第1个第三晶体管M3_1受第一节点N1的 高电平信号的控制可以截止。并且，导通的第1个第二晶体管M2_1将第1个驱动节点N0_1的高电平信号提供给第1个驱动输出端GO_1，以使第1个驱动输出端GO_1输出高电平信号。以及，导通的第1个第一晶体管M1_1将第1个驱动节点N0_1的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
需要说明的是，第1个驱动输出端GO_1输出的信号即为栅极扫描信号。在图7a中，相邻两个阶段之间具有保持阶段，即信号inp、ck1、ck2_1、ck2_2、ck2_3均为高电平时，可以使移位寄存器单元在信号稳定后进入下一个阶段。这样使得相邻两级移位寄存器单元的第1个驱动输出端GO_1输出的栅极扫描信号的低电平之间具有间隔时长。示例性地，该间隔时长可以为5H。
在另一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图7b所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第二驱动模式时的另一些工作过程作以描述。示例性地，主要选取如图7b所示的信号时序图中的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23。并且，图3所示的移位寄存器单元结合图7b所示的信号时序图工作时的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23，与图3所示的移位寄存器单元结合图7a所示的信号时序图工作时的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23的工作过程基本相同，在此不作赘述。
需要说明的是，第1个驱动输出端GO_1输出的信号即为栅极扫描信号。在图7b中，相邻两个阶段之间具有保持阶段，即信号inp、ck1、ck2_1、ck2_2、ck2_3均为高电平时，可以使移位寄存器单元在信号稳定后进入下一个阶段。这样使得相邻两级移位寄存器单元的第1个驱动输出端GO_1输出的栅极扫描信号的低电平之间具有间隔时长。示例性地，该间隔时长可以为1H。
在又一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图7c所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第二驱动模式时的另一些工作过程作以描述。示例性地，主要选取如图7b所示的信号时序图中的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23。 并且，图3所示的移位寄存器单元结合图7c所示的信号时序图工作时的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23，与图3所示的移位寄存器单元结合图7a所示的信号时序图工作时的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23的工作过程基本相同，在此不作赘述。
需要说明的是，第1个驱动输出端GO_1输出的信号即为栅极扫描信号。在图7c中，在相邻两个阶段之间不设置上述保持阶段，这样使得相邻两级移位寄存器单元的第1个驱动输出端GO_1输出的栅极扫描信号的低电平之间不具有上述间隔时长。这样可以使移位寄存器单元结合图7c所示的信号时序图对栅线隔行扫描时的刷新时间，小于移位寄存器单元结合图7b所示的信号时序图对栅线隔行扫描时的刷新时间，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
需要说明的是，图3所示的移位寄存器单元结合图7a至图7c所示的信号时序图工作时，可以对与每一级移位寄存器单元的第1个驱动输出端GO_1耦接的栅线输出栅极扫描信号，以仅对这些栅线进行扫描。并且，图7a所示的信号ck2_1～ck2_3的时钟周期为12H，图7b所示的信号ck2_1～ck2_3的时钟周期为4H，图7c所示的信号ck2_1～ck2_3的时钟周期为2H。
在本公开另一些实施例中，可以在第二驱动模式时，控制每一级移位寄存器单元的第2个驱动输出端GO_2对耦接的栅线输出栅极扫描信号，以实现隔行扫描。
在一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图8所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第二驱动模式时的工作过程作以描述。示例性地，主要选取如图8所示的信号时序图中的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23。
并且，inp代表输入信号端INP的信号，ck1代表第一时钟信号端CK1的信号，ck2_1代表第1个第二时钟信号端CK2_1的信号，ck2_2代表第2个第二时钟信号端CK2_2的信号，ck2_3代表第3个第二时钟信号端CK2_3的信号，n0_2代表第2个驱动节点N0_2的信号，go_2代表第2个驱动输出端GO_2 的信号，jo代表级联输出端JO的信号。并且，第2个驱动选择信号端GX_2的信号为低电平信号，第1个驱动选择信号端GX_1和第3个驱动选择信号端GX_3的信号为高电平信号。第2个级联选择信号端JX_2的信号为低电平信号，第1个级联选择信号端JX_1和第3个级联选择信号端JX_3的信号均为高电平信号。由于第1个驱动选择信号端GX_1和第3个驱动选择信号端GX_3的信号均为高电平信号，在本实施例中第1个第二晶体管M2_1和第3个第二晶体管M2_3均是截止的。以及，由于第1个级联选择信号端JX_1和第3个级联选择信号端JX_3的信号均为高电平信号，在本实施例中第1个第一晶体管M1_1和第3个第一晶体管M1_3均是截止的。因此，在本实施例中可以仅将第2个驱动节点N0_2的信号输出给级联输出端JO和第2个驱动输出端GO_2，而第1个驱动节点N0_1和第3个驱动节点N0_3的信号均是不输出的。因此，第1个驱动节点N0_1和第3个驱动节点N0_3的信号的变化过程，对本实施例是没有影响的，因此，下面对第2个驱动节点N0_2的信号的变化进行说明，对第1个驱动节点N0_1和第3个驱动节点N0_3的信号的变化不再说明。
在第二输入阶段T21中，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的低电平信号提供给第一节点N1，使第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的低电平提供给第二节点N2，以使第二节点N2的信号为低电平信号。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，进一步使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第2个第四晶体管M4_2将第一参考信号端VREF1的高电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为高电平信号。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。并且，第2个第五晶体管M5_2也导通， 可以使第2个第三晶体管M3_2的控制极的电平为低电平，因此第2个第三晶体管M3_2导通，以将信号ck2_2的高电平信号提供给第2个驱动节点N0_2，进一步使第2个驱动节点N0_2的信号为高电平信号。并且，导通的第2个第二晶体管M2_2将第2个驱动节点N0_2的高电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出高电平信号。以及，导通的第2个第一晶体管M1_2将第2个驱动节点N0_2的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
在第二输出阶段T22中，信号ck1为高电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均截止。因此第一节点N1处于浮接状态，由于第1个第一电容C1_1的作用，可以保持第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的高电平提供给第二节点N2，以使第二节点N2的信号为高电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均截止。由于第2个第一电容C1_2的作用，可以保持第2个第三晶体管M3_2的控制极的电平为低电平，因此第2个第三晶体管M3_2导通，以将信号ck2_2的低电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为低电平信号。并由于第2个第一电容C1_2的自举作用，可以将第2个第三晶体管M3_2的控制极的电平进一步拉低，以将第2个第三晶体管M3_2尽可能导通完全，将信号ck2_2的低电平信号可以尽可能无电压损失的提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为低电平信号。并且，导通的第2个第二晶体管M2_2将第2个驱动节点N0_2的低电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出低电平信号。以及，导通的第2个第一晶体管M1_2将第2个驱动节点N0_2的低电平信号提供给级联输出端JO，以使级联输出端JO输出低电平信号。
在第二复位阶段T23，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导 通。导通的第六晶体管M6将信号inp的高电平信号提供给第一节点N1，使第一节点N1的信号为高电平信号。第八晶体管M8受第一节点N1的高电平的信号的控制可以截止。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第2个第四晶体管M4_2将第一参考信号端VREF1的高电平信号提供给第2个驱动节点N0_2，使第2个驱动节点N0_2的信号为高电平信号。由于第一节点N1的信号为高电平信号且第2个第五晶体管M5_2导通，因此第2个第三晶体管M3_2截止。并且，导通的第2个第二晶体管M2_2将第2个驱动节点N0_2的高电平信号提供给第2个驱动输出端GO_2，以使第2个驱动输出端GO_2输出高电平信号。以及，导通的第2个第一晶体管M1_2将第2个驱动节点N0_2的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
需要说明的是，第2个驱动输出端GO_2输出的信号即为栅极扫描信号。在图8中，相邻两个阶段之间具有保持阶段，即信号inp、ck1、ck2_1、ck2_2、ck2_3均为高电平时，可以使移位寄存器单元在信号稳定后进入下一个阶段。这样使得相邻两级移位寄存器单元的第2个驱动输出端GO_2输出的栅极扫描信号的低电平之间具有间隔时长。示例性地，该间隔时长可以为5H。示例性地，在控制移位寄存器单元仅的第2个驱动输出端GO_2输出的信号时，可以降低信号ck1、ck2_1、ck2_2、ck2_3的时钟周期，以使相邻两级移位寄存器单元的第2个驱动输出端GO_2输出的栅极扫描信号的低电平之间的间隔时长降低，甚至不具有间隔时长，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
在本公开又一些实施例中，可以在第二驱动模式时，控制每一级移位寄存器单元的第3个驱动输出端GO_3对耦接的栅线输出栅极扫描信号，以实现隔行扫描。
在一些示例中，下面以图3所示的移位寄存器单元的结构为例，结合图9 所示的信号时序图，对本公开实施例提供的上述移位寄存器单元在第二驱动模式时的工作过程作以描述。示例性地，主要选取如图9所示的信号时序图中的第二输入阶段T21、第二输出阶段T22以及第二复位阶段T23。
并且，inp代表输入信号端INP的信号，ck1代表第一时钟信号端CK1的信号，ck2_1代表第1个第二时钟信号端CK2_1的信号，ck2_2代表第2个第二时钟信号端CK2_2的信号，ck2_3代表第3个第二时钟信号端CK2_3的信号，n0_2代表第2个驱动节点N0_2的信号，go_2代表第2个驱动输出端GO_2的信号，jo代表级联输出端JO的信号。并且，第3个驱动选择信号端GX_3的信号为低电平信号，第1个驱动选择信号端GX_1和第2个驱动选择信号端GX_2的信号为高电平信号。第3个级联选择信号端JX_3的信号为低电平信号，第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号。由于第1个驱动选择信号端GX_1和第2个驱动选择信号端GX_2的信号均为高电平信号，在本实施例中第1个第二晶体管M2_1和第2个第二晶体管M2_2均是截止的。以及，由于第1个级联选择信号端JX_1和第2个级联选择信号端JX_2的信号均为高电平信号，在本实施例中第1个第一晶体管M1_1和第2个第一晶体管M1_2均是截止的。因此，在本实施例中可以仅将第3个驱动节点N0_3的信号输出给级联输出端JO和第3个驱动输出端GO_3，而第1个驱动节点N0_1和第2个驱动节点N0_2的信号均是不输出的。因此，第1个驱动节点N0_1和第2个驱动节点N0_2的信号的变化过程，对本实施例是没有影响的，因此，下面对第3个驱动节点N0_3的信号的变化进行说明，对第1个驱动节点N0_1和第2个驱动节点N0_2的信号的变化不再说明。
在第二输入阶段T21中，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的低电平信号提供给第一节点N1，使第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的低电平提供给第二节点N2，以使 第二节点N2的信号为低电平信号。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，进一步使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第3个第四晶体管M4_3将第一参考信号端VREF1的高电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为高电平信号。由于第二参考信号端VREF2的信号为低电平信号，可以控制第1个第五晶体管M5_1导通。并且，第3个第五晶体管M5_3也导通，可以使第3个第三晶体管M3_3的控制极的电平为低电平，因此第3个第三晶体管M3_3导通，以将信号ck2_3的高电平信号提供给第3个驱动节点N0_3，进一步使第3个驱动节点N0_3的信号为高电平信号。并且，导通的第3个第二晶体管M2_3将第3个驱动节点N0_3的高电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出高电平信号。以及，导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
在第二输出阶段T22中，信号ck1为高电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均截止。因此第一节点N1处于浮接状态，由于第1个第一电容C1_1的作用，可以保持第一节点N1的信号为低电平信号。第八晶体管M8受第一节点N1的低电平的信号的控制可以导通，以将信号ck1的高电平提供给第二节点N2，以使第二节点N2的信号为高电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均截止。由于第3个第一电容C1_3的作用，可以保持第3个第三晶体管M3_3的控制极的电平为低电平，因此第3个第三晶体管M3_3导通，以将信号ck2_3的低电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为低电平信号。并由于第3个第一电容C1_3的自举作用，可以将第3个第三晶体管M3_3的控制极的电平进一步拉低，以将第3个第三晶体管M3_3尽可能导通完全，将信号ck2_3的低电平信号可以尽可能无电压损失的提供给第3个驱动节点N0_3，使第3 个驱动节点N0_3的信号为低电平信号。并且，导通的第3个第二晶体管M2_3将第3个驱动节点N0_3的低电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出低电平信号。以及，导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的低电平信号提供给级联输出端JO，以使级联输出端JO输出低电平信号。
在第二复位阶段T23，信号ck1为低电平信号，可以控制第六晶体管M6、第七晶体管M7、第2个第五晶体管M5_2以及第3个第五晶体管M5_3均导通。导通的第六晶体管M6将信号inp的高电平信号提供给第一节点N1，使第一节点N1的信号为高电平信号。第八晶体管M8受第一节点N1的高电平的信号的控制可以截止。导通的第七晶体管M7将第二参考信号端VREF2的低电平信号提供给第二节点N2，使第二节点N2的信号为低电平信号，以控制第1个第四晶体管M4_1、第2个第四晶体管M4_2、第3个第四晶体管M4_3均导通。导通的第3个第四晶体管M4_3将第一参考信号端VREF1的高电平信号提供给第3个驱动节点N0_3，使第3个驱动节点N0_3的信号为高电平信号。由于第一节点N1的信号为高电平信号且第3个第五晶体管M5_3导通，因此第3个第三晶体管M3_3截止。并且，导通的第3个第二晶体管M2_3将第3个驱动节点N0_3的高电平信号提供给第3个驱动输出端GO_3，以使第3个驱动输出端GO_3输出高电平信号。以及，导通的第3个第一晶体管M1_3将第3个驱动节点N0_3的高电平信号提供给级联输出端JO，以使级联输出端JO输出高电平信号。
需要说明的是，第3个驱动输出端GO_3输出的信号即为栅极扫描信号。在图7a中，相邻两个阶段之间具有保持阶段，即信号inp、ck1、ck2_1、ck2_2、ck2_3均为高电平时，可以使移位寄存器单元在信号稳定后进入下一个阶段。这样使得相邻两级移位寄存器单元的第1个驱动输出端GO_1输出的栅极扫描信号的低电平之间具有间隔时长。示例性地，该间隔时长可以为5H。示例性地，在控制移位寄存器单元仅的第3个驱动输出端GO_3输出的信号时，可以降低信号ck1、ck2_1、ck2_2、ck2_3的时钟周期，以使相邻两级移位寄 存器单元的第3个驱动输出端GO_3输出的栅极扫描信号的低电平之间的间隔时长降低，甚至不具有间隔时长，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
本公开实施例还提供了栅极驱动电路，可以包括级联的多个上述移位寄存器单元。其中，第一级移位寄存器单元的输入信号端与帧起始信号线耦接。并且，每相邻两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的级联输出端耦接。这样可以将上一级移位寄存器单元的级联输出端输出的信号，输入下一级移位寄存器单元的输入信号端，以使下一级移位寄存器单元的级联信号端和驱动信号端可以输出相应的信号。
示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，如图10所示，第一级移位寄存器单元SR1的输入信号端INP与帧起始信号线STV耦接。第二级移位寄存器单元SR2的输入信号端INP与第一级移位寄存器单元SR1的级联输出端JO耦接。第三级移位寄存器单元SR3的输入信号端INP与第二级移位寄存器单元SR2的级联输出端JO耦接。第四级移位寄存器单元SR4的输入信号端INP与第三级移位寄存器单元SR3的级联输出端JO耦接。
需要说明的是，上述栅极驱动电路中的每个移位寄存器单元的具体结构与本公开上述移位寄存器单元在功能和结构上均相同，重复之处不再赘述。
在本公开一些实施例中，各级移位寄存器单元的第一参考信号端VREF1均与同一第一参考信号线耦接，以及，各级移位寄存器单元的第二参考信号端VREF2均与同一第二参考信号线耦接。
本公开实施例还提供了显示装置，如图11所示，显示装置可以包括显示面板100和时序控制器200。其中，显示面板100可以包括：多个阵列排布的像素单元、多条栅线GA、与栅线GA绝缘相交设置的多条数据线DA、分别与各条栅线GA耦接的栅极驱动电路110、以及与各条数据线DA耦接的源极驱动电路120。示例性地，源极驱动电路120可以设置为2个，其中一个源极驱动电路120耦接一半数量的数据线，另一个源极驱动电路120耦接另一半 数量的数据线。当然，源极驱动电路120也可以设置3个、4个、或更多个，其可以根据实际应用的需求进行设计确定，在此不作限定。
在本公开一些实施例中，每个像素单元可以包括多个子像素SPX。示例性地，像素单元可以包括沿列方向排列的多个不同颜色的子像素。例如，像素单元可以包括列方向依次排列的第一颜色子像素、第二颜色子像素以及第三颜色子像素。这样可以使一行子像素的颜色相同。例如可以采用第一颜色子像素行、第二颜色子像素行以及第三颜色子像素行的形式重复排列。
示例性地，第一颜色子像素、第二颜色子像素以及第三颜色子像素可以从红色子像素，绿色子像素以及蓝色子像素中进行选取。例如，第一颜色子像素为红色子像素，第二颜色子像素为绿色子像素，第三颜色子像素为蓝色子像素，这样可以采用红色子像素行、绿色子像素行以及蓝色子像素行的形式重复排列，以通过红绿蓝白进行混色，实现彩色显示。例如，如图12所示，第一行子像素为红色子像素R11～R16，第二行子像素为绿色子像素G11～G16，第三行子像素为蓝色子像素B11～B16，第四行子像素为红色子像素R21～R26，第五行子像素为绿色子像素G21～G26，第六行子像素为蓝色子像素B21～B26，第七行子像素为红色子像素R31～R36，第八行子像素为绿色子像素G31～G36，第九行子像素为蓝色子像素B31～B36，第十行子像素为红色子像素R41～R46，第十一行子像素为绿色子像素G41～G46，第十二行子像素为蓝色子像素B41～B46。并且，红色子像素R11、绿色子像素G11以及蓝色子像素B11为一个像素单元，红色子像素R12、绿色子像素G12以及蓝色子像素B12为一个像素单元，红色子像素R13、绿色子像素G13以及蓝色子像素B13为一个像素单元，红色子像素R14、绿色子像素G14以及蓝色子像素B14为一个像素单元，红色子像素R15、绿色子像素G15以及蓝色子像素B15为一个像素单元，红色子像素R16、绿色子像素G16以及蓝色子像素B16为一个像素单元。其余同理，可依此类推，在此不作赘述。
需要说明的是，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
示例性地，参见图13所示，每个像素SPX中可以包括晶体管11和像素电极12。例如，一行子像素SPX对应耦接一条栅线，一列子像素SPX对应耦接一条数据线。例如，晶体管11的栅极与对应的栅线耦接，晶体管11的源极与对应的数据线耦接，晶体管11的漏极与像素电极12耦接。需要说明的是，本公开像素阵列结构还可以是双栅结构，即相邻两行子像素之间设置两条栅线，此排布方式可以减少一半的数据线，即有的相邻两列子像素之间包含数据线，有的相邻两列子像素之间不可以包括数据线，具体子像素排布结构和数据线，扫描线的排布方式不限定。
示例性地，时序控制器200可以在每一个显示帧中获取待显示画面的显示数据，时序控制器200可以向栅极驱动电路110输入时钟信号，以使栅极驱动电路110可以根据输入的时钟信号，向栅线GA输出栅极扫描信号，从而对栅线GA进行扫描，以控制耦接的子像素中的晶体管导通。以及，时序控制器200向源极驱动电路120输入相应的显示数据，以使源极驱动电路120可以根据输入的显示数据，向耦接的数据线DA输入相应的数据电压，从而通过子像素中导通的晶体管将数据线DA上的电压输入到子像素中，以对子像素充电，进而使各子像素充入相应的数据电压，实现画面显示功能。
需要说明的是，本公开实施例中的显示面板可以为液晶显示面板、OLED显示面板等，在此不作限定。示例性地，液晶显示面板一般可以包括对盒的上基板和下基板，以及封装在上基板和下基板之间的液晶分子。在显示画面时，由于加载在子像素的像素电极上的数据电压和公共电极上的公共电极电压之间具有电压差，该电压差可以形成电场，从而使液晶分子在该电场的作用下进行偏转。由于不同强度的电场使液晶分子的偏转程度不同，从而导致子像素的透过率不同，以使子像素SPX实现不同灰阶的亮度，进而实现画面显示。
在本公开一些实施例中，如图10所示，栅极驱动电路可以包括级联的多个移位寄存器单元。栅极驱动电路中的每一个移位寄存器单元的每一个驱动输出端与多条栅线一一对应耦接，这样可以通过驱动输出端对耦接的栅极输 出栅极扫描信号。示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，如图10所示，第一级移位寄存器单元SR1的第1个驱动输出端GO_1与栅线GA1耦接，第一级移位寄存器单元SR1的第2个驱动输出端GO_2与栅线GA2耦接，第一级移位寄存器单元SR1的第3个驱动输出端GO_3与栅线GA3耦接。第二级移位寄存器单元SR2的第1个驱动输出端GO_1与栅线GA4耦接，第二级移位寄存器单元SR2的第2个驱动输出端GO_2与栅线GA5耦接，第二级移位寄存器单元SR2的第3个驱动输出端GO_3与栅线GA6耦接。第三级移位寄存器单元SR3的第1个驱动输出端GO_1与栅线GA7耦接，第三级移位寄存器单元SR3的第2个驱动输出端GO_2与栅线GA8耦接，第三级移位寄存器单元SR3的第3个驱动输出端GO_3与栅线GA9耦接。第四级移位寄存器单元SR4的第1个驱动输出端GO_1与栅线GA10耦接，第四级移位寄存器单元SR4的第2个驱动输出端GO_2与栅线GA11耦接，第四级移位寄存器单元SR4的第3个驱动输出端GO_3与栅线GA12耦接。
示例性地，栅极扫描信号的有效电平可以控制对应栅线耦接的子像素中的晶体管导通，无效电平可以控制对应栅线耦接的子像素中的晶体管截止。示例性地，结合图3所示的移位寄存器单元的结构，栅极扫描信号的有效电平可以为低电平，无效电平为高电平。当然，还可以使栅极扫描信号的有效电平为高电平，无效电平为低电平，在此不作限定。
在本公开一些实施例中，显示面板还可以包括多条时钟信号线和帧起始信号线，并且该多条时钟信号线和帧起始信号线分别与栅极驱动电路耦接。这样可以通过时钟信号线向栅极驱动电路输入相应的多个时钟信号，该多个时钟信号分别输入移位寄存器单元的第一时钟信号端CK1和M个第二时钟信号端，从而使移位寄存器单元对耦接的栅线输出栅极扫描信号。示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，如图10所示，显示面板可以包括4条时钟信号线CKS1～CKS4和1条帧起始信号线STVS_1。其中，该4条时钟信号线 CKS1～CKS4和1条帧起始信号线STVS_1分别与栅极驱动电路110耦接。并且，CKS1作为第一时钟信号线，CKS2作为第二时钟信号线，CKS3作为第三时钟信号线，CKS4作为第四时钟信号线。并且，第4k_3级移位寄存器单元的第一时钟信号端CK1、第4k_2级移位寄存器单元的第1个第二时钟信号端CK2_1、第4k_1级移位寄存器单元的第2个第二时钟信号端CK2_2以及第4k级移位寄存器单元的第3个第二时钟信号端CK2_3，均与第一时钟信号线耦接；第4k_3级移位寄存器单元的第1个第二时钟信号端CK2_1、第4k_2级移位寄存器单元的第2个第二时钟信号端CK2_2、第4k_1级移位寄存器单元的第3个第二时钟信号端CK2_3以及第4k级移位寄存器单元的第一时钟信号端CK1，均与第二时钟信号线耦接；第4k_3级移位寄存器单元的第2个第二时钟信号端CK2_2、第4k_2级移位寄存器单元的第3个第二时钟信号端CK2_3、第4k_1级移位寄存器单元的第一时钟信号端CK1以及第4k级移位寄存器单元的第1个第二时钟信号端CK2_1，均与第三时钟信号线耦接；第4k_3级移位寄存器单元的第3个第二时钟信号端CK2_3、第4k_2级移位寄存器单元的第一时钟信号端CK1、第4k_1级移位寄存器单元的第1个第二时钟信号端CK2_1以及第4k级移位寄存器单元的第2个第二时钟信号端CK2_2，均与第三时钟信号线耦接；k为大于0的整数。
需要说明的是，图10仅是以4条时钟信号线和1条帧起始信号线为例进行说明，在实际应用中，时钟信号线和帧起始信号线的具体数量可以根据实际应用的需求进行确定，在此不作限定，例如也可以是2的整数倍的其他数量的时钟信号线和帧起始信号线，如2、4、6、10、12等条数的时钟信号线和帧起始信号线。
在本公开一些实施例中，显示面板还可以包括多条级联选择信号线和多条驱动选择信号线，并且栅极驱动电路中的移位寄存器单元的级联选择信号端与级联选择信号线耦接，栅极驱动电路中的移位寄存器单元的驱动选择信号端与驱动选择信号线耦接。示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，如图10所示， 显示面板可以包括3条级联选择信号线JXS1～JXS3和3条驱动选择信号线GXS1～GXS3。其中，该3条级联选择信号线JXS1～JXS3分别与栅极驱动电路110中的移位寄存器单元的级联选择信号端耦接。以及，该和3条驱动选择信号线GXS1～GXS3分别与栅极驱动电路110中的移位寄存器单元的驱动选择信号端耦接。并且，JXS1作为第一级联选择信号线，JXS2作为第二级联选择信号线，JXS3作为第三级联选择信号线。GXS1作为第一驱动选择信号线，GXS2作为第二驱动选择信号线，GXS3作为第三驱动选择信号线。并且，各级移位寄存器单元的第1个级联选择信号端JX_1与第一级联选择信号线耦接，各级移位寄存器单元的第2个级联选择信号端JX_2与第二级联选择信号线耦接，各级移位寄存器单元的第3个级联选择信号端JX_3与第三级联选择信号线耦接。以及，各级移位寄存器单元的第1个驱动选择信号端GX_1与第一驱动选择信号线耦接，各级移位寄存器单元的第2个驱动选择信号端GX_2与第二驱动选择信号线耦接，各级移位寄存器单元的第3个驱动选择信号端GX_3与第三驱动选择信号线耦接。
需要说明的是，图10仅是以3条级联选择信号线JXS1～JXS3和3条驱动选择信号线GXS1～GXS3为例进行说明，在实际应用中，级联选择信号线和驱动选择信号线的具体数量可以根据实际应用的需求进行确定，在此不作限定。
在本公开一些实施例中，可以使一行像素单元对应栅极驱动电路中的一个移位寄存器单元。并且，每一个移位寄存器单元的第m个驱动输出端耦接同一颜色子像素对应的栅线。示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，如图10与图12所示，第一级移位寄存器单元至第四级移位寄存器单元的第1个驱动输出端GO_1耦接红色子像素对应的栅线GA1、GA4、GA7、GA10。第一级移位寄存器单元至第四级移位寄存器单元的第2个驱动输出端GO_2耦接绿色子像素对应的栅线GA2、GA5、GA8、GA11。第一级移位寄存器单元至第四级移位寄存器单元的第3个驱动输出端GO_3耦接红色子像素对应的栅线GA3、 GA6、GA9、GA12。
在本公开一些实施例中，可以仅在栅线的第一端设置栅极驱动电路。也可以仅在栅线的第二端设置栅极驱动电路。也可以在栅线的第一端和第二端均设置栅极驱动电路，以使耦接于同一栅线的移位寄存器单元同时向栅线输入栅极扫描信号的有效电平。示例性地，如图11所示，在多条栅线的左侧设置一个栅极驱动电路。或者，如图13所示，在多条栅线的左侧和右侧分别设置一个栅极驱动电路。
本公开实施例还提供了显示装置的控制方法，如图14所示，可以包括如下步骤：
S10、在第一驱动模式时，在一个显示帧中，对各时钟信号线加载不同的第一时钟信号，对各驱动选择信号线加载栅极导通信号，对第M个驱动输出电路耦接的级联选择信号线加载栅极导通信号，对其余级联选择信号线加载栅极截止信号，控制各移位寄存器单元顺序工作，将至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端，以及将至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个驱动节点的驱动输出端，对多条栅线逐行扫描。
在一些示例中，栅极驱动电路通过驱动输出端对耦接的栅线输出栅极扫描信号，该栅极扫描信号的有效电平可以控制对应栅线耦接的晶体管导通，无效电平可以控制对应栅线耦接的晶体管截止。示例性地，该栅极扫描信号的有效电平可以为高电平，无效电平为低电平。或者，该栅极扫描信号的有效电平也可以为低电平，无效电平为高电平，在此不作限定。
可选地，第一时钟信号的有效电平用于输出对栅线进行扫描的栅极扫描信号的有效电平。可选地，第一时钟信号的有效电平的维持时长相同。可选地，第一时钟信号的时钟周期相同。
示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，在第一驱动模式时，图10所示的栅极驱动电路对应的信号时序图，如图15所示。其中，cks1_1代表输入到第一时 钟信号线CKS1上的第一时钟信号，cks2_1代表输入到第二时钟信号线CKS2上的第一时钟信号，cks3_1代表输入到第三时钟信号线CKS3上的第一时钟信号，cks4_1代表输入到第四时钟信号线CKS4上的第一时钟信号，stvs_1代表输入到帧起始信号线STVS_1上的帧起始信号。并且，信号ga1_1代表栅极驱动电路110输出到栅线GA1上的栅极扫描信号，信号ga2_1代表栅极驱动电路110输出到栅线GA2上的栅极扫描信号，……信号ga10_1代表栅极驱动电路110输出到栅线GA10上的栅极扫描信号，信号ga11_1代表栅极驱动电路110输出到栅线GA11上的栅极扫描信号，信号ga12_1代表栅极驱动电路110输出到栅线GA12上的栅极扫描信号。并且，对第一驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第1个第二晶体管M2_1均导通。对第二驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第2个第二晶体管M2_2均导通。对第三驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第3个第二晶体管M2_3均导通。以及，对第一级联选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第1个第一晶体管M1_1均截止。对第二驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第2个第一晶体管M1_2均截止。对第三驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第3个第一晶体管M1_3均导通。当然，栅极导通信号也可以为高电平信号，栅极截止信号也可以为低电平信号，在此不作限定。
以及，以低电平为栅极扫描信号的有效电平为例，信号stvs_1输入移位寄存器单元SR1的输入信号端INP，移位寄存器单元SR1将第一时钟信号cks2_1的第一个低电平，通过第1个驱动输出端GO_1输出到栅线GA1上，以产生栅极扫描信号ga1_1中的低电平。移位寄存器单元SR1将第一时钟信号cks3_1的第一个低电平，通过第2个驱动输出端GO_2输出到栅线GA2上，以产生栅极扫描信号ga2_1中的低电平。移位寄存器单元SR1将第一时钟信号cks4_1的第一个低电平，通过第3个驱动输出端GO_3输出到栅线GA3上， 以产生栅极扫描信号ga3_1中的低电平。栅极扫描信号ga3_1输入移位寄存器单元SR2的输入信号端INP，移位寄存器单元SR2将第一时钟信号cks1_1的第二个低电平，通过第1个驱动输出端GO_1输出到栅线GA4上，以产生栅极扫描信号ga4_1中的低电平。移位寄存器单元SR2将第一时钟信号cks2_1的第二个低电平，通过第2个驱动输出端GO_2输出到栅线GA5上，以产生栅极扫描信号ga5_1中的低电平。移位寄存器单元SR2将第一时钟信号cks3_1的第二个低电平，通过第3个驱动输出端GO_3输出到栅线GA6上，以产生栅极扫描信号ga6_1中的低电平。栅极扫描信号ga6_1输入移位寄存器单元SR3的输入信号端INP，移位寄存器单元SR3将第一时钟信号cks4_1的第二个低电平，通过第1个驱动输出端GO_1输出到栅线GA7上，以产生栅极扫描信号ga7_1中的低电平。移位寄存器单元SR3将第一时钟信号cks1_1的第三个低电平，通过第2个驱动输出端GO_2输出到栅线GA8上，以产生栅极扫描信号ga8_1中的低电平。移位寄存器单元SR3将第一时钟信号cks2_1的第三个低电平，通过第3个驱动输出端GO_3输出到栅线GA9上，以产生栅极扫描信号ga9_1中的低电平。栅极扫描信号ga9_1输入移位寄存器单元SR4的输入信号端INP，移位寄存器单元SR4将第一时钟信号cks3_1的第三个低电平，通过第1个驱动输出端GO_1输出到栅线GA10上，以产生栅极扫描信号ga10_1中的低电平。移位寄存器单元SR4将第一时钟信号cks4_1的第三个低电平，通过第2个驱动输出端GO_2输出到栅线GA11上，以产生栅极扫描信号ga11_1中的低电平。移位寄存器单元SR4将第一时钟信号cks1_1的第四个低电平，通过第3个驱动输出端GO_3输出到栅线GA12上，以产生栅极扫描信号ga12_1中的低电平。
并且，如图15所示，各第一时钟信号cks1_1～cks4_1的低电平的维持时长相同，各第一时钟信号cks1_1～cks4_1的时钟周期ts11相同。并且，第一时钟信号cks1_1～cks4_1的低电平可以为其有效电平，高电平为其无效电平。当然，在移位寄存器单元将第一时钟信号的高电平输出，以产生栅极扫描信号中控制晶体管导通的高电平信号时，可以将第一时钟信号的高电平作为其 有效电平，低电平作为其无效电平。
可选地，如图15所示，各第一时钟信号cks1_1～cks4_1的时钟周期ts11可以为8H。或者，也可以使各第一时钟信号的时钟周期可以为4H。在实际应用中，可以根据实际应用的需求确定各第一时钟信号的时钟周期的具体数值，在此不作限定。
S20、在第二驱动模式时，在一个显示帧中，对各时钟信号线加载第二时钟信号，对第m个级联输出电路耦接的驱动选择信号线加载栅极导通信号，对其余驱动选择信号线加载栅极截止信号，对第m个驱动输出电路耦接的级联选择信号线加载栅极导通信号，且对其余级联选择信号线加载栅极截止信号，控制各移位寄存器单元顺序工作，将至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端，以及将第m个驱动节点的信号提供给对应的驱动输出端，对多条栅线隔行扫描。可选地，第二时钟信号的时钟周期与第一时钟信号的时钟周期不同。
在本公开一些实施例中，M＝3，步骤S20可以包括：在第二驱动模式时，对第一时钟信号线和第三时钟信号线加载相同的第二时钟信号，且对第二时钟信号线和第四时钟信号线加载相同的第二时钟信号，对第一级联选择信号线加载栅极导通信号，且对第二级联选择信号线和第三级联选择信号线均加载栅极截止信号，对第一驱动选择信号线加载栅极导通信号，且对第二驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各移位寄存器单元顺序工作，将第1个驱动节点的信号提供给级联输出端，以及将第1个驱动节点的信号提供给第1个驱动输出端，对每一个第一颜色子像素行耦接的栅线进行扫描；其中，对第一时钟信号线和第二时钟信号端加载的第二时钟信号不同。
示例性地，第一颜色子像素行可以为红色子像素行，这样在第二驱动模式时，对第一时钟信号线和第三时钟信号线加载相同的第二时钟信号，且对第二时钟信号线和第四时钟信号线加载相同的第二时钟信号，对第一级联选择信号线加载栅极导通信号，且对第二级联选择信号线和第三级联选择信号 线均加载栅极截止信号，对第一驱动选择信号线加载栅极导通信号，且对第二驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各移位寄存器单元顺序工作，将第1个驱动节点的信号提供给级联输出端，及将第1个驱动节点的信号提供给第1个驱动输出端，对每一个红色子像素行耦接的栅线进行扫描。也就是说，在第二驱动模式时，在一个显示帧中，可以仅对红色子像素行耦接的栅极输出栅极扫描信号，从而仅对红色子像素输入数据电压。
可选地，可以使第二时钟信号的时钟周期不大于第一时钟信号的时钟周期的3/2。示例性地，可以使第二时钟信号的时钟周期等于第一时钟信号的时钟周期的3/2。例如，如图15与图16a所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的时钟周期ts21可以为12H。或者，也可以使第二时钟信号的时钟周期等于第一时钟信号的时钟周期的1/2。例如，如图15与图16b所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的时钟周期ts22可以为4H。第一时钟信号的时钟周期为4H，第二时钟信号的时钟周期可以为2H。或者，也可以使第二时钟信号的时钟周期等于第一时钟信号的时钟周期的1/4。例如，如图15与图16c所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的时钟周期ts23可以为2H。
当然，在实际应用中，在一个显示帧中仅对第一颜色子像素行耦接的栅线进行扫描时加载的第二时钟信号的时钟周期与第一时钟信号的时钟周期之间的关系，可以根据实际应用的需求进行确定，在此不作限定。
示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，在第二驱动模式时，对每一个红色子像素行耦接的栅线进行扫描时，对应的信号时序图，如图16a至图16c所示。其中，cks1_2代表输入到第一时钟信号线CKS1上的第二时钟信号，cks2_2代表输入到第二时钟信号线CKS2上的第二时钟信号，cks3_2代表输入到第三时钟信号线CKS3上的第二时钟信号，cks4_2代表输入到第四时钟信号线 CKS4上的第二时钟信号，stvs_2代表输入到帧起始信号线STVS_2上的帧起始信号。并且，信号ga1_2代表栅极驱动电路110输出到栅线GA1上的栅极扫描信号，信号ga4_2代表栅极驱动电路110输出到栅线GA4上的栅极扫描信号，……信号ga7_2代表栅极驱动电路110输出到栅线GA7上的栅极扫描信号，信号ga10_2代表栅极驱动电路110输出到栅线GA10上的栅极扫描信号。
并且，对第一驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第1个第二晶体管M2_1均导通。对第二驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第2个第二晶体管M2_2均截止。对第三驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第3个第二晶体管M2_3均截止。以及，对第一级联选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第1个第一晶体管M1_1均导通。对第二驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第2个第一晶体管M1_2均截止。对第三驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第3个第一晶体管M1_3均截止。当然，栅极导通信号也可以为高电平信号，栅极截止信号也可以为低电平信号，在此不作限定。
以及，以低电平为栅极扫描信号的有效电平为例，信号stvs_2输入移位寄存器单元SR1的输入信号端INP，移位寄存器单元SR1将第二时钟信号cks2_2的第一个低电平，通过第1个驱动输出端GO_1输出到栅线GA1上，以产生栅极扫描信号ga1_2中的低电平。栅极扫描信号ga1_2输入移位寄存器单元SR2的输入信号端INP，移位寄存器单元SR2将第二时钟信号cks1_2的第二个低电平，通过第1个驱动输出端GO_1输出到栅线GA4上，以产生栅极扫描信号ga4_2中的低电平。栅极扫描信号ga4_2输入移位寄存器单元SR3的输入信号端INP，移位寄存器单元SR3将第二时钟信号cks4_2的第二个低电平，通过第1个驱动输出端GO_1输出到栅线GA7上，以产生栅极扫描信号ga7_2中的低电平。栅极扫描信号ga7_2输入移位寄存器单元SR4的输入 信号端INP，移位寄存器单元SR4将第二时钟信号cks3_2的第三个低电平，通过第1个驱动输出端GO_1输出到栅线GA10上，以产生栅极扫描信号ga10_2中的低电平。
可选地，各第二时钟信号cks1_2～cks4_2的低电平的维持时长相同，各第二时钟信号cks1_2～cks4_2的时钟周期相同。并且，第二时钟信号cks1_2～cks4_2的低电平可以为其有效电平，高电平为其无效电平。当然，在移位寄存器单元将第二时钟信号的高电平输出，以产生栅极扫描信号中控制晶体管导通的高电平信号时，可以将第二时钟信号的高电平作为其有效电平，低电平作为其无效电平。
可选地，如图16a所示，各第二时钟信号cks1_2～cks4_2的时钟周期ts21可以为12H。如图16b所示，各第二时钟信号cks1_2～cks4_2的时钟周期ts22可以为4H。如图16c所示，各第二时钟信号cks1_2～cks4_2的时钟周期ts23可以为2H。在本公开实施例中，可以通过降低第二时钟信号的时钟周期，可以降低对红色子像素耦接的栅线的扫描时间，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
在本公开另一些实施例中，M＝3，步骤S20可以包括：在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第二级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第三级联选择信号线均加载栅极截止信号，对第二驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各移位寄存器单元顺序工作，将第2个驱动节点的信号提供给级联输出端，以及将第2个驱动节点的信号提供给第2个驱动输出端，对每一个第二颜色子像素行耦接的栅线进行扫描；其中，第二时钟信号具有两个不同的时钟周期。
示例性地，第二颜色子像素行可以为绿色子像素行，这样在第二驱动模式时对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第二级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第三级 联选择信号线均加载栅极截止信号，对第二驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各移位寄存器单元顺序工作，将第2个驱动节点的信号提供给级联输出端，以及将第2个驱动节点的信号提供给第2个驱动输出端，对每一个绿色子像素行耦接的栅线进行扫描。也就是说，在第二驱动模式时，在一个显示帧中，可以仅对绿色子像素行耦接的栅极输出栅极扫描信号，从而仅对绿色子像素输入数据电压。
可选地，两个不同的时钟周期可以包括第一时钟周期和第二时钟周期。其中，第一时钟周期不大于第一时钟信号的时钟周期的3/4，第二时钟周期不大于第一时钟信号的时钟周期的9/4。
示例性地，可以使第一时钟周期等于第一时钟信号的时钟周期的3/4，第二时钟周期等于第一时钟信号的时钟周期的9/4。例如，如图15与图17a所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的第二时钟周期ts31_2可以为18H，第一时钟周期ts31_1为6H。或者，也可以使第一时钟周期等于第一时钟信号的时钟周期的2/3，第二时钟周期等于第一时钟信号的时钟周期的3/2。例如，如图15与图17b所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的第二时钟周期ts32_2可以为12H，第一时钟周期ts32_1为4H。
当然，在实际应用中，在一个显示帧中仅对第二颜色子像素行耦接的栅线进行扫描时，加载的第二时钟信号的第一时钟周期和第二时钟周期与第一时钟信号的时钟周期之间的关系，可以根据实际应用的需求进行确定，在此不作限定。
示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，在第二驱动模式时，对每一个绿色子像素行耦接的栅线进行扫描时，对应的信号时序图，如图17a与图17b所示。其中，cks1_2代表输入到第一时钟信号线CKS1上的第二时钟信号，cks2_2代表输入到第二时钟信号线CKS2上的第二时钟信号，cks3_2代表输入到第 三时钟信号线CKS3上的第二时钟信号，cks4_2代表输入到第四时钟信号线CKS4上的第二时钟信号，stvs_2代表输入到帧起始信号线STVS_2上的帧起始信号。并且，信号ga2_2代表栅极驱动电路110输出到栅线GA2上的栅极扫描信号，信号ga5_2代表栅极驱动电路110输出到栅线GA5上的栅极扫描信号，……信号ga8_2代表栅极驱动电路110输出到栅线GA8上的栅极扫描信号，信号ga11_2代表栅极驱动电路110输出到栅线GA11上的栅极扫描信号。
并且，对第二驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第2个第二晶体管M2_2均导通。对第一驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第1个第二晶体管M2_1均截止。对第三驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第3个第二晶体管M2_3均截止。以及，对第二级联选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第2个第一晶体管M1_2均导通。对第一驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第1个第一晶体管M1_1均截止。对第三驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第3个第一晶体管M1_3均截止。当然，栅极导通信号也可以为高电平信号，栅极截止信号也可以为低电平信号，在此不作限定。
以及，以低电平为栅极扫描信号的有效电平为例，信号stvs_2输入移位寄存器单元SR1的输入信号端INP，移位寄存器单元SR1将第二时钟信号cks3_2的第一个低电平，通过第2个驱动输出端GO_2输出到栅线GA2上，以产生栅极扫描信号ga2_2中的低电平。栅极扫描信号ga2_2输入移位寄存器单元SR2的输入信号端INP，移位寄存器单元SR2将第二时钟信号cks2_2的第二个低电平，通过第2个驱动输出端GO_2输出到栅线GA5上，以产生栅极扫描信号ga5_2中的低电平。栅极扫描信号ga5_2输入移位寄存器单元SR3的输入信号端INP，移位寄存器单元SR3将第二时钟信号cks1_2的第二个低电平，通过第2个驱动输出端GO_2输出到栅线GA8上，以产生栅极扫描信 号ga8_2中的低电平。栅极扫描信号ga8_2输入移位寄存器单元SR4的输入信号端INP，移位寄存器单元SR4将第二时钟信号cks4_2的第三个低电平，通过第2个驱动输出端GO_2输出到栅线GA11上，以产生栅极扫描信号ga11_2中的低电平。
可选地，各第二时钟信号cks1_2～cks4_2的低电平的维持时长相同，各第二时钟信号cks1_2～cks4_2的第一时钟周期相同，第二时钟周期相同。并且，第二时钟信号cks1_2～cks4_2的低电平可以为其有效电平，高电平为其无效电平。当然，在移位寄存器单元将第二时钟信号的高电平输出，以产生栅极扫描信号中控制晶体管导通的高电平信号时，可以将第二时钟信号的高电平作为其有效电平，低电平作为其无效电平。
可选地，如图17a所示，各第二时钟信号cks1_2～cks4_2的第二时钟周期ts31_2可以为18H，第一时钟周期ts31_1可以为6H。如图17b所示，各第二时钟信号cks1_2～cks4_2的第二时钟周期ts32_2可以为12H，第一时钟周期ts32_1可以为4H。在本公开实施例中，可以通过降低第一时钟周期和第二时钟周期，可以降低对绿色子像素耦接的栅线的扫描时间，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
在本公开又一些实施例中，M＝3，步骤S20可以包括：在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第三级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第二级联选择信号线均加载栅极截止信号，对第三驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第二驱动选择信号线均加载栅极截止信号，控制各移位寄存器单元顺序工作，将第3个驱动节点的信号提供给级联输出端，以及将第3个驱动节点的信号提供给第3个驱动输出端，对每一个第三颜色子像素行耦接的栅线进行扫描。
示例性地，第三颜色子像素行可以为蓝色子像素行，这样在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第三级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第二 级联选择信号线均加载栅极截止信号，对第三驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第二驱动选择信号线均加载栅极截止信号，控制各移位寄存器单元顺序工作，将第3个驱动节点的信号提供给级联输出端，以及将第3个驱动节点的信号提供给第3个驱动输出端，对每一个第三颜色子像素行耦接的栅线进行扫描。也就是说，在第二驱动模式时，在一个显示帧中，可以仅对蓝色子像素行耦接的栅极输出栅极扫描信号，从而仅对蓝色子像素输入数据电压。
可选地，可以使第二时钟周期不大于第一时钟信号的时钟周期的三倍。示例性地，可以使第二时钟周期等于第一时钟信号的时钟周期的三倍。例如，如图15与图18a所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的时钟周期ts41可以为24H。或者，也可以使第二时钟周期等于第一时钟信号的时钟周期的二倍。例如，第一时钟信号cks1_1～cks4_1的时钟周期为8H，第二时钟信号cks1_2～cks4_2的时钟周期可以为16H。或者，也可以使第二时钟周期等于第一时钟信号的时钟周期的1/2。例如，如图15与图18b所示，第一时钟信号cks1_1～cks4_1的时钟周期ts11为8H，第二时钟信号cks1_2～cks4_2的时钟周期ts42可以为4H。
当然，在实际应用中，在一个显示帧中仅对第三颜色子像素行耦接的栅线进行扫描时加载的第二时钟信号的时钟周期与第一时钟信号的时钟周期之间的关系，可以根据实际应用的需求进行确定，在此不作限定。
示例性地，以图3所示的移位寄存器单元的结构，以及第一级移位寄存器单元至第四级移位寄存器单元为例，在第二驱动模式时，对每一个红色子像素行耦接的栅线进行扫描时，对应的信号时序图，如图18a与图18b所示。其中，cks1_2代表输入到第一时钟信号线CKS1上的第二时钟信号，cks2_2代表输入到第二时钟信号线CKS2上的第二时钟信号，cks3_2代表输入到第三时钟信号线CKS3上的第二时钟信号，cks4_2代表输入到第四时钟信号线CKS4上的第二时钟信号，stvs_2代表输入到帧起始信号线STVS_2上的帧起始信号。并且，信号ga3_2代表栅极驱动电路110输出到栅线GA3上的栅极 扫描信号，信号ga6_2代表栅极驱动电路110输出到栅线GA6上的栅极扫描信号，……信号ga9_2代表栅极驱动电路110输出到栅线GA9上的栅极扫描信号，信号ga12_2代表栅极驱动电路110输出到栅线GA12上的栅极扫描信号。
并且，对第三驱动选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第3个第二晶体管M2_3均导通。对第二驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第2个第二晶体管M2_2均截止。对第一驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第1个第二晶体管M2_1均截止。以及，对第三级联选择信号线加载低电平的栅极导通信号，以控制各级移位寄存器单元中的第3个第一晶体管M1_3均导通。对第二驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第2个第一晶体管M1_2均截止。对第一驱动选择信号线加载高电平的栅极截止信号，以控制各级移位寄存器单元中的第1个第一晶体管M1_1均截止。当然，栅极导通信号也可以为高电平信号，栅极截止信号也可以为低电平信号，在此不作限定。
以及，以低电平为栅极扫描信号的有效电平为例，信号stvs_2输入移位寄存器单元SR1的输入信号端INP，移位寄存器单元SR1将第二时钟信号cks4_2的第一个低电平，通过第3个驱动输出端GO_3输出到栅线GA3上，以产生栅极扫描信号ga3_2中的低电平。栅极扫描信号ga3_2输入移位寄存器单元SR2的输入信号端INP，移位寄存器单元SR2将第二时钟信号cks3_2的第一个低电平，通过第3个驱动输出端GO_3输出到栅线GA6上，以产生栅极扫描信号ga6_2中的低电平。栅极扫描信号ga6_2输入移位寄存器单元SR3的输入信号端INP，移位寄存器单元SR3将第二时钟信号cks2_2的第一个低电平，通过第3个驱动输出端GO_3输出到栅线GA9上，以产生栅极扫描信号ga9_2中的低电平。栅极扫描信号ga9_2输入移位寄存器单元SR4的输入信号端INP，移位寄存器单元SR4将第二时钟信号cks1_2的第二个低电平，通过第3个驱动输出端GO_3输出到栅线GA12上，以产生栅极扫描信号 ga12_2中的低电平。
可选地，各第二时钟信号cks1_2～cks4_2的低电平的维持时长相同，各第二时钟信号cks1_2～cks4_2的时钟周期相同。并且，第二时钟信号cks1_2～cks4_2的低电平可以为其有效电平，高电平为其无效电平。当然，在移位寄存器单元将第二时钟信号的高电平输出，以产生栅极扫描信号中控制晶体管导通的高电平信号时，可以将第二时钟信号的高电平作为其有效电平，低电平作为其无效电平。
可选地，如图18a所示，各第二时钟信号cks1_2～cks4_2的时钟周期ts41可以为24H。如图18b所示，各第二时钟信号cks1_2～cks4_2的时钟周期ts42可以为4H。在本公开实施例中，可以通过降低第二时钟信号的时钟周期，可以降低对蓝色子像素耦接的栅线的扫描时间，从而可以降低一个显示帧的扫描时间，进而提高刷新频率。
在本公开一些实施例中，第二时钟信号在一个时钟周期内的有效电平的维持时长不小于第一时钟信号在一个时钟周期内的有效电平的维持时长。示例性地，可以使第二时钟信号在一个时钟周期内的有效电平的维持时长等于第一时钟信号在一个时钟周期内的有效电平的维持时长。例如，对第一颜色子像素行耦接的栅线进行扫描时对应的第二时钟信号在一个时钟周期内的有效电平的维持时长等于第一时钟信号在一个时钟周期内的有效电平的维持时长，对第二颜色子像素行耦接的栅线进行扫描时对应的第二时钟信号在一个时钟周期内的有效电平的维持时长等于第一时钟信号在一个时钟周期内的有效电平的维持时长，对第三颜色子像素行耦接的栅线进行扫描时对应的第二时钟信号在一个时钟周期内的有效电平的维持时长等于第一时钟信号在一个时钟周期内的有效电平的维持时长。或者，对第一颜色子像素行耦接的栅线进行扫描时对应的第二时钟信号在一个时钟周期内的有效电平的维持时长大于第一时钟信号在一个时钟周期内的有效电平的维持时长，对第二颜色子像素行耦接的栅线进行扫描时对应的第二时钟信号在一个时钟周期内的有效电平的维持时长等于第一时钟信号在一个时钟周期内的有效电平的维持时长， 对第三颜色子像素行耦接的栅线进行扫描时对应的第二时钟信号在一个时钟周期内的有效电平的维持时长等于第一时钟信号在一个时钟周期内的有效电平的维持时长。这样可以提高对红色子像素的充电率。
在本公开一些实施例中，可以在多个显示帧中的每一个显示帧，针对同一颜色子像素执行第二驱动模式的工作过程。示例性地，可以在该多个显示帧中的每一个显示帧中，执行对每一个红色子像素行耦接的栅线进行扫描的工作过程，以对红色子像素充电，以实现红色画面的显示。或者，也可以在该多个显示帧中的每一个显示帧中，执行对每一个绿色子像素行耦接的栅线进行扫描的工作过程，以对绿色子像素充电，以实现绿色画面的显示。或者，也可以在该多个显示帧中的每一个显示帧中，执行对每一个蓝色子像素行耦接的栅线进行扫描的工作过程，以对蓝色子像素充电，以实现蓝色画面的显示。
在本公开一些实施例中，可以在多个显示帧中相邻的多个显示帧针对不同颜色子像素，执行第二驱动模式的工作过程。示例性地，可以在多个显示帧中，以红色子像素、绿色子像素以及蓝色子像素的顺序，执行第二驱动模式的工作过程。例如，该多个显示帧可以包括：第q-1个显示帧Fq-1、第q个显示帧Fq、第q+1个显示帧Fq+1。其中，在第q-1个显示帧Fq-1中，执行对每一个红色子像素行耦接的栅线进行扫描的工作过程，以对红色子像素充电。在第q个显示帧Fq中，执行对每一个绿色子像素行耦接的栅线进行扫描的工作过程，以对绿色子像素充电。在第q+1个显示帧Fq+1中，执行对每一个蓝色子像素行耦接的栅线进行扫描的工作过程，以对蓝色子像素充电。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(可以包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产 品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生可以包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为可以包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (22)

  1. 一种移位寄存器单元，包括：
    第一控制电路，被配置为根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；
    第二控制电路，被配置为根据所述第一节点、所述第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；
    级联输出电路，被配置为根据级联选择信号端，将所述至少两个驱动节点中的一个驱动节点的信号提供给级联输出端；
    驱动输出电路，被配置为根据驱动选择信号端，将所述至少两个驱动节点中的至少一个驱动节点的信号提供给对应所述驱动节点的驱动输出端。
  2. 如权利要求1所述的移位寄存器单元，其中，所述驱动节点包括M个驱动节点，所述第二时钟信号端包括M个第二时钟信号端，所述驱动输出端包括M个驱动输出端；M为大于1的整数；
    所述第二控制电路包括M个第二控制电路；其中，所述M个第二控制电路中的第m个第二控制电路与所述M个驱动节点中的第m个驱动节点对应，且所述第m个第二控制电路与所述M个第二时钟信号端中的第m个第二时钟信号端对应；并且，所述第m个第二控制电路被配置为响应于所述第一节点的信号，将所述第m个第二时钟信号端的信号提供给所述第m个驱动节点，以及，响应于所述第二节点的信号，将第一参考信号端的信号提供给所述第m个驱动节点；1≤m≤M，且m为整数；
    所述级联输出电路包括M个级联输出电路，所述级联选择信号端包括M个级联选择信号端；其中，所述M个级联输出电路中的第m个级联输出电路与所述第m个驱动节点对应，且所述第m个级联输出电路与所述M个级联选择信号端中的第m个级联选择信号端对应；所述第m个级联输出电路被配置为响应于所述第m个级联选择信号端的信号，将所述第m个驱动节点的信号提供给所述级联输出端；
    所述驱动输出电路包括M个驱动输出电路，所述驱动选择信号端包括M个驱动选择信号端；所述M个驱动输出电路中的第m个驱动输出电路与所述第m个驱动节点对应，且所述第m个驱动输出电路与所述M个驱动选择信号端中的第m个驱动选择信号端对应；所述第m个驱动输出电路被配置为响应于所述第m个驱动选择信号端的信号，将所述第m个驱动节点的信号提供给所述第m个驱动输出端。
  3. 如权利要求2所述的移位寄存器单元，其中，所述第m个级联输出电路包括：第m个第一晶体管；
    所述第m个第一晶体管的控制极与所述第m个级联选择信号端耦接，所述第m个第一晶体管的第一极与所述第m个驱动节点耦接，所述第m个第一晶体管的第二极与所述级联输出端耦接。
  4. 如权利要求2所述的移位寄存器单元，其中，所述第m个驱动输出电路包括：第m个第二晶体管；
    所述第m个第二晶体管的控制极与所述第m个驱动选择信号端耦接，所述第m个第二晶体管的第一极与所述第m个驱动节点耦接，所述第m个第二晶体管的第二极与所述驱动输出端耦接。
  5. 如权利要求2-4任一项所述的移位寄存器单元，其中，所述第m个第二控制电路包括：第m个第三晶体管、第m个第四晶体管以及第m个第一电容；
    所述第m个第三晶体管的控制极与所述第一节点耦接，所述第m个第三晶体管的第一极与所述第m个第二时钟信号端耦接，所述第m个第三晶体管的第二极与所述第m个驱动节点耦接；
    所述第m个第四晶体管的控制极与所述第二节点耦接，所述第m个第四晶体管的第一极与所述第一参考信号端耦接，所述第m个第四晶体管的第二极与所述第m个驱动节点耦接；
    所述第m个第一电容的第一电极板与所述第一节点耦接，所述第m个第一电容的第二电极板与所述第m个驱动节点耦接。
  6. 如权利要求5所述的移位寄存器单元，其中，所述第m个第二控制电路还包括：第m个第五晶体管；所述第m个第三晶体管的控制极通过所述第m个第五晶体管与所述第一节点耦接；所述第m个第五晶体管的第一极与所述第一节点耦接，所述第m个第五晶体管的第二极与所述第m个第三晶体管的控制极耦接；
    在m＝1时，所述第m个第五晶体管的控制极与第二参考信号端耦接；
    在1<m≤M时，所述第m个第五晶体管的控制极与所述第一时钟信号端耦接。
  7. 如权利要求1-6任一项所述的移位寄存器单元，其中，所述第一控制电路包括：输入电路和节点控制电路；
    所述输入电路被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点；
    所述节点控制电路被配置为响应于所述第一时钟信号端的信号，将第二参考信号端的信号提供给所述第二节点，响应于所述第一节点的信号，将所述第一时钟信号端的信号提供给所述第二节点，以及响应于所述第二节点和第1个第二时钟信号端的信号，将所述第一参考信号端的信号提供给所述第一节点。
  8. 如权利要求7所述的移位寄存器单元，其中，所述输入电路包括：第六晶体管；所述第六晶体管的控制极与所述第一时钟信号端耦接，所述第六晶体管的第一极与所述输入信号端耦接，所述第六晶体管的第二极与所述第一节点耦接；
    所述节点控制电路包括：第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第二电容；其中，所述第七晶体管的控制极与所述第一时钟信号端耦接，所述第七晶体管的第一极与所述第二参考信号端耦接，所述第七晶体管的第二极与所述第二节点耦接；所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的第一极与所述第一时钟信号端耦接，所述第八晶体管的第二极与所述第二节点耦接；所述第九晶体管的控制极与所述第二节 点耦接，所述第九晶体管的第一极与所述第一参考信号端耦接，所述第九晶体管的第二极与所述第十晶体管的第一极耦接；所述第十晶体管的控制极与所述第1个第二时钟信号端耦接，所述第十晶体管的第二极与所述第一节点耦接；所述第二电容的第一电极板与所述第二节点耦接，所述第二电容的第二电极板与所述第一参考信号端耦接。
  9. 一种栅极驱动电路，包括级联的多个如权利要求1-8任一项所述的移位寄存器单元；
    第一级移位寄存器单元的输入信号端与帧起始信号线耦接；
    每相邻两级移位寄存器单元中，下一级移位寄存器单元的输入信号端与上一级移位寄存器单元的级联输出端耦接。
  10. 一种显示装置，包括显示面板；所述显示面板包括：多条栅线、多条时钟信号线、多条级联选择信号线、多条驱动选择信号线以及如权利要求9所述的栅极驱动电路；
    所述栅极驱动电路中的每一个所述移位寄存器单元的每一个驱动输出端与所述多条栅线一一对应耦接，且所述栅极驱动电路中的一个所述移位寄存器单元与所述多条时钟信号线耦接；
    所述栅极驱动电路中的所述移位寄存器单元的级联选择信号端与所述级联选择信号线耦接；
    所述栅极驱动电路中的所述移位寄存器单元的驱动选择信号端与所述驱动选择信号线耦接。
  11. 如权利要求10所述的显示装置，其中，所述显示面板还包括阵列排布的多个像素单元；一行所述像素单元对应所述栅极驱动电路中的一个所述移位寄存器单元；
    所述像素单元包括沿列方向排列的多个不同颜色的子像素，一行所述子像素耦接一条所述栅线；
    每一个所述移位寄存器单元的第m个驱动输出端耦接同一颜色子像素对应的栅线。
  12. 如权利要求11所述的显示装置，其中，M＝3，所述像素单元包括列方向依次排列的第一颜色子像素、第二颜色子像素以及第三颜色子像素；
    所述多条时钟信号线包括第一时钟信号线、第二时钟信号线、第三时钟信号线以及第四时钟信号线；其中，第4k_3级移位寄存器单元的第一时钟信号端、第4k_2级移位寄存器单元的第1个第二时钟信号端、第4k_1级移位寄存器单元的第2个第二时钟信号端以及第4k级移位寄存器单元的第3个第二时钟信号端，均与所述第一时钟信号线耦接；第4k_3级移位寄存器单元的第1个第二时钟信号端、第4k_2级移位寄存器单元的第2个第二时钟信号端、第4k_1级移位寄存器单元的第3个第二时钟信号端以及第4k级移位寄存器单元的第一时钟信号端，均与所述第二时钟信号线耦接；第4k_3级移位寄存器单元的第2个第二时钟信号端、第4k_2级移位寄存器单元的第3个第二时钟信号端、第4k_1级移位寄存器单元的第一时钟信号端以及第4k级移位寄存器单元的第1个第二时钟信号端，均与所述第三时钟信号线耦接；第4k_3级移位寄存器单元的第3个第二时钟信号端、第4k_2级移位寄存器单元的第一时钟信号端、第4k_1级移位寄存器单元的第1个第二时钟信号端以及第4k级移位寄存器单元的第2个第二时钟信号端，均与所述第三时钟信号线耦接；k为大于0的整数；
    所述多条级联选择信号线包括第一级联选择信号线、第二级联选择信号线以及第三级联选择信号线；其中，各级移位寄存器单元的第1个级联选择信号端与所述第一级联选择信号线耦接，各级移位寄存器单元的第2个级联选择信号端与所述第二级联选择信号线耦接，各级移位寄存器单元的第3个级联选择信号端与所述第三级联选择信号线耦接；
    所述多条驱动选择信号线包括第一驱动选择信号线、第二驱动选择信号线以及第三驱动选择信号线；其中，各级移位寄存器单元的第1个驱动选择信号端与所述第一驱动选择信号线耦接，各级移位寄存器单元的第2个驱动选择信号端与所述第二驱动选择信号线耦接，各级移位寄存器单元的第3个驱动选择信号端与所述第三驱动选择信号线耦接。
  13. 一种如权利要求1-8任一项所述的移位寄存器单元的驱动方法，包括：
    在第一驱动模式时，一个显示帧包括第一输入阶段、第一输出阶段以及第一复位阶段；
    在所述第一输入阶段，第一控制电路根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第一节点、所述第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端；
    在所述第一输出阶段，第二控制电路根据所述第一节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端；
    在所述第一复位阶段，第一控制电路根据第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第二节点的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端；
    在第二驱动模式时，一个显示帧包括第二输入阶段、第二输出阶段以及第二复位阶段；
    在所述第二输入阶段，第一控制电路根据输入信号端和第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第一节点、所述第二节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第m个驱 动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的所述第m个驱动节点的信号提供给对应的驱动输出端；
    在所述第二输出阶段，第二控制电路根据所述第一节点以及第二时钟信号端的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的所述第m个驱动节点的信号提供给对应的驱动输出端；
    在所述第二复位阶段，第一控制电路根据第一时钟信号端的信号，控制第一节点和第二节点的信号；第二控制电路根据所述第二节点的信号，控制至少两个驱动节点的信号；级联输出电路根据级联选择信号端，将所述至少两个驱动节点中的第m个驱动节点的信号提供给级联输出端；驱动输出电路根据驱动选择信号端，将所述至少两个驱动节点中的所述第m个驱动节点的信号提供给对应的驱动输出端。
  14. 一种如权利要求10-12任一项所述的显示装置的驱动方法，包括：
    在第一驱动模式时，在一个显示帧中，对各所述时钟信号线加载不同的第一时钟信号，对各所述驱动选择信号线加载栅极导通信号，对第M个驱动输出电路耦接的级联选择信号线加载栅极导通信号，对其余级联选择信号线加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将所述至少两个驱动节点中的第M个驱动节点的信号提供给级联输出端，以及将所述至少两个驱动节点中的每一个驱动节点的信号提供给对应每一个所述驱动节点的驱动输出端，对所述多条栅线逐行扫描；
    在第二驱动模式时，在一个显示帧中，对各所述时钟信号线加载第二时钟信号，对第m个级联输出电路耦接的驱动选择信号线加载栅极导通信号，对其余驱动选择信号线加载栅极截止信号，对第m个驱动输出电路耦接的级联选择信号线加载栅极导通信号，且对其余级联选择信号线加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将所述至少两个驱动节点中的第m 个驱动节点的信号提供给级联输出端，以及将所述第m个驱动节点的信号提供给对应的驱动输出端，对所述多条栅线隔行扫描；其中，所述第二时钟信号的时钟周期与所述第一时钟信号的时钟周期不同。
  15. 如权利要求14所示的显示装置的驱动方法，其中，M＝3，在第二驱动模式时，对第一时钟信号线和第三时钟信号线加载相同的第二时钟信号，且对第二时钟信号线和第四时钟信号线加载相同的第二时钟信号，对第一级联选择信号线加载栅极导通信号，且对第二级联选择信号线和第三级联选择信号线均加载栅极截止信号，对第一驱动选择信号线加载栅极导通信号，且对第二驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将第1个驱动节点的信号提供给所述级联输出端，以及将所述第1个驱动节点的信号提供给第1个驱动输出端，对每一个第一颜色子像素行耦接的栅线进行扫描；其中，对所述第一时钟信号线和所述第二时钟信号端加载的第二时钟信号不同。
  16. 如权利要求15所示的显示装置的驱动方法，其中，所述第二时钟信号的时钟周期不大于所述第一时钟信号的时钟周期的3/2。
  17. 如权利要求14所示的显示装置的驱动方法，其中，在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第二级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第三级联选择信号线均加载栅极截止信号，对第二驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第三驱动选择信号线均加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将第2个驱动节点的信号提供给所述级联输出端，以及将所述第2个驱动节点的信号提供给第2个驱动输出端，对每一个第二颜色子像素行耦接的栅线进行扫描；其中，所述第二时钟信号具有两个不同的时钟周期。
  18. 如权利要求17所示的显示装置的驱动方法，其中，所述两个不同的时钟周期包括第一时钟周期和第二时钟周期；所述第一时钟周期不大于所述第一时钟信号的时钟周期的3/4，所述第二时钟周期不大于所述第一时钟信号 的时钟周期的9/4。
  19. 如权利要求14所示的显示装置的驱动方法，其中，M＝3，在第二驱动模式时，对第一时钟信号线至第四时钟信号线分别加载不同的第二时钟信号，对第三级联选择信号线加载栅极导通信号，且对第一级联选择信号线和第二级联选择信号线均加载栅极截止信号，对第三驱动选择信号线加载栅极导通信号，且对第一驱动选择信号线和第二驱动选择信号线均加载栅极截止信号，控制各所述移位寄存器单元顺序工作，将第3个驱动节点的信号提供给所述级联输出端，以及将所述第3个驱动节点的信号提供给第3个驱动输出端，对每一个第三颜色子像素行耦接的栅线进行扫描。
  20. 如权利要求19所示的显示装置的驱动方法，其中，所述第二时钟周期不大于所述第一时钟信号的时钟周期的三倍。
  21. 如权利要求15-20任一项所述的显示装置的驱动方法，其中，所述第二时钟信号在一个时钟周期内的有效电平的维持时长不小于所述第一时钟信号在一个时钟周期内的有效电平的维持时长。
  22. 如权利要求21所述的显示装置的驱动方法，其中，对所述第一颜色子像素行耦接的栅线进行扫描时对应的所述第二时钟信号在一个时钟周期内的有效电平的维持时长大于所述第一时钟信号在一个时钟周期内的有效电平的维持时长；
    对所述第二颜色子像素行耦接的栅线进行扫描时对应的所述第二时钟信号在一个时钟周期内的有效电平的维持时长等于所述第一时钟信号在一个时钟周期内的有效电平的维持时长；
    对所述第三颜色子像素行耦接的栅线进行扫描时对应的所述第二时钟信号在一个时钟周期内的有效电平的维持时长等于所述第一时钟信号在一个时钟周期内的有效电平的维持时长。
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