WO2023240713A1 - Puce de del et écran d'affichage la comprenant - Google Patents

Puce de del et écran d'affichage la comprenant Download PDF

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Publication number
WO2023240713A1
WO2023240713A1 PCT/CN2022/103436 CN2022103436W WO2023240713A1 WO 2023240713 A1 WO2023240713 A1 WO 2023240713A1 CN 2022103436 W CN2022103436 W CN 2022103436W WO 2023240713 A1 WO2023240713 A1 WO 2023240713A1
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WO
WIPO (PCT)
Prior art keywords
type
layer
led chip
led
microns
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Application number
PCT/CN2022/103436
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English (en)
Chinese (zh)
Inventor
顾伟
李文涛
简弘安
胡加辉
Original Assignee
江西兆驰半导体有限公司
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Publication of WO2023240713A1 publication Critical patent/WO2023240713A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the technical field of semiconductor devices, and in particular to an LED chip and a display screen carrying the LED chip.
  • the P pad metal and N pad metal often connect to each other, causing the LED chip to short circuit.
  • the above problems are especially obvious in Micro LED chips. Since the distance between the P pad metal and N pad metal of the Micro LED chip is closer, it is easier for the P pad metal to appear after the Micro LED chip is solidified on the substrate. Tin is connected to the N pad metal, causing a short circuit on the Micro LED chip. Therefore, how to solve the risk of tin connection after the LED chip is solidified on the substrate has become an urgent technical problem that needs to be solved.
  • this application provides an LED chip and a display screen carrying the LED chip, aiming to solve the problem that the P pad metal and N pad metal connection of the LED chip when solidified on the substrate is easy to occur in the prior art. Tin technical issues.
  • an LED chip which includes: a substrate, a connecting metal, and several LED sub-chips;
  • each of the P-type pads is individually connected to an anode substrate pad on the substrate through metal tin, and each of the P-type pads is connected to an anode substrate pad on the substrate through metal tin.
  • the N-type pad is individually connected to a cathode substrate pad on the substrate through the metal tin, and the P-type conductive metal layer or N-type conductive metal layer of each LED sub-chip achieves electrical properties through the connection metal. connect.
  • the LED chip also includes a Bragg reflective layer, and the Bragg reflective layer is provided with P-type Bragg reflective layer through holes and N-type Bragg reflective layer through holes;
  • the P-type soldering pad is electrically connected to the P-type conductive metal layer or the connection metal through the P-type Bragg reflective layer through hole, and the N-type soldering pad passes through the N-type Bragg reflective layer through hole. Electrically connect the N-type conductive metal layer or the connection metal.
  • the Bragg reflective layer is formed by stacking 5-50 layers of SiO2 and Ti3O5 material pairs.
  • the LED sub-chip further includes: a current spreading layer, an active light-emitting layer, a P-type semiconductor and an N-type semiconductor;
  • the active light-emitting layer is disposed between the P-type semiconductor and the N-type semiconductor, the P-type conductive metal layer is electrically connected to the current expansion layer, and the current expansion layer is connected to the P-type conductive metal layer.
  • the N-type semiconductor is electrically connected to excite holes, and the N-type conductive metal layer is electrically connected to the conductive step of the N-type semiconductor to excite electrons.
  • the forward projection of the P-type semiconductor is smaller than the forward projection of the N-type semiconductor, and the exposed portion of the N-type semiconductor serves as the conductive step.
  • the LED sub-chip further includes: an insulating protective layer, with P-type insulating protective layer through holes and N-type insulating protective layer through holes provided on the insulating protective layer;
  • the P-type conductive metal layer is electrically connected to the current expansion layer through the P-type insulating protective layer through hole
  • the N-type conductive metal layer is electrically connected to the N-type insulating protective layer through the N-type insulating protective layer through hole.
  • the conductive steps of the type semiconductor are electrically connected.
  • the material of the insulating protective layer is selected from one or more of SiO2, TiO2, Ti3O5, and SiN.
  • the P-type semiconductor has a length of 1-500 microns and a width of 1-500 microns; the N-type semiconductor has a length of 20-550 microns and a width of 20-550 microns.
  • the length of the anode substrate pad is 10-200 microns and the width is 10-200 microns; the length of the cathode substrate pad is 10-200 microns and the width is 10-200 microns; the metal tin is The length is 10 ⁇ 200 microns, the width is 10 ⁇ 200 microns, and the height is 1 ⁇ 100 microns.
  • the LED sub-chip is any one of a traditional LED chip, a Micro LED chip, and a Mini LED chip.
  • embodiments of the present application provide a display screen carrying an LED chip, which includes:
  • a substrate on which are provided several anode substrate pads and several cathode substrate pads;
  • the LED chips include: a substrate, a connecting metal and several LED sub-chips;
  • each of the anode substrate pads is individually connected to one of the P-type pads through metal tin
  • each of the cathode substrates The soldering pad is individually connected to one of the N-type soldering pads through the metal tin, and the P-type conductive metal layer or N-type conductive metal layer of each LED sub-chip is electrically connected through the connecting metal.
  • the LED chip further includes a Bragg reflective layer, and the Bragg reflective layer is provided with P-type Bragg reflective layer through holes and N-type Bragg reflective layer through holes;
  • the P-type soldering pad is electrically connected to the P-type conductive metal layer or the connection metal through the P-type Bragg reflective layer through hole, and the N-type soldering pad passes through the N-type Bragg reflective layer through hole. Electrically connect the N-type conductive metal layer or the connection metal.
  • the Bragg reflective layer is formed by stacking 5-50 layers of SiO2 and Ti3O5 material pairs.
  • the LED sub-chip further includes: a current spreading layer, an active light-emitting layer, a P-type semiconductor and an N-type semiconductor;
  • the active light-emitting layer is disposed between the P-type semiconductor and the N-type semiconductor, the P-type conductive metal layer is electrically connected to the current expansion layer, and the current expansion layer is connected to the P-type conductive metal layer.
  • the N-type semiconductor is electrically connected to excite holes, and the N-type conductive metal layer is electrically connected to the conductive step of the N-type semiconductor to excite electrons.
  • the forward projection of the P-type semiconductor is smaller than the forward projection of the N-type semiconductor, and the exposed portion of the N-type semiconductor serves as the conductive step.
  • the LED sub-chip further includes: an insulating protective layer, with P-type insulating protective layer through holes and N-type insulating protective layer through holes provided on the insulating protective layer;
  • the P-type conductive metal layer is electrically connected to the current expansion layer through the P-type insulating protective layer through hole
  • the N-type conductive metal layer is electrically connected to the N-type insulating protective layer through the N-type insulating protective layer through hole.
  • the conductive steps of the type semiconductor are electrically connected.
  • the material of the insulating protective layer is selected from one or more of SiO2, TiO2, Ti3O5, and SiN.
  • the P-type semiconductor has a length of 1-500 microns and a width of 1-500 microns; the N-type semiconductor has a length of 20-550 microns and a width of 20-550 microns.
  • the length of the anode substrate pad is 10-200 microns and the width is 10-200 microns; the length of the cathode substrate pad is 10-200 microns and the width is 10-200 microns; the metal tin is The length is 10 ⁇ 200 microns, the width is 10 ⁇ 200 microns, and the height is 1 ⁇ 100 microns.
  • the LED sub-chip is any one of a traditional LED chip, a Micro LED chip, and a Mini LED chip.
  • the LED chip and the display screen carrying the LED chip provided by the embodiment of the present application are provided with several LED chips on the substrate.
  • Each LED chip is composed of a substrate, a connecting metal and several LED sub-chips, and the LED sub-chips are The P-type pad and N-type pad are set separately on the substrate.
  • each anode substrate pad on the substrate is individually connected to a P-type pad through metal tin
  • each cathode substrate pad is individually connected to a P-type pad through metal tin.
  • the P-type pad, the P-type conductive metal layer or N-type conductive metal layer of each LED sub-chip is electrically connected through the connecting metal, thereby solving the problem caused by the P-type pad and N-type pad being too close in the existing technology
  • Technical problems include tin connection, short circuit, and low yield.
  • Figure 1 is a schematic structural diagram of a display screen carrying an LED chip provided by an embodiment of the present application
  • Figure 2 is a schematic structural diagram of a substrate in a display screen carrying an LED chip provided by an embodiment of the present application
  • Figure 3 is a schematic partial structural diagram of a display screen carrying an LED chip provided by an embodiment of the present application.
  • Figure 4 is a cross-sectional view of a display screen carrying an LED chip provided by an embodiment of the present application
  • Figure 5 is a partial structural schematic diagram of a display screen carrying an LED chip provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of an LED chip provided by an embodiment of the present application.
  • FIG. 7 is another structural schematic diagram of an LED chip provided by an embodiment of the present application.
  • Figure 8 is another structural schematic diagram of an LED chip provided by an embodiment of the present application.
  • Figure 9 is another structural schematic diagram of an LED chip provided by an embodiment of the present application.
  • Figure 10 is another structural schematic diagram of an LED chip provided by an embodiment of the present application.
  • FIG. 11 is a partial structural diagram of a display screen carrying an LED chip provided by an embodiment of the present application.
  • Figure 1 is a schematic structural diagram of a display screen carrying an LED chip provided by an embodiment of the present application
  • Figure 2 is a schematic structural diagram of a substrate in a display screen carrying an LED chip provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of a partial structure of a display screen carrying an LED chip provided by an embodiment of the present application
  • Figure 4 is a cross-sectional view of a display screen equipped with an LED chip provided by an embodiment of the present application
  • Figure 5 is a schematic diagram of a display screen equipped with an LED chip provided by an embodiment of the present application. Schematic diagram of the partial structure of the LED chip display screen.
  • a display screen carrying an LED chip includes:
  • Substrate 10 with several anode substrate pads 111 and several cathode substrate pads 112 provided on the substrate 10;
  • the LED chips 30 include: a substrate 20, a connecting metal 50 and a plurality of LED sub-chips 31;
  • each of the anode substrate bonding pads 111 is individually connected to one of the P-type bonding pads 211 through metal tin 40.
  • Each of the cathode substrate pads 112 is individually connected to one of the N-type pads 212 through the metal tin 40 , and the P-type conductive metal layer 311 or N-type conductive metal layer 312 of each LED sub-chip 31 is connected through the metal tin 40 .
  • the connecting metal 50 realizes electrical connection.
  • the LED chip 30 in the display screen carrying the LED chip provided by the embodiment of the present application is one LED chip 30 or multiple LED chips 30 .
  • the multiple LED chips 30 can be arranged in an array on the substrate 10 or in a non-array arrangement.
  • the specific arrangement method and the number of LED chips 30 in the display screen can be The selection is made according to the actual application and is not specifically limited in this embodiment.
  • an LED chip 30 in this embodiment can be understood as an LED chip unit, and an LED sub-chip 31 can be any one of a traditional LED chip, a Micro LED chip, and a Mini LED chip.
  • the traditional LED chip The size is larger than Micro LED chip, and Mini LED chip is an LED chip with a chip size of 50 ⁇ 200 ⁇ m.
  • the metal tin 40 can be a spherical tin ball or a non-spherical tin block
  • the connecting metal 50 contains a conductive metal material
  • the LED sub-chip 31 is disposed between the substrate 10 and the substrate 20 .
  • One LED sub-chip 31 may be present in one LED chip 30 , or multiple LED sub-chips 31 may be present.
  • the multiple LED sub-chips 31 can be arranged in an array on the substrate 20, or in a non-array arrangement.
  • the specific arrangement method and the LED chip The number of LED sub-chips 31 in 30 can be selected according to actual applications, and is not specifically limited in this embodiment.
  • the number of anode substrate pads 111 and cathode substrate pads 112 provided on the substrate 10 can be one anode substrate pad 111 and one cathode substrate pad 112, or can be one anode substrate pad.
  • An equal number of anode substrate welding pads 111 and cathode substrate welding pads 112 can be provided, and an unequal number of anode substrate welding pads 111 and cathode substrate welding pads 112 can also be provided.
  • the anode substrate welding pads 111 and the cathode are provided on the substrate 10
  • the number of substrate pads 112 can be selected according to actual applications, and is not specifically limited in this embodiment.
  • the LED chip 30 further includes a Bragg reflective layer 220, and the Bragg reflective layer 220 is provided with a P-type Bragg reflective layer through hole 221 and an N-type Bragg reflective layer.
  • the N-type Bragg reflective layer through hole 222 is electrically connected to the N-type conductive metal layer 312 or the connection metal 50 .
  • the Bragg reflective layer 220 is deposited on the substrate 20 and is arranged between the substrate 20 and the substrate 10 , and the LED sub-chips 31 in each LED chip 30 are arranged between the Bragg reflective layer 220 and the substrate 20 .
  • the connection metal 50 is passed through the P-type conductive metal layer 312.
  • the Bragg reflective layer through hole 221 or the N-type Bragg reflective layer through hole 222 can realize the electrical connection between the P-type pad 211 and the P-type conductive metal layer 311, or the N-type pad 212 and the N-type conductive metal.
  • the layers 312 are electrically connected.
  • the P-type Bragg reflective layer through hole 221 has the connecting metal 50, and at the same time, the connecting metal 50 can also pass through
  • the N-type Bragg reflective layer through hole 222 is used to realize the electrical connection between the N-type pad 212 and the connecting metal 50; when the N-type pad 212 is electrically connected to the N-type conductive metal layer 312 through the N-type Bragg reflective layer through hole 222, N
  • the connection metal 50 is provided in the type Bragg reflective layer through hole 222 .
  • the connection metal 50 can also achieve electrical connection between the P type pad 211 and the connection metal 50 through the P type Bragg reflection layer through hole 221 .
  • the Bragg reflective layer 220 is formed by stacking 5-50 layers of SiO2 and Ti3O5 material pairs.
  • the Bragg reflective layer 220 can also be formed by stacking 1-5 layers or more than 50 layers of SiO2 and Ti3O5 material pairs. In this embodiment, the Bragg reflective layer 220 is formed by stacking 5-50 layers of SiO2 and Ti3O5 material pairs as Preferred embodiments in this application.
  • the LED sub-chip 31 also includes: a current spreading layer 340, an active light-emitting layer 350, a P-type semiconductor 321 and an N-type semiconductor 322; wherein, the The source light-emitting layer 350 is located between the P-type semiconductor 321 and the N-type semiconductor 322.
  • the P-type conductive metal layer 311 is electrically connected to the current spreading layer 340.
  • the current spreading layer 340 is electrically connected to the P-type semiconductor 321.
  • the N-type conductive metal layer 312 is electrically connected to the conductive step of the N-type semiconductor 322 to excite holes.
  • the current spreading layer 340 is located between the P-type conductive metal layer 311 and the P-type semiconductor 321
  • the N-type semiconductor 322 is located between the N-type conductive metal layer 312 and the substrate 20
  • the N-type semiconductor 322 is also located between the P-type semiconductor 321 and substrate 20.
  • the forward projection of the P-type semiconductor 321 is smaller than the forward projection of the N-type semiconductor 322 , and the exposed part of the N-type semiconductor 322 serves as the conductive steps.
  • the LED sub-chip 31 further includes: an insulating protective layer 330 .
  • the insulating protective layer 330 is provided with a P-type insulating protective layer through hole 331 and an N-type insulating protective layer through hole. Hole 332; wherein, the P-type conductive metal layer 311 is electrically connected to the current expansion layer 340 through the P-type insulating protection layer through hole 331, and the N-type conductive metal layer 312 is protected by the N-type insulating layer.
  • the layer via 332 is electrically connected to the conductive step of the N-type semiconductor 322 .
  • the insulating protective layer 330 is located between the N-type conductive metal layer 312 and the N-type semiconductor 322, and at the same time, the insulating protective layer 330 is also located between the P-type conductive metal layer 311 and the current spreading layer 340.
  • the material of the insulating protective layer 330 is selected from one or more of SiO2, TiO2, Ti3O5, and SiN.
  • the P-type semiconductor has a length of 1-500 microns and a width of 1-500 microns; the N-type semiconductor has a length of 20-550 microns and a width of 20-550 microns.
  • the anode substrate pad 111 has a length of 10-200 microns and a width of 10-200 microns; the cathode substrate pad 112 has a length of 10-200 microns and a width of 10-200 microns;
  • the length of the metal tin 40 is 10-200 microns, the width is 10-200 microns, and the height is 1-100 microns.
  • the LED chip and the display screen carrying the LED chip provided by the embodiment of the present application are provided with several LED chips 30 on the substrate 10.
  • Each LED chip 30 is composed of a substrate 20, a connecting metal 50 and several LED sub-chips 31.
  • the P-type pad 211 and the N-type pad 212 of the LED sub-chip 31 are separately arranged on the substrate 20, and each anode substrate pad 111 on the substrate 10 is individually connected to a P-type pad through the metal tin 40.
  • each cathode substrate pad 112 is individually connected to a P-type pad 211 through metal tin 40, and the P-type conductive metal layer 311 or N-type conductive metal layer 312 of each LED sub-chip 31 realizes electrical properties through the connecting metal 50 connection, thus solving the technical problems in the prior art that the P-type pad 211 and the N-type pad 212 are too close to each other, such as tin connection, short circuit, and low yield.
  • a display screen carrying Micro LED chips includes:
  • the substrate 10 is provided with an anode substrate pad 111 and a cathode substrate pad 112.
  • the anode substrate pad 111 has a length and a width of 80 microns
  • the cathode substrate pad 112 has a length of 160 microns and a width of 160 microns. is 80 microns;
  • each LED chip 30 includes a substrate 20, a connecting metal 50 and three Micro LED chips;
  • each anode substrate pad 111 is individually connected to a P-type pad 211 through metal tin 40, and each cathode substrate pad is connected to a P-type pad 211 through metal tin 40.
  • 112 is individually connected to an N-type pad 212 through a solder ball with a height of 20 microns;
  • the LED chip 30 includes a P-type conductive metal layer 311, an N-type conductive metal layer 312, a Bragg reflective layer 220, a current spreading layer 340, a P-type semiconductor 321, an N-type semiconductor 322, an insulating protective layer 330 and an active light-emitting layer 350;
  • the Bragg reflective layer 220 is provided with a P-type Bragg reflective layer through hole 221 and an N-type Bragg reflective layer through hole 222.
  • the P-type pad 211 is electrically connected to the P-type conductive metal layer 311 through the P-type Bragg reflective layer through hole 221.
  • the N-type pad 212 is electrically connected to the connecting metal 50 through the N-type Bragg reflective layer through hole 222.
  • the Bragg reflective layer 220 is formed by stacking 28 layers of SiO2 and Ti3O5 materials;
  • the P-type semiconductor layer 321 has a length of 80 microns and a width of 50 microns, and the N-type semiconductor layer 322 has a length of 100 microns and a width of 55 microns;
  • the insulating protective layer 330 is provided with a P-type insulating protective layer through hole 331 and an N-type insulating protective layer through hole 332.
  • the P-type conductive metal layer 311 is electrically connected to the current expansion layer 340 through the P-type insulating protective layer through hole 331, and the current
  • the extension layer 340 is electrically connected to the P-type semiconductor 321 to excite holes
  • the N-type conductive metal layer 312 is electrically connected to the steps of the N-type semiconductor 322 through the N-type insulating protective layer through hole 332 to excite electrons;
  • the forward projection is smaller than the forward projection of the N-type semiconductor 322, the exposed part of the N-type semiconductor 322 serves as a conductive step, and the material of the insulating protective layer 330 is selected from SiO2.
  • a display screen carrying a Micro LED chip is similar to the display screen carrying a Micro LED chip in Embodiment 1, and the only difference is:
  • the LED chip 30 includes a Micro LED chip, and a P-type bonding pad 211 and two N-type bonding pads 212 are provided on the substrate 20 .
  • a display screen carrying a Micro LED chip is similar to the display screen carrying a Micro LED chip in Embodiment 1. The only difference is:
  • the LED chip 30 includes five Micro LED chips, and the substrate 20 is provided with five P-type bonding pads 211 and two N-type bonding pads 212 .
  • a display screen carrying a Micro LED chip is similar to the display screen carrying a Micro LED chip in Embodiment 1, and the only difference is:
  • the LED chip 30 includes 7 Micro LED chips, and the substrate 20 is provided with 7 P-type bonding pads 211 and 2 N-type bonding pads 212 .
  • a display screen carrying a Micro LED chip is similar to the display screen carrying a Micro LED chip in Embodiment 1, and the only difference is:
  • the LED chip 30 includes three Micro LED chips, and three P-type bonding pads 211 and one N-type bonding pad 212 are provided on the substrate 20 .
  • a display screen carrying a Micro LED chip is similar to the display screen carrying a Micro LED chip in Embodiment 1, and the only difference is:
  • the LED chip 30 includes three Micro LED chips, and the substrate 20 is provided with two P-type pads 211 and three N-type pads 212;
  • the anode substrate pad 111 is connected to the P-type pad 211 through solder balls, and the P-type pad 211 is electrically connected to the connecting metal 50 through the P-type Bragg reflective layer through hole 221; the connecting metal 50 is connected to the P-type conductive metal layer 311.
  • the P-type conductive metal is electrically connected to the current spreading layer 340 through the P-type insulating protective layer through hole 331; the current spreading layer 340 is electrically connected to the P-type semiconductor 321 layer to excite holes;
  • the cathode substrate pad 112 is connected to the N-type pad 212 through solder balls.
  • the N-type pad 212 is electrically connected to the N-type conductive metal layer 312 through the N-type Bragg reflective layer through hole 222.
  • the N-type conductive metal layer 312 passes through the N-type Bragg reflective layer through hole 222.
  • the insulating protective layer through hole 332 is electrically connected to the conductive step of the N-type semiconductor 322 to excite electrons.
  • each of the above units or structures can be implemented as an independent entity, or can be combined in any way to be implemented as the same or several entities.
  • each of the above units or structures please refer to the previous embodiments and will not be discussed here. Again.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La présente invention concerne une puce de DEL (30) et un écran d'affichage la comprenant. La puce de DEL (30) comprend : un substrat (20), un métal de connexion (50), et plusieurs sous-puces de DEL (31), plusieurs plots de type P (211) et plusieurs plots de type N (212) étant disposés sur le substrat (20) ; chaque plot de type P (211) est indépendamment relié à un plot de substrat d'anode (111) sur le substrat (10) par de l'étain métallique (40) ; chaque plot de type N (212) est indépendamment connecté à un plot de substrat de cathode (112) sur le substrat (10) par de l'étain métallique (40) ; et une couche métallique conductrice de type P (311) ou une couche métallique conductrice de type N (312) de chaque sous-puce de DEL (31) réalise une connexion électrique par l'intermédiaire du métal de connexion (50). Les plots de type P (211) et les plots de type N (212) sont disposés séparément sur le substrat (20), et la couche métallique conductrice de type P (311) ou la couche métallique conductrice de type N (312) réalise une connexion électrique par l'intermédiaire du métal de connexion (50), de telle sorte que les problèmes techniques de connexion à l'étain, de court-circuit et de faible rendement de l'art antérieur sont résolus, ces problèmes étant causés par la trop grande proximité des plots de type P (211) par rapport aux plots de type N (212).
PCT/CN2022/103436 2022-06-14 2022-07-01 Puce de del et écran d'affichage la comprenant WO2023240713A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210666625.6 2022-06-14
CN202210666625.6A CN114975395A (zh) 2022-06-14 2022-06-14 载有led芯片的显示屏

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WO2023240713A1 true WO2023240713A1 (fr) 2023-12-21

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