WO2023238498A1 - アナログ回路 - Google Patents

アナログ回路 Download PDF

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Publication number
WO2023238498A1
WO2023238498A1 PCT/JP2023/014588 JP2023014588W WO2023238498A1 WO 2023238498 A1 WO2023238498 A1 WO 2023238498A1 JP 2023014588 W JP2023014588 W JP 2023014588W WO 2023238498 A1 WO2023238498 A1 WO 2023238498A1
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Prior art keywords
current
power supply
amplifier
supply voltage
output terminal
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PCT/JP2023/014588
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English (en)
French (fr)
Japanese (ja)
Inventor
英一 中本
信久 小澤
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2024526256A priority Critical patent/JPWO2023238498A1/ja
Publication of WO2023238498A1 publication Critical patent/WO2023238498A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion

Definitions

  • the present technology relates to analog circuits. Specifically, the present technology relates to an analog circuit provided with an IDAC (Current Digital to Analog Converter).
  • IDAC Current Digital to Analog Converter
  • class G amplifiers that combine the advantages of class AB bias and adaptive power supplies are sometimes used to achieve both high sound quality and high efficiency.
  • Adaptive power supplies sometimes use charge pump circuits that do not require inductance for voltage conversion.
  • an audio system has been proposed in which a positive power supply voltage and a negative power supply voltage are respectively supplied to the upper power line and lower power line of the main amplifier ( For example, see Patent Document 1).
  • This technology was created in view of this situation, and its purpose is to reduce the noise of analog circuits equipped with IDACs.
  • This technology was developed to solve the above-mentioned problems, and its first aspect is to generate a differential current according to digital data based on a positive power supply voltage and a negative power supply voltage.
  • the analog circuit includes a current generation section and a switching circuit that switches the output of the differential current based on the digital data. This brings about the effect that differential currents generated based on the positive power supply voltage and the negative power supply voltage are differentially output.
  • the switching circuit further includes a first external output terminal and a second external output terminal that output the differential current to the outside, and the switching circuit is configured to output the differential current from the current generating section when the digital data is not input.
  • the output may be separated from the first external output terminal and the second external output terminal. This brings about the effect that the first external output terminal and the second external output terminal are set to the ground potential when no digital data is input.
  • the first external output terminal and the second external output terminal may be set to a ground potential when the digital data is not input. This brings about the effect that the voltage at the output terminal of the IDAC when no digital data is input becomes equal to the common mode voltage of the amplifier to which the differential current generated by the IDAC is input.
  • the current generation unit includes a positive current generation unit that generates a positive current based on the positive power supply voltage, and a negative current generation unit that generates a negative current based on the negative power supply voltage.
  • a first switching element that supplies the output of the positive current generation section to the first external output terminal; and a first switching element that supplies the output of the negative current generation section to the second external output terminal.
  • a second switching element that supplies the output of the positive current generation section to the second external output terminal, and a third switching element that supplies the output of the negative current generation section to the first external output terminal.
  • the first switching element and the second switching element are switched synchronously based on the digital data
  • the third switching element and the fourth switching element are switched synchronously based on the digital data.
  • the fifth switching element and the sixth switching element may be switched synchronously based on the digital data. This brings about the effect that, while outputting the differential current generated by the IDAC based on digital data, the differential current generated by the IDAC when no digital data is input is separated from the output of the IDAC.
  • the positive current generation section includes a first cascode current mirror circuit
  • the negative current generation section includes a second cascode current mirror circuit
  • the first cascode current mirror circuit may include an operational amplifier used to generate a mirror source current
  • the second cascode current mirror circuit may include a current source used to generate a mirror source current.
  • the first aspect may further include a first capacitor that decouples the bias gate voltage of the first cascode current mirror circuit, and a second capacitor that decouples the bias gate voltage of the second cascode current mirror circuit. . This brings about the effect that the noise of the bias gate voltage is reduced.
  • the device may further include a first charge pump circuit that generates the positive power supply voltage and the negative power supply voltage based on a single power supply voltage. This brings about the effect that a positive power supply voltage and a negative power supply voltage are supplied to the IDAC.
  • the positive power supply voltage and the negative power supply voltage may be step-down voltages obtained by stepping down the single power supply voltage. This brings about the effect that the power consumption of the IDAC is reduced.
  • the current generating section and the switching circuit may be provided for a plurality of systems, and the first charge pump circuit may be shared by the current generating section for the plurality of systems. This brings about the effect that DA conversion for a plurality of channels can be performed while suppressing an increase in circuit scale.
  • the device may further include an amplifier that outputs a differential voltage based on the input of the differential current. This brings about the effect of improving the drive capability with differential current input.
  • the amplifier may include a fully differential amplifier. This brings about the effect that distortion of the differential output is reduced.
  • the amplifier includes an integrator that inputs the differential current generated by the current generation section, an inverting amplifier connected to a subsequent stage of the integrator, and an output of the inverting amplifier. It may also include a resistor that feeds back to the input of the integrator. This brings about the effect that noise can be reduced while increasing gain at low frequencies.
  • the first aspect further includes a second charge pump circuit that adaptively generates a positive power supply voltage and a negative power supply voltage of the amplifier based on a single power supply voltage according to the output amplitude of the amplifier. Good too. This brings about the effect that a positive power supply voltage and a negative power supply voltage are supplied to the amplifier.
  • the amplifiers may be provided for a plurality of systems, and the second charge pump circuit may be shared by the amplifiers for the plurality of systems. This brings about the effect that signals for a plurality of channels are amplified while suppressing an increase in circuit scale.
  • FIG. 3 is a diagram showing a configuration example of an analog circuit according to the first embodiment.
  • 1 is a diagram showing an example of a circuit configuration of an IDAC according to a first embodiment;
  • FIG. 3 is a diagram showing an example of an output waveform of an IDAC and an output waveform of an amplifier according to the first embodiment.
  • FIG. 7 is a diagram showing a configuration example of an analog circuit according to a second embodiment.
  • FIG. 7 is a diagram showing a configuration example of an analog circuit according to a third embodiment.
  • First embodiment (example of driving IDAC with half voltage of positive and negative power supply voltages) 2.
  • Second embodiment (example of driving IDAC with positive and negative power supply voltages) 3.
  • Third embodiment (example with two systems of IDAC and amplifier)
  • FIG. 1 is a diagram showing a configuration example of an analog circuit according to the first embodiment.
  • an analog circuit 100 is supplied with a positive power supply voltage and a negative power supply voltage. Then, analog circuit 100 generates differential voltages VOP and VON based on differential currents IOP and ION generated according to digital data DA, and drives speaker 105.
  • Analog circuit 100 includes charge pump circuits 101 and 102, IDAC 103, and amplifier 104. Charge pump circuits 101 and 102, IDAC 103, and amplifier 104 may be integrated into one semiconductor chip, or may have a discrete configuration. The output of amplifier 104 is connected to speaker 105. Speaker 105 may be mounted on wireless headphones, for example.
  • a power supply voltage AVD is supplied as a power supply to the charge pump circuit 101, and is connected to the ground potential GND.
  • Charge pump circuit 101 generates a positive power supply voltage and a negative power supply voltage based on a single power supply voltage AVD, and supplies them to IDAC 103.
  • the charge pump circuit 101 can generate a positive half voltage +AVD/2 and a negative half voltage -AVD/2 by stepping down the power supply voltage AVD, and supply them to the IDAC 103.
  • a power supply voltage AVD is supplied as a power source to the charge pump circuit 102, and is connected to the ground potential GND.
  • Charge pump circuit 102 adaptively generates a positive power supply voltage and a negative power supply voltage according to the output amplitude of amplifier 104 and supplies them to amplifier 104 .
  • the charge pump circuit 102 generates a positive power supply voltage and a negative power supply voltage, and a positive step-down voltage and a negative step-down voltage obtained by stepping down the power supply voltage AVD, based on the single power supply voltage AVD, It may also be supplied to the amplifier 104.
  • the charge pump circuit 102 generates a positive power supply voltage +AVD and a negative power supply voltage -AVD, and a positive half voltage +AVD/2 and a negative half voltage -AVD/2 based on a single power supply voltage AVD. can be generated and supplied to amplifier 104.
  • IDAC 103 generates differential currents IOP and ION according to digital data DA based on positive half voltage +AVD/2 and negative half voltage -AVD/2 generated by charge pump circuit 101. At this time, the IDAC 103 can switch the output of the differential currents IOP and ION based on the digital data DA. For example, the IDAC 103 can separate the outputs of the differential currents IOP and ION from the amplifier 104 when no digital data DA is input. At this time, external output terminals TOP and TON of differential currents IOP and ION connected to amplifier 104 are set to ground potential GND. In order to reduce ripples in the output voltage from the charge pump circuit 101, the output voltage from the charge pump circuit 101 may be stabilized by a series regulator. Note that the IDAC 103 is an example of a current generation unit and a switching circuit described in the claims.
  • Amplifier 104 generates differential voltages VOP and VON based on the input of differential currents IOP and ION generated by IDAC 103, and drives speaker 105.
  • Amplifier 104 may constitute a multiple feedback filter. At this time, when the amplitudes of differential voltages VOP and VON are small, a positive half voltage +AVD/2 and a negative half voltage -AVD/2 are supplied from charge pump circuit 102 to amplifier 104. When the amplitudes of differential voltages VOP and VON are large, positive power supply voltage +AVD and negative power supply voltage -AVD are supplied from charge pump circuit 102 to amplifier 104.
  • Amplifier 104 includes an integrator 106, an inverting amplifier 107, and resistors 151 and 152.
  • Integrator 106 includes a fully differential amplifier 111 and capacitors 121 and 131.
  • Inverting amplifier 107 includes a fully differential amplifier 112 and resistors 122, 132, 141, and 142.
  • a non-inverting output terminal of the fully differential amplifier 111 is connected to an inverting input terminal of the fully differential amplifier 111 via a capacitor 121.
  • the inverting output terminal of the fully differential amplifier 111 is connected to the non-inverting input terminal of the fully differential amplifier 111 via a capacitor 131.
  • Differential currents IOP and ION are input from the IDAC 103 to an inverting input terminal and a non-inverting input terminal of the fully differential amplifier 111, respectively.
  • a non-inverting output terminal of the fully differential amplifier 112 is connected to an inverting input terminal of the fully differential amplifier 112 via a resistor 122.
  • the inverting output terminal of the fully differential amplifier 112 is connected to the non-inverting input terminal of the fully differential amplifier 112 via a resistor 132.
  • the inverting input terminal of the fully differential amplifier 112 is connected to the inverting output terminal of the fully differential amplifier 111 via a resistor 141.
  • a non-inverting input terminal of the fully differential amplifier 112 is connected to a non-inverting output terminal of the fully differential amplifier 111 via a resistor 142.
  • the non-inverting output terminal of the fully differential amplifier 112 is connected to the inverting input terminal of the fully differential amplifier 111 via a resistor 151.
  • the inverting output terminal of the fully differential amplifier 112 is connected to the non-inverting input terminal of the fully differential amplifier 111 via a resistor 152.
  • a non-inverting output terminal and an inverting output terminal of the fully differential amplifier 112 are connected to the speaker 105.
  • the integrator 106 operates at high speed to follow changes in the differential currents IOP and ION output from the IDAC 103, and can adapt to the input response from the IDAC 103.
  • the integrator 106 has a large output load resistance, so it can operate at high speed with low power, and the inverting amplifier 107 can have a low bandwidth and low gain, and is suitable for large output. be able to.
  • low frequency noise of the inverting amplifier 107 is corrected by feedback and is not output. Therefore, even when the two fully differential amplifiers 111 and 112 are provided in the amplifier 104, the noise is not doubled, but only by the amount of the fully differential amplifier 111 in the first stage.
  • the external output terminals TOP and TON of the IDAC 103 are connected to the external output terminals TAP and TAN of the amplifier 104 via resistors 151 and 152, respectively.
  • external output terminals TOP and TON can be set to ground potential GND. Therefore, the voltages at the external output terminals TOP and TON of the IDAC 103 become equal to the common-mode voltages at the external output terminals TAP and TAN of the amplifier 104, and there is no need to shift the common-mode voltage output from the amplifier 104.
  • noise accompanying the shift of the common mode voltage output from the amplifier 104 can be eliminated, and noise can be reduced.
  • FIG. 1 shows an example in which the amplifier 104 outputs the differential voltages VOP and VON, it may be a single-output amplifier.
  • FIG. 2 is a diagram showing an example of the circuit configuration of the IDAC according to the first embodiment.
  • the IDAC 103 includes a positive current generation section 401, a negative current generation section 402, and a switching circuit 403. At this time, the IDAC 103 can operate as a current addition type DA converter.
  • the positive current generation unit 401 generates a positive current based on the positive half voltage +AVD/2.
  • the positive current generation section 401 includes an operational amplifier 510, resistors 511, 514, 531, 551, and 571, and PMOS transistors 512, 513, 532, 533, 552, 553, 572, and 573.
  • the negative current generation unit 402 generates a negative current based on the negative half voltage -AVD/2.
  • the negative current generation section 402 includes a current source 500, resistors 520, 521, 524, 541, 561, and 581, and NMOS transistors 501, 502, 522, 523, 542, 543, 562, 563, 582, and 583. Be prepared.
  • the switching circuit 403 switches the output of the differential currents IOP and ION based on the digital data DA.
  • the switching circuit 403 includes switching elements 534 to 536, 544 to 546, 554 to 556, 564 to 566, 574 to 576, and 584 to 586.
  • the switching elements 534 to 536, 544 to 546, 554 to 556, 564 to 566, 574 to 576, and 584 to 586 may be MOS transistors.
  • the positive current generation section 401 can configure a cascode current mirror circuit.
  • a cascode current mirror circuit in the positive current generation section 401 the output impedance can be increased and the influence of ripples on the output voltage from the charge pump circuit 101 can be reduced.
  • PMOS transistors 512 and 513 are connected in series with each other, and PMOS transistors 532 and 533 are connected in series with each other.
  • PMOS transistors 552 and 553 are connected in series with each other, and PMOS transistors 572 and 573 are connected in series with each other.
  • the series circuit of PMOS transistors 512 and 513 can act as a current copy source.
  • the series circuit of PMOS transistors 532 and 533, the series circuit of PMOS transistors 552 and 553, and the series circuit of PMOS transistors 572 and 573 can each operate as current copy destinations.
  • the number of series circuits of PMOS transistors to which the current is copied can be provided as many as the number of bits of the digital data DA.
  • each PMOS transistor 512, 532, 552, and 572 are connected to the power supply terminal TVP via resistors 511, 531, 551, and 571, respectively.
  • a positive half voltage +AVD/2 is supplied to the power supply terminal TVP.
  • the gate of each PMOS transistor 532, 552 and 572 is connected to bias terminal TBP.
  • the gate of PMOS transistor 532 is connected to the gate of PMOS transistor 512 via resistor 514, and the gate of PMOS transistor 512 is connected to the output terminal of operational amplifier 510.
  • the inverting input terminal of the operational amplifier 510 is connected to the ground potential GND, and the non-inverting input terminal of the operational amplifier 510 is connected to the drain of the PMOS transistor 513.
  • the operational amplifier 510 to generate the mirror source current of the positive current generating section 401, it is possible to reduce the power supply voltage supplied to the positive current generating section 401. Therefore, it is possible to stably operate the positive current generation section 401 based on the positive half voltage +AVD/2 generated by the charge pump circuit 101.
  • a capacitor 515 is connected between the gate of the PMOS transistor 532 and the power supply terminal TVP. Resistor 514 and capacitor 515 can act as a low pass filter to attenuate bias current noise.
  • Bias gate voltage BA2 is applied to the gates of PMOS transistors 513, 533, 553, and 573. The bias gate voltage BA2 can be set to a value that allows the cascode current mirror circuit of the positive current generation section 401 to operate stably while allowing the PMOS transistors 513, 533, 553, and 573 to operate in saturation.
  • the series circuit of the PMOS transistors 532 and 533 and the resistor 531 can generate a positive current corresponding to the value of the first bit of the digital data DA.
  • the series circuit of PMOS transistors 552 and 553 and resistor 551 can generate a positive current corresponding to the value of the second bit of digital data DA.
  • the series circuit of PMOS transistors 572 and 573 and resistor 571 can generate a positive current corresponding to the value of the third bit of digital data DA.
  • the negative side current generation section 402 can configure a cascode current mirror circuit.
  • a cascode current mirror circuit in the negative side current generation section 402 the output impedance can be increased and the influence of ripples on the output voltage from the charge pump circuit 101 can be reduced.
  • NMOS transistors 501 and 502 are connected in series
  • NMOS transistors 522 and 523 are connected in series
  • NMOS transistors 542 and 543 are connected in series.
  • NMOS transistors 562 and 563 are connected in series with each other
  • NMOS transistors 582 and 583 are connected in series with each other.
  • the series circuit of NMOS transistors 501 and 502 can act as a current copy source.
  • the series circuit of NMOS transistors 542 and 543, the series circuit of NMOS transistors 562 and 563, and the series circuit of NMOS transistors 582 and 583 can each operate as current copy destinations.
  • the number of series circuits of NMOS transistors to which the current is copied can be provided as many as the number of bits of the digital data DA.
  • the drains of the NMOS transistors 502, 522, 542, 562, and 582 are connected to the power supply terminal TVN via resistors 520, 521, 541, 561, and 581, respectively.
  • a negative half voltage -AVD/2 is supplied to the power supply terminal TVN.
  • the gate of each NMOS transistor 542, 562 and 582 is connected to bias terminal TBN.
  • the gate of NMOS transistor 542 is connected to the gate of NMOS transistor 522 via resistor 524, and the gate of NMOS transistor 522 is connected to the gate of NMOS transistor 502. Further, the gate of the NMOS transistor 502 is connected to the drain of the NMOS transistor 501, and the current source 500 is connected to the drain of the NMOS transistor 501.
  • a capacitor 525 is connected between the gate of the NMOS transistor 542 and the power supply terminal TVN. Resistor 524 and capacitor 525 can act as a low pass filter to attenuate bias current noise.
  • a bias gate voltage BA1 is applied to the gates of NMOS transistors 501, 523, 543, 563, and 583. Bias gate voltage BA1 can be set to a value that allows the cascode current mirror circuit of negative side current generation section 402 to operate stably while allowing NMOS transistors 501, 523, 543, 563, and 583 to operate in saturation.
  • the series circuit of the NMOS transistors 542 and 543 and the resistor 541 can generate a negative current corresponding to the value of the first bit of the digital data DA.
  • the series circuit of NMOS transistors 562 and 563 and resistor 561 can generate a negative current corresponding to the value of the second bit of digital data DA.
  • the series circuit of NMOS transistors 582 and 583 and resistor 581 can generate a negative current corresponding to the value of the third bit of digital data DA.
  • a capacitor 591 is connected between the power supply terminal TVP and the bias terminal TBP, and a capacitor 592 is connected between the power supply terminal TVN and the bias terminal TBN.
  • Capacitor 591 can decouple the bias gate voltage applied to the gates of PMOS transistors 512, 532, 552, and 572.
  • Capacitor 592 can decouple the bias gate voltage applied to the gates of NMOS transistors 502, 522, 542, 562, and 582.
  • Each capacitor 591 and 592 may be attached externally. At this time, each capacitor 591 and 592 may have a large capacity.
  • Switching elements 534 and 544 are connected in series with each other, switching elements 535 and 545 are connected in series with each other, and switching elements 536 and 546 are connected in series with each other.
  • a series circuit of switching elements 534 and 544, a series circuit of switching elements 535 and 545, and a series circuit of switching elements 536 and 546 are connected between the drain of PMOS transistor 533 and the drain of NMOS transistor 543. .
  • Switching elements 554 and 564 are connected in series with each other, switching elements 555 and 565 are connected in series with each other, and switching elements 556 and 566 are connected in series with each other.
  • a series circuit of switching elements 554 and 564, a series circuit of switching elements 555 and 565, and a series circuit of switching elements 556 and 566 are connected between the drain of PMOS transistor 553 and the drain of NMOS transistor 563. .
  • Switching elements 574 and 584 are connected in series with each other, switching elements 575 and 585 are connected in series with each other, and switching elements 576 and 586 are connected in series with each other.
  • a series circuit of switching elements 574 and 584, a series circuit of switching elements 575 and 585, and a series circuit of switching elements 576 and 586 are connected between the drain of PMOS transistor 573 and the drain of NMOS transistor 583. .
  • a connection point between switching elements 534 and 544, a connection point between switching elements 554 and 564, and a connection point between switching elements 574 and 584 are connected to an external output terminal TOP.
  • a connection point between switching elements 536 and 546, a connection point between switching elements 556 and 566, and a connection point between switching elements 576 and 586 are connected to external output terminal TON.
  • a connection point between switching elements 535 and 545, a connection point between switching elements 555 and 565, and a connection point between switching elements 575 and 585 are connected to ground potential GND.
  • the current flowing through the drain of the PMOS transistor 533 and the current flowing through the drain of the NMOS transistor 543 are caused to flow through the external output terminal TOP or TON. be able to.
  • the current flowing through the drain of PMOS transistor 533 and the current flowing through the drain of NMOS transistor 543 can flow through the ground point.
  • the current flowing through the drain of the PMOS transistor 553 and the current flowing through the drain of the NMOS transistor 563 are caused to flow through the external output terminal TOP or TON. be able to.
  • the current flowing through the drain of PMOS transistor 553 and the current flowing through the drain of NMOS transistor 563 can flow through the ground point.
  • the current flowing through the drain of the PMOS transistor 573 and the current flowing through the drain of the NMOS transistor 583 are caused to flow through the external output terminal TOP or TON. be able to.
  • the current flowing through the drain of PMOS transistor 573 and the current flowing through the drain of NMOS transistor 583 can flow through the ground point.
  • the voltages at the external output terminals TOP and TON of the IDAC 103 can be made equal to the common mode voltages at the external output terminals TAP and TAN of the amplifier 104, making it unnecessary to shift the common mode voltage output from the amplifier 104. Therefore, the noise accompanying the shift of the common mode voltage output from the amplifier 104 can be eliminated, and the noise of the analog circuit 100 can be reduced.
  • FIG. 3 is a diagram showing an example of the output waveform of the IDAC and the output waveform of the amplifier according to the first embodiment. Note that a in FIG. 3 indicates the output waveform of the differential currents IOP and ION, and b in FIG. 3 indicates the output waveform of the differential voltages VOP and VON.
  • the IDAC 103 generates differential currents IOP and ION in a stepwise manner according to the digital data DA, and outputs them via external output terminals TOP and TON, respectively.
  • amplifier 104 generates differential voltages VOP and VON based on differential currents IOP and ION, and outputs them via external output terminals TAP and TAN, respectively.
  • the waveforms of the differential voltages VOP and VON become waveforms obtained by smoothing the step-like waveforms of the differential currents IOP and ION.
  • a positive power supply voltage +AVD and a negative power supply voltage -AVD, and a positive half voltage +AVD/2 and a negative half voltage -AVD/2 are switched according to the amplitudes of the differential voltages VOP and VON.
  • the amplifier 104 can operate as a class G amplifier that combines a class AB bias and an adaptive power supply.
  • the IDAC 103 generates the differential currents IOP and ION according to the digital data DA based on the positive power supply voltage and the negative power supply voltage.
  • the IDAC 103 and the amplifier 104 can be connected without interposing the DAC amplifier between the IDAC 103 and the amplifier 104, and it is possible to prevent signal quality from deteriorating due to noise of the DAC amplifier.
  • an inverting amplifier 107 is connected after the integrator 106, and the output of the inverting amplifier 107 is fed back to the input of the integrator 106. This makes it possible to increase the gain of the amplifier 104 at low frequencies while reducing noise.
  • the IDAC 103 is provided that generates the differential currents IOP and ION according to the digital data DA based on the positive half voltage +AVD/2 and the negative half voltage -AVD/2.
  • an IDAC 203 is provided that generates differential currents IOP and ION according to digital data DA based on power supply voltage AVD and negative power supply voltage -AVD generated by a charge pump circuit.
  • FIG. 4 is a diagram showing a configuration example of an analog circuit according to the second embodiment.
  • an analog circuit 200 includes a charge pump circuit 201 and an IDAC 203 in place of the charge pump circuit 101 and IDAC 103 of the first embodiment described above.
  • the rest of the configuration of the analog circuit 200 of the second embodiment is similar to the configuration of the analog circuit 100 of the first embodiment described above.
  • Charge pump circuit 201 is supplied with power supply voltage AVD and connected to ground potential GND.
  • Charge pump circuit 101 generates negative power supply voltage -AVD based on single power supply voltage AVD and supplies it to IDAC 103.
  • IDAC 203 generates differential currents IOP and ION according to digital data DA based on power supply voltage AVD and negative power supply voltage -AVD generated by charge pump circuit 201. At this time, the IDAC 203 can switch the output of the differential currents IOP and ION based on the digital data DA. For example, the IDAC 203 can separate the outputs of the differential currents IOP and ION from the amplifier 104 when no digital data DA is input.
  • the IDAC 203 generates a differential current IOP according to the digital data DA based on the power supply voltage AVD and the negative power supply voltage -AVD generated by the charge pump circuit 201. Generate ION. Thereby, the operating margin of the IDAC 203 can be improved.
  • FIG. 5 is a diagram showing a configuration example of an analog circuit according to the third embodiment.
  • an analog circuit 300 includes an IDAC 303 and an amplifier 304 instead of the IDAC 103 and amplifier 104 of the first embodiment described above.
  • the rest of the configuration of the analog circuit 300 of the third embodiment is similar to the configuration of the analog circuit 100 of the first embodiment described above.
  • the IDAC 303 has an IDAC 313 added to the IDAC 103 of the first embodiment described above.
  • IDAC 313 can be configured similarly to IDAC 103.
  • the digital data DA1 is input to the IDAC 103, and the digital data DA2 is input to the IDAC 313.
  • Digital data DA1 and DA2 are stereo data.
  • the amplifier 304 has an amplifier 314 added to the amplifier 104 of the first embodiment described above.
  • Amplifier 314 can be configured similarly to amplifier 104.
  • An amplifier 314 is connected after the IDAC 313 .
  • the output of amplifier 314 is connected to speaker 315.
  • the charge pump circuit 101 is shared by the IDACs 103 and 313. At this time, charge pump circuit 101 can supply positive half voltage +AVD/2 and negative half voltage -AVD/2 to IDACs 103 and 313.
  • Charge pump circuit 102 is shared by amplifiers 104 and 314. At this time, charge pump circuit 102 can supply positive power supply voltage +AVD, negative power supply voltage -AVD, and positive half voltage +AVD/2 and negative half voltage -AVD/2 to amplifiers 104 and 314. can.
  • two systems of IDACs 103 and 313 and amplifiers 104 and 314 are provided in order to support stereo output.
  • three or more IDACs and amplifiers may be provided.
  • a single charge pump circuit may be shared by IDACs for three or more systems, or a separate charge pump circuit may be shared by amplifiers for three or more systems.
  • the charge pump circuit 201 of the above-described second embodiment may be used instead of the charge pump circuit 101.
  • analog circuits 100 to 300 described above may be applied to, for example, car audio or component audio in addition to wireless headphones, or may be applied to audio equipment attached to a monitor or television.
  • the embodiments described above are examples for embodying the present technology, and the matters in the embodiments and the matters specifying the invention in the claims have a corresponding relationship, respectively.
  • the matters specifying the invention in the claims and the matters in the embodiments of the present technology having the same names have a corresponding relationship.
  • the present technology is not limited to the embodiments, and can be realized by making various modifications to the embodiments without departing from the gist thereof. Further, the effects described in this specification are merely examples and are not limited, and other effects may also be present.
  • a current generation unit that generates a differential current according to digital data based on a positive power supply voltage and a negative power supply voltage; and a switching circuit that switches the output of the differential current based on the digital data.
  • (2) further comprising a first external output terminal and a second external output terminal that output the differential current to the outside;
  • the analog circuit according to (1) wherein the switching circuit separates the output from the current generation section from the first external output terminal and the second external output terminal when the digital data is not input.
  • the first external output terminal and the second external output terminal are set to a ground potential when no digital data is input.
  • the current generating section includes: a positive current generation section that generates a positive current based on the positive power supply voltage; and a negative current generation unit that generates a negative current based on the negative power supply voltage
  • the switching circuit includes: a first switching element that supplies the output of the positive current generation section to the first external output terminal; a second switching element that supplies the output of the negative current generation section to the second external output terminal; a third switching element that supplies the output of the positive current generation section to the second external output terminal; a fourth switching element that supplies the output of the negative current generation section to the first external output terminal; a fifth switching element that sets the output of the positive current generation section to a ground potential; a sixth switching element that sets the output of the negative side current generation section to the ground potential,
  • the first switching element and the second switching element are switched synchronously based on the digital data
  • the third switching element and the fourth switching element are switched synchronously based on the digital data,
  • the analog circuit according to any one of (1) to (3), wherein the fifth switching element and
  • the positive current generation section includes a first cascode current mirror circuit
  • the negative current generation section includes a second cascode current mirror circuit
  • the first cascode current mirror circuit includes an operational amplifier used to generate a mirror source current
  • (6) a first capacitor that decouples the bias gate voltage of the first cascode current mirror circuit;
  • the current generation section and the switching circuit are provided for multiple systems, The analog circuit according to (7) or (8), wherein the first charge pump circuit is shared by the current generation units for the plurality of systems.
  • the amplifier includes a fully differential amplifier.
  • the amplifier is an integrator that receives the differential current generated by the current generation section; an inverting amplifier connected after the integrator; The analog circuit according to (10) or (11), further comprising a resistor that feeds back the output of the inverting amplifier to the input of the integrator. (13) From (10) above, further comprising a second charge pump circuit that adaptively generates a positive power supply voltage and a negative power supply voltage of the amplifier based on a single power supply voltage according to the output amplitude of the amplifier. 12) The analog circuit according to any one of 12). (14) The amplifier is provided for multiple systems, The analog circuit according to (13), wherein the second charge pump circuit is shared by the amplifiers of the plurality of systems.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
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PCT/JP2023/014588 2022-06-07 2023-04-10 アナログ回路 Ceased WO2023238498A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335838A (ja) * 1992-05-29 1993-12-17 Nec Corp 全差動型アナログ回路
JPH11178005A (ja) * 1997-12-08 1999-07-02 Rohm Co Ltd デジタルビデオエンコーダ
US7733178B1 (en) * 2007-10-24 2010-06-08 Fairchild Semiconductor Corporation High efficiency audio amplifier
JP2015519778A (ja) * 2012-03-28 2015-07-09 日本テキサス・インスツルメンツ株式会社 オーディオ信号を再生するための低ノイズ及び低電力配置
US10009686B1 (en) * 2017-04-17 2018-06-26 Cirrus Logic, Inc. Fully-differential current digital-to-analog converter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335838A (ja) * 1992-05-29 1993-12-17 Nec Corp 全差動型アナログ回路
JPH11178005A (ja) * 1997-12-08 1999-07-02 Rohm Co Ltd デジタルビデオエンコーダ
US7733178B1 (en) * 2007-10-24 2010-06-08 Fairchild Semiconductor Corporation High efficiency audio amplifier
JP2015519778A (ja) * 2012-03-28 2015-07-09 日本テキサス・インスツルメンツ株式会社 オーディオ信号を再生するための低ノイズ及び低電力配置
US10009686B1 (en) * 2017-04-17 2018-06-26 Cirrus Logic, Inc. Fully-differential current digital-to-analog converter

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