WO2023236811A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2023236811A1
WO2023236811A1 PCT/CN2023/097066 CN2023097066W WO2023236811A1 WO 2023236811 A1 WO2023236811 A1 WO 2023236811A1 CN 2023097066 W CN2023097066 W CN 2023097066W WO 2023236811 A1 WO2023236811 A1 WO 2023236811A1
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WIPO (PCT)
Prior art keywords
dielectric layer
groove
layer
semiconductor device
preparation
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PCT/CN2023/097066
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English (en)
French (fr)
Inventor
苏帅
冯鹏
韩明涛
李皓天
何林峰
武龙
魏巍
张亚文
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华为技术有限公司
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Publication of WO2023236811A1 publication Critical patent/WO2023236811A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L29/66409—
    • H01L29/778—

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a semiconductor device, an electronic chip, an electronic device, and a method for preparing a semiconductor device.
  • the semiconductor device may include a stacked substrate, epitaxial layer, dielectric layer, etc.
  • the substrate can contain elements such as silicon, arsenic, and carbon
  • the epitaxial layer can contain elements such as gallium, nitrogen, and aluminum
  • the dielectric layer can contain elements such as silicon, oxygen, and nitrogen.
  • the material contained in the dielectric layer determines the insulation of the dielectric layer, which in turn affects the static power consumption of the semiconductor device.
  • the present application provides a semiconductor device, an electronic chip, an electronic device and a method for preparing the semiconductor device, which can improve the insulation of the first dielectric layer, reduce the static current of the semiconductor device, and thereby reduce the static power consumption of the semiconductor device.
  • the present application provides a semiconductor device, which may include a substrate, an epitaxial layer, a first dielectric layer and a second dielectric layer.
  • the substrate, the epitaxial layer, the first dielectric layer and the second dielectric layer may be stacked in sequence.
  • the first dielectric layer may include a first material
  • the second dielectric layer may include a second material
  • the elements contained in the first material and the elements contained in the second material may not be exactly the same. That is to say, the elements contained in the first material and the elements contained in the second material may be partially the same, or completely different.
  • the first material may contain aluminum element
  • the second material may contain silicon element
  • the elements contained in the first material contained in the first dielectric layer and the elements contained in the second material contained in the second dielectric layer are not exactly the same, and the first dielectric layer contains a first material containing aluminum element,
  • the second dielectric layer contains a second material containing silicon element, which can increase the relative dielectric constant (also called relative permittivity) of the first dielectric layer, thereby improving the insulation of the first dielectric layer and reducing the resistance of the semiconductor device.
  • Quiescent current reduces the static power consumption of semiconductor devices.
  • the first material may be aluminum oxide or aluminum nitride.
  • the second material may be silicon oxide, silicon nitride or silicon oxynitride.
  • the first material can also be other materials containing aluminum elements, and the second material can also be other materials containing silicon elements, which are not limited in this application.
  • the second dielectric layer may not contain aluminum element. That is to say, the first dielectric layer may contain aluminum element, the second dielectric layer may contain silicon element, but the second dielectric layer The dielectric layer may not contain aluminum.
  • the thickness of the first dielectric layer may be 5 nm to 30 nm.
  • the thickness of the second dielectric layer may be 100 nm to 300 nm.
  • the first dielectric layer and the second dielectric layer can also have other thickness ranges, which are not limited in this application.
  • the elements contained in the material contained in the epitaxial layer may not be exactly the same as the elements contained in the material contained in the substrate. That is to say, the elements contained in the material contained in the epitaxial layer may be partially or completely different from the elements contained in the material contained in the substrate. Therefore, the epitaxial layer can be called heteroepitaxial.
  • the present application provides an electronic chip, which may include passive devices and the semiconductor device provided by the above-mentioned first aspect and its possible implementations.
  • the passive device can be electrically connected to the semiconductor device.
  • passive components may include resistors, capacitors, etc., and this application does not limit passive components.
  • this application provides an electronic device, which may include a circuit board and the electronic chip provided by the above-mentioned second aspect and possible implementations thereof.
  • the electronic chip can be arranged on the circuit board.
  • the present application provides a method for manufacturing a semiconductor device.
  • the semiconductor device may include a substrate, an epitaxial layer, a first dielectric layer and a second dielectric layer that are stacked in sequence.
  • the preparation method may include: performing photolithography on the second dielectric layer to form a mask layer.
  • the second dielectric layer is etched according to the mask layer, and the mask layer is removed to form a first groove.
  • the first dielectric layer is etched according to the first groove to form a second groove.
  • the first dielectric layer may include a first material
  • the second dielectric layer may include a second material
  • the elements contained in the first material and the elements contained in the second material may not be exactly the same. That is to say, the elements contained in the first material and the elements contained in the second material may be partially the same, or completely different.
  • the first material may contain aluminum element
  • the second material may contain silicon element
  • performing photolithography on the second dielectric layer to form a mask layer may include: applying photoresist on the surface of the second dielectric layer, and baking it according to the preset baking temperature and preset baking time.
  • the second dielectric layer coated with photoresist is baked. Expose the baked second dielectric layer according to the preset exposure time. Using a developing solution, the exposed second dielectric layer is developed according to a preset development time to form a mask layer.
  • the photoresist can be a positive resist or a negative resist.
  • the photoresist in the exposed area can be dissolved, which means that the positive resist is developed in the exposed area.
  • the photoresist in the non-exposed area can be dissolved, which means that the negative resist develops in the non-exposed area.
  • the preset baking temperature may be 90°C to 120°C, and the preset baking time may be 3min to 5min.
  • the preset baking temperature can also be in other temperature ranges, and the preset baking time can also be in other time ranges, which are not limited in this application.
  • the preset exposure time may be 100 ms to 300 ms, and the preset development time may be 40 s to 70 s.
  • the preset exposure time and the preset development time can also be in other time ranges, which are not limited in this application.
  • the developer may be tetramethylammonium hydroxide.
  • the developer can also be of other types, which is not limited in this application.
  • etching the second dielectric layer according to the mask layer, and removing the mask layer to form the first groove may include: using a dry etching process according to the mask layer.
  • the second dielectric layer is etched to obtain an etched second dielectric layer.
  • a remover is used to remove the mask layer on the surface of the etched second dielectric layer to form a first groove. That is to say, the photoresist is used as a mask layer, and a dry etching process is used to etch the second dielectric layer. It can be seen that in this application, the second dielectric layer is etched through a dry etching process to form the first groove.
  • the depth of the first groove is the etching depth of the second dielectric layer, and does not include the thickness of the mask layer on the surface of the second dielectric layer after etching.
  • This application uses a dry etching process to etch the second dielectric layer, which can accurately control the depth of the first groove, thereby improving the uniformity and yield rate of the semiconductor device.
  • fluorine-based gas or chlorine-based gas can be selected, and a dry etching process is used to etch the second dielectric layer.
  • the fluorine-based gas can be a gas containing fluorine element, carbon element, sulfur element, etc., such as sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, perfluoropropane, etc.
  • the chlorine-based gas can be a gas containing chlorine element, such as carbon tetrachloride, chlorine, boron chloride, etc.
  • the dry etching process can be a reactive ion etching (RIE) process (RIE process for short), an inductively coupled plasma (ICP) etching process (ICP process for short), Any of the advanced oxide etch (AOE) process (referred to as AOE process), etc.
  • RIE reactive ion etching
  • ICP inductively coupled plasma
  • AOE advanced oxide etch
  • other dry etching processes can also be used to etch the second dielectric layer, which is not limited in this application.
  • a glue remover is used to remove the mask layer on the surface of the etched second dielectric layer.
  • Different glue removers can be used to remove the mask layer on the surface of the etched second dielectric layer. Clean to form the first groove.
  • the glue remover may include any one of acetone, isopropyl alcohol, absolute ethanol, and N-methylpyrrolidone.
  • the glue remover may also include a combination of at least two of acetone, isopropyl alcohol, absolute ethanol, and N-methylpyrrolidone.
  • removing the mask layer on the surface of the etched second dielectric layer can avoid the impact on the corrosion rate and corrosion depth of the first dielectric layer, and improves the reliability of the preparation method.
  • etching the first dielectric layer according to the first groove to form the second groove may include: etching the first dielectric layer according to the first groove using a wet etching process. , forming a second groove.
  • the first dielectric layer at the bottom of the first groove is etched to obtain the second groove.
  • the depth of the first groove may be the etching depth of the second dielectric layer
  • the depth of the second groove may be the sum of the etching depth of the second dielectric layer and the etching depth of the first dielectric layer, so , the depth of the second groove may be greater than the depth of the first groove.
  • the first dielectric layer can be etched with an etching solution according to a preset etching time to form the second groove. That is to say, this application can etch the first dielectric layer through a wet etching process to form the second groove.
  • the corrosion solution includes any one of a solution of sulfuric acid and hydrogen peroxide in a preset ratio, a tetramethylammonium hydroxide solution, and a potassium hydroxide solution.
  • the corrosive solution can also be other solutions that can corrode the first dielectric layer, which is not limited in this application.
  • the preset corrosion time may be 1 min to 20 min.
  • the preset corrosion time can also be in other time ranges, which is not limited in this application.
  • This application uses a wet etching process to etch the first dielectric layer to avoid damage to the interface of the second groove, thereby reducing the interface state of the gate (which refers to the energy value at the forbidden interface at the interface between the gate and the epitaxial layer).
  • the first material may be aluminum oxide or aluminum nitride.
  • the second material may be silicon oxide, silicon nitride or silicon oxynitride.
  • the first material can also be other materials containing aluminum elements, and the second material can also be other materials containing silicon elements, which are not limited in this application.
  • the second dielectric layer may not contain aluminum element. That is to say, the first dielectric layer may contain aluminum element, the second dielectric layer may contain silicon element, but the second dielectric layer may not contain aluminum element.
  • the thickness of the first dielectric layer may be 5 nm to 30 nm.
  • the thickness of the second dielectric layer may be 100 nm to 300 nm.
  • the first dielectric layer and the second dielectric layer can also have other thickness ranges, which are not limited in this application.
  • the preparation method of a semiconductor device combines a dry etching process and a wet etching process, and forms a first groove through the dry etching process, and forms a first groove for deposition through the wet etching process.
  • the second groove of the gate Not only can the depth of the first groove be accurately controlled, improving the uniformity and yield rate of semiconductor devices, but it can also avoid damage to the interface of the second groove, reduce the interface state of the gate, avoid gate leakage, and improve the quality of semiconductor devices. reliability.
  • the present application provides a method for manufacturing a semiconductor device.
  • the semiconductor device may include a substrate, an epitaxial layer, a first dielectric layer and a second dielectric layer that are stacked in sequence.
  • the preparation method may include: forming an epitaxial layer on the surface of the substrate.
  • the first material is used to form a first dielectric layer on the surface of the epitaxial layer.
  • the second material is used to form a second dielectric layer on the surface of the first dielectric layer.
  • the first dielectric layer may include a first material
  • the second dielectric layer may include a second material
  • the elements contained in the first material and the elements contained in the second material may not be exactly the same. That is to say, the elements contained in the first material and the elements contained in the second material may be partially the same, or completely different.
  • the first material may contain aluminum element
  • the second material may contain silicon element
  • the first material may be aluminum oxide or aluminum nitride.
  • the second material may be silicon oxide, silicon nitride or silicon oxynitride.
  • the first material can also be other materials containing aluminum elements, and the second material can also be other materials containing silicon elements, which are not limited in this application.
  • the second dielectric layer may not contain aluminum element. That is to say, the first dielectric layer may contain aluminum element, the second dielectric layer may contain silicon element, but the second dielectric layer may not contain aluminum element.
  • the thickness of the first dielectric layer may be 5 nm to 30 nm.
  • the thickness of the second dielectric layer may be 100 nm to 300 nm.
  • the first dielectric layer and the second dielectric layer can also have other thickness ranges, which are not limited in this application.
  • Figure 1 is a schematic structural diagram of a semiconductor device 1 in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of the semiconductor device 1 in the embodiment of the present application.
  • Figure 3 is a schematic flow chart of process 100 in the embodiment of the present application.
  • Figure 4 is a schematic structural diagram of forming the mask layer 50 in the embodiment of the present application.
  • Figure 5 is a schematic structural diagram of forming the groove 401 in the embodiment of the present application.
  • Figure 6 is a schematic flow chart of process 200 in the embodiment of the present application.
  • Figure 7 is a schematic flow chart of process 300 in the embodiment of the present application.
  • Figure 8 is a schematic flow chart of process 400 in the embodiment of the present application.
  • At least one (item) refers to one or more, and “plurality” refers to two or more.
  • “And/or” is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, “A and/or B” can mean: only A exists, only B exists, and A and B exist simultaneously. , where A and B can be singular or plural. The character “/” generally indicates that the related objects are in an "or” relationship. “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • At least one of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c” ”, where a, b, c can be single or multiple.
  • the semiconductor device may include a stacked substrate, epitaxial layer, dielectric layer, etc.
  • the substrate can contain silicon (silicon), arsenic (arsenic), carbon (carbon) and other elements
  • the epitaxial layer can contain gallium (gallium), nitrogen (nitride), aluminum (aluminum) and other elements
  • the dielectric layer can contain elements such as silicon, oxygen (oxide), and nitrogen. The material contained in the dielectric layer determines the insulation of the dielectric layer, which in turn affects the static power consumption of the semiconductor device.
  • the semiconductor device 1 may include a substrate 10, an epitaxial layer 20, a dielectric layer 30 (ie, a first dielectric layer) and a dielectric layer 40 (ie, a second dielectric layer).
  • the substrate 10, the epitaxial layer 20, the dielectric layer 30 and the dielectric layer 40 may be stacked in sequence.
  • the dielectric layer 30 may include material A (ie, the first material), and the dielectric layer 40 may include material B (ie, the second material).
  • the elements contained in material A and the elements contained in material B may not be exactly the same. In other words, the elements contained in material A and the elements contained in material B may be partially the same, or completely different.
  • material A may contain aluminum element
  • material B may contain silicon element
  • the dielectric layer 30 includes material A containing aluminum elements, which can increase the relative dielectric constant of the dielectric layer 30 , thereby improving the insulation of the dielectric layer 30 , reducing the quiescent current of the semiconductor device 1 , and reducing the quiescent power of the semiconductor device 1 Consumption.
  • the dielectric layer 40 includes material B containing silicon element.
  • the dielectric layer 30 and the dielectric layer 40 may be provided with a groove 301 (ie, a second groove), and the depth of the groove 301 may be the thickness of the dielectric layer 30 (ie, the thickness of the dielectric layer 30 below).
  • the sum of the etching depth) and the thickness of the dielectric layer 40 (ie, the etching depth of the dielectric layer 40 below), the groove 301 is used to form the gate of the semiconductor device 1, and can be Please refer to the introduction below.
  • the material included in the epitaxial layer 20 may not contain exactly the same elements as the material included in the substrate 10 . That is to say, the elements contained in the material contained in the epitaxial layer 20 and the elements contained in the material contained in the substrate 10 may be partially different, or may be completely different. Therefore, the epitaxial layer 20 can be called heteroepitaxial.
  • the epitaxial layer 20 may include a buffer layer 201, a channel layer 202, an insertion layer 203, a barrier layer 204 and a cap layer 205 that are stacked in sequence.
  • the buffer layer 201 is in contact with the substrate 10
  • the capping layer 205 is in contact with the dielectric layer 30 .
  • the substrate 10 may include silicon, silicon carbide (SiC), sapphire (sapphire), etc.
  • the buffer layer 201 may include materials such as gallium nitride (gallium nitride) or aluminum nitride (AlN).
  • the channel layer 202 may include materials such as gallium nitride (GaN).
  • the insertion layer 203 may include materials such as aluminum nitride AlN.
  • the barrier layer 204 may include aluminum gallium nitride AlGaN (aluminum gallium nitride), indium aluminum nitride InAlN (indium aluminum nitride) and other materials.
  • the capping layer 205 may include materials such as gallium nitride (GaN).
  • the buffer layer 201, the channel layer 202, the insertion layer 203, the barrier layer 204 and the capping layer 205 may also include other materials respectively, which are not limited in the embodiments of this application.
  • the substrate 10 may include silicon Si
  • the buffer layer 201, the channel layer 202 and the cap layer 205 may include gallium nitride GaN
  • the insertion layer 203 may include aluminum nitride AlN
  • the barrier layer 204 may include nitrogen.
  • the epitaxial layer 20 in the embodiment of the present application is heteroepitaxial.
  • the semiconductor device 1 may also include a gate dielectric layer 60, a source electrode 90, a gate electrode 70 and a drain electrode 80, as shown in FIG. 2 .
  • the gate dielectric layer 60 may be stacked on the surface of the dielectric layer 40 and inside the groove 301 , and the gate electrode 70 may be provided on the surface of the gate dielectric layer 60 .
  • the source electrode 90 and the drain electrode 80 can also be disposed on the surface of the gate dielectric layer 60 .
  • the source electrode 90 can pass through the dielectric layer 30 and the dielectric layer 40 to contact the cap layer 205 .
  • the drain electrode 80 can also pass through the dielectric layer 30 And the dielectric layer 40 is in contact with the capping layer 205. Therefore, an ohmic contact can be formed between the source electrode 90 and the capping layer 205, and an ohmic contact can also be formed between the drain electrode 80 and the capping layer 205.
  • material A may be aluminum oxide or aluminum nitride.
  • Material B may be silicon oxide, silicon nitride or silicon oxynitride.
  • material A can also be other materials containing aluminum elements, and material B can also be other materials containing silicon elements, which are not limited in this application.
  • dielectric layer 40 may not contain aluminum element. That is to say, the dielectric layer 30 may contain the aluminum element, and the dielectric layer 40 may contain the silicon element, but the dielectric layer 40 may not contain the aluminum element.
  • the dielectric layer 30 may include aluminum oxide Al 2 O 3 (aluminum oxide), and the dielectric layer 40 may include silicon dioxide SiO 2 .
  • the thickness of the dielectric layer 30 may be 5 nm to 30 nm.
  • the thickness of the dielectric layer 40 may range from 100 nm to 300 nm.
  • the dielectric layer 30 and the dielectric layer 40 can also have other thickness ranges, which are not limited in this application.
  • the thickness of the dielectric layer 30 may be 25 nm, and the thickness of the dielectric layer 40 may be 200 nm.
  • the semiconductor device 1 provided in the embodiment of the present application may be a field effect transistor, and further may be a high electron mobility transistor (HEMT), a heterojunction field effect transistor (HFET), or a modulated doping transistor.
  • HEMT high electron mobility transistor
  • HFET heterojunction field effect transistor
  • MODFET modulated doping transistor
  • the embodiment of the present application also provides an electronic chip, which may include passive devices and semiconductor devices 1 .
  • the passive device may be electrically connected to the semiconductor device 1 .
  • passive components may include resistors, capacitors, etc., and the embodiments of this application do not limit passive components.
  • An embodiment of the present application also provides an electronic device, which may include a circuit board and the above-mentioned electronic chip.
  • the electronic chip can be arranged on the circuit board.
  • the embodiments of the present application provide a method for preparing a semiconductor device.
  • the semiconductor device please refer to the above, and the details of the embodiments of the present application will not be repeated.
  • the process 100 can be implemented according to the following steps.
  • Step S101 Perform photolithography on the dielectric layer 40 to form a mask layer 50, as shown in FIG. 4 .
  • Step S102 Etch the dielectric layer 40 according to the mask layer 50, and remove the mask layer 50 to form a groove 401, as shown in FIG. 5.
  • the depth of the groove 401 can be the etching depth of the dielectric layer 40 , excluding the thickness of the mask layer 50 on the surface of the etched dielectric layer 40 , that is, excluding the mask layer in FIG. 4 50 thickness.
  • Step S103 Etch the dielectric layer 30 according to the groove 401 to form the groove 301, as shown in FIG. 1 .
  • step S101 can be implemented as follows:
  • Step S101a Coat photoresist on the surface of the dielectric layer 40, and bake the dielectric layer 40 coated with photoresist according to the preset baking temperature and preset baking time.
  • the photoresist can be a positive resist or a negative resist.
  • the photoresist in the exposed area can be dissolved, which means that the positive resist is developed in the exposed area.
  • negative resist the photoresist in the non-exposed area can be dissolved, which means that the negative resist develops in the non-exposed area.
  • positive glue is applied to the surface of the dielectric layer 40 .
  • the preset baking temperature may be 90°C to 120°C, and the preset baking time may be 3min to 5min.
  • the preset baking temperature can also be in other temperature ranges, and the preset baking time can also be in other time ranges, which are not limited in this application.
  • the preset baking temperature may be 100°C, and the preset baking time may be 4 minutes.
  • Step S101b Expose the baked dielectric layer 40 according to the preset exposure time.
  • the preset exposure time may be 100 ms to 300 ms.
  • the preset exposure time may also be other time ranges, which is not limited in this application.
  • the preset exposure time may be 110 ms.
  • Step S101c Use a developer to develop the exposed dielectric layer 40 according to a preset development time to form a mask layer 50, as shown in FIG. 4 .
  • the preset development time may be 40s ⁇ 70s.
  • the preset development time can also be in other time ranges, which is not limited in this application.
  • the preset development time may be 50 seconds.
  • the developer may be tetramethylammonium hydroxide C 4 H 13 NO (tetramethylammonium hydroxide).
  • the developer can also be of other types, which is not limited in this application.
  • the mask layer 50 can also be formed in other ways, which is not limited by the embodiments of the present application.
  • Dry etching processes usually use reactive gases (such as reactive ions (RI), inductively coupled plasma (ICP) or ion beams (IB)) and then apply radio frequency voltage to generate ions and electrons. Ions and electrons can physically bombard the surface of the dielectric layer, and a chemical reaction occurs between the reactive gas and the dielectric layer to achieve etching of the dielectric layer.
  • reactive gases such as reactive ions (RI), inductively coupled plasma (ICP) or ion beams (IB)
  • the photoresist can be used as the mask layer 50, and a dry etching process can be used to etch the dielectric layer 40.
  • step S102 can be implemented as follows:
  • Step S102a According to the mask layer 50, use a dry etching process to etch the dielectric layer 40 to obtain an etched dielectric layer 40.
  • Step S102b Use a glue remover to remove the mask layer 50 on the surface of the etched dielectric layer 40 to form a groove 401, as shown in FIG. 5 .
  • a fluorine-based gas or a chlorine-based gas can be selected, and a dry etching process is used to etch the dielectric layer 40 according to a preset etching time.
  • the fluorine-based gas may be a gas containing fluorine, carbon, sulfur, etc., such as sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, perfluoropropane, etc.
  • the chlorine-based gas can be a gas containing chlorine element, such as carbon tetrachloride, chlorine, boron chloride, etc.
  • the etching time may be the ratio of the thickness of the dielectric layer 40 to the etching rate.
  • the dry etching process can be a reactive ion etching (RIE) process (RIE process for short), an inductively coupled plasma (ICP) etching process (ICP for short) process), advanced oxide etch (AOE) process (referred to as AOE process), etc.
  • RIE reactive ion etching
  • ICP inductively coupled plasma
  • AOE advanced oxide etch
  • other dry etching processes can also be used to etch the dielectric layer 40 , which is not limited in this application.
  • carbon tetrafluoride is selected, and the dielectric layer 40 is etched using the AOE process.
  • the etching time is 1 minute, and the etching depth of the dielectric layer 40 is 210 nm. It can be understood that the depth of the groove 401 is 210 nm.
  • step S102b different glue removers may be used to clean the mask layer 50 on the surface of the etched dielectric layer 40 to form the groove 401.
  • the glue remover may include acetone CH 3 COCH 3 (acetone), isopropyl alcohol C 3 H 8 O (isopropyl alcohol, IPA), absolute ethanol C 2 H 6 O (ethanol absolute), N-methylpyrrolidone Any one of C 5 H 9 NO(N-methylpyrrolidone).
  • the glue remover may also include a combination of at least two of acetone, isopropyl alcohol, absolute ethanol, and N-methylpyrrolidone. In the embodiment of the present application, acetone and isopropyl alcohol are used to clean the mask layer 50 on the surface of the etched dielectric layer 40 .
  • removing the mask layer 50 on the surface of the etched dielectric layer 40 can avoid the impact on the corrosion rate and corrosion depth of the dielectric layer 30 and improve the reliability of the preparation method.
  • the groove 401 can also be formed in other ways, which is not limited by the embodiments of the present application.
  • the dielectric layer 40 is etched through a dry etching process, so that the depth of the groove 401 can be precisely controlled, thereby improving the uniformity and yield rate of the semiconductor device 1 .
  • the wet etching process is a process that uses a corrosive solution to etch the dielectric layer.
  • the etching solution can be used to etch the dielectric layer 30 according to the groove 401 and according to the preset etching time to form the groove 301. That is to say, in the embodiment of the present application, the groove 301 is formed through a wet etching process, as shown in FIG. 1 .
  • the corrosion solution may include a solution of sulfuric acid H 2 SO 4 (sulfuric acid) and hydrogen peroxide H 2 O 2 (hydrogen peroxide) configured in a preset ratio, tetramethylammonium hydroxide C 4 H 13 NO Either (tetramethylammonium hydroxide, TMAH) solution or potassium hydroxide KOH (potassium hydroxide) solution.
  • TMAH tetramethylammonium hydroxide
  • KOH potassium hydroxide
  • the corrosion solution is a solution in which sulfuric acid (i.e., concentrated sulfuric acid) and hydrogen peroxide with a mass fraction of greater than or equal to 70% are configured according to a preset ratio.
  • the preset ratio is a mixture of concentrated sulfuric acid and hydrogen peroxide.
  • the volume ratio can be 7:3.
  • the preset corrosion time may be 1 min to 20 min.
  • the preset corrosion time can also be in other time ranges, which is not limited in this application. In the embodiment of this application, the preset corrosion time may be 5 minutes.
  • the groove 301 can also be formed in other ways, which is not limited by the embodiments of the present application.
  • This application uses a wet etching process to corrode the dielectric layer 30 to avoid damage to the interface of the groove 301, thereby reducing the interface state of the gate (meaning that at the interface where the gate contacts the epitaxial layer, the energy value is in the forbidden band some discrete or continuous electronic energy states or energy bands) to avoid gate leakage and improve the reliability of semiconductor devices.
  • the method for manufacturing a semiconductor device combines a dry etching process and a wet etching process, and forms the groove 401 through the dry etching process, and forms the groove 401 for depositing through the wet etching process.
  • the groove 301 of the positive gate Not only can the depth of the groove 401 be accurately controlled, thereby improving the uniformity and yield rate of the semiconductor device, but it can also avoid damage to the interface of the groove 301, reduce the interface state of the gate, and avoid gate leakage, thereby improving the quality of the semiconductor device. reliability.
  • the preparation method provided by the embodiment of the present application may also form the dielectric layer 30 and the dielectric layer 40 according to the following steps before performing the above process 100:
  • Step S401a Form the epitaxial layer 20 on the surface of the substrate 10.
  • Step S401b Use material A to form the dielectric layer 30 on the surface of the epitaxial layer 20.
  • Step S401c Use material B to form the dielectric layer 40 on the surface of the dielectric layer 30.
  • a deposition process may be used to form the dielectric layer 30 on the surface of the epitaxial layer 20.
  • the deposition process can include atomic layer deposition (ALD) process (ALD process for short), plasma enhanced atomic layer deposition (PEALD) process (PEALD process for short), plasma enhanced Chemical vapor deposition (plasma enhanced chemical vapor, PECVD) process (referred to as PECVD process), inductively coupled plasma chemical vapor deposition (ICPCVD) process (referred to as ICPCVD process), low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD) process (referred to as LPCVD process), electron beam evaporation (electronic beam evaporation, EBE) process (referred to as EBE process) or sputter deposition process, etc.
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PECVD plasma enhanced Chemical vapor deposition
  • ICPCVD inductively coupled plasma chemical vapor deposition
  • the PEALD process is used to form the dielectric layer 30 on the surface of the epitaxial layer 20 .
  • the dielectric layer 30 may include aluminum oxide, and the thickness of the dielectric layer 30 may be 25 nm.
  • step S401c the above-described deposition process can be used to form the dielectric layer 40 on the surface of the dielectric layer 30.
  • the PEALD process is used to form the dielectric layer 40 on the surface of the dielectric layer 30.
  • the dielectric layer 40 may contain silicon dioxide, and the thickness of the dielectric layer 40 may be 200 nm.
  • the relevant processes for forming the dielectric layer 30 and the dielectric layer 40 are introduced above.
  • the dielectric layer 30 and the dielectric layer 40 can also be formed in other ways, which are not limited by the embodiments of the present application.
  • the size of the sequence numbers of the above-mentioned processes does not mean the order of execution.
  • the execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation.

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Abstract

本申请提供了一种半导体器件及其制备方法，半导体器件可以包括依次层叠设置的衬底、外延层、第一介质层和第二介质层。第一介质层可以包含第一材料，第二介质层可以包含第二材料。第一材料含有的元素和第二材料含有的元素可以不完全相同。第一材料可以含有铝元素，第二材料可以含有硅元素，能够提高第一介质层的绝缘性，减小半导体器件的静态电流，进而降低半导体器件的静态功耗。制备方法将干法刻蚀工艺和湿法腐蚀工艺结合，进而形成用于淀积栅极的第二凹槽。不仅能够精确控制第二凹槽的深度，提高半导体器件的均匀性和良品率，而且能够避免对第二凹槽的界面造成损伤，减小栅极的界面态，避免栅极漏电，提高半导体器件的可靠性。

Description

半导体器件及其制备方法
本申请要求于2022年06月07日提交中国专利局、申请号为202210634224.2、申请名称为“半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件、电子芯片、电子设备及半导体器件的制备方法。
背景技术
随着科技的发展，包括半导体器件(如场效应晶体管等)的电子芯片在手机、平板电脑等电子设备中得到了广泛的应用。半导体器件可以包括层叠设置的衬底、外延层和介质层等。其中，衬底可以含有硅、砷、碳等元素，外延层可以含有镓、氮、铝等元素，介质层可以含有硅、氧、氮等元素。由于介质层包含的材料决定了介质层的绝缘性，进而影响半导体器件的静态功耗。
因此，如何降低半导体器件的静态功耗低成了亟需解决的技术问题。
发明内容
本申请提供了一种半导体器件、电子芯片、电子设备及半导体器件的制备方法，能够提高第一介质层的绝缘性，减小半导体器件的静态电流，进而降低半导体器件的静态功耗。
第一方面，本申请提供了一种半导体器件，可以包括衬底、外延层、第一介质层和第二介质层。衬底、外延层、第一介质层和第二介质层可以依次层叠设置。
其中，第一介质层可以包含第一材料，第二介质层可以包含第二材料。
进一步地，第一材料含有的元素和第二材料含有的元素可以不完全相同。也就是说，第一材料含有的元素和第二材料含有的元素可以部分相同，或者完全不同。
更进一步地，第一材料可以含有铝元素，第二材料可以含有硅元素。
本申请提供的半导体器件中，第一介质层包含的第一材料含有的元素和第二介质层包含的第二材料含有的元素不完全相同，第一介质层包含含有铝元素的第一材料，第二介质层包含含有硅元素的第二材料，能够增大第一介质层的相对介电常数(也可以称为相对电容率)，进而提高第一介质层的绝缘性，减小半导体器件的静态电流，降低半导体器件的静态功耗。
在一种可能的实现方式中，第一材料可以为氧化铝或者氮化铝。第二材料可以为氧化硅、氮化硅或氮氧化硅。当然，第一材料还可以为含有铝元素的其他材料，第二材料还可以为含有硅元素的其他材料，本申请不做限定。
在另一种可能的实现方式中，在第一材料含有铝元素的基础上，第二介质层可以不含有铝元素。也就是说，第一介质层可以含有铝元素，第二介质层可以含有硅元素，但第二 介质层可以不含有铝元素。
在又一种可能的实现方式中，第一介质层的厚度可以为5nm～30nm。第二介质层的厚度可以为100nm～300nm。当然，第一介质层和第二介质层分别还可以为其他厚度范围，本申请不做限定。
在再一种可能的实现方式中，外延层包含的材料含有的元素与衬底包含的材料含有的元素可以不完全相同。也就是说，外延层包含的材料含有的元素与衬底包含的材料含有的元素可以部分不同，也可以完全不同。于是，外延层可以叫作异质外延。
第二方面，本申请提供了一种电子芯片，可以包括无源器件和上述第一方面及其可能的实现方式提供的半导体器件。其中，无源器件可以与半导体器件电连接。
在一种可能的实现方式中，无源器件可以包括电阻、电容等，本申请对无源器件不做限定。
第三方面，本申请提供了一种电子设备，可以包括电路板和上述第二方面及其可能的实现方式提供的电子芯片。其中，电子芯片可以设置在电路板。
第四方面，本申请提供了一种半导体器件的制备方法。其中，半导体器件可以包括依次层叠设置的衬底、外延层、第一介质层和第二介质层。制备方法可以包括：对第二介质层进行光刻，形成掩膜层。根据掩膜层，对第二介质层进行刻蚀，并去除掩膜层，形成第一凹槽。根据第一凹槽，对第一介质层进行腐蚀，形成第二凹槽。
其中，第一介质层可以包含第一材料，第二介质层可以包含第二材料。
进一步地，第一材料含有的元素和第二材料含有的元素可以不完全相同。也就是说，第一材料含有的元素和第二材料含有的元素可以部分相同，或者完全不同。
更进一步地，第一材料可以含有铝元素，第二材料可以含有硅元素。
在一种可能的实现方式中，对第二介质层进行光刻，形成掩膜层，可以包括：在第二介质层表面涂光刻胶，并按照预设烘烤温度和预设烘烤时间对涂有光刻胶的第二介质层进行烘烤。按照预设曝光时间，对烘烤后的第二介质层进行曝光。采用显影液，并按照预设显影时间对曝光后的第二介质层进行显影，形成掩膜层。
进一步地，光刻胶可以为正胶或者负胶。其中，对于正胶，曝光区域的光刻胶可以溶解，也就是说正胶在曝光区域显影。对于负胶，非曝光区域的光刻胶可以溶解，也就是说负胶在非曝光区域显影。
在一示例中，预设烘烤温度可以为90℃～120℃，预设烘烤时间可以为3min～5min。当然，预设烘烤温度还可以为其他温度范围，预设烘烤时间还可以为其他时间范围，本申请不做限定。
在另一示例中，预设曝光时间可以为100ms～300ms，预设显影时间可以为40s～70s。当然，预设曝光时间和预设显影时间还可以分别为其他时间范围，本申请不做限定。
在又一示例中，显影液可以为四甲基氢氧化铵。当然，显影液还可以为其他类型，本申请不做限定。
在一种可能的实现方式中，根据掩膜层，对第二介质层进行刻蚀，并去除掩膜层，形成第一凹槽，可以包括：根据掩膜层，采用干法刻蚀工艺对第二介质层进行刻蚀，得到刻蚀后的第二介质层。采用去胶剂去除刻蚀后的第二介质层表面的掩膜层，形成第一凹槽。也就是说，以光刻胶作为掩膜层，采用干法刻蚀工艺对第二介质层进行刻蚀。可以看出，本申请通过干法刻蚀工艺刻蚀第二介质层，以形成第一凹槽。
需要说明的是，第一凹槽的深度为第二介质层的刻蚀深度，不包括刻蚀后的第二介质层表面的掩膜层的厚度。
本申请通过干法刻蚀工艺刻蚀第二介质层，能够精确控制第一凹槽的深度，进而提高半导体器件的均匀性和良品率。
在一种可能的实现方式中，可以选择氟基气体或氯基气体，采用干法刻蚀工艺对第二介质层进行刻蚀。
其中，氟基气体可以为含有氟元素、碳元素、硫元素等的气体，如六氟化硫、四氟化碳、三氟甲烷、六氟乙烷、全氟丙烷等。氯基气体可以为含有氯元素的气体，如四氯化碳、氯气、氯化硼等。
进一步地，干法刻蚀工艺可以为反应离子刻蚀(reaction ion etch，RIE)工艺(简称为RIE工艺)、电感耦合等离子体(inductively coupling plasma，ICP)刻蚀工艺(简称为ICP工艺)、先进氧化物刻蚀(advanced oxide etch，AOE)工艺(简称为AOE工艺)等中的任意一项。当然，还可以采用其他干法刻蚀工艺刻蚀第二介质层，本申请不做限定。
在一种可能的实现方式中，采用去胶剂去除刻蚀后的第二介质层表面的掩膜层，可以采用不同的去胶剂对刻蚀后的第二介质层表面的掩膜层进行清洗，以形成第一凹槽。
进一步地，去胶剂可以包括丙酮、异丙醇、无水乙醇、N-甲基吡咯烷酮中的任意一种。去胶剂还可以包括丙酮、异丙醇、无水乙醇、N-甲基吡咯烷酮中至少两种的组合。
可以看出，去除刻蚀后的第二介质层表面的掩膜层能够避免对第一介质层的腐蚀速率和腐蚀深度的影响，提高了制备方法的可靠性。
在一种可能的实现方式中，根据第一凹槽，对第一介质层进行腐蚀，形成第二凹槽，可以包括：根据第一凹槽，采用湿法腐蚀工艺对第一介质层进行腐蚀，形成第二凹槽。
也就是说，在第一凹槽的基础上，对第一凹槽底部的第一介质层进行腐蚀，得到第二凹槽。
可以想到的是，第一凹槽的深度可以为第二介质层的刻蚀深度，第二凹槽的深度可以为第二介质层的刻蚀深度和第一介质层的腐蚀深度之和，因此，第二凹槽的深度可以大于第一凹槽的深度。
进一步地，可以根据第一凹槽，按照预设腐蚀时间，采用腐蚀溶液对第一介质层进行腐蚀，形成第二凹槽。也就是说，本申请可以通过湿法腐蚀工艺腐蚀第一介质层，以形成第二凹槽。
在一示例中，腐蚀溶液包括硫酸与过氧化氢按照预设配比配置的溶液、四甲基氢氧化铵溶液和氢氧化钾溶液中的任意一种。当然，腐蚀溶液还可以为其他可以腐蚀第一介质层的溶液，本申请不做限定。
在另一示例中，预设腐蚀时间可以为1min～20min。当然，预设腐蚀时间还可以为其他时间范围，本申请不做限定。
本申请通过湿法腐蚀工艺腐蚀第一介质层，避免对第二凹槽的界面造成损伤，进而减小栅极的界面态(是指在栅极与外延层接触的界面处，能值位于禁带中的一些分立或连续的电子能态或能带)，避免栅极漏电，提高半导体器件的可靠性。
在一种可能的实现方式中，第一材料可以为氧化铝或者氮化铝。第二材料可以为氧化硅、氮化硅或氮氧化硅。当然，第一材料还可以为含有铝元素的其他材料，第二材料还可以为含有硅元素的其他材料，本申请不做限定。
在另一种可能的实现方式中，在第一材料含有铝元素的基础上，第二介质层可以不含有铝元素。也就是说，第一介质层可以含有铝元素，第二介质层可以含有硅元素，但第二介质层可以不含有铝元素。
在又一种可能的实现方式中，第一介质层的厚度可以为5nm～30nm。第二介质层的厚度可以为100nm～300nm。当然，第一介质层和第二介质层分别还可以为其他厚度范围，本申请不做限定。
综上所述，本申请提供的半导体器件的制备方法将干法刻蚀工艺和湿法腐蚀工艺结合，并通过干法刻蚀工艺形成第一凹槽，通过湿法腐蚀工艺形成用于淀积栅极的第二凹槽。不仅能够精确控制第一凹槽的深度，提高半导体器件的均匀性和良品率，而且能够避免对第二凹槽的界面造成损伤，减小栅极的界面态，避免栅极漏电，提高半导体器件的可靠性。
第五方面，本申请提供了一种半导体器件的制备方法。其中，半导体器件可以包括依次层叠设置的衬底、外延层、第一介质层和第二介质层。制备方法可以包括：在衬底的表面形成外延层。采用第一材料在外延层的表面形成第一介质层。采用第二材料在第一介质层的表面形成第二介质层。
其中，第一介质层可以包含第一材料，第二介质层可以包含第二材料。
进一步地，第一材料含有的元素和第二材料含有的元素可以不完全相同。也就是说，第一材料含有的元素和第二材料含有的元素可以部分相同，或者完全不同。
更进一步地，第一材料可以含有铝元素，第二材料可以含有硅元素。
在一种可能的实现方式中，第一材料可以为氧化铝或者氮化铝。第二材料可以为氧化硅、氮化硅或氮氧化硅。当然，第一材料还可以为含有铝元素的其他材料，第二材料还可以为含有硅元素的其他材料，本申请不做限定。
在另一种可能的实现方式中，在第一材料含有铝元素的基础上，第二介质层可以不含有铝元素。也就是说，第一介质层可以含有铝元素，第二介质层可以含有硅元素，但第二介质层可以不含有铝元素。
在又一种可能的实现方式中，第一介质层的厚度可以为5nm～30nm。第二介质层的厚度可以为100nm～300nm。当然，第一介质层和第二介质层分别还可以为其他厚度范围，本申请不做限定。
应当理解的是，本申请的第二方面至第五方面与本申请的第一方面的技术方案一致，各方面及对应的可行实施方式所取得的有益效果相似，不再赘述。
附图说明
为了更清楚地说明本申请或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中半导体器件1的一种示意性结构图；
图2为本申请实施例中半导体器件1的一种示意性结构图；
图3为本申请实施例中过程100的一种示意性流程图；
图4为本申请实施例中形成掩膜层50的一种示意性结构图；
图5为本申请实施例中形成凹槽401的一种示意性结构图；
图6为本申请实施例中过程200的一种示意性流程图；
图7为本申请实施例中过程300的一种示意性流程图；
图8为本申请实施例中过程400的一种示意性流程图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
随着科技的发展，包括半导体器件(如场效应晶体管等)的电子芯片在手机、平板电脑等电子设备中得到了广泛的应用。半导体器件可以包括层叠设置的衬底、外延层和介质层等。其中，衬底可以含有硅Si(silicon)、砷As(arsenic)、碳C(carbon)等元素，外延层可以含有镓Ga(gallium)、氮N(nitride)、铝Al(aluminum)等元素，介质层可以含有硅、氧O(oxide)、氮等元素。由于介质层包含的材料决定了介质层的绝缘性，进而影响半导体器件的静态功耗。
为了降低半导体器件的静态功耗，本申请实施例提供了一种半导体器件，如图1所示。半导体器件1可以包括衬底10、外延层20、介质层30(即第一介质层)和介质层40(即第二介质层)。其中，衬底10、外延层20、介质层30和介质层40可以依次层叠设置。
其中，介质层30可以包含材料A(即第一材料)，介质层40可以包含材料B(即第二材料)。
进一步地，材料A含有的元素和材料B含有的元素可以不完全相同。也就是说，材料A含有的元素和材料B含有的元素可以部分相同，或者完全不同。
更进一步地，材料A可以含有铝元素，材料B可以含有硅元素。
本申请提供的半导体器件1中，介质层30包含的材料A含有的元素和介质层40包含的材料B含有的元素不完全相同。介质层30包含含有铝元素的材料A，能够增大介质层30的相对介电常数，进而提高了介质层30的绝缘性，减小了半导体器件1的静态电流，降低半导体器件1的静态功耗。介质层40包含含有硅元素的材料B。
在一示例中，如图1所示，介质层30和介质层40可以设置凹槽301(即第二凹槽)，凹槽301的深度可以为介质层30的厚度(即下文介质层30的刻蚀深度)与介质层40的厚度(即下文介质层40的腐蚀深度)之和，凹槽301用于形成半导体器件1的栅极，可 以参考下文介绍。
在另一示例中，外延层20包含的材料含有的元素与衬底10包含的材料含有的元素可以不完全相同。也就是说，外延层20包含的材料含有的元素与衬底10包含的材料含有的元素可以部分不同，也可以完全不同。于是，外延层20可以叫作异质外延。
进一步地，外延层20可以包括依次层叠设置的缓冲层201、沟道层202、插入层203、势垒层204和盖帽层205。其中，缓冲层201与衬底10接触，盖帽层205与介质层30接触。
更进一步地，衬底10可以包含硅、碳化硅SiC(silicon carbide)、蓝宝石(sapphire)等。缓冲层201可以包含氮化镓GaN(gallium nitride)或氮化铝AlN(aluminum nitride)等材料。沟道层202可以包含氮化镓GaN等材料。插入层203可以包含氮化铝AlN等材料。势垒层204可以包含氮化铝镓AlGaN(aluminum gallium nitride)、氮化铟铝InAlN(indium aluminum nitride)等材料。盖帽层205可以包含氮化镓GaN等材料。当然，缓冲层201、沟道层202、插入层203、势垒层204和盖帽层205还可以分别包含其他材料，本申请实施例不做限定。
本申请实施例中，衬底10可以包含硅Si，缓冲层201、沟道层202和盖帽层205可以包括氮化镓GaN，插入层203可以包含氮化铝AlN，势垒层204可以包含氮化铝镓AlGaN。因此，外延层20包含的材料含有的元素与衬底10包含的材料含有的元素完全不同，本申请实施例中的外延层20为异质外延。
在一种可能的实现方式中，半导体器件1还可以包括栅介质层60、源极90、栅极70和漏极80，如图2所示。
其中，栅介质层60可以层叠设置于介质层40的表面以及凹槽301的内部，栅极70可以设置于栅介质层60的表面。源极90和漏极80也可以设置于栅介质层60的表面，源极90可以穿过介质层30和介质层40与盖帽层205接触，类似的，漏极80也可以穿过介质层30和介质层40与盖帽层205接触。于是，源极90与盖帽层205之间可以形成欧姆接触，漏极80与盖帽层205之间也可以形成欧姆接触。
在另一种可能的实现方式中，材料A可以为氧化铝或者氮化铝。材料B可以为氧化硅、氮化硅或氮氧化硅。当然，材料A还可以为含有铝元素的其他材料，材料B还可以为含有硅元素的其他材料，本申请不做限定。
在又一种可能的实现方式中，在材料A含有铝元素的基础上，介质层40可以不含有铝元素。也就是说，介质层30可以含有铝元素，介质层40可以含有硅元素，但介质层40可以不含有铝元素。
本申请实施例中，介质层30可以包含三氧化二铝Al2O3(aluminium oxide)，介质层40可以包含二氧化硅SiO2。
在又一种可能的实现方式中，介质层30的厚度可以为5nm～30nm。介质层40的厚度可以为100nm～300nm。当然，介质层30和介质层40分别还可以为其他厚度范围，本申请不做限定。
本申请实施例中，介质层30的厚度可以为25nm，介质层40的厚度可以为200nm。
本申请实施例提供的半导体器件1可以为场效应晶体管，进一步可以为高电子迁移率晶体管(high electron mobility transistor，HEMT)、异质结场效应晶体管(heterojunction field effect transistor，HFET)或者调制掺杂场效应管(modulation-doped FET，MODFET)，本 申请实施例是以HEMT为例进行说明的。
本申请实施例还提供了一种电子芯片，可以包括无源器件和半导体器件1。其中，无源器件可以与半导体器件1电连接。
在一种可能的实现方式中，无源器件可以包括电阻、电容等，本申请实施例对无源器件不做限定。
本申请实施例还提供了一种电子设备，可以包括电路板和上述电子芯片。其中，电子芯片可以设置在电路板。
本申请实施例提供了一种半导体器件的制备方法，半导体器件的相关介绍可以参考上文，本申请实施例不再赘述。
如图3所示，过程100可以按照以下步骤实现。
步骤S101：对介质层40进行光刻，形成掩膜层50，如图4所示。
步骤S102：根据掩膜层50，对介质层40进行刻蚀，并去除掩膜层50，形成凹槽401，如图5所示。从图5可以看出，凹槽401的深度可以为介质层40的刻蚀深度，不包括刻蚀后的介质层40表面的掩膜层50的厚度，也就是不包括图4中掩膜层50的厚度。
步骤S103：根据凹槽401，对介质层30进行腐蚀，形成凹槽301，如图1所示。
在一种可能的实现方式中，如图6所示的过程200，上述步骤S101可以按照如下步骤实现：
步骤S101a：在介质层40表面涂光刻胶，并按照预设烘烤温度和预设烘烤时间对涂有光刻胶的介质层40进行烘烤。
在一示例中，光刻胶可以为正胶或者负胶。其中，对于正胶，曝光区域的光刻胶可以溶解，也就是说正胶在曝光区域显影。对于负胶，非曝光区域的光刻胶可以溶解，也就是说负胶在非曝光区域显影。本申请实施例中，在介质层40表面涂正胶。
在另一示例中，预设烘烤温度可以为90℃～120℃，预设烘烤时间可以为3min～5min。当然，预设烘烤温度还可以为其他温度范围，预设烘烤时间还可以为其他时间范围，本申请不做限定。本申请实施例中，预设烘烤温度可以为100℃，预设烘烤时间可以为4min。
步骤S101b：按照预设曝光时间，对烘烤后的介质层40进行曝光。
示例性的，预设曝光时间可以为100ms～300ms，当然，预设曝光时间还可以为其他时间范围，本申请不做限定。本申请实施例中，预设曝光时间可以为110ms。
步骤S101c：采用显影液，并按照预设显影时间对曝光后的介质层40进行显影，形成掩膜层50，如图4所示。
在一示例中，预设显影时间可以为40s～70s。当然，预设显影时间还可以为其他时间范围，本申请不做限定。本申请实施例中，预设显影时间可以为50s。
在另一示例中，显影液可以为四甲基氢氧化铵C4H13NO(tetramethylammonium hydroxide)。当然，显影液还可以为其他类型，本申请不做限定。
以上介绍了形成掩膜层50的相关过程，当然，还可以采用其他方式形成掩膜层50，本申请实施例不做限定。
干法刻蚀工艺通常使用反应气体(如反应离子(reactive ion，RI)、电感耦合等离子体(inductively coupled plasma，ICP)或离子束(ion beam，IB))再附以射频电压，即可生成离子和电子。离子和电子对介质层的表面可以进行物理轰击，反应气体和介质层之间进行化学反应，即可实现对介质层的刻蚀。
于是，在上述步骤S102中，可以以光刻胶作为掩膜层50，采用干法刻蚀工艺对介质层40进行刻蚀。
在一种实现方式中，如图7所示的过程300，上述步骤S102可以按照如下步骤实现：
步骤S102a：根据掩膜层50，采用干法刻蚀工艺对介质层40进行刻蚀，得到刻蚀后的介质层40。
步骤S102b：采用去胶剂去除刻蚀后的介质层40表面的掩膜层50，形成凹槽401，如图5所示。在一示例中，上述步骤S102a中，可以选择氟基气体或氯基气体，按照预设的刻蚀时间，采用干法刻蚀工艺对介质层40进行刻蚀。
在一示例中，氟基气体可以为含有氟元素、碳元素、硫元素等的气体，如六氟化硫、四氟化碳、三氟甲烷、六氟乙烷、全氟丙烷等。氯基气体可以为含有氯元素的气体，如四氯化碳、氯气、氯化硼等。
在另一示例中，刻蚀时间可以为介质层40的厚度与刻蚀速率之比。
在又一示例中，干法刻蚀工艺可以为反应离子刻蚀(reaction ion etch，RIE)工艺(简称为RIE工艺)、电感耦合等离子体(inductively coupling plasma，ICP)刻蚀工艺(简称为ICP工艺)、先进氧化物刻蚀(advanced oxide etch，AOE)工艺(简称为AOE工艺)等中的任意一项。当然，还可以采用其他干法刻蚀工艺刻蚀介质层40，本申请不做限定。
本申请实施例中，选择四氟化碳，采用AOE工艺对介质层40进行刻蚀，刻蚀时间为1min，介质层40的刻蚀深度为210nm。可以理解为，凹槽401的深度为210nm。
在另一示例中，上述步骤S102b中，可以采用不同的去胶剂对刻蚀后的介质层40表面的掩膜层50进行清洗，以形成凹槽401。
进一步地，去胶剂可以包括丙酮CH3COCH3(acetone)、异丙醇C3H8O(isopropyl alcohol，IPA)、无水乙醇C2H6O(ethanol absolute)、N-甲基吡咯烷酮C5H9NO(N-methylpyrrolidone)中的任意一种。去胶剂还可以包括丙酮、异丙醇、无水乙醇、N-甲基吡咯烷酮中至少两种的组合。本申请实施例中，采用丙酮和异丙醇对刻蚀后的介质层40表面的掩膜层50进行清洗。
可以看出，去除刻蚀后的介质层40表面的掩膜层50能够避免对介质层30的腐蚀速率和腐蚀深度的影响，提高了制备方法的可靠性。
以上介绍了形成凹槽401的相关过程，当然，还可以采用其他方式形成凹槽401，本申请实施例不做限定。
本申请实施例通过干法刻蚀工艺刻蚀介质层40，能够精确控制凹槽401的深度，进而提高半导体器件1的均匀性和良品率。
湿法腐蚀工艺是一种利用腐蚀溶液对介质层进行腐蚀的工艺。本申请实施例的上述步骤S103中，可以根据凹槽401，按照预设腐蚀时间，采用腐蚀溶液对介质层30进行腐蚀，形成凹槽301。也就是说，本申请实施例通过湿法腐蚀工艺形成凹槽301，如图1所示。
在一示例中，腐蚀溶液可以包括硫酸H2SO4(sulfuric acid)与过氧化氢H2O2(hydrogen peroxide)按照预设配比配置的溶液、四甲基氢氧化铵C4H13NO(tetramethylammonium hydroxide，TMAH)溶液和氢氧化钾KOH(potassium hydroxide)溶液中的任意一种。当然，腐蚀溶液还可以为其他可以腐蚀介质层30的溶液，本申请实施例不做限定。本申请实施例中，腐蚀溶液为质量分数大于或等于70％的硫酸(即浓硫酸)与过氧化氢按照预设配比配置的溶液，其中，预设配比为浓硫酸与过氧化氢的体积比，可以为7:3。
在另一示例中，预设腐蚀时间可以为1min～20min。当然，预设腐蚀时间还可以为其他时间范围，本申请不做限定。本申请实施例中，预设腐蚀时间可以为5min。
以上介绍了形成凹槽301的相关过程，当然，还可以采用其他方式形成凹槽301，本申请实施例不做限定。
本申请通过湿法腐蚀工艺腐蚀介质层30，避免对凹槽301的界面造成损伤，进而减小栅极的界面态(是指在栅极与外延层接触的界面处，能值位于禁带中的一些分立或连续的电子能态或能带)，避免栅极漏电，提高半导体器件的可靠性。
综上所述，本申请实施例提供的半导体器件的制备方法将干法刻蚀工艺和湿法腐蚀工艺结合，并通过干法刻蚀工艺形成凹槽401，通过湿法腐蚀工艺形成用于淀积栅极的凹槽301。不仅能够精确控制凹槽401的深度，进而提高半导体器件的均匀性和良品率，而且能够避免对凹槽301的界面造成损伤，减小栅极的界面态，避免栅极漏电，进而提高半导体器件的可靠性。
在一种可能的实现方式中，如图8所示的过程400，本申请实施例提供的制备方法在执行上述过程100之前，还可以按照以下步骤形成介质层30和介质层40：
步骤S401a：在衬底10的表面形成外延层20。
步骤S401b：采用材料A在外延层20的表面形成介质层30。
步骤S401c：采用材料B在介质层30的表面形成介质层40。
示例性的，步骤S401b中，可以利用沉积工艺在外延层20的表面形成介质层30。其中，沉积工艺可以包括原子层沉积(atomic layer deposition，ALD)工艺(简称为ALD工艺)、等离子体增强原子层沉积(plasma enhanced atomic layer deposition，PEALD)工艺(简称为PEALD工艺)、等离子体增强化学气相沉积(plasma enhanced chemical vapor，PECVD)工艺(简称为PECVD工艺)、电感耦合等离子体化学气相沉积(inductively coupled plasma chemical vapor deposition，ICPCVD)工艺(简称为ICPCVD工艺)、低压化学气相沉积(low pressure chemical vapor deposition，LPCVD)工艺(简称为LPCVD工艺)、电子束蒸发(electronic beam evaporation，EBE)工艺(简称为EBE工艺)或溅射沉积工艺等。
本申请实施例中，利用PEALD工艺在外延层20的表面形成介质层30，介质层30可以包含三氧化二铝，介质层30的厚度可以为25nm。
示例性的，步骤S401c中，可以利用上述沉积工艺在介质层30的表面形成介质层40。
本申请实施例中，利用PEALD工艺在介质层30的表面形成介质层40，介质层40可以包含二氧化硅，介质层40的厚度可以为200nm。
需要说明的是，以上介绍了形成介质层30和介质层40的相关过程，当然，还可以采用其他方式形成介质层30和介质层40，本申请实施例不做限定。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (21)

  1. 一种半导体器件，其特征在于，包括依次层叠设置的衬底、外延层、第一介质层和第二介质层；
    所述第一介质层包含第一材料，所述第二介质层包含第二材料；
    所述第一材料含有的元素和所述第二材料含有的元素不完全相同，所述第一材料含有铝元素，所述第二材料含有硅元素。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述第一材料为氧化铝或者氮化铝；
    所述第二材料为氧化硅、氮化硅或氮氧化硅。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述第二材料不含有铝元素。
  4. 根据权利要求1至3中任一项所述的半导体器件，其特征在于，所述第一介质层的厚度为5nm～30nm；
    所述第二介质层的厚度为100nm～300nm。
  5. 根据权利要求1至4中任一项所述的半导体器件，其特征在于，所述外延层包含的材料含有的元素与所述衬底包含的材料含有的元素不完全相同。
  6. 一种半导体器件的制备方法，所述半导体器件包括依次层叠设置的衬底、外延层、第一介质层和第二介质层，其特征在于，所述制备方法包括：
    对第二介质层进行光刻，形成掩膜层；
    根据所述掩膜层，对所述第二介质层进行刻蚀，并去除所述掩膜层，形成第一凹槽；
    根据所述第一凹槽，对所述第一介质层进行腐蚀，形成第二凹槽；
    所述第一介质层采用第一材料，所述第二介质层采用第二材料；
    所述第一材料含有的元素和所述第二材料含有的元素不完全相同，所述第一材料含有铝元素，所述第二材料含有硅元素。
  7. 根据权利要求6所述的制备方法，其特征在于，所述对第二介质层进行光刻，形成掩膜层，包括：
    在所述第二介质层表面涂光刻胶，并按照预设烘烤温度和预设烘烤时间对涂有光刻胶的所述第二介质层进行烘烤；
    按照预设曝光时间，对烘烤后的所述第二介质层进行曝光；
    采用显影液，并按照预设显影时间对曝光后的所述第二介质层进行显影，形成所述掩膜层。
  8. 根据权利要求7所述的制备方法，其特征在于，所述根据所述掩膜层，对所述第二介质层进行刻蚀，并去除所述掩膜层，形成第一凹槽，包括：
    根据所述掩膜层，采用干法刻蚀工艺对所述第二介质层进行刻蚀，得到刻蚀后的所述第二介质层；
    采用去胶剂去除刻蚀后的所述第二介质层表面的所述掩膜层，形成所述第一凹槽。
  9. 根据权利要求7所述的制备方法，其特征在于，所述干法刻蚀工艺包括反应离子刻蚀工艺、电感耦合等离子体刻蚀工艺、先进氧化物刻蚀工艺中的任意一项；
    所述去胶剂包括丙酮、异丙醇、无水乙醇、N-甲基吡咯烷酮中的任意一种或多种。
  10. 根据权利要求6至9中任一项所述的制备方法，其特征在于，所述根据所述第一 凹槽，对所述第一介质层进行腐蚀，形成第二凹槽，包括：
    根据所述第一凹槽，采用湿法腐蚀工艺对所述第一介质层进行腐蚀，形成所述第二凹槽；所述第二凹槽的深度大于所述第一凹槽的深度。
  11. 根据权利要求10所述的制备方法，其特征在于，所述根据所述第一凹槽，采用湿法腐蚀工艺对所述第一介质层进行腐蚀，形成所述第二凹槽，包括：
    根据所述第一凹槽，按照预设腐蚀时间，采用腐蚀溶液对所述第一介质层进行腐蚀，形成所述第二凹槽。
  12. 根据权利要求11所述的制备方法，其特征在于，所述腐蚀溶液包括硫酸与过氧化氢按照预设配比配置的溶液、四甲基氢氧化铵溶液和氢氧化钾溶液中的任意一种。
  13. 根据权利要求6至12中任一项所述的制备方法，其特征在于，所述第一材料为氧化铝或氮化铝；
    所述第二材料为氧化硅、氮化硅或氮氧化硅。
  14. 根据权利要求6至13中任一项所述的制备方法，其特征在于，所述第二材料不含有铝元素。
  15. 根据权利要求6至14中任一项所述的制备方法，其特征在于，所述第一介质层的厚度为5nm～30nm；
    所述第二介质层的厚度为100nm～300nm。
  16. 一种半导体器件的制备方法，所述半导体器件包括依次层叠设置的衬底、外延层、第一介质层和第二介质层，其特征在于，所述制备方法包括：
    在衬底的表面形成外延层；
    采用第一材料在所述外延层的表面形成第一介质层；
    采用第二材料在所述第一介质层的表面形成第二介质层；
    其中，所述第一材料含有的元素和所述第二材料含有的元素不完全相同，所述第一材料含有铝元素，所述第二材料含有硅元素。
  17. 根据权利要求16所述的制备方法，其特征在于，所述第一材料为氧化铝或者氮化铝；
    所述第二材料为氧化硅、氮化硅或氮氧化硅。
  18. 根据权利要求16或17所述的制备方法，其特征在于，所述第二材料不含有铝元素。
  19. 根据权利要求16至18中任一项所述的制备方法，其特征在于，所述第一介质层的厚度为5nm～30nm；
    所述第二介质层的厚度为100nm～300nm。
  20. 一种电子芯片，其特征在于，包括无源器件和与所述无源器件电连接的如权利要求1至5中任一项所述的半导体器件。
  21. 一种电子设备，其特征在于，包括电路板和设置在所述电路板上的如权利要求20所述的电子芯片。
PCT/CN2023/097066 2022-06-07 2023-05-30 半导体器件及其制备方法 WO2023236811A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009035A (zh) * 2013-02-26 2014-08-27 飞思卡尔半导体公司 Mishfet及肖特基器件集成
US20170117401A1 (en) * 2015-10-23 2017-04-27 The Board Of Trustees Of The University Of Illinois Mishfet having a comparatively high and selectable or customizable breakdown voltage
CN208368513U (zh) * 2018-07-17 2019-01-11 中山市华南理工大学现代产业技术研究院 基于金属氧化物/二氧化硅叠栅的GaN基MOS-HEMT器件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104009035A (zh) * 2013-02-26 2014-08-27 飞思卡尔半导体公司 Mishfet及肖特基器件集成
US20170117401A1 (en) * 2015-10-23 2017-04-27 The Board Of Trustees Of The University Of Illinois Mishfet having a comparatively high and selectable or customizable breakdown voltage
CN208368513U (zh) * 2018-07-17 2019-01-11 中山市华南理工大学现代产业技术研究院 基于金属氧化物/二氧化硅叠栅的GaN基MOS-HEMT器件

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