WO2023231756A1 - Puce empilée tridimensionnelle et procédé de traitement de données associé - Google Patents

Puce empilée tridimensionnelle et procédé de traitement de données associé Download PDF

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Publication number
WO2023231756A1
WO2023231756A1 PCT/CN2023/094307 CN2023094307W WO2023231756A1 WO 2023231756 A1 WO2023231756 A1 WO 2023231756A1 CN 2023094307 W CN2023094307 W CN 2023094307W WO 2023231756 A1 WO2023231756 A1 WO 2023231756A1
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storage
module
control
data
modules
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PCT/CN2023/094307
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English (en)
Chinese (zh)
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李乾男
王棋
薛小飞
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西安紫光国芯半导体股份有限公司
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Publication of WO2023231756A1 publication Critical patent/WO2023231756A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular to a three-dimensional stacked chip and a data processing method thereof.
  • the traditional Dynamic Random Access Memory (DRAM) interface consists of address bits, data bits and command bits.
  • the command bits and address bits are first received and decoded to generate a storage array module (bank). Control signals and address information, then receive the data for serial-to-parallel conversion and then send it to the bank.
  • the command bit and address bit are first received, decoded to generate the bank's control signal and address information, and then the bank outputs the data, which is output through parallel-to-serial conversion.
  • traditional DRAM can only perform read and write operations on one bank at a time, that is, all banks operate in a time-sharing manner, and the bandwidth is greatly limited.
  • embodiments of the present application provide a three-dimensional stacked chip and a data processing method thereof, which can increase the bandwidth of the DARM, thus helping to increase the data processing speed of the chip.
  • embodiments of the present application provide a three-dimensional stacked chip, including: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer.
  • the storage wafer layer includes M storage array modules.
  • N storage control modules are correspondingly provided in the logic wafer layer, each of the storage control modules is connected to k storage array modules through a wafer-level interlayer connection structure, and is used to control the respective connected storage array modules.
  • the storage array module performs data writing or reading operations, where M and N are both integers greater than or equal to 2, and N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M.
  • each of the storage control modules is directly connected to the data and control bus of one of the storage array modules through the wafer-level interlayer connection structure, and the data and control buses of different storage array modules are independent of each other.
  • the storage wafer layer also includes: a control set in one-to-one correspondence with the storage control module.
  • Logic module the storage control module is connected to the control logic module through a wafer-level interlayer connection structure, and the control logic module is directly connected to the data and control buses of k storage array modules respectively.
  • the control logic module The module is used to: time-share control of k storage array modules to perform data writing or reading operations according to the data writing or reading signals sent by the storage control module.
  • the data writing or reading signal includes chip selection control information and writing or reading information
  • the control logic module is specifically configured to: select data from k memory array modules according to the chip selection control information. Determine the storage array module to be written or read, and perform operations on the storage array module based on the write or read information. Row data writing or reading operations.
  • control logic module is specifically configured to: determine the storage array module to be written or read from the k storage array modules according to the address space corresponding to the data writing or reading signal, and according to The data write or read signal performs a data write or read operation on the storage array module.
  • the storage wafer layer includes k storage wafers arranged in a stack, and k storage array modules connected to one storage control module are respectively distributed in There are k memory wafers, and a chip select channel is provided between the memory control module and the k memory array modules for selecting one of the memory array modules to perform the data writing or reading operation.
  • the logic wafer layer is also provided with a processing module, and each of the storage control modules is connected to the processing module.
  • the processing module is used to determine the storage array module to be operated, and to connect the storage array module to be operated.
  • the storage control module of the storage array module sends data operation information; each storage control module is provided with a decoding and analysis module, and the decoding and analysis module decodes and analyzes the commands and addresses in the data operation information, to perform data writing or reading operations on the storage array module to be operated.
  • the processing module receives the data write command and the write data, and determines the write address of the write data according to the occupied space of the write data and the storage space of the storage array module to determine the The storage array module is to be operated.
  • the processing module stores the written data in the first storage array module and the second storage array module, the The first storage array module and the second storage array module are controlled by different storage control modules; or the first storage array module and the second storage array module are located on different storage wafer layers, and are controlled by different storage control modules. Control module control.
  • the inter-layer connection structure includes a data channel and a control channel, the data channel is used to transmit data signals for writing or reading, and the control channel is used for transmitting control signals for controlling data writing or reading.
  • control signal includes a command signal and an address signal; wherein the command signal includes a row operation enable signal, a column operation enable signal and a write data control signal; the address signal includes a row address signal and a column address. Signal.
  • embodiments of the present application also provide a data processing method for a three-dimensional stacked chip.
  • the three-dimensional stacked chip includes: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer.
  • the storage wafer layer includes M storage array modules, and N storage control modules are correspondingly provided in the logic wafer layer.
  • Each of the storage control modules is connected to k storage array modules through a wafer-level interlayer connection structure. connection, used to control the respective connected storage array modules to perform data writing or reading operations, where M and N are both integers greater than or equal to 2, and N is less than or equal to M, and k is greater than or equal to 1 and An integer less than M.
  • the method includes: receiving a storage control signal; based on the storage control signal, using multiple storage control modules to perform data writing or reading operations in parallel on the storage array module connected to the storage control module.
  • each storage control module is connected to k storage array modules through the wafer-level interlayer connection structure
  • the blocks are directly connected, and k is an integer greater than or equal to 1 and less than M, so that different storage control modules control the respective connected storage array modules to perform data writing or reading operations.
  • the DRAM interface bit width is no longer limited by packaging and hardware systems, and the DRAM storage array interface signal can be output directly to realize parallel read and write access to multiple storage array modules in the storage wafer layer, effectively improving the performance of DRAM. Data access bandwidth, thereby helping to improve the data processing speed of the chip.
  • Figure 1 shows an exemplary conventional DRAM block diagram
  • Figure 2 shows a schematic diagram 1 of the packaging of a three-dimensional stacked chip in the embodiment of this specification
  • Figure 3 shows a schematic diagram 1 of a two-layer structure chip in the embodiment of this specification
  • Figure 4 shows a schematic diagram of data writing in the embodiment of this specification
  • Figure 5 shows a schematic diagram of a three-layer structure chip in an embodiment of this specification
  • Figure 6 shows a schematic diagram 2 of a two-layer structure chip in the embodiment of this specification
  • Figure 7 shows a flow chart of a data processing method for three-dimensional stacked chips in an embodiment of this specification
  • Figure 8 shows the second package schematic diagram of the three-dimensional stacked chip in the embodiment of this specification
  • Figure 9 shows an exemplary timing relationship diagram of the address signal and the address enable signal
  • Figure 10 shows a circuit diagram of the first timing control circuit in the embodiment of this specification
  • Figure 11 shows an exemplary transmission timing diagram of the address enable signal and the address signal in the embodiment of this specification
  • Figure 12 shows a flow chart of the timing control method in the embodiment of this specification.
  • Figure 1 shows a traditional DRAM block diagram with an 8-bit data interface and 8x internal prefetching.
  • the entire DRAM has a total of 8 storage array modules (banks), namely bank0 ⁇ bank7.
  • the address and control lines of bank0 ⁇ bank7 are all connected to the same decoding and address analysis module set in the DRAM, and the data lines are all connected to the same decoding and address analysis module set in the DRAM.
  • the same parallel-to-serial conversion module is connected.
  • rwd0 to rwd7 represent the data of bank0 to bank7, and are illustrated as 64 bits in the figure. Taking the write operation as an example, the decoding and address parsing module first receives the command and address information sent from the outside.
  • the address information includes the bank address information.
  • the parallel-to-serial conversion module receives the data signal dqs/dq ⁇ 7:0> to be written, performs serial-to-parallel conversion, converts it into a 64-bit data signal rwd ⁇ 63:0>, and then sends it to the The bank completes data writing. In other words, only one bank can be read and written at a time.
  • the DRAM interface data bit width cannot be very large, which results in the internal storage array interface bit width being much larger than the DRAM interface bit width. Therefore, the interface speed after parallel-to-serial conversion is much higher than the internal Storage array storage rate, for example, for the 8x prefetch structure in the above example, if the external interface data bit width is 8 bits, then the internal storage array bit width is 64 bits, and if the storage array speed is 200Mbps, the interface rate needs to reach 1600Mbps. Therefore, it is not conducive to improving the data access bandwidth of DRAM.
  • embodiments of this specification provide a three-dimensional stacked chip that abandons the decoding and address resolution modules and serial-to-parallel conversion modules in traditional DRAM.
  • the chip package is Previously, each storage control module was directly connected to k storage array modules through a wafer-level interlayer connection structure, where k was an integer greater than or equal to 1 and less than M, thereby controlling the respective connected storage array modules through different storage control modules.
  • the embodiment of this specification provides a three-dimensional stacked chip 100, which may be, for example, a SOC chip (System on Chip).
  • the three-dimensional stacked chip 100 may include: a storage wafer layer 102 and a logic wafer layer 101 stacked with the storage wafer layer 102 .
  • the number of layers of memory wafers and logic wafers in the three-dimensional stacked chip 100 shown in the drawings provided in this embodiment is only for illustration and is not limiting. During specific implementation, it can be set according to actual needs.
  • the storage wafer layer 102 includes one or more stacked storage wafers for expanding storage space.
  • M memory array modules 121 are distributed in the memory wafer layer 102, where M is an integer greater than or equal to 2.
  • the specific number of layers of the storage wafer and the number of storage array modules 121 are set according to the requirements for chip storage capacity in actual application scenarios.
  • each memory wafer may include 4, 8, or 16 memory array modules 121.
  • N storage control modules 111 are provided in the logic wafer layer 101. N is also an integer greater than or equal to 2, and N is less than or equal to M. Each storage control module 111 is connected to k storage array modules 121 through the wafer-level interlayer connection structure 103, and is used to control the respective connected storage array modules 121 to perform data writing or reading operations. Where, k is an integer greater than or equal to 1 and less than M. Each storage array module 121 is connected to a storage control module 111 , and different storage control modules 111 are connected to different storage array modules 121 .
  • one storage control module 111 can be connected to one storage array module 121, that is, the storage control module 111 and the storage array module 121 are connected in a one-to-one correspondence; in another embodiment, one storage control module 111 can be connected to one storage array module 121. Connect multiple storage array modules 121, for example, a storage control module 111 Two storage array modules 121 are connected, and another storage control module 111 is connected to three storage array modules 121 .
  • multiple storage control modules 111 can simultaneously control the corresponding connected storage array modules 121 to perform data reading and writing operations, so that the logic wafer can read and write in parallel one of the storage array modules connected to different storage control modules 111 121, that is, it can at least realize parallel read and write access to N storage array modules 121 in the storage wafer layer 102, without being restricted by packaging and hardware systems, effectively improving the data access bandwidth of DRAM, thereby conducive to improving the data of the chip. Processing speed.
  • the specific number of storage control modules 111 and the connected storage array modules 121 are determined according to the number of storage array modules 121 in the storage wafer layer 102 and the actual control logic.
  • k can be 1, and N equals M, that is, one storage control module 111 can correspondingly control one storage array module 121.
  • the logic wafer can read and write all the storage array modules 121 of the storage wafer in parallel, so the bandwidth can be greatly improved.
  • the M storage array modules 121 distributed in the storage wafer layer 102 can also be divided into multiple groups. At least one group includes multiple storage array modules 121.
  • One storage control module 111 correspondingly controls one group of storage array modules 121.
  • k is the number of storage array modules 121 in the corresponding group, and N is equal to the number of divided groups.
  • the memory wafer (DRAM die) and the logic wafer (logic die) can be connected through wafer-level interconnection methods such as hybrid bonding technology (Hyrid bonding), RDL (Redistribution Layer, rewiring layer) and TSV (Through Silicon Via) technology are connected and packaged together to form a three-dimensional stacked chip 100.
  • wafer-level interconnection methods such as hybrid bonding technology (Hyrid bonding), RDL (Redistribution Layer, rewiring layer) and TSV (Through Silicon Via) technology are connected and packaged together to form a three-dimensional stacked chip 100.
  • each storage control module 111 and the corresponding k storage array modules 121 can be achieved through the wafer-level interlayer connection structure 103 .
  • the DRAM interface bit width is no longer limited by packaging and hardware systems, and the interface signals of the storage array module 121 can be directly output.
  • the logic wafer can directly control multiple storage array modules 121 to read and write at the same time, effectively improving the data of DRAM. Access bandwidth.
  • the inter-layer connection structure 103 can be implemented using applicable wafer-level interconnection technology, which is determined based on the actual wiring requirements between the storage control module 111 and the storage array module 121, and is not limited here.
  • the interlayer connection structure 103 may include one or more combinations of a hybrid bonding structure, a wiring structure in an RDL layer, and a through silicon via structure.
  • the inter-layer connection structure 103 serves as a signal transmission channel between the storage control module 111 and the storage array module 121, and is used to transmit signals required for data writing or reading operations on the storage array module 121.
  • the inter-layer connection structure 103 may include data channels and control channels.
  • the data channel is used to transmit written or read data signals, and the bit width of the data channel can be determined based on the data bit width that the storage array module 121 can write or read at one time and the data bit width of the actual logic wafer. As shown in Figure 3, 64 bits are used as an example.
  • rwd0 ⁇ 63:0> ⁇ rwd7 ⁇ 63:0> represent the data signals of bank0 ⁇ bank7. During specific implementation, it can also be other widths such as 128 or 256.
  • the control channel is used to transmit control signals that control data writing or reading.
  • the control signals transmitted in the control channel may include command signals and address signals.
  • the command signal may include but is not limited to: a row operation enable signal, a column operation enable signal, and a write data control signal, and the details may be determined according to actual needs.
  • the row operation enable signal can also be called a bank row valid indication, which is used to indicate that the row address can be captured for decoding.
  • the column operation enable signal which can also be called the bank column write and read address control signal, is used to indicate that the column address can be captured for decoding.
  • the write data control signal is used to instruct data to be written in the corresponding column.
  • the address signals may include row address signals and column address signals.
  • the address bit width is determined according to the row and column structure of DRAM.
  • control and status signals in Figure 3 represent the control signals required for DRAM operation, such as powerdown control, bank_fail, etc.
  • the specific signal types and the structure of other control circuits can be referred to DRAM related technologies, and will not be described in detail here.
  • a processing module 110 may also be provided in the logic wafer layer 101.
  • Each storage control module 111 is connected to the processing module 110.
  • the processing module 110 is used to determine the storage array module to be operated. , that is, determine which storage array modules 121 in the storage wafer layer 102 are to perform data reading or writing operations, and send data operation information to the storage control module connected to the above-mentioned storage array module to be operated.
  • the data operation information may include commands and addresses, and if the data operation is a write operation, it may also include data information to be written.
  • Each storage control module 111 includes a decoding and analysis module. The decoding and analysis module decodes and analyzes the commands and addresses in the data operation information to perform data writing or reading operations on the storage array module to be operated.
  • the processing module 110 may receive a data write command and write data, and determine the write address of the write data based on the occupied space of the write data and the storage space of the storage array module 121, that is, determine the storage array module to be operated. In response to the occupied space of the written data being less than or equal to the storage space of the storage array module 121, one storage array module 121 may be determined as the storage array module to be operated.
  • the processing module 110 In response to the occupied space of the written data being larger than the storage space of the storage array module 121, the processing module 110 needs to determine multiple storage array modules 121 that are adapted to the above occupied space as the storage array modules to be operated. The specific number is determined according to the written data. The occupied space and the storage space of the storage array module 121 are determined. For example, if the storage array module to be operated includes a first storage array module 121a and a second storage array module 121b, then the write data is stored in the first storage array module and the second storage array module. The first storage array module and the second storage array module are controlled by different storage control modules 111 . It should be noted that the first memory array module and the second memory array module may be located on the same storage wafer layer, or may be located on different memory wafer layers.
  • the storage control module 111 that controls the first storage array module 121a is the first storage control module 111a
  • the storage control module 111 that controls the second storage array module 121b is the second storage control module 111b
  • the processing module 110 may send the first data writing information to the first storage control module 111a and the second data writing information to the second storage control module 111b, so that the writing is performed in parallel through the first storage control module 111a and the second storage control module 111b.
  • the input data is stored in the first storage array module 121a and the second storage array module 121b.
  • the processing module 110 can respectively send the first data reading information to the first storage control module 111a and the second data reading information to the second storage control module 111b according to the data reading address, whereby, the first storage control module 111a and the second storage control module 111b process data from the first storage control module 111b in parallel. Data is read from the memory array module 121a and the second memory array module 121b.
  • the processing module 110 determines bank0 and bank1 as the storage array modules to be operated based on the occupied space of the written data and the storage space of the storage array module 121, Thus, part of the written data is stored in bank0 in parallel through bank0_ctrl and bank1_ctrl respectively, and the other part of the written data is stored in bank1. Specifically, the processing module 110 sends the first data writing information to bank0_ctrl and the second data writing information to bank1_ctrl respectively.
  • the information includes writing command, writing address and data information; the decoding and analysis module in bank0_ctrl
  • the write command and write address in the data write information are decoded and analyzed.
  • bank0_ctrl sends bank activation information to bank0.
  • the write command and write address are sent to bank0 through the data channel and control channel respectively. address and data information to complete the data writing to bank0; the decoding and analysis module in bank1_ctrl decodes and analyzes the write command and write address in the second data write information.
  • bank1_ctrl sends bank activation information to bank1 , after bank1 is activated, send the write command, write address and data information to bank1 through the data channel and control channel respectively to complete the data writing to bank1.
  • the processing module 110 can respectively send the first data reading information to bank0_ctrl, send the second data reading information to bank1_ctrl, and read from bank0 and bank1 in parallel through bank0_ctrl and bank1_ctrl. data.
  • connection relationship between the storage control module 111 in the logic wafer layer 101 and the storage array module 121 in the storage wafer layer 102 may have various situations. set up. Below are some main examples for explanation.
  • the structure is directly connected to the data and control bus of one memory array module 121 in the memory wafer, and the data and control buses of different memory array modules 121 are independent of each other.
  • the data and control bus include: data signal lines and control signal lines.
  • the data signal lines can be used to transmit data signals, such as rwd0 ⁇ 63:0>.
  • the control signal lines include command signal lines and address signal lines, which can be used to transmit the above command signals and address signals. In this way, the M memory array modules 121 in the memory wafer can perform read and write access at the same time.
  • the three-dimensional stacked chip chip0 includes a logic die and a DRAM die.
  • the DRAM die includes 8 banks, respectively represented as bank0 ⁇ bank7.
  • the logic die includes 8 storage control modules 111, respectively represented as bank0_ctrl ⁇ bank7_ctrl.
  • bank0_ctrl is connected to bank0 through the inter-layer connection structure
  • bank1_ctrl is connected to bank1 through the inter-layer connection structure
  • bank7_ctrl is connected to bank7 through the inter-layer connection structure.
  • the storage wafer layer includes multi-layer storage wafers.
  • the interconnection structure is directly connected to the data and control buses of each memory array module 121 in the memory wafer layer, and the data and control buses of different memory array modules 121 are independent of each other. In this way, all memory array modules 121 in different memory wafers can perform read and write access at the same time.
  • the three-dimensional stacked chip chip1 is a three-layer structure including one logic die and two DRAM dies, namely DRAM die0 and DRAM die1.
  • DRAM die0 includes 8 banks, respectively Represented as bank00 ⁇ bank07
  • DRAM die1 also includes 8 banks, respectively represented as bank10 ⁇ bank17.
  • there are 16 storage control modules 111 in the logic die respectively represented as bank0_ctrl ⁇ bank15_ctrl.
  • bank0_ctrl ⁇ bank7_ctrl are connected to bank00 ⁇ bank07 in DRAM die0 through the inter-layer connection structure in a one-to-one correspondence
  • bank8_ctrl ⁇ bank15_ctrl are connected through the layer
  • the inter-connection structure is connected to bank10 ⁇ bank17 in DRAM die1 in a one-to-one correspondence (not shown in the figure), so that bank00 ⁇ bank07 and bank10 ⁇ bank17 can perform read and write access at the same time.
  • k is an integer greater than or equal to 2 and less than M
  • the k memory array modules 121 connected to each memory control module 111 are distributed on the same memory wafer.
  • the storage wafer is also provided with: a control logic module corresponding to the storage control module 111.
  • the storage control module 111 is connected to the control logic module through a wafer-level interlayer connection structure.
  • the control logic module is respectively connected to the above k
  • the data and control buses of the storage array modules 121 are directly connected.
  • the control logic module is used to: time-share control of the k connected storage array modules 121 to perform data writing or reading operations according to the data writing or reading signals sent by the storage control module 111.
  • the specific control logic of the control logic module can be set according to actual needs.
  • chip selection control information can be set in the data writing or reading signal, and the control logic module determines the storage array module 121 to be activated this time by identifying the chip selection control information. That is to say, the data writing or reading signal includes chip selection control information and writing or reading information.
  • the control logic module is specifically used to: determine the data to be written from the k memory array modules 121 according to the chip selection control information. or read the memory array module 121, and perform data writing or reading operations on the memory array module 121 according to the writing or reading information.
  • k storage array modules 121 connected to the same control logic module can also be divided into different address spaces, and the address space corresponding to the address information in the data writing or reading signal can be determined by distinguishing the address space.
  • the first control logic module 501, the second control logic module 502, the third control logic module 503 and the fourth control logic module 504 are respectively connected to the four storage control modules in the logic die through the wafer level inter-layer connection structure: bank01_ctrl, bank23_ctrl , bank45_ctrl, bank67_ctrl are connected in one-to-one correspondence.
  • the eight banks are respectively represented as bank0 ⁇ bank7.
  • the first control logic module 501 is connected to bank0 and bank1 respectively.
  • the second control logic module 502 is connected to bank2 and bank3 respectively.
  • the third control logic module 503 is connected to bank4 and bank5 respectively.
  • the four control logic modules 504 are connected to bank6 and bank7 respectively. In this way, each group of banks can be time-shared and connected to the interface in the DRAM die for connection with the corresponding storage control module 111 through the corresponding control logic module.
  • the logic die can realize parallel reading and writing of the four banks in the DRAM die.
  • k is an integer greater than or equal to 2 and less than M.
  • the storage wafer layer includes k stacked storage wafers.
  • the k storage array modules 121 connected to each storage control module 111 are respectively distributed in k Storage wafer. At this time, there are disposed between the storage control module 111 and the k connected storage array modules 121
  • the chip select channel is used to select one of the memory array modules 121 to perform data writing or reading operations.
  • the three-dimensional stacked chip 100 is a three-layer structure including one logic die and two DRAM dies, namely DRAM die0 and DRAM die1.
  • DRAM die0 includes 8 banks, represented by bank00 ⁇ bank07 respectively.
  • DRAM die1 also includes 8 banks, represented by bank10 ⁇ bank17 respectively.
  • bank0_ctrl is connected to bank00 in DRAM die0 and bank10 in DRAM die1 through the inter-layer connection structure
  • bank2_ctrl ⁇ bank7_ctrl is connected to bank0_ctrl. similar.
  • a chip select channel is set up between bank0_ctrl and the connected bank00 and bank10, and banks on different DRAM dies are activated according to the chip select channel.
  • the command channel used to transmit row valid instructions can be used as the chip select channel
  • other control channels and data channels between bank0_ctrl and bank00 and bank10 except the command channel can be used as the chip select channel. Can be shared.
  • inventions of this specification also provide a data processing method for three-dimensional stacked chips.
  • the three-dimensional stacked chip includes: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer.
  • the storage wafer layer includes M storage array modules 121 , and there are N corresponding logic wafer layers.
  • Each storage control module 111 is connected to k storage array modules 121 through a wafer-level interlayer connection structure, and is used to control the respective connected storage array modules 121 to perform data writing or reading operations, where M , N are all integers greater than or equal to 2, and N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M.
  • M , N are all integers greater than or equal to 2
  • N is less than or equal to M
  • k is an integer greater than or equal to 1 and less than M.
  • the data processing method includes the following steps S701 and S702.
  • Step S701 receive storage control signal
  • Step S702 Based on the storage control signal, use multiple storage control modules to perform data writing or reading operations in parallel on the storage array module connected to the storage control module.
  • the storage control signal is used to indicate the storage array module 121 to be operated for this data access and operation-related information such as commands, addresses, data, etc.
  • the storage array module 121 to be operated may be one or multiple.
  • multiple storage control modules 111 can be used to perform data writing or reading operations on the connected storage array modules 121 in parallel.
  • the storage control signal may include a data writing command and writing data, and the writing address of the writing data may be determined according to the occupied space of the writing data and the storage space of the storage array module 121, so as to The storage array module 121 to be operated is determined. Specifically, in response to the occupied space of the written data being larger than the storage space of the storage array module 121, the written data is stored in the first storage array module and the second storage array module.
  • the first storage array module and the second storage array module They are controlled by different storage control modules 111; or, the first storage array module and the second storage array module are located on different storage wafer layers and are controlled by different storage control modules 111.
  • the specific process please refer to the relevant descriptions above and will not be repeated here.
  • bank0_ctrl For example, for the first three-dimensional stacked chip structure mentioned above, taking the exemplary structure shown in FIG. 3 as an example, assuming that the memory array modules 121 to be operated are: bank0 ⁇ bank7, the processing can be completed in parallel through bank0_ctrl ⁇ bank7_ctrl. Data writing or reading operations of bank0 ⁇ bank7. write with data Taking the operation as an example, you can send data operation information to bank0_ctrl ⁇ bank7_ctrl respectively. This information includes write command, write address and data information; then, the decoding and analysis module in bank0_ctrl writes the write command in the data write information and Write the address for decoding analysis. After that, bank0_ctrl sends bank activation information to bank0.
  • bank0 After bank0 is activated, it sends the write command, write address and data information to bank0 through the data channel and control channel respectively to complete the data writing to bank0. Enter; similarly, bank1_ctrl ⁇ bank7_ctrl complete the data writing to bank1 ⁇ bank7 respectively.
  • the memory array modules 121 to be operated are: bank0, bank2, bank4 and bank6, through bank01_ctrl, bank23_ctrl, bank45_ctrl and bank67_ctrl
  • the control logic module activates bank0, bank2, bank4 and bank6, thereby completing the data writing or reading operations on bank0, bank2, bank4 and bank6 in parallel.
  • the above three-layer structure of logic die, DRAM die0 and DRAM die1 is also taken as an example.
  • the memory array module 121 to be operated is: bank00 ⁇ bank07 in DRAM die0, then it can Activate bank00 ⁇ bank07 on DRAM die0 through the chip select channel, so that the data writing or reading operations on bank00 ⁇ bank07 are completed in parallel through bank0_ctrl ⁇ bank7_ctrl.
  • the three-dimensional stacked chip 200 provided by the embodiment of this specification includes: a logic chip 201, a memory chip 202, and a first timing control circuit 230.
  • the memory chip 202 includes M memory array modules 121 (banks) for storing data. M is an integer greater than or equal to 2.
  • the logic chip 201 and the memory chip 202 are stacked and packaged using chip stack packaging technology.
  • Chip stack packaging technology is a technology that realizes three-dimensional heterogeneous integration of chips.
  • the current technology that realizes three-dimensional heterogeneous integration of logic chips 201 and memory chips 202 is mainly hybrid bonding technology.
  • the logic chip 201 can access multiple banks in the memory chip 202 in parallel through the wafer-level interlayer connection structure 103, such as a hybrid bonding structure, a through silicon via structure, etc.
  • the specific structure of the logic chip 201 may refer to the structure of the logic wafer layer 101 in the first embodiment.
  • the specific structure of the memory chip 202 may refer to the structure of the storage wafer layer 102 in the first embodiment.
  • N storage control modules 111 are correspondingly provided in the logic chip 201.
  • N is also an integer greater than or equal to 2, and N is less than or equal to M.
  • Each storage control module 111 is connected to k storage array modules 121 through the wafer-level interlayer connection structure 103, and is used to control the respective connected storage array modules 121 to perform data writing or reading operations.
  • k is an integer greater than or equal to 1 and less than M.
  • multiple storage control modules 111 can simultaneously control the corresponding connected storage array modules 121 to perform data reading and writing operations.
  • the logic chip 201 can read and write in parallel one of the storage array modules connected to different storage control modules 111.
  • 121 that is, it can at least realize parallel read and write access to the N memory array modules 121 in the memory chip 202 without being limited by packaging and hardware systems, effectively improving the data access bandwidth of DRAM, thereby conducive to improving High chip data processing speed.
  • the three-dimensional stacked chip 200 includes a logic die and a DRAM die.
  • the DRAM die includes 8 banks, respectively represented as bank0 ⁇ bank7.
  • bank0_ctrl is connected to bank0 through the wafer-level interlayer connection structure 103
  • bank1_ctrl is connected to bank1 through the wafer-level interlayer connection structure 103
  • bank7_ctrl is connected to bank7 through the wafer-level interlayer connection structure 103.
  • the logic die can access all banks in parallel through eight storage control modules 111.
  • the logic die can also be equipped with a number of storage control modules 111 less than the number of banks.
  • storage control modules 111 there are four storage control modules 111, namely bank0_ctrl ⁇ bank3_ctrl.
  • bank0_ctrl is connected to bank0 and bank1 through the wafer level interlayer connection structure 103
  • bank1_ctrl is connected to bank2 and bank3 through the wafer level interlayer connection structure 103
  • bank3_ctrl is connected to bank6 and bank7 through the wafer level interlayer connection structure 103. connect.
  • each storage control module 111 in the logic chip 201 accesses the bank directly and directly accesses the storage array.
  • the access process involves the transmission of various signals needed to read and write data, such as address enable signal, address signal, data enable signal and data signal.
  • some signals need to meet certain timing relationships.
  • the address enable signal and the address signal need to match each other.
  • the required establishment time range of the address signal relative to the address enable signal is -100ps to 100ps;
  • the data enable signal and the data signal match each other to accurately complete the data read and write operations.
  • the above-mentioned multi-channel signals with timing matching relationships are called multiple-channel first target signals, and the port in the storage control module 111 that outputs the above-mentioned multiple-channel first target signals is referred to as a target output end.
  • the decoding and analysis module of each storage control module 111 is provided with a signal generation circuit that generates the multiple first target signals, and the above target output end is the output end of the corresponding signal generation circuit.
  • timing control logic can be added to the target output end of each storage control module 111 in the logic chip 201 to control the target output end to output the output of the multiple first target signals. time to meet the interface timing conditions of the DRAM memory array to the above-mentioned multiple first target signals. At this time, the target output terminals of each storage control module 111 in the logic chip 201 are connected to the above-mentioned timing control logic, and the output terminals of the timing control logic are directly connected to the storage array module 121 through the wafer-level interlayer connection structure.
  • the design of the above-mentioned timing control logic is relatively difficult. It is usually necessary to use a fully customized method to design a dedicated physical interface hard core on the logic chip 201 to meet this timing. This brings additional overhead to the design of the logic chip 201, which mostly adopts a semi-custom process, and also makes the semi-custom layout Cabling is restricted.
  • the logic chip 201 contains multiple hard cores PHY to meet the interface timing requirements of the DRAM, the timing and functional verification between these hard cores and the logic of the logic chip 201 involves full customization and semi-customization co-design verification, workload and difficulty Both are very large. In addition, the existence of the hard core blocks the layout and routing of the logic chip 201, making the back-end design more difficult.
  • a first timing control circuit 230 can be provided in the three-dimensional stacked chip to control the multiple first target signals output by the target output terminal to reach the memory array module based on the received clock signal. 121 to meet the interface timing conditions of the memory array module 121 for the above-mentioned multiple first target signals. This can meet the timing requirements of the storage array for these first target signals with timing matching relationships, thereby ensuring the normal operation of the three-dimensional stacked chip, and is easy to implement. There is no need to design a special physical interface hard core on the logic chip 201, which is beneficial to reducing the cost. The design difficulty of logic chip 201.
  • a first timing control circuit 230 can be added to control the timing of signals output by the corresponding signal output ports of the storage control module 111 reaching the corresponding bank.
  • this semi-custom process design is conducive to simplifying the design process and difficulty of the logic chip 201, thereby accelerating the logic chip 201 development progress.
  • each memory control module 111 in the logic chip 201 are connected to the corresponding terminals in the memory chip 202 through the first timing control circuit 230.
  • Storage array module 121 is connected. It should be noted that as a schematic, FIG. 10 only shows one storage control module 111 and one storage array module 121. In actual application, the specific number of storage control module 111, first timing control circuit 230 and storage array module 121 is It needs to be set according to the actual needs of three-dimensional stacked chips.
  • the first timing control circuit 230 is used to control the transmission timing of the multiple first target signals output from the target output terminal to the memory array module 121 based on the received clock signal, so as to meet the requirements of the memory array for the multiple first target signals.
  • Interface timing conditions are determined based on the timing requirements of the storage array in actual application scenarios. In this embodiment, there is a timing matching relationship between the multiple first target signals, such as the signals in the logic chip 201 that need to be output to the storage array module 121 synchronously.
  • the above-mentioned multiple first target signals include an address enable signal and an address signal.
  • the target output end includes an address enable output end of the address enable signal generation circuit in the logic chip 201 and an address output end of the address generation circuit.
  • the corresponding first timing control circuit 230 needs to control the transmission timing of the address enable signal output by the address enable output terminal and the address signal output by the address output terminal to reach the memory array module 121 to meet the requirements of the memory array for both types. Signal timing requirements.
  • the multiple first target signals include a write data enable signal and a write data signal, that is, a data signal that needs to be written to the memory array module 121.
  • the target output terminal includes a write data enable signal of the write data enable generation circuit. energy output terminal and the data output terminal of the data supply circuit.
  • the corresponding first timing control circuit 230 needs to control the transmission timing of the write data enable signal output by the write data enable output terminal and the write data signal output by the data output terminal to reach the memory array module 121 to meet the requirements of the memory array. Timing requirements for these two signals.
  • the first timing control circuit 230 may include: a first sampling sub-circuit 231 and a second sampling sub-circuit 232.
  • the first sampling sub-circuit 231 is provided on the logic chip 201
  • the second sampling sub-circuit 232 is provided on the memory chip 202 .
  • the above-mentioned three-dimensional stacked chip also includes a clock interface for providing a clock signal.
  • the clock terminals of the first sampling sub-circuit 231 and the second sampling sub-circuit 232 are both connected to the clock interface, that is, they are controlled by the same clock signal.
  • the clock interface can be the output interface of the internal clock circuit of the logic chip 201, or it can be an external Clock interface, this embodiment does not limit this.
  • the input end of the first sampling sub-circuit 231 is connected to the target output end, and is used to synchronously trigger the multiple first target signals output from the target output end to be output from the logic chip 201 under the control of the clock signal.
  • the input end of the second sampling sub-circuit 232 is connected to the output end of the first sampling sub-circuit 231, and the output end is connected to the memory array module 121, for synchronously triggering the output from the logic chip 201 under the control of the above clock signal.
  • the multiple first target signals are received by the storage array module 121 .
  • the first sampling sub-circuit 231 and the second sampling sub-circuit 232 may be connected through the wafer-level interlayer connection structure 103 .
  • the first sampling sub-circuit 231 may include: a plurality of first flip-flops arranged in one-to-one correspondence with the multiple first target signals.
  • the input terminals of the plurality of first flip-flops are connected to the above-mentioned target output terminals, that is, connected to the output terminals of respective first target signals, the clock terminals are connected to the above-mentioned clock interface, and the output terminals are connected to the second sampling sub-circuit 232 .
  • These first flip-flops are used to synchronously trigger multiple first target signals output from the above target output terminals to be output from the logic chip 201 at a first sampling time point based on the same clock signal.
  • the above target output terminal includes an address enable output terminal and an address output terminal
  • the first sampling subcircuit 231 includes a first flip-flop DFF0 and a first flip-flop DFF1.
  • the input terminal of the first flip-flop DFF0 and the address enable output terminal are terminal is connected, and the input terminal of the first flip-flop DFF1 is connected with the address output terminal.
  • the first flip-flop DFF0 and the first flip-flop DFF1 can synchronously trigger the output of the address enable signal and the address signal from the logic chip 201 to the memory chip 202 at the first sampling time point based on the same clock signal.
  • the second sampling sub-circuit 232 may include: a plurality of second flip-flops arranged in one-to-one correspondence with the plurality of first flip-flops.
  • the input terminals of the plurality of second flip-flops are connected to the output terminals of the corresponding first flip-flops, the clock terminals are connected to the above-mentioned clock interfaces, and the output terminals are connected to the storage array module 121 .
  • the clock terminals of the plurality of second flip-flops and the clock terminals of the plurality of first flip-flops are connected to the same clock interface and receive the same clock signal provided by the clock interface.
  • the plurality of second flip-flops are used to latch the first target signal received respectively, and based on the same clock signal, trigger the latched first target signal synchronously at the second sampling time point and output it to the storage array module 121 . Since the signal needs to be output from the logic chip 201 before being latched in the memory chip 202, the second sampling time point should be later than the first sampling time point.
  • the first sampling sub-circuit 231 includes the first flip-flop DFF0 and the first flip-flop DFF1.
  • the second sampling sub-circuit 232 may include the second flip-flop DFF2 and the second flip-flop DFF3.
  • the input terminal of the second flip-flop DFF2 is connected to the output terminal Q0 of the first flip-flop DFF0, and the received address enable signal is latched.
  • the input terminal of the second flip-flop DFF3 is connected to the output terminal Q1 of the first flip-flop DFF1 to latch the received address signal.
  • the second flip-flop DFF2 and the second flip-flop DFF3 can synchronously trigger the address enable signal and the address signal to be output to the memory array module 121 at the second sampling time point based on the same clock signal, that is, they are synchronously received by the memory array module 121 .
  • the address enable signal and the time when the address signal reaches the DRAM can be basically synchronized, and the address enable port and the address port between the logic chip 201 and the DRAM can be converted into a synchronization port.
  • the times when the multiple channels of first target signals arrive at the corresponding second flip-flop are located between the first sampling time point and the second sampling time. points, and the effective duration of the multiple first target signals is greater than or equal to the time interval between the first sampling time point and the second sampling time point. This ensures that each first target signal can be correctly sampled at the second sampling time point.
  • the time interval between the first sampling time point and the second sampling time point can be set according to the needs of the actual application scenario.
  • the time interval can be set to one clock cycle of the above-mentioned clock signal.
  • FIG. 11 shows an exemplary transmission timing diagram of the address enable signal and the address signal.
  • time Ta represents the first sampling time point
  • time Tb represents the second sampling time point
  • CLK represents the clock signal
  • Q0 represents the address enable signal represented by the output of the first flip-flop DFF0
  • Q1 represents the output of the first flip-flop DFF1
  • the address signal Q2 represents the address enable latch signal output by the second flip-flop DFF2
  • Q3 represents the address latch signal output by the second flip-flop DFF3.
  • first flip-flops DFF0 and DFF1 and the second flip-flops DFF2 and DFF3 adopt rising edge triggering mode.
  • the clock signal CLK jumps to high level, triggering the Q0 port of the first flip-flop DFF0 to output the address enable signal received by its own D port, causing the second flip-flop DFF2 to enable the address.
  • the signal is latched, and at the same time, the Q1 port of the first flip-flop DFF1 is triggered to output the address signal received by its own D port, causing the second flip-flop DFF3 to latch the address signal.
  • the clock signal CLK jumps from low level to high level, triggering the Q2 port of the second flip-flop DFF2 to output the latched address enable signal, that is, the address enable latch signal, and at the same time, triggering the second flip-flop
  • the Q3 port of DFF3 outputs the latched address signal, that is, the address latch signal, so that the address enable signal and the address signal can be received by the DRAM synchronously. It should be noted that considering that the flip-flop takes a certain amount of time from clock triggering to output response, it takes a certain period of time after the clock triggers before the output port outputs the corresponding signal.
  • the first timing control circuit 230 may also include: a delay sub-circuit 233 disposed in the memory chip 202, and the output end of the second sampling sub-circuit 232 is connected to the memory array module 121 through the delay sub-circuit 233.
  • the delay subcircuit 233 is used to adjust the relative time relationship between the first target signals output from the second sampling subcircuit 232 and arriving at the memory array module 121 to meet the above-mentioned interface timing conditions.
  • an adjustable delay unit can be set for each first target signal, and the delay time of each delay unit can be adjusted according to a preset delay rule.
  • the preset delay rules can be set according to the interface sampling timing requirements of the specific storage array.
  • the first delay unit and the second delay unit can be respectively set in a targeted manner, and the input end of the first delay unit and the second trigger
  • the output terminal Q2 of the flip-flop DFF2 is connected
  • the input terminal of the second delay unit is connected with the output terminal Q3 of the second flip-flop DFF3
  • the output terminals of the first delay unit and the second delay unit are respectively connected with the memory array module 121 Connect the corresponding signal receiving port.
  • the address enable latch signal output by the second flip-flop DFF2 and the address latch signal output by the second flip-flop DFF3 by respectively configuring the delay time of the first delay unit and the second delay unit.
  • the relative time relationship that finally reaches the memory array module 121 is to meet the timing requirements of the memory array for the address enable signal and the address signal. For example, if the storage array requires the address signal to arrive before the address enable signal, and the interval time is t, then the delay time of the first delay unit can be configured to be greater than the delay time of the second delay unit, and the delay time difference is t .
  • the delay unit can also be specifically set to delay a latch signal that arrives after it is needed, so as to meet the signal sampling timing requirements of the memory array.
  • the delay unit The specific implementation of sub-circuit 233 is not limited.
  • the technical solution provided by this embodiment can effectively synchronize the signal output by the logic chip 201 to the DRAM by setting the above-mentioned first timing control circuit 230 and inputting a synchronization clock, thereby converting the interface between the logic chip 201 and the DRAM into a synchronized state. interface.
  • the logic chip 201 When designing the logic chip 201, it is only necessary to set corresponding output delay constraints for the signals output to the DRAM interface according to the DRAM interface path to realize the semi-customized process design of the logic chip 201.
  • the memory chip 202 is a universal design and the corresponding logic chip 201 may have multiple forms, the synchronous output of the logic chip 201 is achieved by adding a second sampling sub-circuit 232 in the DRAM, which simplifies the design of the logic chip 201 The process and difficulty accelerated the development progress of logic chip 201.
  • the above-mentioned three-dimensional stacked chip further includes: a second timing control circuit (not shown in the figure).
  • the target input terminals of each memory control module 111 in the logic chip 201 are connected to the memory array module 121 in the memory chip 202 through the second timing control circuit.
  • the clock end of the second timing control circuit is also connected to the above-mentioned clock interface, that is, it is controlled by the same clock signal as the first timing control circuit 230 .
  • the second timing control circuit is used to control the transmission timing of the multiple second target signals output by the memory array module 121 to the target input terminal based on the clock signal, so as to meet the interface timing conditions of the logic chip 201 for the multiple second target signals.
  • the multiple second target signals are multiple signals with timing matching relationships. For example, they may include a read data enable signal and a read data signal, that is, a data signal read from the memory array module 121 .
  • the specific principle of the second timing control circuit is similar to the above-mentioned first timing control circuit 230.
  • the target input terminal in the logic chip 201 has its own signal capture logic.
  • the second timing control circuit does not need to set a delay sub-circuit. The circuit is used to adjust the relative time relationship of each second target signal arriving at the target input terminal.
  • the signal output by the DRAM to the logic chip 201 can be effectively synchronized, thereby converting the interface between the logic chip 201 and the DRAM into a synchronous interface.
  • the embodiment of this specification provides a timing control method, which can be applied to the three-dimensional stacked chip in the embodiment of FIG. 9 .
  • the method includes the following steps:
  • Step S1201 obtain the clock signal
  • Step S1202 Based on the clock signal, control the transmission timing of the multiple first target signals output from the target output terminal in the logic chip 201 to the memory array module 121 to meet the requirements of the memory array module 121 for the above multiple channels. Interface timing conditions for the first target signal.
  • step S1201 and step S1202 may refer to the corresponding descriptions in the above chip structure embodiment, and will not be described again here.
  • the above step S1202 may include: based on the clock signal, synchronously triggering the multiple first target signals output from the target output terminal at the first sampling time point to be output from the logic chip 201; A target signal is latched, and based on the clock signal, each latched first target signal is synchronously triggered and output to the storage array module 121 at a second sampling time point, which is later than the first sampling time point.
  • a target signal is latched, and based on the clock signal, each latched first target signal is synchronously triggered and output to the storage array module 121 at a second sampling time point, which is later than the first sampling time point.
  • the step of outputting each first target signal of the synchronous trigger latch to the memory array module 121 at the second sampling time point may include: synchronously triggering the latch at the second sampling time point.
  • Each channel of the stored first target signal is output; according to the preset delay rule, each channel of the output first target signal is delayed respectively, so as to calculate the relative time of each channel of the first target signal arriving at the storage array module 121 The relationship is adjusted to meet the interface timing conditions.
  • the above timing control method further includes: based on the clock signal, controlling the transmission timing of the multiple second target signals output by the memory array module 121 to the target input terminal in the logic chip 201, so as to The interface timing conditions of the logic chip 201 for the multiple second target signals are met.

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Abstract

La présente demande divulgue une puce empilée tridimensionnelle et un procédé de traitement de données associé. La puce empilée tridimensionnelle comprend une couche de puce de stockage et une couche de puce logique empilée sur la couche de puce de stockage. La couche de puce de stockage comprend M modules de réseau de stockage, N modules de commande de stockage sont disposés de manière correspondante dans la couche de puce logique, et chaque module de commande de stockage est connecté à k modules de réseau de stockage au moyen d'une structure de connexion intercouche au niveau de la tranche et est utilisé pour commander l'exécution d'une opération d'écriture ou de lecture de données sur les modules de réseau de stockage connectés respectifs. M et N sont des nombres entiers supérieurs ou égaux à 2, N est inférieur ou égal à M, et k est un nombre entier supérieur ou égal à 1 et inférieur à M. De cette manière, un accès en lecture-écriture parallèle à une pluralité de modules de réseau de stockage peut être mis en œuvre, et la bande passante d'accès aux données est efficacement améliorée.
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