WO2023231756A1 - Three-dimensional stacked chip and data processing method therefor - Google Patents

Abstract

The present application discloses a three-dimensional stacked chip and a data processing method therefor. The three-dimensional stacked chip comprises a storage die layer and a logic die layer stacked on the storage die layer. The storage die layer comprises M storage array modules, N storage control modules are correspondingly provided in the logic die layer, and each storage control module is connected to k storage array modules by means of a wafer-level interlayer connection structure and is used for controlling to perform a data writing or reading operation on the respective connected storage array modules. M and N are integers greater than or equal to 2, N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M. In this way, parallel read-write access to a plurality of storage array modules can be implemented, and the data access bandwidth is effectively improved.

Description

A three-dimensional stacked chip and its data processing method

Cross-references to related applications

This application claims priority based on Chinese patent application 202210619304.0 submitted on June 2, 2022, the entire contents of which are incorporated herein by reference.

【Technical field】

The present application relates to the field of integrated circuit technology, and in particular to a three-dimensional stacked chip and a data processing method thereof.

【Background technique】

The traditional Dynamic Random Access Memory (DRAM) interface consists of address bits, data bits and command bits. During a write operation, the command bits and address bits are first received and decoded to generate a storage array module (bank). Control signals and address information, then receive the data for serial-to-parallel conversion and then send it to the bank. During the read operation, the command bit and address bit are first received, decoded to generate the bank's control signal and address information, and then the bank outputs the data, which is output through parallel-to-serial conversion. In other words, traditional DRAM can only perform read and write operations on one bank at a time, that is, all banks operate in a time-sharing manner, and the bandwidth is greatly limited.

[Content of the invention]

In view of this, embodiments of the present application provide a three-dimensional stacked chip and a data processing method thereof, which can increase the bandwidth of the DARM, thus helping to increase the data processing speed of the chip.

In a first aspect, embodiments of the present application provide a three-dimensional stacked chip, including: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer. The storage wafer layer includes M storage array modules. , N storage control modules are correspondingly provided in the logic wafer layer, each of the storage control modules is connected to k storage array modules through a wafer-level interlayer connection structure, and is used to control the respective connected storage array modules. The storage array module performs data writing or reading operations, where M and N are both integers greater than or equal to 2, and N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M.

Further, each of the storage control modules is directly connected to the data and control bus of one of the storage array modules through the wafer-level interlayer connection structure, and the data and control buses of different storage array modules are independent of each other.

Further, k is an integer greater than or equal to 2 and less than M, and k of the storage array modules are distributed on the same storage wafer. The storage wafer layer also includes: a control set in one-to-one correspondence with the storage control module. Logic module, the storage control module is connected to the control logic module through a wafer-level interlayer connection structure, and the control logic module is directly connected to the data and control buses of k storage array modules respectively. The control logic module The module is used to: time-share control of k storage array modules to perform data writing or reading operations according to the data writing or reading signals sent by the storage control module.

Further, the data writing or reading signal includes chip selection control information and writing or reading information, and the control logic module is specifically configured to: select data from k memory array modules according to the chip selection control information. Determine the storage array module to be written or read, and perform operations on the storage array module based on the write or read information. Row data writing or reading operations.

Further, the control logic module is specifically configured to: determine the storage array module to be written or read from the k storage array modules according to the address space corresponding to the data writing or reading signal, and according to The data write or read signal performs a data write or read operation on the storage array module.

Further, k is an integer greater than or equal to 2 and less than M, the storage wafer layer includes k storage wafers arranged in a stack, and k storage array modules connected to one storage control module are respectively distributed in There are k memory wafers, and a chip select channel is provided between the memory control module and the k memory array modules for selecting one of the memory array modules to perform the data writing or reading operation.

Further, the logic wafer layer is also provided with a processing module, and each of the storage control modules is connected to the processing module. The processing module is used to determine the storage array module to be operated, and to connect the storage array module to be operated. The storage control module of the storage array module sends data operation information; each storage control module is provided with a decoding and analysis module, and the decoding and analysis module decodes and analyzes the commands and addresses in the data operation information, to perform data writing or reading operations on the storage array module to be operated.

Further, the processing module receives the data write command and the write data, and determines the write address of the write data according to the occupied space of the write data and the storage space of the storage array module to determine the The storage array module is to be operated.

Further, in response to the occupied space of the written data being larger than the storage space of the storage array module, the processing module stores the written data in the first storage array module and the second storage array module, the The first storage array module and the second storage array module are controlled by different storage control modules; or the first storage array module and the second storage array module are located on different storage wafer layers, and are controlled by different storage control modules. Control module control.

Further, the inter-layer connection structure includes a data channel and a control channel, the data channel is used to transmit data signals for writing or reading, and the control channel is used for transmitting control signals for controlling data writing or reading.

Further, the control signal includes a command signal and an address signal; wherein the command signal includes a row operation enable signal, a column operation enable signal and a write data control signal; the address signal includes a row address signal and a column address. Signal.

In a second aspect, embodiments of the present application also provide a data processing method for a three-dimensional stacked chip. The three-dimensional stacked chip includes: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer. The storage wafer layer includes M storage array modules, and N storage control modules are correspondingly provided in the logic wafer layer. Each of the storage control modules is connected to k storage array modules through a wafer-level interlayer connection structure. connection, used to control the respective connected storage array modules to perform data writing or reading operations, where M and N are both integers greater than or equal to 2, and N is less than or equal to M, and k is greater than or equal to 1 and An integer less than M. The method includes: receiving a storage control signal; based on the storage control signal, using multiple storage control modules to perform data writing or reading operations in parallel on the storage array module connected to the storage control module.

The three-dimensional stacked chips and their data processing methods provided by the embodiments of this application abandon the decoding and address parsing modules and serial-to-parallel conversion modules in traditional memories. By setting N storage control modules on the logic wafer layer, before chip packaging, , each storage control module is connected to k storage array modules through the wafer-level interlayer connection structure The blocks are directly connected, and k is an integer greater than or equal to 1 and less than M, so that different storage control modules control the respective connected storage array modules to perform data writing or reading operations. In this way, the DRAM interface bit width is no longer limited by packaging and hardware systems, and the DRAM storage array interface signal can be output directly to realize parallel read and write access to multiple storage array modules in the storage wafer layer, effectively improving the performance of DRAM. Data access bandwidth, thereby helping to improve the data processing speed of the chip.

The above description is only an overview of the technical solutions of the present application. In order to have a clearer understanding of the technical means of the present application, they can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present application more obvious and understandable. , the specific implementation methods of the present application are specifically listed below.

[Picture description]

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be construed as limiting the application. Also throughout the drawings, the same reference characters are used to designate the same components. In the attached picture:

Figure 1 shows an exemplary conventional DRAM block diagram;

Figure 2 shows a schematic diagram 1 of the packaging of a three-dimensional stacked chip in the embodiment of this specification;

Figure 3 shows a schematic diagram 1 of a two-layer structure chip in the embodiment of this specification;

Figure 4 shows a schematic diagram of data writing in the embodiment of this specification;

Figure 5 shows a schematic diagram of a three-layer structure chip in an embodiment of this specification;

Figure 6 shows a schematic diagram 2 of a two-layer structure chip in the embodiment of this specification;

Figure 7 shows a flow chart of a data processing method for three-dimensional stacked chips in an embodiment of this specification;

Figure 8 shows the second package schematic diagram of the three-dimensional stacked chip in the embodiment of this specification;

Figure 9 shows an exemplary timing relationship diagram of the address signal and the address enable signal;

Figure 10 shows a circuit diagram of the first timing control circuit in the embodiment of this specification;

Figure 11 shows an exemplary transmission timing diagram of the address enable signal and the address signal in the embodiment of this specification;

Figure 12 shows a flow chart of the timing control method in the embodiment of this specification.

【Detailed ways】

Figure 1 shows a traditional DRAM block diagram with an 8-bit data interface and 8x internal prefetching. The entire DRAM has a total of 8 storage array modules (banks), namely bank0~bank7. The address and control lines of bank0~bank7 are all connected to the same decoding and address analysis module set in the DRAM, and the data lines are all connected to the same decoding and address analysis module set in the DRAM. The same parallel-to-serial conversion module is connected. In Figure 1, rwd0 to rwd7 represent the data of bank0 to bank7, and are illustrated as 64 bits in the figure. Taking the write operation as an example, the decoding and address parsing module first receives the command and address information sent from the outside. The address information includes the bank address information. Through decoding, it determines the bank targeted by this write operation and generates the control signal of the bank. and address information, and then the parallel-to-serial conversion module receives the data signal dqs/dq<7:0> to be written, performs serial-to-parallel conversion, converts it into a 64-bit data signal rwd<63:0>, and then sends it to the The bank completes data writing. In other words, only one bank can be read and written at a time.

Moreover, due to packaging and hardware system limitations, the DRAM interface data bit width cannot be very large, which results in the internal storage array interface bit width being much larger than the DRAM interface bit width. Therefore, the interface speed after parallel-to-serial conversion is much higher than the internal Storage array storage rate, for example, for the 8x prefetch structure in the above example, if the external interface data bit width is 8 bits, then the internal storage array bit width is 64 bits, and if the storage array speed is 200Mbps, the interface rate needs to reach 1600Mbps. Therefore, it is not conducive to improving the data access bandwidth of DRAM.

In view of this, embodiments of this specification provide a three-dimensional stacked chip that abandons the decoding and address resolution modules and serial-to-parallel conversion modules in traditional DRAM. By arranging N storage control modules on the logic wafer layer, the chip package is Previously, each storage control module was directly connected to k storage array modules through a wafer-level interlayer connection structure, where k was an integer greater than or equal to 1 and less than M, thereby controlling the respective connected storage array modules through different storage control modules. Perform data writing or reading operations. This allows the DRAM interface bit width to no longer be limited by packaging and hardware systems, and directly outputs the DRAM storage array interface signal, allowing the logic wafer to directly read and write multiple storage array modules in parallel, effectively improving DRAM data access. bandwidth, thereby helping to increase the data processing speed of the chip.

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that the "logic wafer layer" and "logic chip" described in this article should be understood as the same structure, and the "storage wafer layer" and "memory chip" should also be understood as the same structure. The small piece of wafer obtained after cutting the wafer is called a die, and the die is packaged to form a chip. Embodiment 1

The embodiment of this specification provides a three-dimensional stacked chip 100, which may be, for example, a SOC chip (System on Chip). As shown in FIG. 2 , the three-dimensional stacked chip 100 may include: a storage wafer layer 102 and a logic wafer layer 101 stacked with the storage wafer layer 102 . It should be noted that the number of layers of memory wafers and logic wafers in the three-dimensional stacked chip 100 shown in the drawings provided in this embodiment is only for illustration and is not limiting. During specific implementation, it can be set according to actual needs.

The storage wafer layer 102 includes one or more stacked storage wafers for expanding storage space. M memory array modules 121 are distributed in the memory wafer layer 102, where M is an integer greater than or equal to 2. During specific implementation, the specific number of layers of the storage wafer and the number of storage array modules 121 are set according to the requirements for chip storage capacity in actual application scenarios. For example, each memory wafer may include 4, 8, or 16 memory array modules 121.

Correspondingly, N storage control modules 111 are provided in the logic wafer layer 101. N is also an integer greater than or equal to 2, and N is less than or equal to M. Each storage control module 111 is connected to k storage array modules 121 through the wafer-level interlayer connection structure 103, and is used to control the respective connected storage array modules 121 to perform data writing or reading operations. Where, k is an integer greater than or equal to 1 and less than M. Each storage array module 121 is connected to a storage control module 111 , and different storage control modules 111 are connected to different storage array modules 121 . In a specific embodiment, one storage control module 111 can be connected to one storage array module 121, that is, the storage control module 111 and the storage array module 121 are connected in a one-to-one correspondence; in another embodiment, one storage control module 111 can be connected to one storage array module 121. Connect multiple storage array modules 121, for example, a storage control module 111 Two storage array modules 121 are connected, and another storage control module 111 is connected to three storage array modules 121 . When reading and writing data, multiple storage control modules 111 can simultaneously control the corresponding connected storage array modules 121 to perform data reading and writing operations, so that the logic wafer can read and write in parallel one of the storage array modules connected to different storage control modules 111 121, that is, it can at least realize parallel read and write access to N storage array modules 121 in the storage wafer layer 102, without being restricted by packaging and hardware systems, effectively improving the data access bandwidth of DRAM, thereby conducive to improving the data of the chip. Processing speed.

During specific implementation, the specific number of storage control modules 111 and the connected storage array modules 121 are determined according to the number of storage array modules 121 in the storage wafer layer 102 and the actual control logic. For example, k can be 1, and N equals M, that is, one storage control module 111 can correspondingly control one storage array module 121. In this way, the logic wafer can read and write all the storage array modules 121 of the storage wafer in parallel, so the bandwidth can be greatly improved. Similarly, taking the storage wafer rate of 200Mbps and the data interface bit width of 64 bits as an example, in the 8bank shown in Figure 3 In the example, the access bandwidth can reach 200Mbps×64bit×8banks=100Gbps, which is 8 times that of the traditional solution. For another example, the M storage array modules 121 distributed in the storage wafer layer 102 can also be divided into multiple groups. At least one group includes multiple storage array modules 121. One storage control module 111 correspondingly controls one group of storage array modules 121. At this time, k is the number of storage array modules 121 in the corresponding group, and N is equal to the number of divided groups.

It is understandable that in a 3DIC (three Dimensional Integrated Circuit) chip, the memory wafer (DRAM die) and the logic wafer (logic die) can be connected through wafer-level interconnection methods such as hybrid bonding technology (Hyrid bonding), RDL (Redistribution Layer, rewiring layer) and TSV (Through Silicon Via) technology are connected and packaged together to form a three-dimensional stacked chip 100.

Therefore, direct connection between each storage control module 111 and the corresponding k storage array modules 121 can be achieved through the wafer-level interlayer connection structure 103 . In this way, the DRAM interface bit width is no longer limited by packaging and hardware systems, and the interface signals of the storage array module 121 can be directly output. The logic wafer can directly control multiple storage array modules 121 to read and write at the same time, effectively improving the data of DRAM. Access bandwidth.

From a structural perspective, the inter-layer connection structure 103 can be implemented using applicable wafer-level interconnection technology, which is determined based on the actual wiring requirements between the storage control module 111 and the storage array module 121, and is not limited here. For example, the interlayer connection structure 103 may include one or more combinations of a hybrid bonding structure, a wiring structure in an RDL layer, and a through silicon via structure.

From a functional perspective, the inter-layer connection structure 103 serves as a signal transmission channel between the storage control module 111 and the storage array module 121, and is used to transmit signals required for data writing or reading operations on the storage array module 121.

For example, the inter-layer connection structure 103 may include data channels and control channels. The data channel is used to transmit written or read data signals, and the bit width of the data channel can be determined based on the data bit width that the storage array module 121 can write or read at one time and the data bit width of the actual logic wafer. As shown in Figure 3, 64 bits are used as an example. rwd0<63:0>~rwd7<63:0> represent the data signals of bank0~bank7. During specific implementation, it can also be other widths such as 128 or 256.

The control channel is used to transmit control signals that control data writing or reading. For example, the control signals transmitted in the control channel may include command signals and address signals.

The command signal may include but is not limited to: a row operation enable signal, a column operation enable signal, and a write data control signal, and the details may be determined according to actual needs. Among them, the row operation enable signal can also be called a bank row valid indication, which is used to indicate that the row address can be captured for decoding. The column operation enable signal, which can also be called the bank column write and read address control signal, is used to indicate that the column address can be captured for decoding. The write data control signal is used to instruct data to be written in the corresponding column.

The address signals may include row address signals and column address signals. The address bit width is determined according to the row and column structure of DRAM.

It should be noted that other control and status signals in Figure 3 represent the control signals required for DRAM operation, such as powerdown control, bank_fail, etc. The specific signal types and the structure of other control circuits can be referred to DRAM related technologies, and will not be described in detail here.

In addition, in an optional implementation, a processing module 110 may also be provided in the logic wafer layer 101. Each storage control module 111 is connected to the processing module 110. The processing module 110 is used to determine the storage array module to be operated. , that is, determine which storage array modules 121 in the storage wafer layer 102 are to perform data reading or writing operations, and send data operation information to the storage control module connected to the above-mentioned storage array module to be operated. The data operation information may include commands and addresses, and if the data operation is a write operation, it may also include data information to be written. Each storage control module 111 includes a decoding and analysis module. The decoding and analysis module decodes and analyzes the commands and addresses in the data operation information to perform data writing or reading operations on the storage array module to be operated.

For example, the processing module 110 may receive a data write command and write data, and determine the write address of the write data based on the occupied space of the write data and the storage space of the storage array module 121, that is, determine the storage array module to be operated. In response to the occupied space of the written data being less than or equal to the storage space of the storage array module 121, one storage array module 121 may be determined as the storage array module to be operated.

In response to the occupied space of the written data being larger than the storage space of the storage array module 121, the processing module 110 needs to determine multiple storage array modules 121 that are adapted to the above occupied space as the storage array modules to be operated. The specific number is determined according to the written data. The occupied space and the storage space of the storage array module 121 are determined. For example, if the storage array module to be operated includes a first storage array module 121a and a second storage array module 121b, then the write data is stored in the first storage array module and the second storage array module. The first storage array module and the second storage array module are controlled by different storage control modules 111 . It should be noted that the first memory array module and the second memory array module may be located on the same storage wafer layer, or may be located on different memory wafer layers.

For example, as shown in Figure 4, the storage control module 111 that controls the first storage array module 121a is the first storage control module 111a, the storage control module 111 that controls the second storage array module 121b is the second storage control module 111b, and the processing module 110 may send the first data writing information to the first storage control module 111a and the second data writing information to the second storage control module 111b, so that the writing is performed in parallel through the first storage control module 111a and the second storage control module 111b. The input data is stored in the first storage array module 121a and the second storage array module 121b.

Correspondingly, when reading data, the processing module 110 can respectively send the first data reading information to the first storage control module 111a and the second data reading information to the second storage control module 111b according to the data reading address, Thereby, the first storage control module 111a and the second storage control module 111b process data from the first storage control module 111b in parallel. Data is read from the memory array module 121a and the second memory array module 121b.

For example, still taking writing data as an example, in the example shown in Figure 3, assume that the processing module 110 determines bank0 and bank1 as the storage array modules to be operated based on the occupied space of the written data and the storage space of the storage array module 121, Thus, part of the written data is stored in bank0 in parallel through bank0_ctrl and bank1_ctrl respectively, and the other part of the written data is stored in bank1. Specifically, the processing module 110 sends the first data writing information to bank0_ctrl and the second data writing information to bank1_ctrl respectively. The information includes writing command, writing address and data information; the decoding and analysis module in bank0_ctrl The write command and write address in the data write information are decoded and analyzed. After that, bank0_ctrl sends bank activation information to bank0. After bank0 is activated, the write command and write address are sent to bank0 through the data channel and control channel respectively. address and data information to complete the data writing to bank0; the decoding and analysis module in bank1_ctrl decodes and analyzes the write command and write address in the second data write information. After that, bank1_ctrl sends bank activation information to bank1 , after bank1 is activated, send the write command, write address and data information to bank1 through the data channel and control channel respectively to complete the data writing to bank1.

Further, when reading the above written data, the processing module 110 can respectively send the first data reading information to bank0_ctrl, send the second data reading information to bank1_ctrl, and read from bank0 and bank1 in parallel through bank0_ctrl and bank1_ctrl. data.

During specific implementation, depending on the actual architecture of the three-dimensional stacked chip 100 and the different bandwidth requirements, the connection relationship between the storage control module 111 in the logic wafer layer 101 and the storage array module 121 in the storage wafer layer 102 may have various situations. set up. Below are some main examples for explanation.

First, the three-dimensional stacked chip 100 is a two-layer wafer structure including one layer of logic wafer and one layer of storage wafer, k=1, that is, each storage control module 111 in the logic wafer is connected through wafer-level interlayer The structure is directly connected to the data and control bus of one memory array module 121 in the memory wafer, and the data and control buses of different memory array modules 121 are independent of each other. It can be understood that the data and control bus include: data signal lines and control signal lines. The data signal lines can be used to transmit data signals, such as rwd0<63:0>. The control signal lines include command signal lines and address signal lines, which can be used to transmit the above command signals and address signals. In this way, the M memory array modules 121 in the memory wafer can perform read and write access at the same time.

For example, as shown in Figure 3, the three-dimensional stacked chip chip0 includes a logic die and a DRAM die. Assume that the DRAM die includes 8 banks, respectively represented as bank0~bank7. Then, the logic die includes 8 storage control modules 111, respectively represented as bank0_ctrl~bank7_ctrl. bank0_ctrl is connected to bank0 through the inter-layer connection structure, bank1_ctrl is connected to bank1 through the inter-layer connection structure, and so on, bank7_ctrl is connected to bank7 through the inter-layer connection structure.

Second, the storage wafer layer includes multi-layer storage wafers. M storage array modules 121 are distributed in different storage wafers, k=1, that is, each storage control module 111 in the logic wafer passes through the wafer level layer. The interconnection structure is directly connected to the data and control buses of each memory array module 121 in the memory wafer layer, and the data and control buses of different memory array modules 121 are independent of each other. In this way, all memory array modules 121 in different memory wafers can perform read and write access at the same time.

For example, as shown in Figure 5, the three-dimensional stacked chip chip1 is a three-layer structure including one logic die and two DRAM dies, namely DRAM die0 and DRAM die1. DRAM die0 includes 8 banks, respectively Represented as bank00 ~ bank07, DRAM die1 also includes 8 banks, respectively represented as bank10 ~ bank17. Correspondingly, there are 16 storage control modules 111 in the logic die, respectively represented as bank0_ctrl~bank15_ctrl. Among them, bank0_ctrl~bank7_ctrl are connected to bank00~bank07 in DRAM die0 through the inter-layer connection structure in a one-to-one correspondence, and bank8_ctrl~bank15_ctrl are connected through the layer The inter-connection structure is connected to bank10~bank17 in DRAM die1 in a one-to-one correspondence (not shown in the figure), so that bank00~bank07 and bank10~bank17 can perform read and write access at the same time.

In the third type, k is an integer greater than or equal to 2 and less than M, and the k memory array modules 121 connected to each memory control module 111 are distributed on the same memory wafer. At this time, the storage wafer is also provided with: a control logic module corresponding to the storage control module 111. The storage control module 111 is connected to the control logic module through a wafer-level interlayer connection structure. The control logic module is respectively connected to the above k The data and control buses of the storage array modules 121 are directly connected. The control logic module is used to: time-share control of the k connected storage array modules 121 to perform data writing or reading operations according to the data writing or reading signals sent by the storage control module 111.

The specific control logic of the control logic module can be set according to actual needs. As an implementation manner, chip selection control information can be set in the data writing or reading signal, and the control logic module determines the storage array module 121 to be activated this time by identifying the chip selection control information. That is to say, the data writing or reading signal includes chip selection control information and writing or reading information. The control logic module is specifically used to: determine the data to be written from the k memory array modules 121 according to the chip selection control information. or read the memory array module 121, and perform data writing or reading operations on the memory array module 121 according to the writing or reading information.

As another implementation manner, k storage array modules 121 connected to the same control logic module can also be divided into different address spaces, and the address space corresponding to the address information in the data writing or reading signal can be determined by distinguishing the address space. Storage array module 121 to be activated. That is to say, the control logic module is specifically used to: determine the storage array module 121 to be written or read from the k storage array modules 121 according to the address space corresponding to the data writing or reading signal, and determine the memory array module 121 to be written or read according to the data writing or reading signal. or read signals to perform data writing or reading operations on the memory array module 121 .

For example, as shown in Figure 6, the three-dimensional stacked chip chip2 is a two-layer structure including a logic die and a DRAM die. It is assumed that the DRAM die includes 8 banks and 4 control logic modules, that is, k=2. The first control logic module 501, the second control logic module 502, the third control logic module 503 and the fourth control logic module 504 are respectively connected to the four storage control modules in the logic die through the wafer level inter-layer connection structure: bank01_ctrl, bank23_ctrl , bank45_ctrl, bank67_ctrl are connected in one-to-one correspondence. The eight banks are respectively represented as bank0 ~ bank7. The first control logic module 501 is connected to bank0 and bank1 respectively. The second control logic module 502 is connected to bank2 and bank3 respectively. The third control logic module 503 is connected to bank4 and bank5 respectively. The four control logic modules 504 are connected to bank6 and bank7 respectively. In this way, each group of banks can be time-shared and connected to the interface in the DRAM die for connection with the corresponding storage control module 111 through the corresponding control logic module. The logic die can realize parallel reading and writing of the four banks in the DRAM die.

In the fourth method, k is an integer greater than or equal to 2 and less than M. The storage wafer layer includes k stacked storage wafers. The k storage array modules 121 connected to each storage control module 111 are respectively distributed in k Storage wafer. At this time, there are disposed between the storage control module 111 and the k connected storage array modules 121 The chip select channel is used to select one of the memory array modules 121 to perform data writing or reading operations.

For example, the three-dimensional stacked chip 100 is a three-layer structure including one logic die and two DRAM dies, namely DRAM die0 and DRAM die1. DRAM die0 includes 8 banks, represented by bank00~bank07 respectively. DRAM die1 also includes 8 banks, represented by bank10~bank17 respectively. Correspondingly, there are 8 storage control modules 111 in the logic die, respectively represented as bank0_ctrl~bank7_ctrl. Among them, bank0_ctrl is connected to bank00 in DRAM die0 and bank10 in DRAM die1 through the inter-layer connection structure, and bank2_ctrl~bank7_ctrl is connected to bank0_ctrl. similar.

Taking bank0_ctrl as an example, in order to realize time-sharing control of bank00 and bank10, a chip select channel is set up between bank0_ctrl and the connected bank00 and bank10, and banks on different DRAM dies are activated according to the chip select channel. For example, in the control channel between bank0_ctrl and bank00 and bank10, the command channel used to transmit row valid instructions can be used as the chip select channel, and other control channels and data channels between bank0_ctrl and bank00 and bank10 except the command channel can be used as the chip select channel. Can be shared.

In addition, embodiments of this specification also provide a data processing method for three-dimensional stacked chips. The three-dimensional stacked chip includes: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer. The storage wafer layer includes M storage array modules 121 , and there are N corresponding logic wafer layers. Storage control module 111. Each storage control module 111 is connected to k storage array modules 121 through a wafer-level interlayer connection structure, and is used to control the respective connected storage array modules 121 to perform data writing or reading operations, where M , N are all integers greater than or equal to 2, and N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M. Regarding the specific structure of the three-dimensional stacked chip, please refer to the relevant description above and will not be described again here.

As shown in Figure 7, the data processing method includes the following steps S701 and S702.

Step S701, receive storage control signal;

Step S702: Based on the storage control signal, use multiple storage control modules to perform data writing or reading operations in parallel on the storage array module connected to the storage control module.

Among them, the storage control signal is used to indicate the storage array module 121 to be operated for this data access and operation-related information such as commands, addresses, data, etc. The storage array module 121 to be operated may be one or multiple. When there are multiple storage array modules 121 to be operated, multiple storage control modules 111 can be used to perform data writing or reading operations on the connected storage array modules 121 in parallel.

In an optional implementation, the storage control signal may include a data writing command and writing data, and the writing address of the writing data may be determined according to the occupied space of the writing data and the storage space of the storage array module 121, so as to The storage array module 121 to be operated is determined. Specifically, in response to the occupied space of the written data being larger than the storage space of the storage array module 121, the written data is stored in the first storage array module and the second storage array module. The first storage array module and the second storage array module They are controlled by different storage control modules 111; or, the first storage array module and the second storage array module are located on different storage wafer layers and are controlled by different storage control modules 111. For the specific process, please refer to the relevant descriptions above and will not be repeated here.

For example, for the first three-dimensional stacked chip structure mentioned above, taking the exemplary structure shown in FIG. 3 as an example, assuming that the memory array modules 121 to be operated are: bank0~bank7, the processing can be completed in parallel through bank0_ctrl~bank7_ctrl. Data writing or reading operations of bank0~bank7. write with data Taking the operation as an example, you can send data operation information to bank0_ctrl~bank7_ctrl respectively. This information includes write command, write address and data information; then, the decoding and analysis module in bank0_ctrl writes the write command in the data write information and Write the address for decoding analysis. After that, bank0_ctrl sends bank activation information to bank0. After bank0 is activated, it sends the write command, write address and data information to bank0 through the data channel and control channel respectively to complete the data writing to bank0. Enter; similarly, bank1_ctrl ~ bank7_ctrl complete the data writing to bank1 ~ bank7 respectively.

For the second three-dimensional stacked chip structure mentioned above, taking the exemplary structure shown in Figure 5 as an example, assuming that the memory array modules 121 to be operated are: bank00~bank07 and bank10~bank17, the alignment can be completed in parallel through bank0_ctrl~bank15_ctrl. Data writing or reading operations for bank00~bank07 and bank10~bank17.

For the third three-dimensional stacked chip structure above, taking the exemplary structure shown in FIG. 6 as an example, assuming that the memory array modules 121 to be operated are: bank0, bank2, bank4 and bank6, through bank01_ctrl, bank23_ctrl, bank45_ctrl and bank67_ctrl And the control logic module activates bank0, bank2, bank4 and bank6, thereby completing the data writing or reading operations on bank0, bank2, bank4 and bank6 in parallel.

For the fourth three-dimensional stacked chip structure above, the above three-layer structure of logic die, DRAM die0 and DRAM die1 is also taken as an example. Assume that the memory array module 121 to be operated is: bank00~bank07 in DRAM die0, then it can Activate bank00~bank07 on DRAM die0 through the chip select channel, so that the data writing or reading operations on bank00~bank07 are completed in parallel through bank0_ctrl~bank7_ctrl.

Embodiment 2

As shown in FIG. 8 , the three-dimensional stacked chip 200 provided by the embodiment of this specification includes: a logic chip 201, a memory chip 202, and a first timing control circuit 230.

Among them, the memory chip 202 includes M memory array modules 121 (banks) for storing data. M is an integer greater than or equal to 2. The logic chip 201 and the memory chip 202 are stacked and packaged using chip stack packaging technology. Chip stack packaging technology is a technology that realizes three-dimensional heterogeneous integration of chips. Specifically, the current technology that realizes three-dimensional heterogeneous integration of logic chips 201 and memory chips 202 is mainly hybrid bonding technology. Specifically, the logic chip 201 can access multiple banks in the memory chip 202 in parallel through the wafer-level interlayer connection structure 103, such as a hybrid bonding structure, a through silicon via structure, etc. The specific structure of the logic chip 201 may refer to the structure of the logic wafer layer 101 in the first embodiment. The specific structure of the memory chip 202 may refer to the structure of the storage wafer layer 102 in the first embodiment.

N storage control modules 111 are correspondingly provided in the logic chip 201. N is also an integer greater than or equal to 2, and N is less than or equal to M. Each storage control module 111 is connected to k storage array modules 121 through the wafer-level interlayer connection structure 103, and is used to control the respective connected storage array modules 121 to perform data writing or reading operations. Among them, k is an integer greater than or equal to 1 and less than M. When reading and writing data, multiple storage control modules 111 can simultaneously control the corresponding connected storage array modules 121 to perform data reading and writing operations. In this way, the logic chip 201 can read and write in parallel one of the storage array modules connected to different storage control modules 111. 121, that is, it can at least realize parallel read and write access to the N memory array modules 121 in the memory chip 202 without being limited by packaging and hardware systems, effectively improving the data access bandwidth of DRAM, thereby conducive to improving High chip data processing speed.

For example, the three-dimensional stacked chip 200 includes a logic die and a DRAM die. Assume that the DRAM die includes 8 banks, respectively represented as bank0~bank7. Then, there are 8 storage control modules 111 correspondingly installed in the logic die, namely bank0_ctrl~bank7_ctrl. bank0_ctrl is connected to bank0 through the wafer-level interlayer connection structure 103, bank1_ctrl is connected to bank1 through the wafer-level interlayer connection structure 103, and so on, bank7_ctrl is connected to bank7 through the wafer-level interlayer connection structure 103. In this way, the logic die can access all banks in parallel through eight storage control modules 111. Of course, in another embodiment, the logic die can also be equipped with a number of storage control modules 111 less than the number of banks. For example, there are four storage control modules 111, namely bank0_ctrl~bank3_ctrl. bank0_ctrl is connected to bank0 and bank1 through the wafer level interlayer connection structure 103, bank1_ctrl is connected to bank2 and bank3 through the wafer level interlayer connection structure 103, and so on, bank3_ctrl is connected to bank6 and bank7 through the wafer level interlayer connection structure 103. connect.

In this way, the logic chip 201 can access multiple DRAM banks in the memory chip 202 in parallel, and the access efficiency is greatly increased. However, since the DRAM at this time is different from the standard DRAM particles, each storage control module 111 in the logic chip 201 accesses the bank directly and directly accesses the storage array. The access process involves the transmission of various signals needed to read and write data, such as address enable signal, address signal, data enable signal and data signal. Among them, some signals need to meet certain timing relationships. For example, the address enable signal and the address signal need to match each other. For example, as shown in Figure 9, the required establishment time range of the address signal relative to the address enable signal is -100ps to 100ps; Similarly, the data enable signal and the data signal match each other to accurately complete the data read and write operations.

In this article, the above-mentioned multi-channel signals with timing matching relationships are called multiple-channel first target signals, and the port in the storage control module 111 that outputs the above-mentioned multiple-channel first target signals is referred to as a target output end. It can be understood that the decoding and analysis module of each storage control module 111 is provided with a signal generation circuit that generates the multiple first target signals, and the above target output end is the output end of the corresponding signal generation circuit.

In order to meet the transmission timing requirements of the multiple first target signals, for example, timing control logic can be added to the target output end of each storage control module 111 in the logic chip 201 to control the target output end to output the output of the multiple first target signals. time to meet the interface timing conditions of the DRAM memory array to the above-mentioned multiple first target signals. At this time, the target output terminals of each storage control module 111 in the logic chip 201 are connected to the above-mentioned timing control logic, and the output terminals of the timing control logic are directly connected to the storage array module 121 through the wafer-level interlayer connection structure.

Considering that the memory array has high timing matching requirements for the above-mentioned multiple first target signals, for example, the establishment time range of the address signal relative to the address enable signal is required to reach -100ps to 100ps, the design of the above-mentioned timing control logic is relatively difficult. It is usually necessary to use a fully customized method to design a dedicated physical interface hard core on the logic chip 201 to meet this timing. This brings additional overhead to the design of the logic chip 201, which mostly adopts a semi-custom process, and also makes the semi-custom layout Cabling is restricted.

If the logic chip 201 contains multiple hard cores PHY to meet the interface timing requirements of the DRAM, the timing and functional verification between these hard cores and the logic of the logic chip 201 involves full customization and semi-customization co-design verification, workload and difficulty Both are very large. In addition, the existence of the hard core blocks the layout and routing of the logic chip 201, making the back-end design more difficult.

Therefore, as shown in FIG. 8 , a first timing control circuit 230 can be provided in the three-dimensional stacked chip to control the multiple first target signals output by the target output terminal to reach the memory array module based on the received clock signal. 121 to meet the interface timing conditions of the memory array module 121 for the above-mentioned multiple first target signals. This can meet the timing requirements of the storage array for these first target signals with timing matching relationships, thereby ensuring the normal operation of the three-dimensional stacked chip, and is easy to implement. There is no need to design a special physical interface hard core on the logic chip 201, which is beneficial to reducing the cost. The design difficulty of logic chip 201.

Specifically, for each storage control module 111 in the logic chip 201, a first timing control circuit 230 can be added to control the timing of signals output by the corresponding signal output ports of the storage control module 111 reaching the corresponding bank. Compared with designing a specialized physical interface hard core to strictly control the output time of these signals within a very short setup time range, this semi-custom process design is conducive to simplifying the design process and difficulty of the logic chip 201, thereby accelerating the logic chip 201 development progress.

Specifically, as shown in Figure 10, the target output terminals (S1 and S2 shown in Figure 10) of each memory control module 111 in the logic chip 201 are connected to the corresponding terminals in the memory chip 202 through the first timing control circuit 230. Storage array module 121 is connected. It should be noted that as a schematic, FIG. 10 only shows one storage control module 111 and one storage array module 121. In actual application, the specific number of storage control module 111, first timing control circuit 230 and storage array module 121 is It needs to be set according to the actual needs of three-dimensional stacked chips.

The first timing control circuit 230 is used to control the transmission timing of the multiple first target signals output from the target output terminal to the memory array module 121 based on the received clock signal, so as to meet the requirements of the memory array for the multiple first target signals. Interface timing conditions. The interface timing conditions are determined based on the timing requirements of the storage array in actual application scenarios. In this embodiment, there is a timing matching relationship between the multiple first target signals, such as the signals in the logic chip 201 that need to be output to the storage array module 121 synchronously.

For example, the above-mentioned multiple first target signals include an address enable signal and an address signal. Correspondingly, the target output end includes an address enable output end of the address enable signal generation circuit in the logic chip 201 and an address output end of the address generation circuit. . At this time, the corresponding first timing control circuit 230 needs to control the transmission timing of the address enable signal output by the address enable output terminal and the address signal output by the address output terminal to reach the memory array module 121 to meet the requirements of the memory array for both types. Signal timing requirements.

For another example, the multiple first target signals include a write data enable signal and a write data signal, that is, a data signal that needs to be written to the memory array module 121. Correspondingly, the target output terminal includes a write data enable signal of the write data enable generation circuit. energy output terminal and the data output terminal of the data supply circuit. At this time, the corresponding first timing control circuit 230 needs to control the transmission timing of the write data enable signal output by the write data enable output terminal and the write data signal output by the data output terminal to reach the memory array module 121 to meet the requirements of the memory array. Timing requirements for these two signals.

Specifically, the first timing control circuit 230 may include: a first sampling sub-circuit 231 and a second sampling sub-circuit 232. The first sampling sub-circuit 231 is provided on the logic chip 201 , and the second sampling sub-circuit 232 is provided on the memory chip 202 .

In addition, the above-mentioned three-dimensional stacked chip also includes a clock interface for providing a clock signal. The clock terminals of the first sampling sub-circuit 231 and the second sampling sub-circuit 232 are both connected to the clock interface, that is, they are controlled by the same clock signal. Among them, the clock interface can be the output interface of the internal clock circuit of the logic chip 201, or it can be an external Clock interface, this embodiment does not limit this.

The input end of the first sampling sub-circuit 231 is connected to the target output end, and is used to synchronously trigger the multiple first target signals output from the target output end to be output from the logic chip 201 under the control of the clock signal. The input end of the second sampling sub-circuit 232 is connected to the output end of the first sampling sub-circuit 231, and the output end is connected to the memory array module 121, for synchronously triggering the output from the logic chip 201 under the control of the above clock signal. The multiple first target signals are received by the storage array module 121 . During specific implementation, the first sampling sub-circuit 231 and the second sampling sub-circuit 232 may be connected through the wafer-level interlayer connection structure 103 .

In an optional implementation, the first sampling sub-circuit 231 may include: a plurality of first flip-flops arranged in one-to-one correspondence with the multiple first target signals. The input terminals of the plurality of first flip-flops are connected to the above-mentioned target output terminals, that is, connected to the output terminals of respective first target signals, the clock terminals are connected to the above-mentioned clock interface, and the output terminals are connected to the second sampling sub-circuit 232 . These first flip-flops are used to synchronously trigger multiple first target signals output from the above target output terminals to be output from the logic chip 201 at a first sampling time point based on the same clock signal.

For example, the above target output terminal includes an address enable output terminal and an address output terminal, then the first sampling subcircuit 231 includes a first flip-flop DFF0 and a first flip-flop DFF1. The input terminal of the first flip-flop DFF0 and the address enable output terminal are terminal is connected, and the input terminal of the first flip-flop DFF1 is connected with the address output terminal. In this way, the first flip-flop DFF0 and the first flip-flop DFF1 can synchronously trigger the output of the address enable signal and the address signal from the logic chip 201 to the memory chip 202 at the first sampling time point based on the same clock signal.

In an optional implementation, the second sampling sub-circuit 232 may include: a plurality of second flip-flops arranged in one-to-one correspondence with the plurality of first flip-flops. The input terminals of the plurality of second flip-flops are connected to the output terminals of the corresponding first flip-flops, the clock terminals are connected to the above-mentioned clock interfaces, and the output terminals are connected to the storage array module 121 . It should be noted that the clock terminals of the plurality of second flip-flops and the clock terminals of the plurality of first flip-flops are connected to the same clock interface and receive the same clock signal provided by the clock interface.

The plurality of second flip-flops are used to latch the first target signal received respectively, and based on the same clock signal, trigger the latched first target signal synchronously at the second sampling time point and output it to the storage array module 121 . Since the signal needs to be output from the logic chip 201 before being latched in the memory chip 202, the second sampling time point should be later than the first sampling time point.

For example, in the above example, the first sampling sub-circuit 231 includes the first flip-flop DFF0 and the first flip-flop DFF1. Correspondingly, the second sampling sub-circuit 232 may include the second flip-flop DFF2 and the second flip-flop DFF3. The input terminal of the second flip-flop DFF2 is connected to the output terminal Q0 of the first flip-flop DFF0, and the received address enable signal is latched. The input terminal of the second flip-flop DFF3 is connected to the output terminal Q1 of the first flip-flop DFF1 to latch the received address signal. In this way, the second flip-flop DFF2 and the second flip-flop DFF3 can synchronously trigger the address enable signal and the address signal to be output to the memory array module 121 at the second sampling time point based on the same clock signal, that is, they are synchronously received by the memory array module 121 . In this way, the address enable signal and the time when the address signal reaches the DRAM can be basically synchronized, and the address enable port and the address port between the logic chip 201 and the DRAM can be converted into a synchronization port.

Further, in order to ensure that the multiple channels of first target signals can all be sampled normally by the clock, the times when the multiple channels of first target signals arrive at the corresponding second flip-flop are located between the first sampling time point and the second sampling time. points, and the effective duration of the multiple first target signals is greater than or equal to the time interval between the first sampling time point and the second sampling time point. This ensures that each first target signal can be correctly sampled at the second sampling time point.

During specific implementation, the time interval between the first sampling time point and the second sampling time point can be set according to the needs of the actual application scenario. For example, the time interval can be set to one clock cycle of the above-mentioned clock signal.

It is understandable that compared to designing a specialized physical interface hard core to control the signal output time of the above target output terminals in a very short settling time range such as -100ps to 100ps, setting corresponding constraints on the relative clocks of these target output terminals, Controlling each first target signal to reach the flip-flop in the DRAM between Ta and Tb is simple and easy to implement, and effectively reduces the design requirements for the target output end of the logic chip 201.

For example, the above-mentioned first flip-flop and the second flip-flop may both adopt D flip-flops. FIG. 11 shows an exemplary transmission timing diagram of the address enable signal and the address signal. In Figure 11, time Ta represents the first sampling time point, time Tb represents the second sampling time point, CLK represents the clock signal, Q0 represents the address enable signal represented by the output of the first flip-flop DFF0, and Q1 represents the output of the first flip-flop DFF1 The address signal, Q2 represents the address enable latch signal output by the second flip-flop DFF2, and Q3 represents the address latch signal output by the second flip-flop DFF3.

It is assumed that the above-mentioned first flip-flops DFF0 and DFF1 and the second flip-flops DFF2 and DFF3 adopt rising edge triggering mode. As shown in Figure 11, at time Ta, the clock signal CLK jumps to high level, triggering the Q0 port of the first flip-flop DFF0 to output the address enable signal received by its own D port, causing the second flip-flop DFF2 to enable the address. The signal is latched, and at the same time, the Q1 port of the first flip-flop DFF1 is triggered to output the address signal received by its own D port, causing the second flip-flop DFF3 to latch the address signal. At time Tb, the clock signal CLK jumps from low level to high level, triggering the Q2 port of the second flip-flop DFF2 to output the latched address enable signal, that is, the address enable latch signal, and at the same time, triggering the second flip-flop The Q3 port of DFF3 outputs the latched address signal, that is, the address latch signal, so that the address enable signal and the address signal can be received by the DRAM synchronously. It should be noted that considering that the flip-flop takes a certain amount of time from clock triggering to output response, it takes a certain period of time after the clock triggers before the output port outputs the corresponding signal.

It can be understood that the above-mentioned second sampling sub-circuit 232 triggers the output of each first target signal synchronously. In an optional implementation, in order to better adapt to the sampling timing of the DRAM, the first timing control circuit 230 It may also include: a delay sub-circuit 233 disposed in the memory chip 202, and the output end of the second sampling sub-circuit 232 is connected to the memory array module 121 through the delay sub-circuit 233. The delay subcircuit 233 is used to adjust the relative time relationship between the first target signals output from the second sampling subcircuit 232 and arriving at the memory array module 121 to meet the above-mentioned interface timing conditions. For example, an adjustable delay unit can be set for each first target signal, and the delay time of each delay unit can be adjusted according to a preset delay rule. The preset delay rules can be set according to the interface sampling timing requirements of the specific storage array.

Still taking the above-mentioned multi-channel first target signal including the address enable signal and the address signal as an example, the first delay unit and the second delay unit can be respectively set in a targeted manner, and the input end of the first delay unit and the second trigger The output terminal Q2 of the flip-flop DFF2 is connected, the input terminal of the second delay unit is connected with the output terminal Q3 of the second flip-flop DFF3, and the output terminals of the first delay unit and the second delay unit are respectively connected with the memory array module 121 Connect the corresponding signal receiving port.

At this time, you can control the address enable latch signal output by the second flip-flop DFF2 and the address latch signal output by the second flip-flop DFF3 by respectively configuring the delay time of the first delay unit and the second delay unit. The relative time relationship that finally reaches the memory array module 121 is to meet the timing requirements of the memory array for the address enable signal and the address signal. For example, if the storage array requires the address signal to arrive before the address enable signal, and the interval time is t, then the delay time of the first delay unit can be configured to be greater than the delay time of the second delay unit, and the delay time difference is t .

Alternatively, in other embodiments of this specification, the delay unit can also be specifically set to delay a latch signal that arrives after it is needed, so as to meet the signal sampling timing requirements of the memory array. In this embodiment, the delay unit The specific implementation of sub-circuit 233 is not limited.

The technical solution provided by this embodiment can effectively synchronize the signal output by the logic chip 201 to the DRAM by setting the above-mentioned first timing control circuit 230 and inputting a synchronization clock, thereby converting the interface between the logic chip 201 and the DRAM into a synchronized state. interface.

When designing the logic chip 201, it is only necessary to set corresponding output delay constraints for the signals output to the DRAM interface according to the DRAM interface path to realize the semi-customized process design of the logic chip 201. In addition, since the memory chip 202 is a universal design and the corresponding logic chip 201 may have multiple forms, the synchronous output of the logic chip 201 is achieved by adding a second sampling sub-circuit 232 in the DRAM, which simplifies the design of the logic chip 201 The process and difficulty accelerated the development progress of logic chip 201.

Further, in an optional implementation, the above-mentioned three-dimensional stacked chip further includes: a second timing control circuit (not shown in the figure). The target input terminals of each memory control module 111 in the logic chip 201 are connected to the memory array module 121 in the memory chip 202 through the second timing control circuit. The clock end of the second timing control circuit is also connected to the above-mentioned clock interface, that is, it is controlled by the same clock signal as the first timing control circuit 230 . The second timing control circuit is used to control the transmission timing of the multiple second target signals output by the memory array module 121 to the target input terminal based on the clock signal, so as to meet the interface timing conditions of the logic chip 201 for the multiple second target signals. The multiple second target signals are multiple signals with timing matching relationships. For example, they may include a read data enable signal and a read data signal, that is, a data signal read from the memory array module 121 .

It should be noted that the specific principle of the second timing control circuit is similar to the above-mentioned first timing control circuit 230. For details, reference can be made to the relevant description of the above-mentioned first timing control circuit 230, which will not be described again here.

In an optional implementation, the target input terminal in the logic chip 201 has its own signal capture logic. At this time, compared with the first timing control circuit 230, the second timing control circuit does not need to set a delay sub-circuit. The circuit is used to adjust the relative time relationship of each second target signal arriving at the target input terminal.

By setting up the second timing control circuit and inputting a synchronization clock, the signal output by the DRAM to the logic chip 201 can be effectively synchronized, thereby converting the interface between the logic chip 201 and the DRAM into a synchronous interface.

In addition, the embodiment of this specification provides a timing control method, which can be applied to the three-dimensional stacked chip in the embodiment of FIG. 9 . As shown in Figure 12, the method includes the following steps:

Step S1201, obtain the clock signal;

Step S1202: Based on the clock signal, control the transmission timing of the multiple first target signals output from the target output terminal in the logic chip 201 to the memory array module 121 to meet the requirements of the memory array module 121 for the above multiple channels. Interface timing conditions for the first target signal.

It should be noted that the specific implementation processes of step S1201 and step S1202 may refer to the corresponding descriptions in the above chip structure embodiment, and will not be described again here.

In an optional implementation, the above step S1202 may include: based on the clock signal, synchronously triggering the multiple first target signals output from the target output terminal at the first sampling time point to be output from the logic chip 201; A target signal is latched, and based on the clock signal, each latched first target signal is synchronously triggered and output to the storage array module 121 at a second sampling time point, which is later than the first sampling time point. For the specific implementation process, reference may be made to the corresponding description in the embodiment provided in the first aspect, and details will not be described again here.

In an optional implementation, the step of outputting each first target signal of the synchronous trigger latch to the memory array module 121 at the second sampling time point may include: synchronously triggering the latch at the second sampling time point. Each channel of the stored first target signal is output; according to the preset delay rule, each channel of the output first target signal is delayed respectively, so as to calculate the relative time of each channel of the first target signal arriving at the storage array module 121 The relationship is adjusted to meet the interface timing conditions. For the specific implementation process, reference may be made to the corresponding description in the embodiment provided in the first aspect, and details will not be described again here.

In an optional implementation, the above timing control method further includes: based on the clock signal, controlling the transmission timing of the multiple second target signals output by the memory array module 121 to the target input terminal in the logic chip 201, so as to The interface timing conditions of the logic chip 201 for the multiple second target signals are met. For the specific implementation process, reference may be made to the corresponding description in the embodiment provided in the first aspect, and details will not be described again here.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described method can be referred to the corresponding process in the foregoing structural embodiment, and will not be described again here.

In this document, relational terms such as first, second, etc. are used only to distinguish one entity or operation from another entity or operation and do not necessarily require or imply the existence of any such entity or operation between these entities or operations. Actual relationship or sequence. Furthermore, the terms "comprises," "comprises," or any other variation thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element. The term "plurality" means more than two, including two or more than two.

Although the preferred embodiments of this specification have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this specification.

Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. In this way, if these modifications and variations of this specification fall within the scope of the claims of this specification and equivalent technologies, this specification is also intended to include these modifications and variations.

Claims (20)

1. A three-dimensional stacked chip, which includes: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer,

   The storage wafer layer includes M storage array modules, and N storage control modules are correspondingly provided in the logic wafer layer. Each of the storage control modules is connected to k storage array modules through a wafer-level interlayer connection structure. Array module connections are used to control the respective connected storage array modules to perform data writing or reading operations,

   Among them, M and N are both integers greater than or equal to 2, and N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M.
2. The three-dimensional stacked chip according to claim 1, wherein each of the storage control modules is directly connected to the data and control bus of one of the storage array modules through the wafer-level interlayer connection structure, and different storage arrays The module's data and control buses are independent of each other.
3. The three-dimensional stacked chip according to claim 1, wherein k is an integer greater than or equal to 2 and less than M, k memory array modules are distributed on the same memory wafer, and the memory wafer layer further includes: The above storage control modules correspond to the control logic modules set one by one.

   The storage control module is connected to the control logic module through a wafer-level interlayer connection structure, and the control logic module is directly connected to the data and control buses of k storage array modules,

   The control logic module is configured to: time-share control of k storage array modules to perform data writing or reading operations according to the data writing or reading signals sent by the storage control module.
4. The three-dimensional stacked chip according to claim 3, wherein the data writing or reading signal includes chip selection control information and writing or reading information, and the control logic module is specifically configured to: control according to the chip selection The information determines the storage array module to be written or read from the k storage array modules, and performs data writing or reading operations on the storage array module according to the writing or reading information.
5. The three-dimensional stacked chip according to claim 3, wherein the control logic module is specifically configured to: determine the data to be written from the k storage array modules according to the address space corresponding to the data writing or reading signal. or read out the memory array module, and perform data writing or reading operations on the memory array module according to the data writing or reading signals.
6. The three-dimensional stacked chip according to claim 1, wherein k is an integer greater than or equal to 2 and less than M, and the storage wafer layer includes k stacked storage wafers, connected to one of the storage control modules. k memory array modules are respectively distributed on k memory wafers,

   A chip select channel is provided between the storage control module and the k storage array modules for selecting one of the storage array modules to perform the data writing or reading operation.
7. The three-dimensional stacked chip according to any one of claims 1 to 6, wherein the logic wafer layer is further provided with a processing module, and each of the storage control modules is connected to the processing module,

   The processing module is used to determine the storage array module to be operated and send data operation information to the storage control module connected to the storage array module to be operated;

   Each storage control module is provided with a decoding and analysis module. The decoding and analysis module decodes and analyzes the commands and addresses in the data operation information to write data to the storage array module to be operated. input or read operation.
8. The three-dimensional stacked chip according to any one of claims 7, wherein the processing module receives a data writing command and writing data, and determines the location of the data according to the occupied space of the writing data and the storage space of the storage array module. The write address of the write data is used to determine the storage array module to be operated.
9. The three-dimensional stacked chip according to claim 8, wherein,

   In response to the occupied space of the written data being larger than the storage space of the storage array module, the processing module stores the written data in the first storage array module and the second storage array module, and the first storage module The array module and the second storage array module are controlled by different storage control modules; or

   The first storage array module and the second storage array module are located on different storage wafer layers and are controlled by different storage control modules.
10. The three-dimensional stacked chip according to any one of claims 1 to 6, wherein the inter-layer connection structure includes a data channel and a control channel, the data channel is used to transmit writing or reading data signals, The control channel is used to transmit control signals that control data writing or reading.
11. The three-dimensional stacked chip according to claim 10, wherein the control signal includes a command signal and an address signal;

    Wherein, the command signal includes: a row operation enable signal, a column operation enable signal and a write data control signal;

    The address signals include row address signals and column address signals.
12. The three-dimensional stacked chip according to claim 1, further comprising:

    A first timing control circuit. The target output end in the logic wafer layer is connected to the memory array module in the storage wafer layer through the first timing control circuit. The first timing control circuit is used to receive The received clock signal controls the transmission timing of the multiple first target signals output from the target output terminal to the memory array module to meet the interface timing conditions of the memory array module for the multiple first target signals.
13. The three-dimensional stacked chip according to claim 12, wherein the first timing control circuit includes:

    A first sampling sub-circuit is provided on the logic wafer layer. The input end of the first sampling sub-circuit is connected to the target output end for synchronously triggering the target output under the control of the clock signal. Multiple first target signals output from the terminal are output from the logic wafer layer;

    A second sampling subcircuit is provided on the storage wafer layer. The input end of the second sampling subcircuit is connected to the output end of the first sampling subcircuit, and the output end is connected to the storage array module. Under the control of the clock signal, multiple first target signals output from the logic wafer layer are synchronously triggered and received by the memory array module;

    The three-dimensional stacked chip further includes a clock interface for providing the clock signal, and clock terminals of the first sampling subcircuit and the second sampling subcircuit are both connected to the clock interface.
14. The three-dimensional stacked chip according to claim 13, wherein the first sampling sub-circuit includes: a plurality of first flip-flops arranged in one-to-one correspondence with the multiple first target signals,

    The input terminals of the plurality of first flip-flops are connected to the target output terminal, the clock terminals are connected to the clock interface, and the output terminals are connected to the second sampling sub-circuit,

    The plurality of first flip-flops are used to trigger the synchronously at a first sampling time point based on the clock signal. The multiple first target signals output from the target output terminal are output from the logic wafer layer.
15. The three-dimensional stacked chip according to claim 14, wherein the second sampling sub-circuit includes: a plurality of second flip-flops arranged in one-to-one correspondence with the plurality of first flip-flops,

    The input terminals of the plurality of second flip-flops are connected to the output terminals of the corresponding first flip-flops, the clock terminals are connected to the clock interface, and the output terminals are connected to the storage array module,

    The plurality of second flip-flops are used to latch the first target signal received respectively, and based on the clock signal, synchronously trigger the latched first target signal to be output to the storage array at a second sampling time point. module, the second sampling time point is later than the first sampling time point.
16. The three-dimensional stacked chip according to claim 15, wherein the times when the multiple first target signals arrive at the corresponding second flip-flop are all between the first sampling time point and the second sampling time point, and The effective durations of the multiple first target signals are all greater than or equal to the time interval between the first sampling time point and the second sampling time point.
17. The three-dimensional stacked chip according to claim 16, wherein the time interval between the first sampling time point and the second sampling time point is one clock cycle of the clock signal.
18. The three-dimensional stacked chip according to claim 13, wherein the first timing control circuit further includes: a delay sub-circuit disposed in the storage wafer layer,

    The output end of the second sampling subcircuit is connected to the memory array module through the delay subcircuit, and the delay subcircuit is used to adjust each first target signal output from the second sampling subcircuit. The relative time relationship of arrival at the storage array module is to satisfy the interface timing conditions.
19. The three-dimensional stacked chip according to claim 12, further comprising: a second timing control circuit,

    The target input end in the logic wafer layer is connected to the memory array module in the storage wafer layer through the second timing control circuit, and the second timing control circuit is used to control all the processes based on the clock signal. The transmission timing of the multiple second target signals output by the memory array module reaching the target input terminal is to meet the interface timing conditions of the logical wafer layer to the multiple second target signals.
20. A data processing method for three-dimensional stacked chips, wherein the three-dimensional stacked chip includes: a storage wafer layer and a logic wafer layer stacked with the storage wafer layer, and the storage wafer layer includes M storage arrays Module, N storage control modules are correspondingly provided in the logic wafer layer, each of the storage control modules is connected to k storage array modules through a wafer-level interlayer connection structure, and is used to control all connected The storage array module performs data writing or reading operations, wherein M and N are both integers greater than or equal to 2, and N is less than or equal to M, and k is an integer greater than or equal to 1 and less than M; the method includes :

    Receive storage control signals;

    Based on the storage control signal, multiple storage control modules are used to perform data writing or reading operations on the storage array module connected to the storage control module in parallel.