CN117437948B - Three-dimensional stacked memory architecture, processing method thereof and memory - Google Patents
Three-dimensional stacked memory architecture, processing method thereof and memory Download PDFInfo
- Publication number
- CN117437948B CN117437948B CN202311772980.2A CN202311772980A CN117437948B CN 117437948 B CN117437948 B CN 117437948B CN 202311772980 A CN202311772980 A CN 202311772980A CN 117437948 B CN117437948 B CN 117437948B
- Authority
- CN
- China
- Prior art keywords
- memory
- storage array
- layer
- array
- ras feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 58
- 239000010703 silicon Substances 0.000 claims abstract description 58
- 238000003491 array Methods 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 11
- 238000012360 testing method Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 14
- 238000013461 design Methods 0.000 description 11
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 10
- 238000004891 communication Methods 0.000 description 6
- 238000004590 computer program Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
Embodiments of the present disclosure provide a three-dimensional stacked memory architecture, a processing method thereof, and a memory. The three-dimensional stacked memory architecture includes: n storage array layers, each storage array layer comprises M storage arrays, H RAS feedback circuits and M silicon through holes; and the N storage array layers are sequentially stacked on the logic control layer along the vertical direction. The M storage arrays in each storage array layer are divided into H storage array groups, and the H storage array groups are respectively and correspondingly connected with H RAS feedback circuits in the layer; in the storage array group correspondingly connected with each RAS feedback circuit, only one storage array and a logic control layer transmit RAS feedback signals; in the same storage array in the same vertical direction, only one storage array and a logic control layer transmit RAS feedback signals; the RAS feedback circuits in the adjacent memory array layers are connected to the logic control layer through silicon through holes;and a=1 when M/N has a remainder, and a=0 when M/N has no remainder.
Description
Technical Field
Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a three-dimensional stacked memory architecture, a processing method thereof, and a memory.
Background
DRAM (Dynamic Random Access Memory ) is a common memory. The memory cell is composed of a transistor and a capacitor, and a plurality of basic memory cells form a memory array. As shown in fig. 1, each of the word lines and the bit lines is connected to a plurality of memory cells, the word lines are horizontal, the bit lines are vertical, and the word lines and the bit lines are not connected. When the word line is high, the transistor in the memory cell is turned on, the capacitor is connected to the bit line, and data stored in the capacitor is transferred through the bit line.
When the DRAM chip is designed by adopting the three-dimensional stacking technology, the structure is shown in fig. 2, the upper layer is a memory array layer, the logic control circuit is at the bottommost layer, and the signal channels between the layers are realized by a through silicon via (Through Silicon Vias, TSV) (not shown in the figure) vertical interconnection technology so as to transmit signals of the stacked chip in the vertical direction. In addition, some protection circuits, such as an RAS (RowAddress Select, row select signal) feedback circuit, are added to the DRAM chip, and the RAS feedback signal is present in each memory array and operates independently. RAS feedback signals are transmitted to the logic control circuit from top to bottom through the through holes, and redundant through holes are usually added in the design in order to avoid the failure of the whole chip caused by incapability of transmitting signals after the through holes of the current layer are damaged. However, the process difficulty of the through silicon vias is high, the cost management and control requirement is high, and as the number of the required through silicon vias increases, the difficulty of circuit design and manufacture is increased, and the reliability of the chip is reduced.
Disclosure of Invention
The embodiment of the disclosure aims to provide a three-dimensional stacked memory architecture, a processing method thereof and a memory, and solves the problems of increased difficulty in circuit design and manufacture and reduced chip reliability caused by excessive number of redundant silicon through holes in the prior art.
To achieve the above object, a first aspect of embodiments of the present disclosure provides a three-dimensional stacked memory architecture, including: each storage array layer comprises M storage arrays, H RAS feedback circuits and M silicon through holes respectively corresponding to the M storage arrays; and the N storage array layers are sequentially stacked on the logic control layer along the vertical direction. The M storage arrays in each storage array layer are divided into H storage array groups, and the H storage array groups are respectively and correspondingly connected with the H RAS feedback circuits in the storage array layer; in the storage array group correspondingly connected with each RAS feedback circuit, only one storage array transmits RAS feedback signals with the logic control layer; in the same vertical directionIn the same memory array, only one memory array transmits RAS feedback signals with the logic control layer; the RAS feedback circuits in adjacent storage array layers are connected to the logic control layer through silicon through holes;and a=1 when M/N has a remainder, and a=0 when M/N has no remainder.
In some embodiments of the present disclosure, each M/N storage array in each storage array layer is a group when M/N has no remainder, each storage array in each storage array layer when M/N has a remainderThe number of memory arrays is one, and the remainder is one.
In some embodiments of the present disclosure, the layout of each of the N storage array layers is the same.
In some embodiments of the present disclosure, the same memory array layout in the N memory array layers is in the same vertical direction.
In some embodiments of the present disclosure, the RAS feedback circuit layouts of the N memory array layers, which are correspondingly connected to the same memory array group, are in the same vertical direction.
In some embodiments of the present disclosure, the layout of through silicon vias in the N memory array layers corresponding to the same memory array is in the same vertical direction.
In some embodiments of the present disclosure, the M memory arrays in each memory array layer are laid out in a centrosymmetric manner.
A second aspect of the embodiments of the present disclosure provides a processing method for processing the three-dimensional stacked memory architecture according to the first aspect of the embodiments of the present disclosure, including: in the chip testing process, obtaining the damage condition of through silicon vias corresponding to the same storage array in the same vertical direction; and determining any one uncorrupted through silicon via as a path for transmitting an RAS feedback signal between the memory array and the logic control layer in the uncorrupted through silicon vias corresponding to the same memory array in the same vertical direction, and simultaneously, only one memory array and the logic control layer in the memory array group correspondingly connected with each RAS feedback circuit are required to transmit the RAS feedback signal.
A third aspect of the disclosed embodiments provides a memory comprising: a three-dimensional stacked memory architecture according to the first aspect of an embodiment of the present disclosure.
In some embodiments of the present disclosure, the memory is a dynamic random access memory, DRAM.
A fourth aspect of the disclosed embodiments provides a processing device for processing the three-dimensional stacked memory architecture according to the first aspect of the disclosed embodiments. The processing device includes at least one processor; and at least one memory storing a computer program. The computer program, when executed by at least one processor, causes the processing device to perform the processing method according to the second aspect of the embodiments of the present disclosure.
Additional features and advantages of embodiments of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the embodiments of the disclosure. In the drawings:
FIG. 1 is a schematic diagram of the basic structure of a memory array;
FIG. 2 is a schematic diagram of a DRAM chip employing a three-dimensional stacked architecture;
FIG. 3 is an exemplary diagram of a 4-layer three-dimensional stacked memory architecture, for example, DDR4 chips;
FIG. 4 is an exemplary diagram of a three-dimensional stacked memory architecture according to an embodiment of the present disclosure;
FIG. 5 is a schematic flow chart of a processing method for processing a three-dimensional stacked memory architecture according to an embodiment of the disclosure;
FIG. 6 is a schematic block diagram of a processing device according to an embodiment of the present disclosure;
FIG. 7 is an exemplary diagram of a plan layout of each memory array in a 4-tier three-dimensional stacked memory architecture, for DDR4 example, in accordance with an embodiment of the present disclosure;
FIG. 8 is an exemplary diagram of a layout of RAS feedback circuitry in a 4-layer three-dimensional stacked memory architecture, for DDR4 example, in accordance with an embodiment of the present disclosure;
fig. 9 is a schematic diagram of a path for transmitting RAS feedback signals between each memory array and a logic control layer in a 4-layer three-dimensional stacked memory architecture, for example DDR4, according to an embodiment of the present disclosure.
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
FIG. 3 illustrates an example diagram of a 4-layer three-dimensional stacked memory architecture, for example, DDR4 chips. As shown in fig. 3, where the DDR4 chip includes 4 BGs and 4 BAs, i.e., 16 memory arrays, placing 16 BGBAs for one BG per layer, each layer will increase by 4 RAS feedback signals from layer 0. In addition, the circuit design of each layer is asymmetric, the number of through silicon vias is increased step by step, and each layer needs to be designed with a through silicon via layout separately. The greater the number of layers, the greater the number of through silicon vias required to reach the bottom layer and the greater the number of redundant through silicon vias required for repair. The three-dimensional stacked memory architecture example described above not only is the circuit design for each memory array layer asymmetric, requiring additional circuit design, but the greater need for redundant through silicon vias also results in increased circuit area.
To solve the above-described problems, an embodiment of the present disclosure provides a three-dimensional stacked memory architecture, as shown in fig. 4, the three-dimensional stacked memory architecture 400 includes: and N storage array layers, wherein each storage array layer comprises M storage arrays, H RAS feedback circuits and M through silicon vias respectively corresponding to the M storage arrays, namely, in each storage array layer, the number of the storage arrays is the number of the through silicon vias. And the N storage array layers are sequentially stacked on the logic control layer along the vertical direction. The M memory arrays in each memory array layer are divided into H memory array groups, the H RAS feedback circuits in the memory array layer are correspondingly connected respectively, and the M through silicon vias are correspondingly divided into H groups along with the M memory arrays. In the memory array group to which each RAS feedback circuit is correspondingly connected, there is only one memory array to which the RAS feedback signal is transferred between the logic control layer. Meanwhile, in the same memory array in the same vertical direction, only one memory array and the logic control layer transmit RAS feedback signals. The RAS feedback circuits in adjacent memory array layers are connected to the logic control layer through silicon through holes. The number of groups of RAS feedback circuits included in each memory array layer and the number of groups into which M memory arrays are divided can be obtained by the following formula (1):
formula (1)
Where a=1 when M/N has a remainder and a=0 when M/N has no remainder.
In the implementation process, the memory array layer in the three-dimensional stacked memory architecture 400 may be any number of layers, and is limited by the process level, the number of stacked layers is generally less than 16, and the more the number of stacked layers, the larger the capacity of the three-dimensional stacked memory architecture. Assuming that the capacity of one layer is 1Gb, 4 layers are stacked to be 4Gb.
In the embodiment of the present disclosure, when the three-dimensional stacked memory architecture 400 designs N memory array layers, N memory arrays are grouped in each memory array layer, and the group of memory arrays is correspondingly connected to one RAS feedback circuit until all M memory arrays are grouped. That is, when M/N has no remainder, each M/N storage array in each storage array layer is a group, if M cannot divide N completely, the remainder of M divided by N is a group, that is, when M/N has remainder, each storage array in each storage array layerThe storage array groups formed by the same remainder storage arrays are correspondingly connected with another RAS feedback circuit, so that H storage array groups are finally obtained and correspondingly connected with the H RAS feedback circuits.
In the embodiment of the disclosure, the layout of each storage array layer in the N storage array layers is the same, that is, the layout of the storage array, the RAS feedback circuit and the through silicon via in each storage array layer is the same, so that each storage array layer is ensured to be reusable, no additional circuit design is needed, and the cost is saved.
In the embodiment of the disclosure, the same storage array layout in the N storage array layers is in the same vertical direction. Meanwhile, the RAS feedback circuits of the N storage array layers, which are correspondingly connected with the same storage array group, are arranged in the same vertical direction, and the through silicon vias of the N storage array layers, which are correspondingly connected with the same storage array group, are correspondingly arranged in the same vertical direction, so that the same storage array can share the N RAS feedback circuits in the same vertical direction. Although the storage arrays in each storage array group have a connection relationship with the corresponding RAS feedback circuits, the same storage array in the same vertical direction also has a connection relationship with the RAS feedback circuits, but in particular, which storage array transmits the RAS feedback signals to the logic control layer, so that only one RAS feedback circuit path needs to be reserved for the same storage array in the same vertical direction, and the same storage array needs to be determined according to the damage condition of the silicon through holes corresponding to each storage array in the chip test process, thereby ensuring that the read-write operation of other addresses of the storage array can not be performed during the read-write operation of a certain address in the same storage array. Meanwhile, the same storage arrays in the same vertical direction correspond to one through silicon via respectively, the number of tolerable through silicon via damage is greatly increased, and the reliability of the chip is improved.
In addition, in the embodiment of the present disclosure, the layout form in each storage array layer is not limited, and the M storage arrays in each storage array layer are preferably laid out in a center-symmetrical manner.
According to the embodiment of the disclosure, the memory arrays in different memory array layers are identical in layout, RAS feedback circuits are identical in layout, and silicon through holes are identical in layout, so that multiplexing of each layer of circuit is realized, the circuit redesign cost is reduced, and the structure in the vertical direction is symmetrical and easy to stack. In addition, occupation of the redundant through silicon vias to circuit area is reduced, the number of tolerable through silicon vias is larger than that of single redundant through silicon vias, and reliability of the chip is improved.
Fig. 5 shows a schematic flow chart of a processing method 500 for processing a three-dimensional stacked memory architecture, according to an embodiment of the disclosure, comprising the steps of:
step S501, obtaining the damage condition of the through silicon vias corresponding to the same storage array in the same vertical direction in the chip test process;
step S502, determining any one undamaged through silicon via among the undamaged through silicon vias corresponding to the same memory array in the same vertical direction as a path for transmitting an RAS feedback signal between the memory array and the logic control layer, and simultaneously satisfying that only one memory array and the logic control layer transmit the RAS feedback signal in the memory array group correspondingly connected to each RAS feedback circuit.
In order to determine which layer of RAS feedback circuit is used by the same memory array in the same vertical direction to transmit an RAS feedback signal to the logic control layer, in the embodiment of the present disclosure, in the process of performing a chip test on the three-dimensional stacked memory architecture 400, a damage condition of a through silicon via corresponding to the same memory array in the same vertical direction is obtained, if more than two through silicon vias corresponding to the same memory array are not damaged, any one of the undamaged through silicon vias may be used as a path for transmitting an RAS feedback signal between the memory array and the logic control layer, and it is required to simultaneously satisfy that only one memory array and the logic control layer transmit an RAS feedback signal in a memory array group correspondingly connected to each RAS feedback circuit. That is, for a three-dimensional stacked memory architecture 400 having N memory array layers, only M paths of RAS feedback signals are ultimately required.
The embodiment of the disclosure provides a combination form of various signal connections by flexibly adjusting the paths for transmitting RAS feedback signals, the number of tolerable silicon through holes is larger than that of single redundant silicon through holes, and the reliability of the chip is improved.
Embodiments of the present disclosure also provide a memory. The memory includes a three-dimensional stacked memory architecture 400 as shown in fig. 4.
Wherein, the memory is DRAM.
Fig. 6 shows a schematic block diagram of a processing device 600 according to an embodiment of the disclosure. The processing device 600 is used to process a three-dimensional stacked memory architecture according to an embodiment of the present disclosure. As shown in fig. 6, the apparatus 600 may include a processor 610 and a memory 620 storing a computer program. The computer program, when executed by the processor 610, causes the apparatus 600 to perform the steps of the method 500 as shown in fig. 5. In one example, the apparatus 600 may be a computer device or a central processor. The device 600 can obtain the damage condition of the through silicon vias corresponding to the same memory array in the same vertical direction during the chip test process. The apparatus 600 may determine any one of the undamaged through silicon vias corresponding to the same memory array in the same vertical direction as a path for transmitting an RAS feedback signal between the memory array and the logic control layer, and simultaneously satisfy that only one memory array and the logic control layer transmit an RAS feedback signal in the memory array group correspondingly connected to each RAS feedback circuit.
In embodiments of the present disclosure, processor 610 may be, for example, a Central Processing Unit (CPU), a microprocessor, a Digital Signal Processor (DSP), a processor of a multi-core based processor architecture, or the like. Memory 620 may be any type of memory implemented using data storage technology including, but not limited to, random access memory, read only memory, semiconductor-based memory, flash memory, disk storage, and the like.
Further, in an embodiment of the present disclosure, the apparatus 600 may also include an input device 630 for inputting an instruction to start a test and inputting a communication instruction of a through silicon via, which is a path for transmitting an RAS feedback signal with the logic control layer. In addition, the apparatus 600 may further include an output device 640 for outputting damage conditions of through silicon vias corresponding to the same memory array in the same vertical direction.
In other embodiments of the present disclosure, there is also provided a computer readable storage medium storing a computer program, wherein the computer program is capable of implementing the steps of the method as shown in fig. 5 when being executed by a processor.
For a better understanding of the disclosed embodiments, DDR4 is described below as an example. Where DDR4 includes 4 BGs and 4 BAs, i.e., 16 independent memory arrays BGiBAj, where i=1, 2,3,4, j=1, 2,3,4. Taking a stacked 4-layer memory architecture as an example, as shown in fig. 7, the same memory array BGiBAj is placed in the same vertical direction. Each layer is composed of 16 memory arrays BGiBAj, and the circuit layout of different layers is the same without additional circuit design. Because of the 4-layer architecture, each layer has 4 memory arrays as a group, and each group of memory arrays corresponds to one RAS feedback circuit. To facilitate circuit layout, the same BG is divided into a group, i.e., BG0BAj is a group, BG1BAj is a group, BG2BAj is a group, and BG3BAj is a group. Taking BG3BAj as a group of memory arrays, as shown in fig. 8, the memory arrays BG3BAj in each group of memory arrays are connected to a RAS feedback circuit (denoted by RAS in the figure), and connected to the logic control layer through silicon vias corresponding to each memory array BG3 BAj. Since the same memory array is connected with the RAS feedback circuits in the same vertical direction, only RAS feedback signals are transmitted between the RAS feedback circuit of one layer and the logic control layer. The specific memory array uses the RAS feedback circuit of which layer, and needs to be determined according to the damage condition of the through silicon vias corresponding to the same memory array in the same vertical direction in the chip test process. After the damage condition of the through silicon vias corresponding to the same storage arrays in the same vertical direction is obtained, any one undamaged through silicon via is determined to be used as a path for transmitting an RAS feedback signal between the storage array and the logic control layer in the undamaged through silicon vias corresponding to the same storage arrays in the same vertical direction, and meanwhile, the condition that only one storage array and the logic control layer transmit the RAS feedback signal in the storage array group correspondingly connected with each RAS feedback circuit is met. As an example provided in fig. 9, for example, BG3BA0 of layer 0 communicates with the RAS feedback circuit of the layer, BG3BA3 of layer 1 communicates with the RAS feedback circuit of the layer, BG3BA2 of layer 2 communicates with the RAS feedback circuit of the layer, and BG3BA1 of layer 3 communicates with the RAS feedback circuit of the layer.
The above-described 4-tier architecture is provided as an example only, and when DDR4 stacks a 2-tier architecture, there are 2 memory arrays in each tier as a group, each group being correspondingly connected to one RAS feedback circuit, there being 8 groups of RAS feedback circuits in each tier. After chip testing, it is determined whether the same memory array in the same vertical direction in layer 2 is in communication with the RAS feedback circuit in the first layer or in communication with the RAS feedback circuit in the second layer.
When DDR4 stacks a 6-layer architecture, 6 storage arrays are used as a group in each layer, namely 6 storage arrays in each layer are used as a group, 6 storage arrays are used as another group, the last 4 storage arrays are used as the last group, each group is correspondingly connected with an RAS feedback circuit, and 3 groups of RAS feedback circuits exist in each layer. After chip testing, the same memory array in the same vertical direction in the 6 layers is determined to be in communication with which RAS feedback circuit in the 6 layers in the group of 6 memory arrays. In the memory array with 4 memory arrays as a group, only the circuit which is finally required to be communicated is determined from the 4-layer RAS feedback circuits, and the rest two-layer RAS feedback circuits can be omitted.
In summary, through the embodiments of the present disclosure, each layer of circuit design is the same, so that the cost of circuit redesign is reduced, and the structure is symmetrical and easy to stack. Meanwhile, the silicon through holes are identical in layout, the purpose of repairing the feedback signal path can be achieved by adjusting the connection relation, and occupation of the redundant silicon through holes to the area is reduced. Through flexible adjustment of RAS signal communication relation, various RAS signal communication arrangement combinations are provided, the number of tolerable silicon through holes is larger than that of single redundant silicon through hole designs, and the reliability of the chip is improved.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (6)
1. A three-dimensional stacked memory architecture, comprising:
each storage array layer comprises M storage arrays, H row selection signal RAS feedback circuits and M silicon through holes respectively corresponding to the M storage arrays;
the N storage array layers are sequentially stacked on the logic control layer along the vertical direction; wherein,
the M storage arrays in each storage array layer are divided into H storage array groups, and the H storage array groups are respectively and correspondingly connected with the H RAS feedback circuits in the storage array layer;
in the storage array group correspondingly connected with each RAS feedback circuit, only one storage array transmits RAS feedback signals with the logic control layer;
in the same storage array in the same vertical direction, only one storage array and the logic control layer transmit RAS feedback signals;
the RAS feedback circuits in adjacent storage array layers are connected to the logic control layer through silicon through holes;
wherein,and +.>When M/N has no remainder +.>，
The layout of each storage array layer in the N storage array layers is the same, the same storage array layout in the N storage array layers is in the same vertical direction, the RAS feedback circuit layout corresponding to the same storage array group in the N storage array layers is in the same vertical direction, and the through silicon via layout corresponding to the same storage array in the N storage array layers is in the same vertical direction.
2. The three-dimensional stacked memory architecture of claim 1, wherein each M/N memory array in each memory array layer is a group when M/N has no remainder, each memory array in each memory array layer when M/N has a remainderThe number of memory arrays is one, and the remainder is one.
3. The three-dimensional stacked memory architecture of claim 1, wherein said M memory arrays in each memory array layer are arranged in a centrosymmetric manner.
4. A processing method for processing the three-dimensional stacked memory architecture of any one of claims 1 to 3, comprising:
in the chip testing process, obtaining the damage condition of through silicon vias corresponding to the same storage array in the same vertical direction;
and determining any one uncorrupted through silicon via as a path for transmitting an RAS feedback signal between the memory array and the logic control layer in the uncorrupted through silicon vias corresponding to the same memory array in the same vertical direction, and simultaneously, only one memory array and the logic control layer in the memory array group correspondingly connected with each RAS feedback circuit are required to transmit the RAS feedback signal.
5. A memory, comprising: a three-dimensional stacked memory architecture as claimed in any one of claims 1 to 3.
6. The memory of claim 5, wherein the memory is a dynamic random access memory, DRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311772980.2A CN117437948B (en) | 2023-12-21 | 2023-12-21 | Three-dimensional stacked memory architecture, processing method thereof and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311772980.2A CN117437948B (en) | 2023-12-21 | 2023-12-21 | Three-dimensional stacked memory architecture, processing method thereof and memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117437948A CN117437948A (en) | 2024-01-23 |
| CN117437948B true CN117437948B (en) | 2024-04-09 |
Family
ID=89548419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311772980.2A Active CN117437948B (en) | 2023-12-21 | 2023-12-21 | Three-dimensional stacked memory architecture, processing method thereof and memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117437948B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117809702B (en) * | 2024-02-29 | 2024-05-28 | 西安紫光国芯半导体股份有限公司 | Three-dimensional stacking structure and control method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9443561B1 (en) * | 2015-05-21 | 2016-09-13 | Advanced Micro Devices, Inc. | Ring networks for intra- and inter-memory I/O including 3D-stacked memories |
| CN112313613A (en) * | 2018-09-28 | 2021-02-02 | 英特尔公司 | Oscillator circuit for facilitating in-memory computations |
| CN114709205A (en) * | 2022-06-02 | 2022-07-05 | 西安紫光国芯半导体有限公司 | Three-dimensional stacked chip and data processing method thereof |
| CN115842013A (en) * | 2023-02-13 | 2023-03-24 | 浙江力积存储科技有限公司 | Three-dimensional stacked memory and data processing method thereof |
| CN116266463A (en) * | 2021-12-16 | 2023-06-20 | 西安紫光国芯半导体有限公司 | Three-dimensional storage unit, storage method, three-dimensional storage chip assembly and electronic equipment |
| CN116529875A (en) * | 2020-10-22 | 2023-08-01 | Arm有限公司 | TSV coupled integrated circuits and methods |
| CN116722008A (en) * | 2023-05-10 | 2023-09-08 | 浙江力积存储科技有限公司 | Three-dimensional memory architecture and memory |
| CN116741227A (en) * | 2023-08-09 | 2023-09-12 | 浙江力积存储科技有限公司 | Three-dimensional memory architecture, operation method thereof and memory |
| CN116864469A (en) * | 2022-03-25 | 2023-10-10 | 长鑫存储技术有限公司 | Through silicon via array structure and semiconductor memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5448698B2 (en) * | 2009-10-09 | 2014-03-19 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and test method thereof |
| US8493089B2 (en) * | 2011-04-06 | 2013-07-23 | International Business Machines Corporation | Programmable logic circuit using three-dimensional stacking techniques |
-
2023
- 2023-12-21 CN CN202311772980.2A patent/CN117437948B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9443561B1 (en) * | 2015-05-21 | 2016-09-13 | Advanced Micro Devices, Inc. | Ring networks for intra- and inter-memory I/O including 3D-stacked memories |
| CN112313613A (en) * | 2018-09-28 | 2021-02-02 | 英特尔公司 | Oscillator circuit for facilitating in-memory computations |
| CN116529875A (en) * | 2020-10-22 | 2023-08-01 | Arm有限公司 | TSV coupled integrated circuits and methods |
| CN116266463A (en) * | 2021-12-16 | 2023-06-20 | 西安紫光国芯半导体有限公司 | Three-dimensional storage unit, storage method, three-dimensional storage chip assembly and electronic equipment |
| CN116864469A (en) * | 2022-03-25 | 2023-10-10 | 长鑫存储技术有限公司 | Through silicon via array structure and semiconductor memory |
| CN114709205A (en) * | 2022-06-02 | 2022-07-05 | 西安紫光国芯半导体有限公司 | Three-dimensional stacked chip and data processing method thereof |
| CN115842013A (en) * | 2023-02-13 | 2023-03-24 | 浙江力积存储科技有限公司 | Three-dimensional stacked memory and data processing method thereof |
| CN116722008A (en) * | 2023-05-10 | 2023-09-08 | 浙江力积存储科技有限公司 | Three-dimensional memory architecture and memory |
| CN116741227A (en) * | 2023-08-09 | 2023-09-12 | 浙江力积存储科技有限公司 | Three-dimensional memory architecture, operation method thereof and memory |
Non-Patent Citations (3)
| Title |
|---|
| Comprehensive_comparison_of_3D-TSV_integrated_solid-state_drives_SSDs_with_storage_class_memory_and_NAND_flash_memory;Shogo Hachiya;《IEEE 2015 International 3D Systems Integration Conference》;20151123;第TS6.2.1-TS6.2.5页 * |
| 三维片上网络TSV复用容错策略;欧阳一鸣;杨懿泽;梁华国;黄正峰;;电子测量与仪器学报;20130315(第03期);全文 * |
| 故障芯片重利用的三维存储器成品率提高方法;刘军;王堂亚;任福继;;微电子学与计算机;20161005(第10期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117437948A (en) | 2024-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10846169B2 (en) | Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices | |
| US8040745B2 (en) | Stacked memory and fuse chip | |
| CN117437948B (en) | Three-dimensional stacked memory architecture, processing method thereof and memory | |
| US7763496B2 (en) | Stacked semiconductor memory device and control method thereof | |
| US8891322B2 (en) | Memory system with a layer comprising a dedicated redundancy area | |
| JP4534132B2 (en) | Stacked semiconductor memory device | |
| US7649760B2 (en) | Semiconductor memory device having dummy sense amplifiers and methods of utilizing the same | |
| CN107045894B (en) | Stacked semiconductor device and system including the same | |
| US11113162B2 (en) | Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface | |
| KR102399014B1 (en) | Shared error detection and correction memory | |
| TWI529740B (en) | Stacked memory structure with redundancy configuration and method thereof | |
| CN212675921U (en) | Memory device and memory system | |
| TWI737020B (en) | Tsv redundancy and tsv test select scheme | |
| CN106782666B (en) | Three-dimensional stacked memory | |
| US10460769B2 (en) | Memory device including error detection circuit | |
| KR102295895B1 (en) | Semiconductor memory apparatus and data processing system | |
| WO2021142816A1 (en) | Wafer to wafer structure and test method therefor, and high bandwidth memory and manufacturing method therefor | |
| US11537462B2 (en) | Apparatuses and methods for cyclic redundancy calculation for semiconductor device | |
| US6021061A (en) | Semiconductor memory device | |
| WO2022057333A1 (en) | Memory device, testing method therefor and usage method therefor, and memory system | |
| US20240029808A1 (en) | Semiconductor memory devices and memory systems including the same | |
| JP2009266317A (en) | Semiconductor memory device and method of performing data reduction test | |
| TW202407699A (en) | Memory device having segmented data line structure | |
| KR20060005608A (en) | Method for arranging cells of semiconductor device | |
| KR20010065746A (en) | Memory module of printer circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |