CN116741227A - Three-dimensional memory architecture, operation method thereof and memory - Google Patents
Three-dimensional memory architecture, operation method thereof and memory Download PDFInfo
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The present application provides a three-dimensional memory architecture comprising: the memory cell comprises a memory cell layer, wherein the memory cell layer comprises a memory array, the memory array comprises a plurality of memory cells and a plurality of bit lines, and the bit lines are connected with the memory cells; a logic control layer on which the memory cell layer is stacked in a vertical direction; the logic control layer comprises a detection amplifier, and two ends of the detection amplifier are respectively connected with the bit line through silicon through holes. The space utilization rate of the chip is improved, and the layout freedom degree is increased. The application also provides an operation method of the three-dimensional memory architecture and a memory.
Description
Technical Field
The present application relates to integrated circuits, and more particularly, to a three-dimensional memory architecture, a method of operating the same, and a memory.
Background
DRAM (Dynamic Random Access Memory ) is a common memory. The basic memory cell is mainly composed of one transistor and one capacitor, and the word line connects the storage capacitor to the bit line through the control transistor. The principle is as follows: when the word line is gated, the transistor is turned on, and charge sharing occurs between the capacitor and the parasitic capacitance of the bit line due to conservation of charge, so that information on the storage capacitor can be read by determining a voltage change on the bit line. Since the charge in the storage capacitor leaks slowly over time, it is necessary to "charge" periodically. The memory cells are regularly arranged to form a memory array.
Because the bit line is connected with a plurality of memory cells, the length of the bit line is longer, the parasitic capacitance of the bit line is large, and the storage capacitance is far smaller than the parasitic capacitance on the bit line. When the word line, i.e. the transistor, is activated, charge sharing occurs between the charge on the storage capacitor and the charge on the parasitic capacitance of the bit line, resulting in very small changes in the voltage of the bit line, requiring the use of a sense amplifier to amplify the voltage difference, and after amplification, charging and discharging the storage capacitor is beneficial to signal integrity. Typically the sense amplifier requires a reference voltage to be compared to the varying bit line voltage. The sense amplifier needs to use a pair of bit lines to sense information in the DRAM and to ensure that the two bit lines used for comparison are matched in voltage and capacitance values to each other so that their trace lengths must match the number of capacitances connected.
In the related art memory architecture, the memory array and the sense amplifier are generally integrated on the same level. The memory density is increased over a limited area, mainly by reducing the memory cell area. However, due to the limitation of "moore's law," planar scaling may reach physical limits.
Therefore, how to further optimize the architecture of the memory to optimize the memory performance is a urgent problem to be solved.
Disclosure of Invention
The application provides a three-dimensional memory architecture for solving all or part of the problems in the prior art, so as to optimize the memory performance and improve the problems of large occupied area, low access speed and the like of a chip.
The present application provides a three-dimensional memory architecture comprising:
the memory cell comprises a memory cell layer, wherein the memory cell layer comprises a memory array, the memory array comprises a plurality of memory cells and a plurality of bit lines, and the bit lines are connected with the memory cells;
a logic control layer on which the memory cell layer is stacked in a vertical direction; wherein, the liquid crystal display device comprises a liquid crystal display device,
the logic control layer comprises a detection amplifier, and two ends of the detection amplifier are respectively connected with the bit line through silicon through holes.
In some embodiments, a plurality of memory cell layers are sequentially stacked on the logic control layer, and adjacent memory cell layers are connected through silicon through holes; the logic control layer comprises a detection amplifier group, the detection amplifier group comprises a plurality of detection amplifiers, and the storage unit layer is respectively communicated with the detection amplifier group. The plurality of memory cell layers can share the detection amplifier, so that the number of the detection amplifiers is further reduced, the power consumption is reduced, and the preparation process is simplified. And the memory cell layers of different layers are connected through silicon through holes, so that the occupied area of the memory can be reduced, the stacking of the memory cell layers is facilitated, and the cost is reduced.
In some embodiments, the memory cell layer further includes a first selector through which the bit line is connected to the through silicon via. By setting the first selector, it is possible to prevent the bit lines of different layers from simultaneously communicating with the sense amplifier to cause data collision.
In some embodiments, the memory cell layer includes a plurality of memory arrays arranged along a first direction, and a first selector and a second selector are included between adjacent memory arrays, wherein two adjacent memory arrays communicate with the shared sense amplifier group through the first selector and the second selector, respectively. Two adjacent memory arrays can share the detection amplifier, and the memory arrays communicated with the detection amplifier are switched through the first selector and the second selector, so that the space utilization rate is improved.
In some embodiments, the bit lines connected at both ends of the sense amplifier are located in the same memory array in the same memory cell layer. Thus, the folded bit line 8F2 design similar to the planar structure is constructed, so that noise is reduced, and the anti-interference capability is high. Wherein F is the process feature size. The unit memory cell structure is one factor affecting the size of the semiconductor memory device. The technology of the folded bit line structure of the traditional plane framework can be partially compatible, and the cost is reduced.
In some embodiments, the bit lines connected at two ends of the sense amplifier are respectively located in two adjacent memory arrays in the same memory cell layer. Thus, an open bit line 6F2 design resembling a planar architecture is constructed. Wherein F is the process feature size. The unit memory cell structure is one factor affecting the size of the semiconductor memory device. The technology of the open bit line structure of the traditional plane framework can be partially compatible, and the cost is reduced.
In some embodiments, the orthographic projection area of the memory cell layer is greater than or equal to the orthographic projection area of the logic control layer, and the projection plane is a plane in which the logic control layer is located. In actual operation, the area required by the logic control layer where the sense amplifier is located is much smaller than the memory cell layer where the memory array is located, so that the area of the three-dimensional memory architecture is not increased by placing the sense amplifier in the logic control layer at the bottom layer. Thereby effectively reducing the occupied area of the chip.
In some embodiments, two ends of the sense amplifier are connected to the through silicon via through a first interconnect line and a second interconnect line, respectively. Because the detection amplifier and the bit line are arranged on different planes respectively, two ends of the detection amplifier are connected with the bit line through the first interconnection line and the second interconnection line respectively, and the space of the logic control layer is rich relative to the memory cell layer, the first interconnection line and the second interconnection line can regulate and control the length, the width and the like, so that the bit lines at two ends of the detection amplifier are matched, for example, the capacitance and the voltage are equal. Thus, the degree of freedom of layout is increased, and the accuracy of the read operation of the detection amplifier is improved.
In some embodiments, a plurality of the bit lines extend in a first direction and are arranged in a second direction; the memory array further includes a plurality of word lines extending in a second direction and arranged in a first direction, each memory cell coupled to the word line;
the logic control layer further comprises: a row decoder configured to determine a row address of a memory cell based on a read-write operation instruction, and address the word line; and the column decoder is configured to determine the column address of the storage unit based on the read-write operation instruction and address the bit line. The logic control layer with the row decoder and the column decoder at the bottom layer can further reduce the occupied area of the chip.
The application also provides an operation method of the three-dimensional memory architecture, which comprises the following steps:
the memory cell comprises a memory cell layer, wherein the memory cell layer comprises a memory array, the memory array comprises a plurality of memory cells and a plurality of bit lines, and the bit lines are connected with the memory cells;
a logic control layer on which the memory cell layer is stacked in a vertical direction; wherein, the liquid crystal display device comprises a liquid crystal display device,
the logic control layer comprises a detection amplifier, and two ends of the detection amplifier are respectively connected with the bit line through silicon through holes. The precharge time can be reduced, the refresh time can be reduced, and the DRAM access speed can be improved.
The application also provides a memory comprising: a three-dimensional memory architecture of any of the above.
Compared with the prior art, the application has the main beneficial effects that:
according to the three-dimensional memory architecture provided by the embodiment of the application, the detection amplifier is arranged in the logic control layer, so that the degree of freedom of layout is increased, and the space utilization rate of a chip is improved. Multiple memory cell layers can be stacked on the logic control layer, improving memory density. The plurality of memory cell layers can share the detection amplifier, so that the number of the detection amplifiers is further reduced, and the preparation process is simplified.
Drawings
FIG. 1 is a schematic diagram of a related art memory architecture;
FIG. 2 is a schematic diagram of a three-dimensional memory architecture according to the present application;
FIG. 3 is a schematic diagram of a three-dimensional memory architecture according to the present application;
FIG. 4 is a schematic diagram of a three-dimensional memory architecture according to the present application;
FIG. 5 is a schematic diagram of a three-dimensional memory architecture according to the present application;
FIG. 6 is a schematic diagram of a three-dimensional memory architecture according to the present application;
FIG. 7 is a schematic diagram of a three-dimensional memory architecture according to the present application;
fig. 8 is a schematic structural diagram of a memory according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully, and it is apparent that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
For a better understanding of the present application, a memory architecture in the related art is exemplarily described. Referring to fig. 1, fig. 1 is a plane memory architecture of a memory array and a sense amplifier in the related art, including:
a plurality of memory arrays 111 arranged in a first direction; the memory array 111 includes a plurality of bit lines 1111 extending in a first direction and arranged in a second direction, a plurality of word lines 1112 extending in the second direction and arranged in the first direction, and a plurality of memory cells 1113 connected to each of the bit lines 1111, wherein the second direction is perpendicular to the first direction;
a plurality of sense amplifier groups 121 arranged along the first direction, the sense amplifier groups 121 being located between adjacent ones of the memory arrays 111, the sense amplifier groups 121 including a plurality of sense amplifiers 1211 arranged along the second direction;
wherein both ends of the sense amplifier 1211 are respectively connected to bit lines 1111 in the adjacent memory array 111.
However, as the demand for memory chip storage capacity increases, conventional planar memory architecture is difficult to meet the demand. And in the planar memory architecture, the sense amplifier groups must be located between adjacent memory arrays, limiting the freedom of the sense amplifiers.
Based on this, as shown in fig. 2, an embodiment of the present application provides a three-dimensional memory architecture 10, including:
a memory cell layer 11, the memory cell layer 11 including a memory array 111, the memory array 111 including a plurality of memory cells 1113 and a plurality of bit lines 1111, the bit lines 1111 being connected to the plurality of memory cells 1113;
a logic control layer 12, the memory cell layer 11 being stacked on the logic control layer 12 in a vertical direction; wherein, the liquid crystal display device comprises a liquid crystal display device,
the logic control layer 12 includes a sense amplifier 1211, and both ends of the sense amplifier 1211 are connected to the bit line 1111 through-silicon vias 13, respectively. It should be noted that, due to the diversity of end use states of the product and different viewing angles, there may be a case where the memory cell layer 11 is below the logic control layer 12 in the vertical direction, and the orientation of the overall architecture is not limited herein. Here, the through silicon via may be any vertical electrical interconnection technology, and the through silicon via may be filled with a conductive material such as copper, tungsten, polysilicon, or the like. In practical operation, the bit lines and the sense amplifier are not limited in connection, and may be through silicon vias or other electrical interconnection techniques.
In the three-dimensional memory architecture provided in the embodiment, the detection amplifier is arranged in the logic control layer, so that the degree of freedom of layout is increased, and the space utilization rate of the chip is improved. Multiple memory cell layers can be stacked on the logic control layer, improving memory density. The plurality of memory cell layers can share the detection amplifier, so that the number of the detection amplifiers is further reduced, and the preparation process is simplified.
Here, the sense amplifier may be a sense amplifier, a bit line sense amplifier, a differential comparison amplifier, or the like, and may include two inverters connected back-to-back, for example. The sense amplifier is used to read out the charge stored in the capacitance of the memory cell when the transistor of the memory cell is turned on.
The memory array 111 includes a plurality of bit lines 1111 extending in a first direction and arranged in a second direction, a plurality of word lines 1112 extending in the second direction and arranged in the first direction, and a plurality of memory cells 1113 connected to each of the bit lines 1111, wherein the second direction is perpendicular to the first direction.
The memory array 111 also includes a plurality of word lines 1112 extending in a second direction and arranged in a first direction, each memory cell 1113 coupled to the word line 1112.
In actual operation, the logic control layer 12 includes a sense amplifier group 121, and the sense amplifier group 121 includes a plurality of sense amplifiers 1211 arranged along the second direction.
Each memory cell basic structure is 1T1C, i.e., one transistor and one capacitor. Each transistor is coupled to a word line that can control turning off and on each connected transistor. The capacitance in the memory cell is coupled to the bit line when the transistor is on, and the capacitance can be decoupled from the bit line when the transistor is off. It should be appreciated that a memory cell may include more than one transistor and that a memory cell may include other memory elements or devices in addition to a capacitor.
In some embodiments, referring to fig. 2, the bit lines 1111 connected at two ends of the sense amplifier 1211 are respectively located in two adjacent memory arrays 111 in the same memory cell layer 11. Thus, constructing an open bit line 6F2 design resembling a planar architecture requires that adjacent memory arrays provide a reference bit line for read and write operations of any one memory array. Wherein F is the process feature size. The unit memory cell structure is one factor affecting the size of the semiconductor memory device. The embodiment of the application can be partially compatible with the process of the open bit line structure of the traditional plane architecture, and reduces the cost.
In some embodiments, the front projection of the sense amplifier unit 121 is located between the front projections of two adjacent storage arrays 111, and the projection plane is the plane in which the logic control layer 12 is located. Thus, the two ends of the detection amplifier are convenient to interconnect with the bit lines in the memory array, and the signal transmission paths are reduced. And the warp control of the three-dimensional framework on the product is more strict, and the warp of the product can be reduced by arranging the storage arrays on two sides of the detection amplifier.
In some embodiments, the orthographic projection area of the memory cell layer 11 is greater than or equal to the orthographic projection area of the logic control layer 12, and the projection plane is the plane in which the logic control layer 12 is located. In actual operation, the area required by the logic control layer 12 where the sense amplifier is located is much smaller than the memory cell layer 11 where the memory array is located, so that the area of the three-dimensional memory architecture is not increased by placing the sense amplifier in the logic control layer 12 at the bottom. Thereby effectively reducing the occupied area of the chip.
In some embodiments, the logic control layer further comprises: a row decoder (not shown) configured to determine a row address of the memory cell based on the read/write operation instruction, and address the word line; a column decoder (not shown) configured to determine a column address of the memory cell based on the read/write operation instruction, and address the bit line. In the conventional planar architecture, the row decoder and the column decoder occupy a larger chip area, and the logic control layer 12 with the row decoder and the column decoder at the bottom layer can further reduce the chip area. In actual operation, the logic control layer may include command controls for activation, reading, writing, and refreshing.
In some embodiments, the two ends of the sense amplifier 1211 are connected to the through silicon via 13 through a first interconnect line 122 and a second interconnect line 123, respectively. In actual operation, the lengths of the first interconnect line 122 and the second interconnect line 123 may be different. Compared with the traditional planar architecture, the sense amplifier is arranged in the middle of the adjacent memory array, two ends of the sense amplifier are directly connected with the bit lines, and due to the limitation of the layout of the sense amplifier, the matching of the bit lines at two ends can only be determined by the process fineness. But the bit lines on both sides of the sense amplifier tend to be mismatched due to unavoidable process errors. In the embodiment of the present application, since the sense amplifier 1211 and the bit line are disposed on different planes, two ends of the sense amplifier 1211 are respectively connected to the bit line through the first interconnect line 122 and the second interconnect line 123, and the space of the logic control layer is relatively rich with respect to the memory cell layer, the first interconnect line 122 and the second interconnect line 123 can regulate the length, the width, etc., so that the bit lines at two ends of the sense amplifier 1211 are matched, for example, the capacitance and the voltage are equal. Thus, the degree of freedom of layout is increased, and the accuracy of the read operation of the detection amplifier is improved.
In some embodiments, referring to fig. 3, the bit lines 1111 connected at both ends of the sense amplifier 1211 are located in the same memory array 111 in the same memory cell layer. Thus, the folded bit line 8F2 design similar to the planar structure is constructed, so that noise is reduced, and the anti-interference capability is high. Wherein F is the process feature size. The unit memory cell structure is one factor affecting the size of the semiconductor memory device. The embodiment of the application can be partially compatible with the process of the folding bit line structure of the traditional plane framework, and reduces the cost.
In some embodiments, referring to fig. 4, a plurality of memory cell layers 11 are sequentially stacked on the logic control layer 12, and adjacent memory cell layers 11 are connected through a through silicon via 13;
the logic control layer 12 includes a sense amplifier group 121, and a plurality of the memory cell layers 11 communicate with the sense amplifier group 121, respectively.
In this way, the plurality of memory cell layers 11 can share the sense amplifier, further reducing the number of sense amplifiers, reducing power consumption, and simplifying the manufacturing process. And the through silicon vias are shared among the memory cell layers 11 of different layers, so that the occupied area of the memory can be reduced, the stacking of the memory cell layers 11 is facilitated, and the cost is reduced.
In some embodiments, referring to fig. 4, the memory cell layer 11 further includes a first selector 112, and the bit line is connected to the through silicon via 13 through the first selector 112. By setting the first selector, it is possible to prevent the bit lines of different layers from simultaneously communicating with the sense amplifier to cause data collision.
In some embodiments, referring to fig. 5, the memory cell layer 11 includes a plurality of memory arrays 111 arranged along a first direction, and a first selector 112 and a second selector 113 are included between adjacent memory arrays 111, where two memory arrays 111 located adjacent are respectively in communication with the sense amplifier group 121 through the first selector 112 and the second selector 113. In actual operation, the first selector 112 and the second selector 113 may be connected to the through silicon via 13 through the common node 114. Here, the first selector and the second selector may be, for example, transistors.
In this way, two adjacent memory arrays 111 can share the sense amplifier, and the memory array switching in communication with the sense amplifier is performed by the first selector and the second selector, thereby improving the space utilization.
In some embodiments, referring to fig. 6 and 7, a plurality of memory cell layers 11 are sequentially stacked on the logic control layer 12, and adjacent memory cell layers 11 are connected through a through silicon via 13.
The application also provides an operation method of the three-dimensional memory architecture, which comprises the following steps:
the memory cell comprises a memory cell layer, wherein the memory cell layer comprises a memory array, the memory array comprises a plurality of memory cells and a plurality of bit lines, and the bit lines are connected with the memory cells;
a logic control layer on which the memory cell layer is stacked in a vertical direction; wherein, the liquid crystal display device comprises a liquid crystal display device,
the logic control layer comprises a detection amplifier, and two ends of the detection amplifier are respectively connected with the bit line through silicon through holes.
Here, the three-dimensional stacked array structure may divide the planar array in the related art into a plurality of sub-arrays, and the different memory cell layers are equivalent to increasing the number of banks (memory blocks), which may be, for example, the smallest controllable unit in the DRAM, for example, one Bank may be composed of 8 memory arrays. The memory controller generally issues read-write instructions directly to the Bank.
In some embodiments, a three-dimensional memory architecture includes a first word line and a second word line, the first word line and the second word line being located at different memory cell layers, the method of operation comprising: the first word line and the second word line are activated sequentially or simultaneously.
In one Bank of the related art planar architecture, two word lines (WL 1 and WL 2) are activated consecutively, and the word line WL1 must be turned off by pre-charging before the word line WL2 is activated. The operation commands that need to be passed through include: activating word line 1 (WL 1); precharge (PRE); word line 2 (WL 2) is activated. The next activation of the word line must be performed after a precharge. This is because the addressing for the same Bank activation is the same, the first must be turned off to identify the second.
According to the embodiment of the application, the original Bank is divided into different memory cell layers through the different memory cell layers, and the division is equivalent to increase the number of banks in a plane. Now different memory cell layers have different addressing and do not require a precharge operation. The operation commands that need to be passed through include: activating word line 1 (WL 1); word line 2 (WL 2) is activated. The embodiment of the application can reduce one precharge time and effectively improve the access speed.
In some embodiments, a three-dimensional memory architecture includes a first memory cell layer and a second memory cell layer, the method of operation comprising: and carrying out refreshing operation on the first memory cell layer and simultaneously carrying out operation on the second memory cell layer. In actual operation, the operation performed on the second memory cell layer includes a read-write operation, a refresh operation, and the like.
Meanwhile, because the DRAM memory cell is required to be refreshed at regular time, the refresh time is long. In the related art planar architecture, the original one planar array cannot perform other operations when performing a refresh operation. The embodiment of the application can realize the refresh operation on one memory cell layer, and other memory cell layers can realize other operations, thereby reducing the refresh time and further improving the access speed of the DRAM.
Compared with the plane architecture of the related art, the embodiment of the application can arrange partial memory cells positioned on the plane in the vertically stacked memory array under the same memory density, thereby reducing the bit line length in the same memory cell layer and reducing the parasitic capacitance CBL on the bit line; so that the charge sharing time decreases when the word line is activated, and the time tRRD, tRAS and tRCD associated with the activation operation decreases, thereby increasing the access speed of the array.
The application also provides a memory 1 comprising: a three-dimensional memory architecture 10 of any of the above. The memory may be used to store software programs as well as various data. The memory may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory may include volatile memory, or the memory may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), DRAM, synchronous Dynamic Random Access Memory (SDRAM), double Data Rate Synchronous dynamic random access memory (ddr SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct RAM (DRRAM).
In summary, in the three-dimensional memory architecture provided in the embodiment, the detection amplifier is disposed in the logic control layer, so that the degree of freedom of layout is increased, and the space utilization of the chip is improved. Multiple memory cell layers can be stacked on the logic control layer, improving memory density. The plurality of memory cell layers can share the detection amplifier, so that the number of the detection amplifiers is further reduced, and the preparation process is simplified.
The use of certain conventional english terms or letters for the sake of clarity of description of the application is intended to be exemplary only and not limiting of the interpretation or particular use, and should not be taken to limit the scope of the application in terms of its possible chinese translations or specific letters.
It should also be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Claims (11)
1. A three-dimensional memory architecture, comprising:
the memory cell comprises a memory cell layer, wherein the memory cell layer comprises a memory array, the memory array comprises a plurality of memory cells and a plurality of bit lines, and the bit lines are connected with the memory cells;
a logic control layer on which the memory cell layer is stacked in a vertical direction; wherein, the liquid crystal display device comprises a liquid crystal display device,
the logic control layer comprises a detection amplifier, and two ends of the detection amplifier are respectively connected with the bit line through silicon through holes.
2. The three-dimensional memory architecture of claim 1, wherein,
the memory cell layers are sequentially stacked on the logic control layer, and adjacent memory cell layers are connected through silicon through holes;
the logic control layer comprises a detection amplifier group, the detection amplifier group comprises a plurality of detection amplifiers, and the storage unit layer is respectively communicated with the detection amplifier group.
3. The three-dimensional memory architecture of claim 2, wherein,
the memory cell layer further includes a first selector through which the bit line is connected to the through silicon via.
4. The three-dimensional memory architecture of claim 3, wherein,
the memory cell layer comprises a plurality of memory arrays which are arranged along a first direction, a first selector and a second selector are arranged between adjacent memory arrays, wherein two adjacent memory arrays are communicated with the detection amplifier group through the first selector and the second selector respectively.
5. The three-dimensional memory architecture of claim 1, wherein the bit lines connected at both ends of the sense amplifier are located in the same memory array in the same memory cell layer.
6. The three-dimensional memory architecture of claim 1, wherein the bit lines connected at both ends of the sense amplifier are respectively located in two adjacent memory arrays in the same memory cell layer.
7. The three-dimensional memory architecture of claim 1, wherein,
the orthographic projection area of the storage unit layer is larger than or equal to the orthographic projection area of the logic control layer, and the projection plane is the plane where the logic control layer is located.
8. The three-dimensional memory architecture of claim 1, wherein both ends of the sense amplifier are connected to the through-silicon via through a first interconnect line and a second interconnect line, respectively.
9. The three-dimensional memory architecture of claim 8, wherein,
a plurality of bit lines extending in a first direction and arranged in a second direction;
the memory array further includes a plurality of word lines extending in a second direction and arranged in a first direction, each memory cell coupled to the word line;
the logic control layer further comprises:
a row decoder configured to determine a row address of a memory cell based on a read-write operation instruction, and address the word line;
and the column decoder is configured to determine the column address of the storage unit based on the read-write operation instruction and address the bit line.
10. A method of operation of a three-dimensional memory architecture, the three-dimensional memory architecture comprising:
the memory cell comprises a memory cell layer, wherein the memory cell layer comprises a memory array, the memory array comprises a plurality of memory cells and a plurality of bit lines, and the bit lines are connected with the memory cells;
a logic control layer on which the memory cell layer is stacked in a vertical direction; wherein, the liquid crystal display device comprises a liquid crystal display device,
the logic control layer comprises a detection amplifier, and two ends of the detection amplifier are respectively connected with the bit line through silicon through holes.
11. A memory, comprising: the three-dimensional memory architecture of any one of claims 1 to 9.
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