CN116266463A - Three-dimensional storage unit, storage method, three-dimensional storage chip assembly and electronic equipment - Google Patents

Three-dimensional storage unit, storage method, three-dimensional storage chip assembly and electronic equipment Download PDF

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CN116266463A
CN116266463A CN202111540112.2A CN202111540112A CN116266463A CN 116266463 A CN116266463 A CN 116266463A CN 202111540112 A CN202111540112 A CN 202111540112A CN 116266463 A CN116266463 A CN 116266463A
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dimensional
data
communication protocol
circuit
volatile memory
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左丰国
周骏
侯彬
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Xian Unilc Semiconductors Co Ltd
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Xian Unilc Semiconductors Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the application discloses a three-dimensional storage unit, a storage method, a three-dimensional storage chip assembly and electronic equipment. The three-dimensional memory unit comprises a volatile memory chip and an interface chip. The volatile memory chip is used for storing data. The interface chip is connected with the volatile memory chip in a three-dimensional stacking way through the three-dimensional heterogeneous integrated structure so as to form a three-dimensional memory unit. The interface chip comprises a communication protocol circuit, and the communication protocol circuit is used for storing a communication protocol. Data is written into the volatile memory chip in a cache consistency mode through the communication protocol circuit; and, data is read from the volatile memory chip in a cache coherent manner by the communication protocol circuit. By arranging the communication protocol circuit on the interface chip, the data can be stored and read in a cache consistency mode without other elements, the data transmission efficiency is improved, the data processing bandwidth of the three-dimensional storage unit is increased, and the service performance of the three-dimensional storage unit is improved.

Description

Three-dimensional storage unit, storage method, three-dimensional storage chip assembly and electronic equipment
Technical Field
The embodiment of the application relates to the technical field of data storage, in particular to a three-dimensional storage unit, a data storage method, a three-dimensional storage chip assembly and electronic equipment.
Background
In the related art, when data is stored, it is necessary to send the data to a component such as a motherboard, and the data is written into a memory for storage after the data is processed by a communication protocol stored in the component such as the motherboard. When data is read from the memory, the data is also required to be sent to components such as a motherboard, and the data is sent to the outside after being processed by a communication protocol stored on the components such as the motherboard.
After the data is processed by components such as a main board, the storage and the reading can be realized, the transmission path of the data is prolonged, the transmission time of the data is prolonged, and the efficiency of data storage and reading is reduced.
Disclosure of Invention
To solve at least one of the above technical problems, embodiments of the present application provide a three-dimensional memory unit, a data storage method, a three-dimensional memory chip assembly, and an electronic device.
In a first aspect, embodiments of the present application provide a three-dimensional memory unit, including a volatile memory chip, where the volatile memory chip is configured to store data; the interface chip is connected with the volatile memory chip in a three-dimensional stacking way through the three-dimensional heterogeneous integrated structure so as to form a three-dimensional memory unit; the interface chip comprises a communication protocol circuit, wherein the communication protocol circuit is used for storing a communication protocol; data is written into the volatile memory chip in a cache consistency mode through the communication protocol circuit; and, data is read from the volatile memory chip in a cache coherent manner by the communication protocol circuit.
In a possible implementation, the interface chip further includes a logic circuit, and the logic circuit is electrically connected with the communication protocol circuit; data is written into the volatile memory chip in a cache consistency mode through the communication protocol circuit and the logic circuit; and, the data is read from the volatile memory chip in a cache coherent manner through the communication protocol circuit and the logic circuit.
In one possible implementation, the volatile memory chip includes a first memory array and a second memory array, the communication protocol circuit is electrically connected to the first memory array through a first three-dimensional heterogeneous integrated structure, and the logic circuit is electrically connected to the second memory array through a second three-dimensional heterogeneous integrated structure; the orthographic projection of the communication protocol circuit falls within the range of the orthographic projection of the first storage array, and the orthographic projection of the logic circuit falls within the range of the orthographic projection of the second storage array.
In one possible implementation, the logic circuitry includes at least one of fixed logic circuitry and programmable logic circuitry.
In one possible implementation, the number of logic circuits is a plurality, the plurality of logic circuits being disposed around the communication protocol circuit.
In a possible implementation manner, the interface chip further comprises a routing unit, and the orthographic projection of the routing unit falls within the orthographic projection range of the volatile memory chip; the logic circuits are electrically connected through the routing unit, and are electrically connected with the communication protocol circuit through the routing unit respectively.
In one possible implementation, the three-dimensional memory unit further includes a memory control circuit disposed on the volatile memory chip; and/or the memory control circuit is arranged on the interface chip.
In one possible implementation, the number of memory control circuits is greater than or equal to the sum of the number of communication protocol circuits and the number of logic circuits.
In one possible implementation, the communication protocol includes at least one of a CXL protocol, a CCIX protocol, a GEN Z protocol, an OpenCPAI protocol, and an Nvlink protocol.
In one possible implementation, the number of volatile memory chips is at least two, and the at least two volatile memory chips are connected through a three-dimensional heterogeneous integrated structure three-dimensional stack.
In one possible implementation mode, the number of the interface chips is at least two, and the at least two interface chips are connected through a three-dimensional heterogeneous integrated structure in a three-dimensional stacking way; or at least two interface chips are respectively connected with the volatile memory chip in a three-dimensional stacking way through the three-dimensional heterogeneous integrated structure.
In one possible embodiment, the front projection of the interface chip coincides completely with the front projection of the volatile memory chip.
In a second aspect, embodiments of the present application provide a data storage method, which is used for the three-dimensional memory unit of the first aspect, where the volatile memory chip includes a first memory array and a second memory array; the interface chip also comprises a plurality of logic circuits, the logic circuits are electrically connected through a routing unit, and the logic circuits are electrically connected with the communication protocol circuit through the routing unit respectively; the data storage method comprises the steps of receiving data from a communication protocol circuit and storing the data from the communication protocol circuit to a first storage array; or, receiving data from the communication protocol circuit, and transmitting the data from the communication protocol to at least one logic circuit through the routing unit; and storing the data processed by the at least one logic circuit to a second storage array.
In a third aspect, embodiments of the present application provide a three-dimensional memory chip assembly, including the three-dimensional memory cell of the first aspect, a substrate, where the substrate is electrically connected to the three-dimensional memory cell, and the substrate is used to package the three-dimensional memory cell.
In a fourth aspect, embodiments of the present application provide an electronic device comprising a processor; the three-dimensional memory chip assembly of the above three aspects is electrically connected to the processor.
The beneficial effects of the embodiment of the application are as follows:
by setting the communication protocol on the interface chip, the data can be written into the volatile memory chip in a cache consistency mode and can be read from the volatile memory chip in a cache consistency mode, so that the data can be stored and read without being transmitted to other components (such as a main board and the like), the data transmission path is shortened, the data transmission time is shortened, the delay of the data storage and reading process is reduced, the data storage and reading efficiency of the three-dimensional memory unit is improved, and the service performance of the three-dimensional memory unit is improved.
And the interface chip is arranged to be connected with the volatile memory chip in a three-dimensional stacking way through the three-dimensional heterogeneous integrated structure, so that on one hand, the data transmission path is shortened, the data processing bandwidth of the three-dimensional memory unit is greatly increased, the power consumption of the three-dimensional memory unit is reduced, the access conflict is avoided, and the usability of the three-dimensional memory unit is improved. On the other hand, the interface chip is arranged to be connected with the volatile memory chip in a three-dimensional stacking way through the three-dimensional heterogeneous integrated structure, so that the occupied area of the three-dimensional memory unit can be reduced, and the use flexibility of the three-dimensional memory unit is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of a three-dimensional memory cell according to one embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a three-dimensional memory cell according to a second embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a third embodiment of a three-dimensional memory cell structure according to the present disclosure;
FIG. 4 is a schematic diagram of a three-dimensional memory cell according to one embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a programmable logic circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an interface chip according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a three-dimensional memory cell according to one embodiment of the present disclosure;
FIG. 8 is a flowchart illustrating steps of a method for storing data according to one embodiment of the present application;
FIG. 9 is a second flowchart illustrating steps of a method for storing data according to one embodiment of the present application;
FIG. 10 is a schematic diagram of a three-dimensional memory chip assembly according to one embodiment of the present disclosure;
fig. 11 is a schematic block diagram of an electronic device according to an embodiment provided in the present application.
The correspondence between the reference numerals and the component names in fig. 1 to 11 is:
100: three-dimensional memory cell, 110: volatile memory chip, 112: first storage array, 114: second storage array, 120: interface chip, 122: communication protocol circuit, 124: logic circuit, 126: fixed logic circuitry, 128: programmable logic circuit, 131: embedded programmable logic circuit, 132: embedded multiplication circuit, 133: embedded memory unit, 134: routing unit, 140: three-dimensional heterogeneous integrated structure, 142: first three-dimensional heterogeneous integrated structure, 144: a second three-dimensional heterogeneous integrated structure, 200: three-dimensional memory chip assembly, 210: substrate, 212: pin, 300: electronic device, 310: a processor.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
In some examples, data is typically required to be processed through a communication protocol stored on the motherboard when stored and read. Specifically, when data is stored, the data needs to be transmitted to a motherboard, processed by a communication protocol stored on the motherboard, and then transmitted to a volatile memory chip for storage. When the data stored in the volatile memory chip is read, the data is also required to be transmitted to the main board, and after the data is processed through a communication protocol stored on the main board, the data is transmitted to a processor or other components, so that the data stored in the volatile memory chip can be transmitted outwards. Therefore, data can be transmitted between the main board and the volatile memory chip, so that storage and reading can be realized, the data transmission path is increased, the data transmission time is prolonged, and the data storage and reading efficiency is reduced.
To solve at least one of the above technical problems, in a first aspect, as shown in fig. 1, an embodiment of the present application provides a three-dimensional memory cell 100. The three-dimensional memory unit 100 includes a volatile memory chip 110 and an interface chip 120. The volatile memory chip 110 is used to store data. The interface chip 120 is three-dimensionally stacked and connected with the volatile memory chip 110 through the three-dimensional heterogeneous integrated structure 140 to form the three-dimensional memory cell 100. The interface chip 120 includes a communication protocol circuit 122, and the communication protocol circuit 122 is used for storing a communication protocol. Data is written to the volatile memory chip 110 in a cache coherent manner by the communication protocol circuit 122; and, data is read from the volatile memory chip 110 in a cache coherent manner by the communication protocol circuit 122.
The volatile memory chip 110 is used to store data, and in some examples, the volatile memory chip 110 may be a DRAM memory (Dynamic Random Access Memory ).
It is understood that the interface chip 120 is for receiving data. The interface chip 120 can be three-dimensionally stacked with the volatile memory chip 110 through the three-dimensional heterogeneous integrated structure 140, so that the interface chip 120 can transmit received data to the volatile memory chip 110 for storage. Similarly, data stored in the volatile memory chip 110 can be read by the interface chip 120 through the three-dimensional heterogeneous integrated structure 140 and transmitted to the outside of the three-dimensional memory unit 100 via the interface chip 120. In some examples, the interface chip 120 is made of silicon, and the semiconductor element may be integrated on the interface chip 120.
In some examples, the three-dimensional heterogeneous integrated structure 140 may be formed between the interface chip 120 and the volatile memory chip 110 by means of hybrid bonding, so that data can be transferred between the interface chip 120 and the volatile memory chip 110 through the three-dimensional heterogeneous integrated structure 140.
Specifically, the three-dimensional heterogeneous integrated structure 140 can directly interconnect the metal layer inside the volatile memory chip 110 and the metal layer inside the interface chip 120 across chips, and build high-density metal layer interconnection inside the chips layer by layer, so that an input/output interface (IO interface) or an input/output circuit (IO circuit) is not required to be set, so that data can be transmitted between the interface chip 120 and the volatile memory chip 110, a data transmission path is shortened, the data processing bandwidth of the three-dimensional memory unit 100 is greatly increased, the power consumption of the three-dimensional memory unit 100 is reduced, access conflicts are avoided, and the service performance of the three-dimensional memory unit 100 is improved. In addition, the interface chip 120 is connected with the volatile memory chip 110 in a three-dimensional stacking manner through the three-dimensional heterogeneous integrated structure 140, so that the occupied area of the three-dimensional memory unit 100 can be reduced, and the use flexibility of the three-dimensional memory unit 100 can be improved.
As shown in fig. 1, the interface chip 120 includes a communication protocol circuit 122, and the communication protocol circuit 122 is used to store a communication protocol. In some examples, the communication protocol circuit 122 may be disposed on the interface chip 120 by way of etching.
It will be appreciated that the communication protocol circuit 122 is capable of processing data in accordance with a stored communication protocol. After being processed by the communication protocol circuit 122, the data can be written to the volatile memory chip 110 and read from the volatile memory chip 110 in a cache coherent manner. It will be appreciated that writing data to the volatile memory chip 110 and reading data from the volatile memory chip 110 in a cache coherent manner means that link coherence can be maintained between the communication protocol circuit 122 and the volatile memory chip 110 such that data can be directly stored and read between the communication protocol circuit 122 and the volatile memory chip 110 without processing via other components (e.g., a motherboard, etc.).
By providing the communication protocol circuit 122, the data processed by the communication protocol circuit 122 can be directly written into the volatile memory chip 110, and the data stored in the volatile memory chip 110 can also be directly read by the communication protocol circuit 122. In this way, when data is stored and read, the data does not need to be sent to other components (such as a motherboard, etc.), the transmission path of the data is shortened, the transmission time of the data is reduced, and the efficiency of writing the data by the three-dimensional memory unit 100 is improved.
As can be seen from the above, by providing the communication protocol circuit 122 on the interface chip 120, data can be written into the volatile memory chip 110 in a cache consistency manner and can be read from the volatile memory chip 110 in a cache consistency manner, so that data can be stored and read without transmitting the data to other components (such as a motherboard, etc.), a data transmission path is shortened, a data transmission time is reduced, a delay of a data storage and reading process is reduced, and efficiency of storing and reading data by the three-dimensional memory unit 100 is improved, thereby improving usability of the three-dimensional memory unit 100.
In some examples, the number of communication protocol circuits 122 may be one or more. The communication protocols stored in the different communication protocol circuits 122 may be the same or different. In some examples, multiple communication protocols may be stored in one communication protocol circuit 122.
In some examples, as shown in fig. 2, the interface chip 120 also includes logic 124. Logic circuit 124 is electrically coupled to communication protocol circuit 122. Data is written to the volatile memory chip 110 in a cache coherent manner through the communication protocol circuit 122 and the logic circuit 124; and, data is read from the volatile memory chip 110 in a cache coherent manner through the communication protocol circuit 122 and the logic circuit 124.
It will be appreciated that the logic circuit 124 stores computational logic to enable logical computation of data. In some examples, logic circuit 124 may be an analog-to-digital conversion circuit, a comparison circuit, an amplification circuit, or the like. In some examples, logic 124 may be disposed on interface chip 120 by way of etching. In some examples, the number of logic circuits 124 may be multiple, and the computational logic stored on different logic circuits 124 may be the same or different.
It is appreciated that the communication protocol circuit 122 is electrically connected to the logic circuit 124 such that data can be transferred between the communication protocol circuit 122 and the logic circuit 124. In some examples, the communication protocol circuit 122 may be electrically connected to the logic circuit 124 by copper wires.
Specifically, when data is stored, the communication protocol circuit 122 may transmit the processed data to the logic circuit 124, and the logic circuit 124 performs logic calculation processing on the data and then writes the data into the volatile memory chip 110 for storage. When the data is read, the data in the volatile memory chip 110 may be transferred to the logic circuit 124, and after the logic circuit 124 performs logic calculation processing on the data, the data is transferred to the communication protocol circuit 122, and the communication protocol circuit 122 transfers the processed data to the outside of the three-dimensional memory unit 100.
As can be seen from the above, by providing the logic circuit 124 electrically connected to the communication protocol circuit 122, data can be transmitted between the communication protocol circuit 122 and the logic circuit 124, so that not only can data be stored and read in a cache consistency manner by the communication protocol circuit 122, but also logic calculation of the data can be realized by the logic circuit 124. In this way, when data is stored and read, logic calculation of the data can be realized without transmitting the data to other components (such as a programmable memory controller, etc.), so that a data transmission path is further shortened, data transmission time is reduced, data processing efficiency of the three-dimensional memory unit 100 is improved, and the three-dimensional memory unit 100 can realize logic processing functions of the data, thereby further improving usability of the three-dimensional memory unit 100.
In some examples, the communication protocol circuit 122 and the logic circuit 124 may be disposed in different areas on the interface chip 120. In some examples, communication protocol circuitry 122 and logic circuitry 124 may also be disposed in the same area on interface chip 120.
In some examples, as shown in fig. 3, the volatile memory chip 110 includes a first memory array 112 and a second memory array 114. The communication protocol circuit 122 is electrically connected to the first memory array 112 through the first three-dimensional heterostructure 142. The logic circuit 124 is electrically connected to the second memory array 114 through the second three-dimensional heterogeneous integrated structure 144. The orthographic projection of the communication protocol circuit 122 falls within the orthographic projection of the first storage array 112. The orthographic projection of logic 124 falls within the orthographic projection of second storage array 114.
It is understood that the number of first storage arrays 112 and second storage arrays 114 may be plural. The first memory array 112 and the second memory array 114 may have the same shape and area or may have different shapes and areas. The first memory array 112 and the second memory array 114 in the embodiments of the present application are only used to distinguish between two different memory areas on the volatile memory chip 110, and the first memory array 112 and the second memory array 114 are not further limited.
The communication protocol circuit 122 is electrically connected to the first storage array 112 through the first three-dimensional heterogeneous integrated structure 142, so that data processed by the communication protocol circuit 122 can be transferred to the first storage array 112 through the first three-dimensional heterogeneous integrated structure 142 for storage. Similarly, data stored in the first memory array 112 can also be transferred to the communication protocol circuit 122 through the first three-dimensional heterogeneous integrated structure 142.
The logic circuit 124 is electrically connected to the second memory array 114 through the second three-dimensional heterostructure 144, so that data processed by the logic circuit 124 can be transferred to the second memory array 114 through the second three-dimensional heterostructure 144. Similarly, data stored in the second memory array 114 can also be transferred to the logic circuit 124 through the second three-dimensional heterogeneous integrated structure 144.
It is understood that the first three-dimensional heterogeneous integrated structure 142 and the second three-dimensional heterogeneous integrated structure 144 may be the same or different. The first three-dimensional heterostructure 142 and the second three-dimensional heterostructure 144 in the embodiments of the present application are used only to distinguish between the three-dimensional heterostructure 140 disposed between the communication protocol circuit 122 and the first memory array 112, and the three-dimensional heterostructure 140 disposed between the logic circuit 124 and the second memory array 114, and the first three-dimensional heterostructure 142 and the second three-dimensional heterostructure 144 are not further limited.
As can be seen from the above, the logic circuit 124 is electrically connected to the communication protocol circuit 122. Thus, in storing data, if logic computation is not required for the data processed by the communication protocol circuit 122, the data may be directly transferred to the first storage array 112 for storage through the first three-dimensional heterogeneous integrated structure 142. If logic computation is required for the data processed by the communication protocol circuit 122, the data processed by the communication protocol circuit 122 may be transmitted to the logic circuit 124, and after logic computation processing is performed on the data by the logic circuit 124, the data is transmitted to the second storage array 114 through the second three-dimensional heterogeneous integrated structure 144 for storage.
Similarly, when the data in the volatile memory chip 110 is read, if logic calculation is not required for the data, the data can be transmitted to the communication protocol circuit 122 through the first three-dimensional heterogeneous integrated structure 142, and then transmitted to the outside of the three-dimensional memory unit 100 after being processed by the communication protocol circuit 122. If logic computation is required for the data, the data can be transmitted to the logic circuit 124 through the second three-dimensional heterogeneous integrated structure 144, the logic computation processing is performed on the data through the logic circuit 124, and then the data is transmitted to the communication protocol circuit 122, and the data is transmitted to the outside of the three-dimensional memory unit 100 after the data is processed by the communication protocol circuit 122.
As can be seen from the above description, by setting the communication protocol circuit 122 to be electrically connected to the first storage array 112 through the first three-dimensional heterogeneous integrated structure 142, the logic circuit 124 is electrically connected to the second storage array 114 through the second three-dimensional heterogeneous integrated structure 144, so that data can be directly stored after being processed by the communication protocol circuit 122, or data can be stored after being processed by the communication protocol circuit 122 and the logic circuit 124, so as to meet processing requirements of different data, and improve flexibility of use of the three-dimensional storage unit 100.
Moreover, by the above arrangement, the data (data subjected to logic calculation and data not subjected to logic calculation) subjected to different processing can be transmitted through the different three-dimensional heterogeneous integrated structures 140 (the first three-dimensional heterogeneous integrated structure 142 and the second three-dimensional heterogeneous integrated structure 144), and the data subjected to different processing can be stored into the different storage arrays (the first storage array 112 and the second storage array 114), so that crosstalk in data transmission and storage processes is reduced, and the use reliability of the three-dimensional storage unit 100 is improved.
In addition, the orthographic projection of the communication protocol circuit 122 falls within the range of the orthographic projection of the first storage array 112, that is, the setting position of the communication protocol circuit 122 corresponds to the setting position of the first storage array 112. The orthographic projection of the logic circuit 124 falls within the orthographic projection of the second storage array 114, that is, the setting position of the logic circuit 124 corresponds to the setting position of the second storage array 114. By the arrangement, the distance between the communication protocol circuit 122 and the first storage array 112 and the distance between the logic circuit 124 and the second storage array 114 are reduced, so that the transmission path of data is further shortened, the transmission time of the data is reduced, and the efficiency of data storage and reading is improved.
In some examples, as shown in fig. 4, logic 124 includes at least one of fixed logic 126 and programmable logic 128.
It will be appreciated that the fixed logic circuitry 126 stores fixed computing logic and the programmable logic circuitry 128 stores programmable computing logic. By providing the logic circuit 124 to include at least one of the fixed logic circuit 126 and the programmable logic circuit 128, different logic circuits 124 can be provided to process data according to different processing requirements, thereby improving the applicability of the three-dimensional memory cell 100.
In some examples, when logic circuit 124 includes fixed logic circuit 126 and programmable logic circuit 128, electrical connections may be made between fixed logic circuit 124 and programmable logic circuit 128, enabling data to be transferred between fixed logic circuit 124 and programmable logic circuit 128, further increasing the flexibility of use of three-dimensional memory cell 100.
In some examples, as shown in fig. 5, programmable logic circuit 128 includes embedded programmable logic circuit 131, embedded multiplication circuit 132, and embedded storage unit 133. The embedded programmable logic circuit 131 is electrically connected to the volatile memory chip 110, thereby enabling data transfer between the programmable logic circuit 128 and the volatile memory chip 110. The embedded memory unit 133 may be electrically connected to the embedded programmable logic circuit 131 through routing or the like. The embedded multiplication circuit 132 may be electrically connected to the embedded programmable logic circuit 131 through an interface or the like.
By providing the embedded programmable logic circuit 131, the embedded multiplication circuit 132, and the embedded storage unit 133, the computational logic of the programmable logic circuit 128 can be modified, improving the applicability of the three-dimensional storage unit 100.
In some examples, as shown in fig. 6, the number of logic circuits 124 is a plurality, with a plurality of logic circuits 124 disposed around the communication protocol circuit 122.
It will be appreciated that a plurality of logic circuits 124 are used to store different computational logic. In some examples, the plurality of logic circuits 124 may be respectively electrically connected with the communication protocol circuit 122 such that any one of the logic circuits 124 is capable of transferring data with the communication protocol circuit 122. In some examples, at least one of the plurality of logic circuits 124 includes a connection logic circuit electrically coupled to the communication protocol circuit 122, and the remaining logic circuits 124 are electrically coupled to the connection logic circuit such that the plurality of logic circuits 124 are capable of data transmission with the communication protocol circuit 122 through the connection logic circuit.
By setting the number of the logic circuits 124 to be plural and setting the plural logic circuits 124 around the communication protocol circuit 122, the distance between the logic circuits 124 and the communication protocol circuit 122 is further reduced, thereby shortening the transmission path of data and further improving the processing efficiency of the three-dimensional memory unit 100 for data.
In some examples, as shown in fig. 6, the three-dimensional storage unit 100 further includes a routing unit 134. The front projection of the routing unit 134 falls within the range of the front projection of the volatile memory chip 110. The plurality of logic circuits 124 are electrically connected to each other through the routing unit 134, and the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing unit 134, respectively.
It is appreciated that routing unit 134 may be a NOC routing unit (network on chip), and that data may be transmitted over routing unit 134.
Specifically, as shown in fig. 4, the orthographic projection of the routing unit 134 falls within the range of the orthographic projection of the volatile memory chip 110, that is, the setting position of the routing unit 134 corresponds to the setting position of the volatile memory chip 110. As can be seen from the above description, the setting position of the communication protocol circuit 122 corresponds to the setting position of the first storage array 112, and the setting position of the logic circuit 124 corresponds to the setting position of the second storage array 114, that is, the setting positions of the communication protocol circuit 122 and the logic circuit 124 both correspond to the setting position of the volatile memory chip 110. Therefore, the setting position of the setting routing unit 134 corresponds to the setting position of the volatile memory chip 110, so that the distance of data transmission between the communication protocol circuit 122 and the logic circuit 124 can be shortened, the data transmission path between the communication protocol circuit 122 and the logic circuit 124 can be shortened, and the data transmission efficiency can be improved.
In some examples, the routing unit 134 is disposed between the communication protocol circuit 122 and the plurality of logic circuits 124.
Specifically, as shown in fig. 6, the plurality of logic circuits 124 are electrically connected through the routing unit 134, and the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing unit 134, respectively, so that data can be transmitted not only between the communication protocol circuit 122 and the logic circuits 124, but also between the plurality of logic circuits 124.
In some examples, the data processed by the communication protocol circuit 122 is transferred to the routing unit 134, transferred to a logic circuit 124 through the routing unit 134, processed by the logic circuit 124, and written to the volatile memory chip 110 for storage.
In some examples, the data processed by the communication protocol circuit 122 is transmitted to the routing unit 134, is transmitted to one logic circuit 124 through the routing unit 134, is processed by one logic circuit 124, is transmitted to the routing unit 134 again, is transmitted to another one or more logic circuits 124 through the routing unit 134, is processed by another one or more logic circuits 124, and is written into the volatile memory chip 110 for storage.
As can be seen from the above description, by providing the plurality of logic circuits 124 electrically connected through the routing unit 134, and the plurality of logic circuits 124 are respectively electrically connected with the communication protocol circuit 122 through the routing unit 134, the data processed by the communication protocol circuit 122 can be received and processed by one or more different logic circuits 124, so as to implement different logic calculation processing on the data, meet different data processing requirements, and further improve the applicability of the three-dimensional memory unit 100.
In addition, by the above arrangement, the data transmission path can be further shortened, and the processing efficiency of the three-dimensional memory unit 100 for data can be improved.
In some examples, the three-dimensional memory cell 100 further includes a memory control circuit. The memory control circuit is provided on the volatile memory chip 110; and/or the memory control circuit is disposed on the interface chip 120.
In some examples, the number of storage control circuits may be one or more, improving the storage and reading efficiency of data. In some examples, the memory control circuitry may be MC (memory controller ).
By arranging the memory control circuit on the volatile memory chip 110 and/or the interface chip 120, that is, arranging the memory control circuit on at least one of the volatile memory chip 110 and the interface chip 120, different use requirements can be satisfied, and flexibility of the three-dimensional memory unit 100 is improved.
In some examples, the memory control circuitry may be provided on the volatile memory chip 110 and/or the interface chip 120 by way of etching.
In some examples, the number of memory control circuits is greater than or equal to the sum of the number of communication protocol circuits 122 and logic circuits 124.
The number of the memory control circuits is set to be greater than or equal to the sum of the numbers of the communication protocol circuits 122 and the logic circuits 124, so that when data is stored, it is ensured that the data in the communication protocol circuits 122 and the data in the plurality of different logic circuits 124 can be written into the volatile memory chip 110 through the memory control circuits in time, accumulation of the data in the communication protocol circuits 122 or the logic circuits 124 is avoided, and the reliability of the three-dimensional memory unit 100 is improved.
Similarly, when reading data, the storage control circuit can timely transmit the data to the communication protocol circuit 122 or a plurality of different logic circuits 124, so that the situation that the communication protocol circuit 122 or the logic circuits 124 are idle due to too small data in the communication protocol circuit 122 or the logic circuits 124 is avoided, the processing efficiency of the three-dimensional memory unit 100 on the data is affected, and the use reliability of the three-dimensional memory unit 100 is further ensured.
In some examples, the number of memory control circuits is equal to the sum of the number of communication protocol circuits 122 and logic circuits 124.
In some examples, the communication protocol includes at least one of a CXL protocol, a CCIX protocol, a GEN Z protocol, an OpenCPAI protocol, and an Nvlink protocol.
The communication protocol includes at least one of CXL protocol (Compute Express Link, computational interconnection protocol), CCIX protocol (CCIX, cache coherence interconnection protocol of accelerator), GEN Z protocol (Generation Z, Z-Generation protocol), openCPAI protocol (Open Computer Assisted Personal Interviewing open computer assisted interview protocol), and Nvlink protocol (bus communication protocol), so that data written into the volatile memory chip 110 and data read from the volatile memory chip 110 can be processed according to different communication protocols, thereby meeting transmission requirements of different data, and improving applicability of the three-dimensional memory unit 100. Meanwhile, by setting the above communication protocol, the transmission speed of data can be further improved, thereby improving the processing efficiency of the three-dimensional memory unit 100 for data.
In some examples, the communication protocol may also include other communication protocols capable of implementing a coherent high speed serial interface.
In some examples, the number of volatile memory chips 110 is at least two, and at least two volatile memory chips 110 are connected by a three-dimensional stack of three-dimensional heterogeneous integrated structures 140.
It can be appreciated that, by setting the number of the volatile memory chips 110 to be at least two, the memory capacity of the three-dimensional memory unit 100 can be increased, the service performance of the three-dimensional memory unit 100 can be further improved, and different memory requirements can be satisfied.
In addition, the at least two volatile memory chips 110 are three-dimensionally stacked and connected through the three-dimensional heterogeneous integrated structure 140, so that the bandwidth of the three-dimensional memory unit 100 for processing data is increased, the transmission efficiency of the data between the at least two volatile memory chips 110 is improved, the power consumption of the three-dimensional memory unit 100 is reduced, and the service performance of the three-dimensional memory unit 100 is improved.
In some examples, the number of interface chips 120 is at least two, with at least two interface chips 120 being connected in a three-dimensional stack by a three-dimensional heterogeneous integrated structure 140; or, at least two interface chips 120 are respectively connected with the volatile memory chip 110 in a three-dimensional stack through the three-dimensional heterogeneous integrated structure 140.
The number of the interface chips 120 is at least two, so that the number of the communication protocol circuits 122 and the logic circuits 124 is increased, and the processing efficiency of the three-dimensional memory unit 100 on data is further improved. Meanwhile, the three-dimensional stacking of the at least two interface chips 120 through the three-dimensional heterogeneous integrated structure 140 can increase the bandwidth of data transmission between the at least two interface chips 120, improve the data transmission efficiency of the three-dimensional memory unit 100, reduce the power consumption of the three-dimensional memory unit 100, and improve the service performance of the three-dimensional memory unit 100.
Alternatively, at least two interface chips 120 are respectively connected with the volatile memory chip 110 in a three-dimensional stacked manner through the three-dimensional heterogeneous integrated structure 140, as shown in fig. 7, so that different interface chips 120 can respectively receive data and write the processed data into the volatile memory chip 110, and similarly, the data stored in the volatile memory chip 110 can also be read through different interface chips 120, thereby improving the flexibility of using the three-dimensional memory unit 100.
In some examples, the front projection of the interface chip 120 coincides completely with the front projection of the volatile memory chip 110.
It can be appreciated that the front projection of the interface chip 120 and the front projection of the volatile memory chip 110 completely coincide, that is, the setting position of the interface chip 120 corresponds to the setting position of the volatile memory chip 110, and the area of the interface chip 120 is the same as or approximately the same as the area of the volatile memory chip 110, so that the reliability of data transmission between the interface chip 120 and the volatile memory chip 110 is further ensured, the transmission path of data between the interface chip 120 and the volatile memory chip 110 is shortened, the data transmission efficiency is improved, and the reliability of the three-dimensional memory unit 100 is improved. In addition, the structural regularity of the three-dimensional memory unit 100 can be improved, the processing is convenient, and the production efficiency of the three-dimensional memory unit 100 is improved.
In a second aspect, embodiments of the present application provide a data storage method for the three-dimensional memory cell 100 of the first aspect. The volatile memory chip 110 includes a first memory array 112 and a second memory array 114. The interface chip 120 further includes a plurality of logic circuits 124, and the plurality of logic circuits 124 are electrically connected through a routing unit 134. The plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing units 134, respectively.
Specifically, as shown in fig. 8, the data storage method includes:
step S102, data from the communication protocol circuit is received and stored in the first storage array.
Or, as shown in fig. 9, the data storage method includes:
step S202, receiving data from a communication protocol circuit, and transmitting the data from the communication protocol to at least one logic circuit through a routing unit; and storing the data processed by the at least one logic circuit to a second storage array.
The data storage method provided in the embodiments of the present application is used for the three-dimensional storage unit 100 of the first aspect, so that all the advantages of the first aspect are provided, and are not described herein.
Specifically, the data storage method includes receiving data from the communication protocol circuit, and directly storing the data from the communication protocol circuit to the first storage array, so that the data processed by the communication protocol circuit can be directly written into the volatile memory chip for storage without being processed by the logic circuit.
Or the data storage method comprises the steps of receiving data from the communication protocol circuit, sending the data to at least one logic circuit through the routing unit, and storing the data processed by the at least one logic circuit to the second storage array, namely enabling the data processed by the communication protocol circuit to be written into the volatile memory chip for storage after being processed by one or more different logic circuits.
By the two different data storage methods, the storage requirements of different data can be met, and the applicability of the data storage method is improved.
In a third aspect, as shown in fig. 10, embodiments of the present application provide a three-dimensional memory chip assembly 200. The three-dimensional memory chip assembly 200 includes the three-dimensional memory cell 100 and the substrate 210 of the first aspect described above. The substrate 210 is electrically connected to the three-dimensional memory cell 100. The substrate 210 is used to encapsulate the three-dimensional memory cell 100.
The three-dimensional memory chip assembly 200 provided in the embodiments of the present application includes the three-dimensional memory unit 100 of the first aspect, so that all the advantages of the first aspect are provided, and are not described herein.
In some examples, substrate 210 includes pins 212, and three-dimensional memory cell 100 is electrically connected to other components through pins 212.
In some examples, when the plurality of volatile memory chips 110 and the plurality of interface chips 120 are connected to each other in a three-dimensional stack, the interface chips 120 may be electrically connected to the pins 212 through TSV technology (Through Silicon Via, through silicon via technology) so that data can be transferred between the interface chips 120 and the pins 212.
In a fourth aspect, as shown in fig. 11, an embodiment of the present application provides an electronic device 300. The electronic device 300 includes a processor 310 and the three-dimensional memory chip assembly 200 of the third aspect described above, the three-dimensional memory chip assembly 200 being electrically connected to the processor 310.
The electronic device 300 provided in the embodiment of the present application includes the three-dimensional memory chip assembly 200 of the third aspect, so that all the advantages of the third aspect are provided, and are not described herein.
In some examples, electronic device 300 may be a cell phone, a computer, or a smart home device.
In one particular embodiment, a three-dimensional memory cell 100 is provided. In some examples, the three-dimensional storage unit 100 may be in data transfer with a host.
Specifically, as shown in fig. 1, the three-dimensional memory unit 100 includes a volatile memory chip 110 and an interface chip 120. The three-dimensional heterogeneous integrated structure 140 is formed between the volatile memory chip 110 and the interface chip 120 by means of hybrid bonding, so that the volatile memory chip 110 and the interface chip 120 can be connected in a three-dimensional stack, and data can be transferred between the volatile memory chip 110 and the interface chip 120.
Specifically, the volatile memory chip 110 is a DRAM volatile memory chip (Dynamic Random Access Memory ).
In some examples, a three-dimensional stacked connection may be implemented between volatile memory chip 110 and interface chip 120 through 3D-IC (three-dimensional chip) technology.
As can be appreciated, the volatile memory chip 110 and the interface chip 120 are configured to be three-dimensionally stacked and connected through the three-dimensional heterogeneous integrated structure 140, so that data can be transmitted between the volatile memory chip 110 and the interface chip 120, the bandwidth of the three-dimensional memory unit 100 for processing the data is greatly increased, the transmission path of the data in the three-dimensional memory unit 100 is shortened, the power consumption of the three-dimensional memory unit 100 is reduced, the delay of the data storage and reading processes is reduced, and the efficiency of data storage and reading is improved. In addition, the area of the three-dimensional memory cell 100 can be reduced, and the flexibility of use of the three-dimensional memory cell 100 can be improved.
In some examples, the above arrangement enables the processing bandwidth of the three-dimensional storage unit 100 for data to reach between 32GB/S and 128 GB/S.
Specifically, the interface chip 120 and the volatile memory chip 110 may be three-dimensionally stacked and connected by way of a WoW (wafer on wafer) connection or a CoW (chip on wafer) connection.
Specifically, as shown in fig. 2, the interface chip 120 includes a communication protocol circuit 122 and a plurality of logic circuits 124. It will be appreciated that the communication protocol circuit 122 is configured to store a communication protocol and the plurality of logic circuits 124 are configured to store different computing logic. As shown in fig. 6, a plurality of logic circuits 124 are disposed around the communication protocol circuit 122. The interface chip 120 is further provided with a routing unit 134, and the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing unit 134, and the plurality of logic circuits 124 are electrically connected through the routing unit 134. Specifically, the routing unit 134 is a NOC routing unit (network on chip), and data can be transmitted on the routing unit 134.
As shown in fig. 3, the volatile memory chip 110 includes a first memory array 112 and a second memory array 114, the communication protocol circuit 122 is electrically connected to the first memory array 112 through a first three-dimensional heterogeneous integrated structure 142, and the logic circuit 124 is electrically connected to the second memory array 114 through a second three-dimensional heterogeneous integrated structure 144.
Specifically, in storing data, the data on the interface chip 120, after being processed by the communication protocol circuit 122, can be stored to the first storage array 112 through the first three-dimensional heterostructure 142. Alternatively, when data is stored, the data on the interface chip 120 is processed by the communication protocol circuit 122, then transmitted to the at least one logic circuit 124 through the routing unit 134, processed by the at least one logic circuit 124, and then stored in the second storage array 114 through the second three-dimensional heterogeneous integrated structure 144.
Similarly, when reading data, the data on the volatile memory chip 110 can be transferred to the communication protocol circuit 122 through the first three-dimensional heterogeneous integrated structure 142, and then transferred outwards after being processed by the communication protocol circuit 122. Alternatively, when reading data, the data on the volatile memory chip 110 can also be transferred to the logic circuit 124 through the second three-dimensional heterogeneous integrated structure 144, and the logic circuit 124 transfers the processed data to other logic circuits 124 or the communication protocol circuit 122 through the routing unit 134. The communication protocol circuit 122 receives the data processed by the at least one logic circuit 124 and transmits the data to the outside.
Therefore, through the arrangement, the data can be written into the volatile memory chip 110 and read from the volatile memory chip 110 in a cache consistency mode, that is, the data can be stored and read without transmitting the data to components such as a main board or a programmable controller, the data transmission path is shortened, and the data storage and reading efficiency is improved.
In addition, by setting the plurality of logic circuits 124 to be electrically connected through the routing unit 134, the plurality of logic circuits 124 are respectively electrically connected with the communication protocol circuit 122 through the routing unit 134, so that the data can be directly stored or read, and the data can be stored or read after being processed by the logic circuits 124, thereby meeting the processing requirements of different data and improving the use flexibility of the three-dimensional memory unit 100.
In addition, the communication protocol circuit 122 is electrically connected to the first memory array 112 through the first three-dimensional heterogeneous integrated structure 142, and the logic circuit 124 is electrically connected to the second memory array 114 through the second three-dimensional heterogeneous integrated structure 144, so that crosstalk generated during storage and reading of data subjected to different processing is reduced, and the reliability of the three-dimensional memory unit 100 is improved.
Specifically, as shown in fig. 3, the volatile memory chip 110 and the interface chip 120 are disposed at corresponding positions, and the areas of the volatile memory chip 110 and the interface chip 120 are equal, so that a data transmission path is further shortened, and reliability of data transmission between the volatile memory chip 110 and the interface chip 120 is improved, thereby improving reliability of use of the three-dimensional memory unit 100, and in addition, structural regularity of the three-dimensional memory unit 100 is improved, processing is facilitated, and production efficiency of the three-dimensional memory unit 100 is improved.
And, the setting position of the communication protocol circuit 122 corresponds to the setting position of the first storage array 112, and the setting position of the logic circuit 124 corresponds to the setting position of the second storage array 114, so that the distance between the communication protocol circuit 122 and the first storage array 112 and the distance between the logic circuit 124 and the second storage array 114 are further shortened. The routing unit 134 is disposed between the communication protocol circuit 122 and the logic circuit 124 such that the disposition position of the routing unit 134 can correspond to the disposition position of the volatile memory chip 110, further shortening the distance between the communication protocol circuit 122 and the logic circuit 124. With the above arrangement, the data transmission path is shortened, and the processing efficiency of the three-dimensional memory unit 100 for data is improved.
The communication protocol circuit 122 stores at least one of CXL protocol (Compute Express Link, computational interconnection protocol), CCIX protocol (CCIX, cache coherence interconnection protocol of accelerator), GEN Z protocol (Generation Z, Z-Generation protocol), openCPAI protocol (Open Computer Assisted Personal Interviewing open computer aided interview protocol), and Nvlink protocol (bus communication protocol), thereby processing data through different communication protocols, and improving applicability of the three-dimensional memory unit 100.
In some examples, the communication protocol circuit 122 may also include other high-speed serial interface protocols capable of implementing cache coherency, further increasing the processing bandwidth of the three-dimensional memory unit 100 for data.
Specifically, as shown in fig. 4, logic 124 includes fixed logic 126 and programmable logic 128. The fixed logic circuitry 126 is used to store fixed computational logic. The programmable logic 128 is used to store programmable computing logic. Specifically, the programmable logic circuit 128 may be an EFPGA (Embedded Field Programmable Gate Array ).
As shown in fig. 5, the programmable logic circuit 128 includes an embedded programmable logic circuit 131, an embedded multiplication circuit 132, and an embedded storage unit 133. The embedded programmable logic circuit 131 is electrically connected with the volatile memory chip 110 through a 3D-IC (three-dimensional chip) technology, so that the programmable logic circuit 128 can perform data transmission with the volatile memory chip 110, and the transmission bandwidth of data is improved. The embedded memory unit 133 may be electrically connected to the embedded programmable logic circuit 131 through routing or the like. The embedded multiplication circuit 132 may be electrically connected to the embedded programmable logic circuit 131 through an interface or the like.
By providing the embedded programmable logic circuit 131 with the embedded multiplication circuit 132 and the embedded storage unit 133, the computational logic of the programmable logic circuit 128 can be modified, improving the applicability of the three-dimensional storage unit 100.
The three-dimensional memory cell 100 further includes a memory control circuit, which may be an MC (memory controller ), as will be appreciated. The memory control circuits may be disposed on the interface chip 120 or the volatile memory chip 110, and the number of the memory control circuits is equal to the sum of the number of the communication protocol circuits 122 and the number of the logic circuits 124, so that data can be written into the volatile memory chip 110 in time and read from the volatile memory chip 110 in time, further improving the reliability of the three-dimensional memory cell 100.
In the present invention, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more, unless expressly defined otherwise. The terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; "coupled" may be directly coupled or indirectly coupled through intermediaries. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "rear", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or units referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention.
In the description of the present specification, the terms "one embodiment," "some embodiments," "particular embodiments," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (15)

1. A three-dimensional memory cell, comprising:
the volatile memory chip is used for storing data;
the interface chip is connected with the volatile memory chip in a three-dimensional stacking way through a three-dimensional heterogeneous integrated structure so as to form the three-dimensional memory unit;
the interface chip comprises a communication protocol circuit, wherein the communication protocol circuit is used for storing a communication protocol; data is written into the volatile memory chip in a cache consistency mode through the communication protocol circuit; and, a step of, in the first embodiment,
data is read from the volatile memory chip in the cache coherent manner by the communication protocol circuit.
2. The three-dimensional memory unit of claim 1, wherein the interface chip further comprises:
a logic circuit electrically connected with the communication protocol circuit;
data is written into the volatile memory chip in the cache consistency mode through the communication protocol circuit and the logic circuit; and, a step of, in the first embodiment,
data is read from the volatile memory chip in the cache coherency manner by the communication protocol circuit and the logic circuit.
3. The three-dimensional storage unit of claim 2, wherein,
the volatile memory chip comprises a first memory array and a second memory array, the communication protocol circuit is electrically connected with the first memory array through a first three-dimensional heterogeneous integrated structure, and the logic circuit is electrically connected with the second memory array through a second three-dimensional heterogeneous integrated structure;
the orthographic projection of the communication protocol circuit falls within the range of the orthographic projection of the first storage array, and the orthographic projection of the logic circuit falls within the range of the orthographic projection of the second storage array.
4. The three-dimensional memory cell of claim 2, wherein the logic circuit comprises at least one of a fixed logic circuit and a programmable logic circuit.
5. The three-dimensional memory cell of claim 2, wherein the number of logic circuits is a plurality, the plurality of logic circuits being disposed about the communication protocol circuit.
6. The three-dimensional memory cell of claim 5, wherein the interface chip further comprises:
the orthographic projection of the routing unit falls into the orthographic projection range of the volatile memory chip; the logic circuits are electrically connected through the routing unit, and the logic circuits are electrically connected with the communication protocol circuit through the routing unit respectively.
7. The three-dimensional storage unit of claim 2, wherein the three-dimensional storage unit further comprises:
a memory control circuit disposed on the volatile memory chip; and/or the number of the groups of groups,
the memory control circuit is arranged on the interface chip.
8. The three-dimensional memory cell of claim 7, wherein the number of memory control circuits is greater than or equal to the sum of the number of communication protocol circuits and the number of logic circuits.
9. The three-dimensional storage unit of any one of claims 1-8, wherein the communication protocol comprises at least one of a CXL protocol, a CCIX protocol, a GEN Z protocol, an OpenCPAI protocol, and an Nvlink protocol.
10. The three-dimensional memory cell of any one of claims 1 to 8, wherein the number of volatile memory chips is at least two, and at least two of the volatile memory chips are three-dimensionally stacked and connected by the three-dimensional heterogeneous integrated structure.
11. The three-dimensional memory unit according to any one of claims 1 to 8, wherein the number of interface chips is at least two, and at least two of the interface chips are connected by the three-dimensional heterogeneous integrated structure three-dimensional stack; or alternatively, the first and second heat exchangers may be,
And at least two interface chips are respectively connected with the volatile memory chip in a three-dimensional stacking way through the three-dimensional heterogeneous integrated structure.
12. The three-dimensional memory unit of any one of claims 1-8, wherein the orthographic projection of the interface chip is fully coincident with the orthographic projection of the volatile memory chip.
13. A method for storing data, wherein the three-dimensional memory unit according to any one of 1 to 12 is used, and the volatile memory chip comprises a first memory array and a second memory array; the interface chip also comprises a plurality of logic circuits, wherein the logic circuits are electrically connected through a routing unit, and the logic circuits are electrically connected with the communication protocol circuit through the routing unit respectively;
the data storage method comprises the following steps:
receiving data from the communication protocol circuit, and storing the data from the communication protocol circuit to the first storage array; or alternatively, the first and second heat exchangers may be,
receiving data from the communication protocol circuit, and transmitting the data from the communication protocol to at least one logic circuit through a routing unit; and storing the data processed by at least one logic circuit into the second storage array.
14. A three-dimensional memory chip assembly, comprising:
the three-dimensional memory unit of any one of claims 1 to 12;
the substrate is electrically connected with the three-dimensional storage unit and is used for packaging the three-dimensional storage unit.
15. An electronic device, comprising:
a processor;
the three-dimensional memory chip assembly of claim 14, the three-dimensional memory chip assembly being electrically connected to the processor.
CN202111540112.2A 2021-12-16 2021-12-16 Three-dimensional storage unit, storage method, three-dimensional storage chip assembly and electronic equipment Pending CN116266463A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117437948A (en) * 2023-12-21 2024-01-23 浙江力积存储科技有限公司 Three-dimensional stacked memory architecture, processing method thereof and memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117437948A (en) * 2023-12-21 2024-01-23 浙江力积存储科技有限公司 Three-dimensional stacked memory architecture, processing method thereof and memory
CN117437948B (en) * 2023-12-21 2024-04-09 浙江力积存储科技有限公司 Three-dimensional stacked memory architecture, processing method thereof and memory

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