CN216450386U

CN216450386U - Nonvolatile three-dimensional memory cell, chip assembly, and electronic apparatus

Info

Publication number: CN216450386U
Application number: CN202123171551.9U
Authority: CN
Inventors: 左丰国; 周骏; 侯彬
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xi'an Ziguang Guoxin Semiconductor Co ltd
Priority date: 2021-12-16
Filing date: 2021-12-16
Publication date: 2022-05-06
Anticipated expiration: 2031-12-16

Abstract

The embodiment of the application discloses a nonvolatile three-dimensional storage unit, a chip assembly and an electronic device. Volatile memory chips are used to store data. The interface chip is connected with the volatile memory chip in a three-dimensional stacking mode through the three-dimensional heterogeneous integrated structure. The nonvolatile memory chip is connected with at least one of the volatile memory chip and the interface chip in a three-dimensional stacking mode through a three-dimensional heterogeneous integrated structure to form a nonvolatile three-dimensional memory unit. The interface chip comprises a communication protocol circuit, and the communication protocol circuit is used for storing a communication protocol. Data is written into at least one of the volatile memory chip and the nonvolatile memory chip in a cache consistency mode through the communication protocol circuit; and, data is read from at least one of the volatile memory chip and the non-volatile memory chip in a cache coherent manner by the communication protocol circuit. Through the arrangement, the data transmission efficiency is improved, the data processing bandwidth is increased, and the data storage reliability is improved.

Description

Nonvolatile three-dimensional memory cell, chip assembly, and electronic apparatus

Technical Field

Embodiments of the present application relate to the field of data storage technologies, and in particular, to a nonvolatile three-dimensional memory cell, a nonvolatile three-dimensional memory chip assembly, and an electronic device.

Background

In the related art, when data is stored, the data needs to be sent to components such as a motherboard, and after the data is processed through a communication protocol stored on the components such as the motherboard, the data is written into a memory for storage. When data is read from the memory, the data also needs to be sent to components such as a motherboard, and after the data is processed through a communication protocol stored on the components such as the motherboard, the data is sent to the outside.

After the data are processed by components such as a main board, the data can be stored and read, the transmission path of the data is prolonged, the transmission time of the data is prolonged, and the data storage and reading efficiency is reduced.

In addition, when the memory is powered off, the data stored in the memory needs to be transmitted to the nonvolatile memory chip for storage, so that data loss is avoided, the transmission path of the data is further prolonged, the transmission efficiency of the data is reduced, and the risk of data loss is increased.

SUMMERY OF THE UTILITY MODEL

In order to solve at least one of the above technical problems, embodiments of the present application provide a nonvolatile three-dimensional memory cell, a data storage method, a nonvolatile three-dimensional memory chip assembly, and an electronic device.

In a first aspect, an embodiment of the present application provides a nonvolatile three-dimensional memory cell, including a volatile memory chip, where the volatile memory chip is used to store data; the interface chip is connected with the volatile memory chip in a three-dimensional stacking manner through a three-dimensional heterogeneous integrated structure; the nonvolatile memory chip is connected with at least one of the volatile memory chip and the interface chip in a three-dimensional stacking manner through a three-dimensional heterogeneous integrated structure to form a nonvolatile three-dimensional memory unit; the interface chip comprises a communication protocol circuit, wherein the communication protocol circuit is used for storing a communication protocol; data is written into at least one of the volatile memory chip and the nonvolatile memory chip in a cache consistency mode through the communication protocol circuit; and data is read from at least one of the volatile memory chip and the non-volatile memory chip in a cache coherent manner by the communication protocol circuit.

In one possible embodiment, the interface chip further includes a logic circuit, the logic circuit being electrically connected to the communication protocol circuit; data is written to at least one of the volatile memory chip and the non-volatile memory chip in a cache coherent manner through the communication protocol circuit and the logic circuit, and data is read from at least one of the volatile memory chip and the non-volatile memory chip in a cache coherent manner through the communication protocol circuit and the logic circuit.

In one possible implementation, the volatile memory chip comprises a first memory array and a second memory array, the communication protocol circuit is electrically connected with the first memory array through a first three-dimensional heterogeneous integrated structure, and the logic circuit is electrically connected with the second memory array through a second three-dimensional heterogeneous integrated structure; the orthographic projection of the communication protocol circuit falls within the range of the orthographic projection of the first storage array, and the orthographic projection of the logic circuit falls within the range of the orthographic projection of the second storage array.

In one possible implementation mode, the nonvolatile memory chip is connected with the interface chip in a three-dimensional stacking mode through the three-dimensional heterogeneous integrated structure; the nonvolatile memory chip comprises a third memory array and a fourth memory array, the communication protocol circuit is electrically connected with the third memory array through a third three-dimensional heterogeneous integrated structure, and the logic circuit is electrically connected with the fourth memory array through a fourth three-dimensional heterogeneous integrated structure; the orthographic projection of the communication protocol circuit falls within the orthographic projection range of the third storage array, and the orthographic projection of the logic circuit falls within the orthographic projection range of the fourth storage array.

In one possible implementation, the logic circuit includes at least one of a fixed logic circuit and a programmable logic circuit.

In one possible embodiment, the number of logic circuits is plural, and the plural logic circuits are disposed around the communication protocol circuit.

In a possible implementation, the interface chip further includes a routing unit, and the orthographic projection of the routing unit falls within the range of the orthographic projection of the volatile memory chip; and, the orthographic projection of the routing unit falls within the range of the orthographic projection of the nonvolatile memory chip; the plurality of logic circuits are electrically connected through the routing unit, and the plurality of logic circuits are electrically connected with the communication protocol circuit through the routing unit respectively.

In one possible implementation, the nonvolatile three-dimensional memory cell further comprises a memory control circuit, the memory control circuit being disposed on the volatile memory chip; and/or, the memory control circuit is arranged on the interface chip; a nonvolatile memory control circuit provided on the nonvolatile memory chip; and/or the nonvolatile memory control circuit is arranged on the interface chip.

In one possible embodiment, the number of memory control circuits is greater than or equal to the sum of the number of communication protocol circuits and the number of logic circuits; the number of nonvolatile memory control circuits is greater than or equal to the sum of the number of communication protocol circuits and the number of logic circuits.

In one possible embodiment, the communication protocol includes at least one of a CXL protocol, a CCIX protocol, a GEN Z protocol, an OpenCPAI protocol, and an Nvlink protocol.

In one possible implementation, the number of the volatile memory chips is at least two, and the at least two volatile memory chips are connected through a three-dimensional heterogeneous integrated structure in a three-dimensional stacking manner.

In a possible implementation manner, the number of the interface chips is at least two, and the at least two interface chips are connected in a three-dimensional stacking manner through a three-dimensional heterogeneous integrated structure; or at least two interface chips are respectively connected with the volatile memory chip in a three-dimensional stacking manner through the three-dimensional heterogeneous integrated structure.

In a possible implementation manner, the number of the nonvolatile memory chips is at least two, and the at least two nonvolatile memory chips are connected through a three-dimensional heterogeneous integrated structure in a three-dimensional stacking manner; or at least two nonvolatile memory chips are respectively connected with the volatile memory chip and the interface chip in a three-dimensional stacking mode through the three-dimensional heterogeneous integrated structure.

In a possible implementation, the orthographic projection of the volatile memory chip, the orthographic projection of the interface chip and the orthographic projection of the nonvolatile memory chip are completely overlapped.

In a possible implementation manner, the nonvolatile three-dimensional memory unit further comprises a capacitor, and the capacitor is electrically connected with the nonvolatile memory chip and used for supplying power to the nonvolatile memory chip.

In a second aspect, embodiments of the present application provide a nonvolatile three-dimensional memory chip assembly, including the nonvolatile three-dimensional memory cell as described in the first aspect above; the substrate is electrically connected with the nonvolatile three-dimensional storage unit and used for packaging the nonvolatile three-dimensional storage unit.

In a third aspect, embodiments of the present application provide an electronic device, comprising a processor; as in the nonvolatile three-dimensional memory chip assembly of the second aspect above, the nonvolatile three-dimensional memory chip assembly is electrically connected to the processor.

The embodiment of the application has the following beneficial effects:

by arranging the communication protocol circuit on the interface chip, data can be written into at least one of the volatile memory chip and the nonvolatile memory chip in a cache consistency mode and can be read from at least one of the volatile memory chip and the nonvolatile memory chip in the cache consistency mode, so that the data can be stored and read without being transmitted to other components (such as a mainboard and the like), the transmission path of the data is shortened, the transmission time of the data is shortened, the time delay of the data storage and reading processes is reduced, the efficiency of the nonvolatile three-dimensional memory unit for storing and reading the data is improved, and the service performance of the nonvolatile three-dimensional memory unit is improved.

In addition, the data are set to be written into the nonvolatile memory chip through the three-dimensional heterogeneous integrated structure, a transmission path when the data are written into the nonvolatile memory chip is shortened, the storage reliability of the data is further improved, the risk of data loss is reduced, and the use reliability of the nonvolatile three-dimensional memory unit is improved.

In addition, the volatile memory chip, the interface chip and the nonvolatile memory chip are connected in a three-dimensional stacking mode through the three-dimensional heterogeneous integrated structure, on one hand, a data transmission path is shortened, the data processing bandwidth of the nonvolatile three-dimensional memory unit is greatly increased, the power consumption of the nonvolatile three-dimensional memory unit is reduced, access conflicts are avoided, and the use performance of the nonvolatile three-dimensional memory unit is improved. On the other hand, the occupied area of the nonvolatile three-dimensional storage unit can be reduced, and the use flexibility of the nonvolatile three-dimensional storage unit is improved.

Drawings

Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a nonvolatile three-dimensional memory cell according to an embodiment of the present disclosure;

FIG. 2 is a second schematic diagram of a nonvolatile three-dimensional memory cell according to an embodiment of the present disclosure;

FIG. 3 is a third schematic diagram illustrating a nonvolatile three dimensional memory cell according to an embodiment of the present invention;

FIG. 4 is a fourth schematic diagram illustrating a nonvolatile three-dimensional memory cell according to an embodiment of the present disclosure;

FIG. 5 is a fifth exemplary schematic view of a nonvolatile three-dimensional memory cell according to the present application;

FIG. 6 is a schematic diagram of a programmable logic circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of an interface chip according to an embodiment of the present disclosure;

FIG. 8 is a sixth schematic view of a nonvolatile three dimensional memory cell according to an embodiment of the present disclosure;

FIG. 9 is a flowchart illustrating steps of a method for storing data according to an embodiment of the present disclosure;

FIG. 10 is a flowchart illustrating a second step of a data storage method according to an embodiment of the present application;

FIG. 11 is a schematic structural diagram of a nonvolatile three-dimensional memory chip assembly according to an embodiment of the present disclosure;

fig. 12 is a block diagram illustrating a structure of an electronic device according to an embodiment of the present disclosure.

Wherein, the correspondence between the reference numbers and the component names in fig. 1 to 12 is:

100: nonvolatile three-dimensional memory cell, 110: volatile memory chip, 112: first storage array, 114: second storage array, 116: third storage array, 118: fourth storage array, 120: interface chip, 122: communication protocol circuit, 124: logic circuit, 126: fixed logic circuit, 128: programmable logic circuit, 130: nonvolatile memory chip, 131: embedded programmable logic circuit, 132: embedded multiplication circuit, 133: embedded memory unit, 134: routing unit, 140: three-dimensional heterogeneous integrated structure, 142: first three-dimensional hetero-integrated structure, 144: second three-dimensional hetero-integrated structure, 146: third-dimensional hetero-integrated structure, 148: fourth-dimensional heterogeneous integrated structure, 200: non-volatile three-dimensional memory chip assembly, 210: substrate, 212: pin, 300: electronic device, 310: a processor.

Detailed Description

In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the utility model will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.

In some examples, data is typically processed through a communication protocol stored on the motherboard when the data is stored and read. Specifically, when data is stored, the data needs to be transmitted to the motherboard, and after the data is processed by a communication protocol stored on the motherboard, the data is transmitted to the volatile memory chip for storage. When data stored in the volatile memory chip is read, the data also needs to be transmitted to the main board, and after the data is processed through a communication protocol stored on the main board, the data is transmitted to the processor or other components, so that the data stored in the volatile memory chip can be sent out. Therefore, data can be stored and read only by being transmitted between the mainboard and the volatile memory chip, and the transmission path of the data is increased, so that the transmission time of the data is prolonged, and the storage and reading efficiency of the data is reduced.

Furthermore, in some examples, the volatile memory chip is communicatively coupled to the non-volatile memory chip such that when the volatile memory chip is powered down, data within the volatile memory chip needs to be transferred to the non-volatile memory chip to avoid data loss. However, the volatile memory chip and the nonvolatile memory chip are in communication connection to transmit data, so that a transmission path of the data is prolonged, transmission time of the data is prolonged, transmission efficiency of the data is reduced, and risk of data loss is increased.

In order to solve at least one of the above technical problems, in a first aspect, as shown in fig. 1, an embodiment of the present application provides a nonvolatile three-dimensional memory cell 100. The nonvolatile three-dimensional memory cell 100 includes a volatile memory chip 110, an interface chip 120, and a nonvolatile memory chip 130. The volatile memory chip 110 is used to store data. The interface chip 120 is connected to the volatile memory chip 110 by three-dimensional stacking through the three-dimensional hetero-integrated structure 140. The nonvolatile memory chip 130 is three-dimensionally stacked and connected with at least one of the volatile memory chip 110 and the interface chip 120 through the three-dimensional hetero-integrated structure 140 to form the nonvolatile three-dimensional memory cell 100. The interface chip 120 includes a communication protocol circuit 122, and the communication protocol circuit 122 is used for storing a communication protocol. Data is written to at least one of the volatile memory chip 110 and the non-volatile memory chip 130 in a cache coherent manner by the communication protocol circuit 122; and, data is read from at least one of the volatile memory chip 110 and the non-volatile memory chip 130 in a cache coherent manner by the communication protocol circuit 122.

It is understood that both the volatile memory chip 110 and the non-volatile memory chip 130 are used to store data. When the nonvolatile three-dimensional memory cell 100 is powered off, the data stored in the volatile memory chip 110 is lost, and the data stored in the nonvolatile memory chip 130 can be saved.

In some examples, the storage capacities of the volatile memory chip 110 and the non-volatile memory chip 130 may be the same or different. In some examples, the storage capacity of the nonvolatile memory chip 130 is greater than that of the volatile memory chip 110, so that data in the volatile memory chip 110 can be written into the nonvolatile memory chip 130, and the reliability of the nonvolatile three-dimensional memory unit 100 is improved.

In some examples, the volatile Memory chip 110 may be a DRAM Memory (Dynamic Random Access Memory). The nonvolatile memory chip 130 may be a PROM (Programmable read-only memory), an EEPROM (Electrically Erasable Programmable read-only memory), an EPROM (Erasable Programmable read-only memory), or the like.

As can be appreciated, the interface chip 120 is used to receive data. The interface chip 120 is connected to the volatile memory chip 110 by three-dimensional stacking through the three-dimensional heterogeneous integrated structure 140, so that the interface chip 120 can transmit the received data to the volatile memory chip 110 for storage. Similarly, the data stored in the volatile memory chip 110 can be read by the interface chip 120 through the three-dimensional hetero-integrated structure 140 and transmitted to the outside of the nonvolatile three-dimensional memory cell 100 via the interface chip 120. In some examples, the interface chip 120 is made of silicon, and the semiconductor element may be integrated on the interface chip 120.

The nonvolatile memory chip 130 is connected to at least one of the volatile memory chip 110 and the interface chip 120 by the three-dimensional heterogeneous integrated structure 140 in a three-dimensional stacked manner, and it can be understood that when the nonvolatile memory chip 130 is connected to the volatile memory chip 110 by the three-dimensional heterogeneous integrated structure 140 in a three-dimensional stacked manner, data in the volatile memory chip 110 can be written into the nonvolatile memory chip 130 by the three-dimensional heterogeneous integrated structure 140. Similarly, data stored in the nonvolatile memory chip 130 can be transmitted to the volatile memory chip 110 through the three-dimensional hetero-integrated structure 140.

When the nonvolatile memory chip 130 is three-dimensionally stacked and connected with the interface chip 120 through the three-dimensional hetero-integrated structure 140, data received by the interface chip 120 can be written into the nonvolatile memory chip 130 through the three-dimensional hetero-integrated structure 140. Similarly, data stored in the nonvolatile memory chip 130 can also be transmitted to the interface chip 120 through the three-dimensional hetero-integrated structure 140.

It can be understood that the three-dimensional heterogeneous integrated structure 140 can directly interconnect metal layers inside two different chips (for example, the interface chip 120 and the volatile memory chip 110) across chips, and high-density metal layer interconnections inside the chips are established layer by layer, so that data can be transmitted between the two different chips without setting an input/output interface (IO interface) or an input/output circuit (IO circuit), a transmission path of the data is shortened, and transmission efficiency of the data is improved.

In some examples, the three-dimensional hetero-integrated structure 140 may be formed by hybrid bonding to enable data transfer between the volatile memory chip 110, the interface chip 120, and the non-volatile memory chip 130.

Therefore, through the arrangement, data are transmitted among the volatile memory chip 110, the interface chip 120 and the nonvolatile memory chip 130 through the three-dimensional heterogeneous integrated structure 140, so that the bandwidth of the nonvolatile three-dimensional memory unit 100 for processing data is greatly increased, the power consumption of the nonvolatile three-dimensional memory unit 100 is reduced, access conflicts are avoided, and the service performance of the nonvolatile three-dimensional memory unit 100 is improved. In addition, through the arrangement, the occupied area of the nonvolatile three-dimensional storage unit 100 can be reduced, and the use flexibility of the nonvolatile three-dimensional storage unit 100 can be improved.

In addition, the set data is written into the nonvolatile memory chip 130 through the three-dimensional heterogeneous integrated structure 140, so that the transmission path for writing the data into the nonvolatile memory chip 130 is shortened, the storage reliability of the data is further improved, the risk of data loss is reduced, and the use reliability of the nonvolatile three-dimensional memory unit 100 is improved.

As shown in fig. 1, the interface chip 120 includes a communication protocol circuit 122, and the communication protocol circuit 122 is used for storing a communication protocol. In some examples, the communication protocol circuit 122 may be disposed on the interface chip 120 by etching.

It will be appreciated that the communication protocol circuit 122 is capable of processing data in accordance with a stored communication protocol. After being processed by the communication protocol circuit 122, the data can be written into at least one of the volatile memory chip 110 and the nonvolatile memory chip 130 in a cache coherent manner, and can be read from at least one of the volatile memory chip 110 and the nonvolatile memory chip 130.

It is to be understood that the data written to at least one of the volatile memory chip 110 and the non-volatile memory chip 130 in a cache coherent manner and capable of being read from at least one of the volatile memory chip 110 and the non-volatile memory chip 130 in a cache coherent manner means that link consistency can be maintained between the communication protocol circuit 122 and the volatile memory chip 110 and also between the communication protocol circuit 122 and the non-volatile memory chip 130. In this way, data can be stored and read in the communication protocol circuit 122 and the volatile memory chip 110 without being processed by other components (such as a motherboard, etc.), and can also be stored and read between the communication protocol circuit 122 and the nonvolatile memory chip 130, so that the transmission path of the data is shortened, and the storage and reading efficiency of the data is improved.

It is understood that link consistency can also be maintained between the volatile memory chip 110 and the non-volatile memory chip 130. Therefore, when the nonvolatile memory chip 130 is connected with the volatile memory chip 110 in a three-dimensional stacked manner through the three-dimensional heterogeneous integrated structure 140, data processed by the communication protocol circuit 122 can be stored and read between the volatile memory chip 110 and the nonvolatile memory chip 130, the efficiency of processing data by the nonvolatile three-dimensional memory unit 100 is further improved, data loss is avoided, and reliable data storage is ensured.

As can be seen from the above, by providing the communication protocol circuit 122 on the interface chip 120, data can be written into at least one of the volatile memory chip 110 and the nonvolatile memory chip 130 in a cache coherent manner, and can be read from at least one of the volatile memory chip 110 and the nonvolatile memory chip 130 in a cache coherent manner, so that data can be stored and read without transmitting the data to other components (such as a motherboard, etc.), a transmission path of the data is shortened, transmission time of the data is reduced, a delay of a data storage and reading process is reduced, efficiency of the nonvolatile three-dimensional memory unit 100 in storing and reading the data is improved, and usability of the nonvolatile three-dimensional memory unit 100 is improved.

In some examples, the number of communication protocol circuits 122 may be one or more. The communication protocols stored in the different communication protocol circuits 122 may be the same or different. In some examples, multiple communication protocols may be stored in one communication protocol circuit 122.

In some examples, as shown in fig. 2, interface chip 120 also includes logic 124. The logic circuit 124 is electrically connected to the communication protocol circuit 122. Data is written to at least one of the volatile memory chip 110 and the non-volatile memory chip 130 in a cache coherent manner through the communication protocol circuit 122 and the logic circuit 124, and data is read from at least one of the volatile memory chip 110 and the non-volatile memory chip 130 in a cache coherent manner through the communication protocol circuit 122 and the logic circuit 124.

It will be appreciated that the logic circuit 124 stores computational logic to enable logical computations on the data. In some examples, the logic circuit 124 may be an analog-to-digital conversion circuit, a comparison circuit, an amplification circuit, or the like. In some examples, the logic 124 may be disposed on the interface chip 120 by etching. In some examples, the number of logic circuits 124 may be multiple, and the computational logic stored on different logic circuits 124 may be the same or different.

It will be appreciated that the communication protocol circuit 122 is electrically connected to the logic circuit 124 such that data can be transferred between the communication protocol circuit 122 and the logic circuit 124. In some examples, the communication protocol circuitry 122 may be electrically connected with the logic circuitry 124 by copper wires.

Specifically, when storing data, the communication protocol circuit 122 may transmit the processed data to the logic circuit 124, and the logic circuit 124 performs logic calculation processing on the data and then writes the data into at least one of the volatile memory chip 110 and the nonvolatile memory chip 130. When reading data, data in at least one of the volatile memory chip 110 and the nonvolatile memory chip 130 can be transmitted to the logic circuit 124, the logic circuit 124 performs logic calculation processing on the data and then transmits the data to the communication protocol circuit 122, and the communication protocol circuit 122 transmits the processed data to the outside of the nonvolatile three-dimensional memory unit 100.

As can be seen from the above description, the logic circuit 124 is electrically connected to the communication protocol circuit 122, so that data can be transmitted between the communication protocol circuit 122 and the logic circuit 124, and thus, not only can the storage and reading of data be realized in a cache-coherent manner by the communication protocol circuit 122, but also the logic calculation of data can be realized by the logic circuit 124. In this way, when data is stored and read, logical calculation of the data can be realized without transmitting the data to other components (for example, a programmable memory controller, etc.), so that a transmission path of the data is further shortened, transmission time of the data is reduced, processing efficiency of the nonvolatile three-dimensional memory unit 100 on the data is improved, the nonvolatile three-dimensional memory unit 100 can realize a logical processing function on the data, and usability of the nonvolatile three-dimensional memory unit 100 is further improved.

In some examples, the communication protocol circuitry 122 and the logic circuitry 124 may be disposed in different areas on the interface chip 120. In some examples, the communication protocol circuit 122 and the logic circuit 124 may also be disposed in the same area on the interface chip 120.

In some examples, as shown in fig. 3, the volatile memory chip 110 includes a first memory array 112 and a second memory array 114. The communication protocol circuit 122 is electrically connected to the first memory array 112 through the first three-dimensional hetero-integrated structure 142. The logic circuit 124 is electrically connected to the second memory array 114 through a second three-dimensional hetero-integrated structure 144. The orthographic projection of the communication protocol circuitry 122 falls within the range of the orthographic projection of the first storage array 112 and the orthographic projection of the logic circuitry 124 falls within the range of the orthographic projection of the second storage array 114.

It is understood that the number of the first storage array 112 and the second storage array 114 may be plural. The first memory array 112 and the second memory array 114 may be identical in shape and area or may be different. The first memory array 112 and the second memory array 114 in the embodiment of the present application are only used for distinguishing two different memory regions on the volatile memory chip 110, and the first memory array 112 and the second memory array 114 are not further limited.

The communication protocol circuit 122 is electrically connected to the first memory array 112 through the first three-dimensional heterogeneous integrated structure 142, so that the data processed by the communication protocol circuit 122 can be transmitted to the first memory array 112 through the first three-dimensional heterogeneous integrated structure 142 for storage. Similarly, data stored within the first memory array 112 can also be transmitted to the communication protocol circuit 122 through the first three-dimensional heterogeneous integrated structure 142.

The logic circuit 124 is electrically connected to the second memory array 114 through the second three-dimensional heterogeneous integrated structure 144 such that data processed by the logic circuit 124 can be transmitted to the second memory array 114 through the second three-dimensional heterogeneous integrated structure 144. Similarly, data stored in the second memory array 114 can also be transferred to the logic circuit 124 through the second three-dimensional hetero-integrated structure 144.

It is understood that the first three-dimensional heterogeneous integrated structure 142 and the second three-dimensional heterogeneous integrated structure 144 may be the same or different. The first three-dimensional hetero-integrated structure 142 and the second three-dimensional hetero-integrated structure 144 in the embodiments of the present application are only used to distinguish the three-dimensional hetero-integrated structure 140 disposed between the communication protocol circuit 122 and the first storage array 112 from the three-dimensional hetero-integrated structure 140 disposed between the logic circuit 124 and the second storage array 114, and the first three-dimensional hetero-integrated structure 142 and the second three-dimensional hetero-integrated structure 144 are not further limited.

As can be seen from the above, the logic circuit 124 is electrically connected to the communication protocol circuit 122. Thus, when storing data into the volatile memory chip 110, if there is no need to perform logic calculation on the data processed by the communication protocol circuit 122, the data can be directly transmitted to the first memory array 112 through the first three-dimensional hetero-integrated structure 142 for storage. If the data processed by the communication protocol circuit 122 needs to be logically calculated, the data processed by the communication protocol circuit 122 may be transmitted to the logic circuit 124, and the data is transmitted to the second storage array 114 for storage through the second three-dimensional heterogeneous integrated structure 144 after being logically calculated by the logic circuit 124.

Similarly, when reading data in the volatile memory chip 110, if no logic computation is needed for the data, the data may be transmitted to the communication protocol circuit 122 through the first three-dimensional heterogeneous integrated structure 142, and transmitted to the outside of the nonvolatile three-dimensional memory cell 100 after being processed by the communication protocol circuit 122. If the data needs to be logically calculated, the data can be transmitted to the logic circuit 124 through the second three-dimensional heterogeneous integrated structure 144, the data is logically calculated and processed through the logic circuit 124, and then transmitted to the communication protocol circuit 122, and then transmitted to the outside of the nonvolatile three-dimensional memory unit 100 after being processed by the communication protocol circuit 122.

As can be seen from the above, the communication protocol circuit 122 is electrically connected to the first storage array 112 through the first three-dimensional heterogeneous integrated structure 142, and the logic circuit 124 is electrically connected to the second storage array 114 through the second three-dimensional heterogeneous integrated structure 144, so that data can be directly stored after being processed by the communication protocol circuit 122, or data can be stored after being processed by the communication protocol circuit 122 and the logic circuit 124, which satisfies processing requirements of different data, and improves flexibility of use of the nonvolatile three-dimensional storage unit 100.

Moreover, with the above arrangement, the differently processed data (data subjected to logic calculation and data not subjected to logic calculation) can be transmitted through the different three-dimensional heterogeneous integrated structures 140 (the first three-dimensional heterogeneous integrated structure 142 and the second three-dimensional heterogeneous integrated structure 144), and the differently processed data can be stored in the different storage arrays (the first storage array 112 and the second storage array 114), so that crosstalk during data transmission and storage is reduced, and the reliability of the nonvolatile three-dimensional storage unit 100 is improved.

In addition, the orthographic projection of the communication protocol circuit 122 falls within the range of the orthographic projection of the first storage array 112, that is, the setting position of the communication protocol circuit 122 corresponds to the setting position of the first storage array 112. The orthographic projection of the logic circuit 124 falls within the range of the orthographic projection of the second storage array 114, that is, the setting position of the logic circuit 124 corresponds to the setting position of the second storage array 114. By the above arrangement, the distance between the communication protocol circuit 122 and the first storage array 112 and the distance between the logic circuit 124 and the second storage array 114 are reduced, so as to further shorten the transmission path of data, reduce the transmission time of data, and improve the efficiency of data storage and reading.

In some examples, as shown in fig. 4, the non-volatile memory chip 130 is connected to the interface chip 120 by a three-dimensional heterogeneous integrated structure 140 in a three-dimensional stack. The non-volatile memory chip 130 includes a third memory array 116 and a fourth memory array 118. The communication protocol circuit 122 is electrically connected to the third memory array 116 through a third three-dimensional heterogeneous integrated structure 146. The logic circuit 124 is electrically connected to the fourth memory array 118 through a fourth three-dimensional hetero-integrated structure 148. The orthographic projection of communication protocol circuitry 122 falls within the orthographic projection of third storage array 116 and the orthographic projection of logic circuitry 124 falls within the orthographic projection of fourth storage array 118.

It is understood that the number of the third storage array 116 and the fourth storage array 118 may be plural. The third memory array 116 and the fourth memory array 118 may be identical in shape and area or may be different. The third storage array 116 and the fourth storage array 118 in the embodiment of the present application are only used to distinguish two different storage areas on the nonvolatile memory chip 130, and the third storage array 116 and the fourth storage array 118 are not further limited.

As shown in fig. 4, when the nonvolatile memory chip 130 is three-dimensionally stacked and connected with the interface chip 120 through the three-dimensional hetero-integrated structure 140, the communication protocol circuit 122 is electrically connected with the third memory array 116 through the third three-dimensional hetero-integrated structure 146, so that data processed by the communication protocol circuit 122 can be transmitted to the third memory array 116 through the third three-dimensional hetero-integrated structure 146 for storage. Similarly, data stored within the third memory array 116 can also be transmitted to the communication protocol circuit 122 through the third three-dimensional heterogeneous integrated structure 146.

The logic circuit 124 is electrically connected to the fourth memory array 118 through the fourth three-dimensional hetero-integrated structure 148 such that data processed by the logic circuit 124 can be transmitted to the fourth memory array 118 through the fourth three-dimensional hetero-integrated structure 148. Similarly, data stored in the fourth memory array 118 can also be transferred to the logic circuit 124 through the fourth three-dimensional hetero-integrated structure 148.

It is understood that the third three-dimensional heterogeneous integrated structure 146 and the fourth three-dimensional heterogeneous integrated structure 148 may be the same or different. The third three-dimensional hetero-integrated structures 146 and the fourth three-dimensional hetero-integrated structures 148 in the embodiments of the present application are only used to distinguish the three-dimensional hetero-integrated structures 140 disposed between the communication protocol circuit 122 and the third storage array 116 from the three-dimensional hetero-integrated structures 140 disposed between the logic circuit 124 and the fourth storage array 118, and the third three-dimensional hetero-integrated structures 146 and the fourth three-dimensional hetero-integrated structures 148 are not further limited.

As can be seen from the above, the logic circuit 124 is electrically connected to the communication protocol circuit 122. Therefore, when data is stored in the nonvolatile memory chip 130, if there is no need to perform logic calculation on the data processed by the communication protocol circuit 122, the data can be directly transmitted to the third memory array 116 through the third three-dimensional heterogeneous integrated structure 146 for storage. If the data processed by the communication protocol circuit 122 needs to be logically calculated, the data processed by the communication protocol circuit 122 may be transmitted to the logic circuit 124, and the data is transmitted to the fourth storage array 118 for storage through the fourth three-dimensional heterogeneous integrated structure 148 after being logically calculated by the logic circuit 124.

Similarly, when reading the data in the nonvolatile memory chip 130, if the data does not need to be logically calculated, the data can be transmitted to the communication protocol circuit 122 through the third three-dimensional heterogeneous integrated structure 146, and then transmitted to the outside of the nonvolatile three-dimensional memory unit 100 after being processed by the communication protocol circuit 122. If the data needs to be logically calculated, the data can be transmitted to the logic circuit 124 through the fourth three-dimensional heterogeneous integrated structure 148, the data is logically calculated and processed through the logic circuit 124, and then transmitted to the communication protocol circuit 122, and then transmitted to the outside of the nonvolatile three-dimensional memory unit 100 after being processed by the communication protocol circuit 122.

As can be seen from the above, the communication protocol circuit 122 is electrically connected to the third storage array 116 through the third three-dimensional heterogeneous integrated structure 146, and the logic circuit 124 is electrically connected to the fourth storage array 118 through the fourth three-dimensional heterogeneous integrated structure 148, so that data can be directly stored after being processed by the communication protocol circuit 122, or data can be stored after being processed by the communication protocol circuit 122 and the logic circuit 124, which meets the processing requirements of different data, and improves the flexibility of the nonvolatile three-dimensional storage unit 100.

Moreover, through the arrangement, the data subjected to different processes (the data subjected to logic calculation and the data not subjected to logic calculation) can be transmitted through the different three-dimensional heterogeneous integrated structures 140 (the third three-dimensional heterogeneous integrated structure 146 and the fourth three-dimensional heterogeneous integrated structure 148), and the data subjected to different processes can be stored in different storage arrays (the third storage array 116 and the fourth storage array 118), so that the crosstalk in the data transmission and storage processes is reduced, and the use reliability of the nonvolatile three-dimensional storage unit 100 is improved.

In addition, the orthographic projection of the communication protocol circuit 122 falls within the range of the orthographic projection of the third storage array 116, that is, the setting position of the communication protocol circuit 122 corresponds to the setting position of the third storage array 116. The orthographic projection of the logic circuit 124 falls within the range of the orthographic projection of the fourth storage array 118, that is, the setting position of the logic circuit 124 corresponds to the setting position of the fourth storage array 118. With the above arrangement, the distance between the communication protocol circuit 122 and the third storage array 116 and the distance between the logic circuit 124 and the fourth storage array 118 are reduced, so as to further shorten the transmission path of data, reduce the transmission time of data, and improve the efficiency of data storage and reading.

In some examples, as shown in fig. 4, the orthographic projection of the communication protocol circuit 122 falls within the orthographic projection range of the first storage array 112 and the third storage array 116, and the orthographic projection of the logic circuit 124 falls within the orthographic projection range of the second storage array 114 and the fourth storage array 118, so that the transmission path of data is further shortened, and the transmission efficiency of data is improved.

In some examples, as shown in fig. 5, the logic circuit 124 includes at least one of a fixed logic circuit 126 and a programmable logic circuit 128.

It will be appreciated that fixed logic 126 stores fixed computational logic and programmable logic 128 stores programmable computational logic. By setting the logic circuit 124 to include at least one of the fixed logic circuit 126 and the programmable logic circuit 128, different logic circuits 124 can be set to process data according to different processing requirements, and the applicability of the nonvolatile three-dimensional memory cell 100 is improved.

In some examples, when the logic circuit 124 includes the fixed logic circuit 126 and the programmable logic circuit 128, the fixed logic circuit 124 and the programmable logic circuit 128 may be electrically connected, so that data can be transmitted between the fixed logic circuit 124 and the programmable logic circuit 128, further improving the flexibility of the nonvolatile three-dimensional memory cell 100.

In some examples, as shown in fig. 6, programmable logic circuit 128 includes an embedded programmable logic circuit 131, an embedded multiplication circuit 132, and an embedded memory unit 133. The embedded programmable logic circuit 131 is electrically connected to at least one of the volatile memory chip 110 and the non-volatile memory chip 130, thereby enabling the programmable logic circuit 128 to perform data transfer with at least one of the volatile memory chip 110 and the non-volatile memory chip 130. The embedded memory unit 133 may be electrically connected to the embedded programmable logic circuit 131 by routing or the like. The embedded multiplication circuit 132 may be electrically connected to the embedded programmable logic circuit 131 through an interface or the like.

By arranging the embedded programmable logic circuit 131, the embedded multiplication circuit 132 and the embedded storage unit 133, the computational logic of the programmable logic circuit 128 can be modified, and the applicability of the nonvolatile three-dimensional storage unit 100 is improved.

In some examples, as shown in fig. 7, the number of logic circuits 124 is plural, and the plurality of logic circuits 124 are disposed around the communication protocol circuit 122.

It will be appreciated that a plurality of logic circuits 124 are used to store different computational logic. In some examples, the plurality of logic circuits 124 may be respectively electrically connected with the communication protocol circuit 122 such that any one of the logic circuits 124 is capable of transmitting data with the communication protocol circuit 122. In some examples, at least one connection logic circuit is included in the plurality of logic circuits 124, the connection logic circuit is electrically connected to the communication protocol circuit 122, and the remaining logic circuits 124 are electrically connected to the connection logic circuit, so that the plurality of logic circuits 124 can realize data transmission with the communication protocol circuit 122 through the connection logic circuit.

By setting the number of the logic circuits 124 to be plural and the plural logic circuits 124 to be arranged around the communication protocol circuit 122, the distance between the logic circuits 124 and the communication protocol circuit 122 is further reduced, thereby shortening the transmission path of data and further improving the processing efficiency of the nonvolatile three-dimensional memory cell 100 for data.

In some examples, as shown in fig. 7, the nonvolatile three dimensional memory cell 100 also includes a routing unit 134. The orthographic projection of the routing unit 134 falls within the range of the orthographic projection of the volatile memory chip 110; and, the orthographic projection of the routing unit 134 falls within the range of the orthographic projection of the nonvolatile memory chip 130. The plurality of logic circuits 124 are electrically connected to each other by the routing unit 134, and the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 by the routing unit 134.

It is understood that the routing unit 134 may be a NOC routing unit (network on chip), and data can be transmitted on the routing unit 134.

Specifically, as shown in fig. 5, the orthographic projection of the routing unit 134 falls within the range of the orthographic projection of the volatile memory chip 110 and the nonvolatile memory chip 130, that is, the setting position of the routing unit 134 corresponds to the setting position of the volatile memory chip 110 and the setting position of the nonvolatile memory chip 130.

As can be seen from the above, the setting position of the communication protocol circuit 122 corresponds to the setting position of the first storage array 112 and the setting position of the third storage array 116, that is, the setting position of the communication protocol circuit 122 corresponds to the setting position of the volatile memory chip 110 and the setting position of the nonvolatile memory chip 130. The setting position of the logic circuit 124 corresponds to the setting position of the second storage array 114 and the setting position of the fourth storage array 118, that is, the setting position of the logic circuit 124 corresponds to the setting position of the volatile memory chip 110 and the setting position of the nonvolatile memory chip 130. Therefore, the installation position of the installation route unit 134 corresponds to the installation position of the volatile memory chip 110 and the installation position of the nonvolatile memory chip 130, and thus the distance for data transmission between the communication protocol circuit 122 and the logic circuit 124 can be shortened, and the data transmission path between the communication protocol circuit 122 and the logic circuit 124 can be further shortened, thereby improving the data transmission efficiency.

In some examples, the routing unit 134 is disposed between the communication protocol circuit 122 and the plurality of logic circuits 124.

Specifically, as shown in fig. 7, the plurality of logic circuits 124 are electrically connected to each other through the routing unit 134, and the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing unit 134, respectively, so that data can be transmitted not only between the communication protocol circuit 122 and the logic circuit 124 but also between the plurality of logic circuits 124.

In some examples, the data processed by the communication protocol circuit 122 is transmitted to the routing unit 134, transmitted to a logic circuit 124 through the routing unit 134, processed by the logic circuit 124, and written into the volatile memory chip 110 and the nonvolatile memory chip 130 for storage.

In some examples, the data processed by the communication protocol circuit 122 is transmitted to the routing unit 134, transmitted to one logic circuit 124 through the routing unit 134, processed by one logic circuit 124, transmitted to the routing unit 134 again, transmitted to another one or more logic circuits 124 through the routing unit 134, processed by another one or more logic circuits 124, and written into the volatile memory chip 110 and the nonvolatile memory chip 130 for storage.

As can be seen from the above, by setting the plurality of logic circuits 124 to be electrically connected through the routing unit 134, and the plurality of logic circuits 124 to be electrically connected to the communication protocol circuit 122 through the routing unit 134, the data processed by the communication protocol circuit 122 can be received and processed by one or more different logic circuits 124, so that different logic calculation processes for the data are realized, different data processing requirements are met, and the applicability of the nonvolatile three-dimensional storage unit 100 is further improved.

In addition, with the above arrangement, the data transmission path can be further shortened, and the processing efficiency of the nonvolatile three-dimensional memory cell 100 for data can be improved.

In some examples, the nonvolatile three dimensional memory cell 100 also includes memory control circuitry and nonvolatile memory control circuitry. The memory control circuit is provided on the volatile memory chip 110; and/or memory control circuitry is provided on interface chip 120. The nonvolatile memory control circuit is provided on the nonvolatile memory chip 130; and/or, non-volatile memory control circuitry is disposed on interface chip 120.

In some examples, the number of the memory control circuits and the number of the nonvolatile memory control circuits may be one or more, improving the efficiency of storing and reading data. In some examples, the memory control circuit and the nonvolatile memory control circuit may be an MC (memory controller). It is to be understood that the number of nonvolatile memory control circuits and the number of memory control circuits may be the same or different.

By arranging the memory control circuit on the volatile memory chip 110 and/or the interface chip 120, that is, by arranging the memory control circuit on at least one of the volatile memory chip 110 and the interface chip 120, different use requirements can be met, and the flexibility of the nonvolatile three-dimensional memory unit 100 is improved.

In addition, by disposing the nonvolatile memory control circuit on the nonvolatile memory chip 130 and/or the interface chip 120, that is, by disposing the nonvolatile memory control circuit on at least one of the nonvolatile memory chip 130 and the interface chip 120, different use requirements can be met, and the flexibility of the nonvolatile three-dimensional memory unit 100 is further improved.

In some examples, the memory control circuitry may be disposed on the volatile memory chip 110 and/or the interface chip 120 by way of etching. The nonvolatile memory control circuit may also be disposed on the nonvolatile memory chip 130 and/or the interface chip 120 by etching.

In some examples, the number of memory control circuits is greater than or equal to the sum of the number of communication protocol circuits 122 and logic circuits 124. The number of non-volatile memory control circuits is greater than or equal to the sum of the number of communication protocol circuits 122 and logic circuits 124.

The number of the storage control circuits is larger than or equal to the sum of the number of the communication protocol circuits 122 and the number of the logic circuits 124, so that when data are stored, the data in the communication protocol circuits 122 and the data in the different logic circuits 124 can be ensured to be written into the volatile memory chip 110 in time through the storage control circuits, the data are prevented from being accumulated in the communication protocol circuits 122 or the logic circuits 124, and the use reliability of the nonvolatile three-dimensional memory unit 100 is improved.

Similarly, when reading data, the memory control circuit can transmit the data to the communication protocol circuit 122 or the plurality of different logic circuits 124 in time, so as to avoid that the communication protocol circuit 122 or the logic circuit 124 is idle due to too small amount of data in the communication protocol circuit 122 or the logic circuit 124, which affects the processing efficiency of the nonvolatile three-dimensional memory unit 100 on the data, and ensure the use reliability of the nonvolatile three-dimensional memory unit 100.

The number of the nonvolatile memory control circuits is larger than or equal to the sum of the number of the communication protocol circuits 122 and the number of the logic circuits 124, so that when data are stored, the data in the communication protocol circuits 122 and the data in the different logic circuits 124 can be written into the nonvolatile memory chip 130 in time through the nonvolatile memory control circuits, data are prevented from being accumulated in the communication protocol circuits 122 or the logic circuits 124, and the use reliability of the nonvolatile three-dimensional memory unit 100 is improved.

Similarly, when reading data, the nonvolatile memory control circuit can transmit the data to the communication protocol circuit 122 or the plurality of different logic circuits 124 in time, so as to avoid that the communication protocol circuit 122 or the logic circuit 124 is idle due to too small amount of data in the communication protocol circuit 122 or the logic circuit 124, which affects the processing efficiency of the nonvolatile three-dimensional memory unit 100 on the data, and further ensure the use reliability of the nonvolatile three-dimensional memory unit 100.

In some examples, the number of memory control circuits is equal to the sum of the number of communication protocol circuits 122 and logic circuits 124. The number of non-volatile memory control circuits is also equal to the sum of the number of communication protocol circuits 122 and logic circuits 124.

In some examples, the communication protocol includes at least one of a CXL protocol, a CCIX protocol, a GEN Z protocol, an OpenCPAI protocol, and an Nvlink protocol.

The communication protocol includes at least one of a CXL protocol (Compute Express Link, Compute interconnect protocol), a CCIX protocol (CCIX, cache coherent interconnect protocol of accelerator), a GEN Z protocol (Generation Z, Z Generation protocol), an OpenCPAI protocol (Open Computer Assisted Personal access protocol) and a Nvlink protocol (bus communication protocol), so that data written into the volatile memory chip 110 and the nonvolatile memory chip 130 can be processed according to different communication protocols, and data read from the volatile memory chip 110 and the nonvolatile memory chip 130 can be processed, thereby satisfying transmission requirements of different data and improving applicability of the nonvolatile three-dimensional memory unit 100. Meanwhile, by setting the communication protocol, the transmission speed of data can be further increased, and the processing efficiency of the nonvolatile three-dimensional memory unit 100 on the data can be improved.

In some examples, the communication protocol may also include other communication protocols that enable a consistent high-speed serial interface.

In some examples, the number of the volatile memory chips 110 is at least two, and at least two of the volatile memory chips 110 are connected by three-dimensional stacking through the three-dimensional hetero-integrated structure 140.

It can be understood that, by setting the number of the volatile memory chips 110 to be at least two, the storage capacity of the nonvolatile three-dimensional memory cell 100 can be increased, the usage performance of the nonvolatile three-dimensional memory cell 100 can be further improved, and different storage requirements can be met.

In addition, the at least two volatile memory chips 110 are connected in a three-dimensional stacked manner through the three-dimensional heterogeneous integrated structure 140, so that the bandwidth of the nonvolatile three-dimensional memory unit 100 for processing data is increased, the transmission efficiency of the data between the at least two volatile memory chips 110 is improved, the power consumption of the nonvolatile three-dimensional memory unit 100 is reduced, and the use performance of the nonvolatile three-dimensional memory unit 100 is improved.

In some examples, the number of the interface chips 120 is at least two, and at least two interface chips are connected by three-dimensional stacking of the three-dimensional heterogeneous integrated structure 140; or, at least two interface chips 120 are respectively connected with the volatile memory chip 110 through the three-dimensional heterogeneous integrated structure 140 in a three-dimensional stacking manner.

The number of the interface chips 120 is at least two, so that the number of the communication protocol circuits 122 and the logic circuits 124 is increased, and the processing efficiency of the nonvolatile three-dimensional memory unit 100 for data is further improved. Meanwhile, the at least two interface chips 120 are three-dimensionally stacked through the three-dimensional heterogeneous integrated structure 140, so that the bandwidth for transmitting data between the at least two interface chips 120 can be increased, the data transmission efficiency of the nonvolatile three-dimensional memory unit 100 can be improved, the power consumption of the nonvolatile three-dimensional memory unit 100 can be reduced, and the service performance of the nonvolatile three-dimensional memory unit 100 can be improved.

Or, at least two interface chips 120 are respectively connected with the volatile memory chip 110 by three-dimensional stacking through the three-dimensional heterogeneous integrated structure 140, so that different interface chips 120 can respectively receive data and write the processed data into the volatile memory chip 110, and similarly, the data stored in the volatile memory chip 110 can also be read through different interface chips 120, thereby improving the flexibility of the nonvolatile three-dimensional memory unit 100.

In some examples, the number of the nonvolatile memory chips 130 is at least two, and at least two nonvolatile memory chips 130 are connected by three-dimensional stacking through the three-dimensional heterogeneous integrated structure 140; or, as shown in fig. 8, at least two non-volatile memory chips 130 are respectively connected with the volatile memory chip 110 and the interface chip 120 by three-dimensional stacking through the three-dimensional hetero-integrated structure 140.

It can be understood that, by setting the number of the nonvolatile memory chips 130 to at least two, the storage capacity of the nonvolatile three-dimensional memory cell 100 can be increased, and the storage reliability of data can be improved.

In addition, the at least two nonvolatile memory chips 130 are connected in a three-dimensional stacked manner through the three-dimensional heterogeneous integrated structure 140, so that the bandwidth of the nonvolatile three-dimensional memory unit 100 for processing data is increased, the transmission efficiency of the data between the at least two nonvolatile memory chips 130 is improved, the power consumption of the nonvolatile three-dimensional memory unit 100 is reduced, and the use performance of the nonvolatile three-dimensional memory unit 100 is improved.

Or, as shown in fig. 8, at least two nonvolatile memory chips 130 are respectively connected with the volatile memory chip 110 and the interface chip 120 by three-dimensional stacking through the three-dimensional heterogeneous integrated structure 140, so that data can be transmitted not only between the nonvolatile memory chip 130 and the volatile memory chip 110, but also between the nonvolatile memory chip 130 and the interface chip 120, thereby meeting different use requirements and further improving the applicability of the nonvolatile three-dimensional memory unit 100.

In some examples, the front projection of the volatile memory chip 110, the front projection of the interface chip 120, and the front projection of the non-volatile memory chip 130 are all coincident.

It can be understood that the orthographic projection of the volatile memory chip 110, the orthographic projection of the interface chip 120, and the orthographic projection of the nonvolatile memory chip 130 are completely overlapped, that is, the setting position of the volatile memory chip 110, the setting position of the interface chip 120, and the setting position of the nonvolatile memory chip 130 correspond to each other, and the area of the volatile memory chip 110, the area of the interface chip 120, and the area of the nonvolatile memory chip 130 are the same or approximately the same, so that the transmission path of data among the volatile memory chip 110, the interface chip 120, and the nonvolatile memory chip 130 is further shortened, and the reliability of data transmission among the volatile memory chip 110, the interface chip 120, and the nonvolatile memory chip 130 is improved. In addition, through the arrangement, the structural regularity of the nonvolatile three-dimensional storage unit 100 can be improved, the processing is convenient, and the production efficiency of the nonvolatile three-dimensional storage unit 100 is improved.

In some examples, the nonvolatile three dimensional memory cell 100 also includes a capacitor. The capacitor is electrically connected to the nonvolatile memory chip 130, and is used for supplying power to the nonvolatile memory chip 130.

It is understood that when the nonvolatile three-dimensional memory cell 100 is powered on, the capacitor can store a certain amount of electrical energy. When the nonvolatile three-dimensional memory cell 100 is powered down, the capacitor can discharge. Because the capacitor is electrically connected with the nonvolatile memory chip 130, when the nonvolatile three-dimensional memory unit 100 is powered off, the capacitor can supply power to the nonvolatile memory chip 130, so that data from the volatile memory chip 110 or the interface chip 120 can be written into the nonvolatile memory chip 130, data loss caused by power off is avoided, the reliability of data storage is improved, and the use reliability of the nonvolatile three-dimensional memory unit 100 is improved.

In some examples, the capacitor may be a plate capacitor, thereby reducing the volume of the nonvolatile three-dimensional memory cell 100 and improving the flexibility of the nonvolatile three-dimensional memory cell 100.

In some embodiments, the embodiments of the present application provide a data storage method for the nonvolatile three-dimensional memory cell 100 of the first aspect. The volatile memory chip 110 includes a first memory array 112 and a second memory array 114. The non-volatile memory chip 130 includes a third memory array 116 and a fourth memory array 118. The interface chip 120 further includes a plurality of logic circuits 124, the plurality of logic circuits 124 are electrically connected to each other through a routing unit 134, and the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing unit 134, respectively.

Specifically, as shown in fig. 9, the data storage method includes:

and S102, receiving data from the communication protocol circuit, and storing the data from the communication protocol circuit into at least one of the first storage array and the third storage array.

Alternatively, as shown in fig. 10, the data storage method includes:

step S202, receiving data from a communication protocol circuit, and sending the data from the communication protocol to at least one logic circuit through a routing unit; and storing the data processed by the at least one logic circuit into at least one of the second storage array and the fourth storage array.

The data storage method provided by the embodiment of the present application is used for the nonvolatile three-dimensional memory cell 100 of the first aspect, and therefore, has all the beneficial effects of the first aspect, and is not described herein again.

Specifically, the data storage method comprises the steps of receiving data from the communication protocol circuit, and directly storing the data from the communication protocol circuit into at least one of the first storage array and the third storage array, so that the data processed by the communication protocol circuit can be directly written into at least one of the volatile storage chip and the nonvolatile storage chip to be stored without being processed by the logic circuit.

Or, the data storage method comprises the steps of receiving data from the communication protocol circuit, sending the data to at least one logic circuit through the routing unit, and storing the data processed by the at least one logic circuit into at least one of the second storage array and the fourth storage array, namely, the data processed by the communication protocol circuit can be written into at least one of the volatile storage chip and the nonvolatile storage chip to be stored after being processed by one or more different logic circuits.

By the two different data storage methods, the storage requirements of different data can be met, and the applicability of the data storage method is improved.

In a second aspect, as shown in fig. 11, embodiments of the present application provide a non-volatile three-dimensional memory chip assembly 200. The nonvolatile three-dimensional memory chip assembly 200 includes the nonvolatile three-dimensional memory cell 100 of the first aspect described above and a substrate 210. The substrate 210 is electrically connected to the nonvolatile three-dimensional memory cell 100. The substrate 210 is used to package the nonvolatile three-dimensional memory cell 100.

The nonvolatile three-dimensional memory chip assembly 200 provided by the embodiment of the present application includes the nonvolatile three-dimensional memory cell 100 of the first aspect, and therefore, has all the advantages of the first aspect, and is not described herein again.

In some examples, the substrate 210 includes pins 212, and the nonvolatile three-dimensional memory cell 100 is electrically connected to other components through the pins 212.

In some examples, when the plurality of volatile memory chips 110 and the plurality of interface chips 120 are three-dimensionally stacked and connected to each other, the interface chips 120 and the pins 212 may be electrically connected Through a Through Silicon Via (TSV) technology, so that data can be transmitted between the interface chips 120 and the pins 212.

In a third aspect, as shown in fig. 12, an embodiment of the present application provides an electronic device 300. The electronic device 300 comprises a processor 310 and the non-volatile three-dimensional memory chip assembly 200 as described in the third aspect above, the non-volatile three-dimensional memory chip assembly 200 being electrically connected to the processor 310.

The electronic device 300 provided by the embodiment of the present application includes the nonvolatile three-dimensional memory chip assembly 200 of the third aspect, and therefore, has all the advantages of the third aspect, and will not be described herein again.

In some examples, the electronic device 300 may be a mobile phone, a computer, or a smart appliance.

In one embodiment, a non-volatile three-dimensional memory cell 100 is provided. In some examples, the nonvolatile three dimensional memory cell 100 may be in data communication with a host.

Specifically, as shown in fig. 1, the nonvolatile three-dimensional memory cell 100 includes a volatile memory chip 110, an interface chip 120, and a nonvolatile memory chip 130. The volatile memory chip 110 and the interface chip 120 are bonded in a hybrid manner to form a three-dimensional heterogeneous integrated structure 140, so that the volatile memory chip 110 and the interface chip 120 can be connected in a three-dimensional stacked manner, and data can be transmitted between the volatile memory chip 110 and the interface chip 120. The nonvolatile memory chip 130 and the interface chip 120 are also bonded in a hybrid manner to form a three-dimensional hetero-integrated structure 140, so that the nonvolatile memory chip 130 and the interface chip 120 can be connected in a three-dimensional stacked manner, and data can be transmitted between the nonvolatile memory chip 130 and the interface chip 120.

Specifically, the volatile Memory chip 110 is a DRAM (Dynamic Random Access Memory) volatile Memory chip. The nonvolatile memory chip 130 may be a PROM (Programmable read-only memory), an EEPROM (Electrically Erasable Programmable read-only memory), an EPROM (Erasable Programmable read-only memory), or the like.

In some examples, the volatile memory chip 110 and the interface chip 120 may be connected in a three-dimensional stacked manner by using a 3D-IC (three-dimensional chip) technology, and the nonvolatile memory chip 130 and the interface chip 120 may be connected in a three-dimensional stacked manner by using a 3D-IC (three-dimensional chip) technology.

It can be understood that the volatile memory chip 110 and the interface chip 120 are connected by three-dimensional stacking through the three-dimensional heterogeneous integrated structure 140, and the nonvolatile memory chip 130 and the interface chip 120 are also connected by three-dimensional stacking through the three-dimensional heterogeneous integrated structure 140, so that data can be transmitted among the volatile memory chip 110, the interface chip 120 and the nonvolatile memory chip 130 through the three-dimensional heterogeneous integrated structure 140, the bandwidth of the nonvolatile three-dimensional memory unit 100 for processing data is greatly increased, the path for transmitting data in the nonvolatile three-dimensional memory unit 100 is shortened, the power consumption of the nonvolatile three-dimensional memory unit 100 is reduced, the time delay of data storage and reading processes is reduced, and the efficiency of data storage and reading is improved. In addition, the area of the nonvolatile three-dimensional memory cell 100 can be reduced, and the flexibility of use of the nonvolatile three-dimensional memory cell 100 can be improved.

In some examples, the processing bandwidth of the nonvolatile three-dimensional storage unit 100 for data can reach between 32GB/S and 128GB/S through the arrangement.

Specifically, the interface chip 120, the volatile memory chip 110 and the nonvolatile memory chip 130 may be three-dimensionally stacked and connected by a WoW (wafer on wafer) connection or a CoW (chip on wafer) connection.

Specifically, the nonvolatile three-dimensional memory cell 100 further includes a capacitor electrically connected to the nonvolatile memory chip 130 for supplying power to the nonvolatile memory chip 130, so that when the power is off, data can be written into the nonvolatile memory chip 130 for storage, thereby improving the storage reliability of the data.

As shown in fig. 2, the interface chip 120 includes a communication protocol circuit 122 and a plurality of logic circuits 124. It will be appreciated that the communication protocol circuit 122 is used to store a communication protocol and the plurality of logic circuits 124 are used to store different computational logic. As shown in fig. 7, a plurality of logic circuits 124 are disposed around the communication protocol circuit 122. The interface chip 120 is further provided with a routing unit 134, the plurality of logic circuits 124 are electrically connected to the communication protocol circuit 122 through the routing unit 134, and the plurality of logic circuits 124 are electrically connected to each other through the routing unit 134. In particular, the routing unit 134 is a NOC routing unit (network on chip), and data can be transmitted on the routing unit 134.

As shown in FIG. 3, the volatile memory chip 110 includes a first memory array 112 and a second memory array 114, the communication protocol circuit 122 is electrically connected to the first memory array 112 through a first three-dimensional hetero-integrated structure 142, and the logic circuit 124 is electrically connected to the second memory array 114 through a second three-dimensional hetero-integrated structure 144.

As shown in FIG. 4, the non-volatile memory chip 130 includes a third memory array 116 and a fourth memory array 118, the communication protocol circuit 122 is electrically connected to the third memory array 116 through a third three-dimensional hetero-integrated structure 146, and the logic circuit 124 is electrically connected to the fourth memory array 118 through a fourth three-dimensional hetero-integrated structure 148.

Specifically, when storing data, the data on the interface chip 120 can be stored in the first storage array 112 through the first three-dimensional heterogeneous integrated structure 142 and can also be stored in the third storage array 116 through the third three-dimensional heterogeneous integrated structure 146 after being processed by the communication protocol circuit 122.

Alternatively, when storing data, the data on the interface chip 120 is processed by the communication protocol circuit 122, transmitted to the at least one logic circuit 124 through the routing unit 134, and stored in the second storage array 114 through the second three-dimensional heterogeneous integrated structure 144 or the fourth storage array 118 through the fourth three-dimensional heterogeneous integrated structure 148 after being processed by the at least one logic circuit 124.

Similarly, when reading data, the data on the volatile memory chip 110 can be transmitted to the communication protocol circuit 122 through the first three-dimensional hetero-integrated structure 142, and then transmitted to the outside after being processed by the communication protocol circuit 122. The data on the nonvolatile memory chip 130 can be transmitted to the communication protocol circuit 122 through the third three-dimensional heterogeneous integrated structure 146, and then transmitted to the outside after being processed by the communication protocol circuit 122.

Alternatively, when reading data, the data on the volatile memory chip 110 can be transmitted to the logic circuit 124 through the second three-dimensional heterogeneous integrated structure 144, and the logic circuit 124 transmits the processed data to the other logic circuit 124 or the communication protocol circuit 122 through the routing unit 134. The data on the nonvolatile memory chip 130 can be transmitted to the logic circuit 124 through the fourth three-dimensional hetero-integrated structure 148, and the logic circuit 124 transmits the processed data to the other logic circuit 124 or the communication protocol circuit 122 through the routing unit 134. The communication protocol circuit 122 receives the data processed by the at least one logic circuit 124 and transmits the data to the outside.

Therefore, through the arrangement, data can be written into the volatile memory chip 110 and the nonvolatile memory chip 130 in a cache consistency mode, and can be read from the volatile memory chip 110 and the nonvolatile memory chip 130 in the cache consistency mode, that is, the data can be stored and read without being transmitted to a mainboard or a programmable controller or other components, and the like, and the logic calculation of the data can be realized, so that the transmission path of the data is shortened, and the storage and reading efficiency of the data is improved.

In addition, the plurality of logic circuits 124 are electrically connected through the routing unit 134, and the plurality of logic circuits 124 are electrically connected with the communication protocol circuit 122 through the routing unit 134, so that data can be directly stored or read, and the data can be stored or read after being processed by the logic circuits 124, thereby meeting the processing requirements of different data and improving the use flexibility of the nonvolatile three-dimensional storage unit 100.

In addition, through the arrangement, mutual crosstalk between data stored in different memory chips (the volatile memory chip 110 and the nonvolatile memory chip 130) can be reduced, and the use reliability of the nonvolatile three-dimensional memory unit 100 is improved. In addition, crosstalk generated when data with different processing requirements (data which needs to be subjected to logic calculation and data which does not need to be subjected to logic calculation) are stored and read can be reduced, and the use reliability of the nonvolatile three-dimensional storage unit 100 is further improved.

Specifically, as shown in fig. 3, the volatile memory chip 110, the interface chip 120, and the nonvolatile memory chip 130 are disposed at corresponding positions, and the volatile memory chip 110, the interface chip 120, and the nonvolatile memory chip 130 have equal areas, which further shortens the transmission path of data, and improves the reliability of data transmission among the volatile memory chip 110, the interface chip 120, and the nonvolatile memory chip 130, thereby improving the reliability of the nonvolatile three-dimensional memory cell 100 in use, and in addition, the nonvolatile three-dimensional memory cell 100 can also improve the structural regularity, facilitate processing, and improve the production efficiency of the nonvolatile three-dimensional memory cell 100.

Also, the setting position of the communication protocol circuit 122 corresponds to the setting position of the first storage array 112 and the setting position of the third storage array 116, and the setting position of the logic circuit 124 corresponds to the setting position of the second storage array 114 and the setting position of the fourth storage array 118, further shortening the distance between the communication protocol circuit 122 and the first storage array 112 and the third storage array 116, and the distance between the logic circuit 124 and the second storage array 114 and the fourth storage array 118.

The routing unit 134 is disposed between the communication protocol circuit 122 and the logic circuit 124 so that the disposed position of the routing unit 134 can correspond to the disposition of the volatile memory chip 110 and the position of the nonvolatile memory chip 130, further shortening the distance between the communication protocol circuit 122 and the logic circuit 124. With the arrangement, the transmission path of the data is shortened, and the processing efficiency of the nonvolatile three-dimensional storage unit 100 on the data is improved.

The communication protocol circuit 122 stores at least one of a CXL protocol (Computer Express Link, Compute interconnect protocol), a CCIX protocol (CCIX, cache coherent interconnect protocol of accelerator), a GEN Z protocol (Generation Z, Z Generation protocol), an OpenCPAI protocol (Open Computer Assisted Personal interfacing protocol), and an Nvlink protocol (bus communication protocol), so as to process data through different communication protocols, thereby improving the applicability of the nonvolatile three-dimensional memory unit 100.

In some examples, the communication protocol circuit 122 may further include other high-speed serial interface protocols that enable cache coherency, further increasing the processing bandwidth of the nonvolatile three-dimensional memory cell 100 for data.

As shown in fig. 5, the logic circuit 124 includes a fixed logic circuit 126 and a programmable logic circuit 128. Fixed logic 126 is used to store fixed computational logic. Programmable logic circuit 128 is used to store programmable computational logic. Specifically, the Programmable logic circuit 128 may be an EFPGA (Embedded Field Programmable Gate Array).

As shown in fig. 6, the programmable logic circuit 128 includes an embedded programmable logic circuit 131, an embedded multiplication circuit 132, and an embedded memory unit 133. The embedded programmable logic circuit 131 is electrically connected with the volatile memory chip 110 and the non-volatile memory chip 130 through a 3D-IC (three-dimensional chip) technology, so that the programmable logic circuit 128 can perform data transmission with the volatile memory chip 110 and the non-volatile memory chip 130, and the data transmission bandwidth is improved. The embedded memory unit 133 may be electrically connected to the embedded programmable logic circuit 131 by routing or the like. The embedded multiplication circuit 132 may be electrically connected to the embedded programmable logic circuit 131 through an interface or the like.

The nonvolatile three-dimensional memory cell 100 further includes a memory control circuit and a nonvolatile memory control circuit, and it is understood that the memory control circuit and the nonvolatile memory control circuit may be an MC (memory controller). The memory control circuits can be arranged on the interface chip 120 or the volatile memory chip 110, and the number of the memory control circuits is equal to the sum of the number of the communication protocol circuits 122 and the number of the logic circuits 124, so that data can be written into the volatile memory chip 110 in time and can be read from the volatile memory chip 110 in time, and the use reliability of the nonvolatile three-dimensional memory unit 100 is improved.

The nonvolatile memory control circuits can be arranged on the interface chip 120 or the nonvolatile memory chip 130, and the number of the nonvolatile memory control circuits is equal to the sum of the number of the communication protocol circuits 122 and the number of the logic circuits 124, so that data can be written into the nonvolatile memory chip 130 in time and can be read from the nonvolatile memory chip 130 in time, and the use reliability of the nonvolatile three-dimensional memory unit 100 is further improved.

In the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless expressly limited otherwise. The terms "mounted," "connected," "fixed," and the like are used broadly and should be construed to include, for example, "connected" may be a fixed connection, a detachable connection, or an integral connection; "coupled" may be direct or indirect through an intermediary. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", "front", "rear", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or unit must have a specific direction, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description herein, the description of the terms "one embodiment," "some embodiments," "specific embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A non-volatile three-dimensional memory cell, comprising:

a volatile memory chip for storing data;

the interface chip is connected with the volatile memory chip in a three-dimensional stacking manner through a three-dimensional heterogeneous integrated structure;

the nonvolatile memory chip is connected with at least one of the volatile memory chip and the interface chip in a three-dimensional stacking mode through the three-dimensional heterogeneous integrated structure to form a nonvolatile three-dimensional memory unit;

the interface chip comprises a communication protocol circuit, wherein the communication protocol circuit is used for storing a communication protocol; data is written into at least one of the volatile memory chip and the nonvolatile memory chip in a cache consistency mode through the communication protocol circuit; and the combination of (a) and (b),

data is read from at least one of the volatile memory chip and the non-volatile memory chip in the cache coherent manner by the communication protocol circuit.

2. The non-volatile three-dimensional memory cell of claim 1, wherein the interface chip further comprises:

a logic circuit electrically connected to the communication protocol circuit;

data is written to at least one of the volatile memory chip and the non-volatile memory chip in the cache coherent manner by the communication protocol circuit and the logic circuit, and,

data is read from at least one of the volatile memory chip and the non-volatile memory chip in the cache coherent manner by the communication protocol circuit and the logic circuit.

3. The non-volatile three-dimensional memory cell of claim 2, wherein the volatile memory chip comprises a first memory array and a second memory array, the communication protocol circuit is electrically connected to the first memory array through a first three-dimensional heterogeneous integrated structure, and the logic circuit is electrically connected to the second memory array through a second three-dimensional heterogeneous integrated structure;

the orthographic projection of the communication protocol circuit falls within the range of the orthographic projection of the first storage array, and the orthographic projection of the logic circuit falls within the range of the orthographic projection of the second storage array.

4. The nonvolatile three-dimensional memory cell of claim 2, wherein the nonvolatile memory chip is connected to the interface chip three-dimensional stack through the three-dimensional heterogeneous integrated structure; the nonvolatile memory chip comprises a third memory array and a fourth memory array, the communication protocol circuit is electrically connected with the third memory array through a third three-dimensional heterogeneous integrated structure, and the logic circuit is electrically connected with the fourth memory array through a fourth three-dimensional heterogeneous integrated structure;

the orthographic projection of the communication protocol circuit falls within the orthographic projection range of the third storage array, and the orthographic projection of the logic circuit falls within the orthographic projection range of the fourth storage array.

5. The nonvolatile three dimensional memory cell of claim 2 wherein the logic circuit comprises at least one of a fixed logic circuit and a programmable logic circuit.

6. The nonvolatile three-dimensional memory cell according to claim 2, wherein the number of the logic circuits is plural, and the plural logic circuits are arranged around the communication protocol circuit.

7. The non-volatile three-dimensional memory cell of claim 6, wherein the interface chip further comprises:

the orthographic projection of the routing unit falls into the orthographic projection range of the volatile memory chip; and the combination of (a) and (b),

the orthographic projection of the routing unit falls into the range of the orthographic projection of the nonvolatile memory chip;

the plurality of logic circuits are electrically connected through the routing unit, and the plurality of logic circuits are electrically connected with the communication protocol circuit through the routing unit respectively.

8. The nonvolatile three dimensional memory cell of claim 2 further comprising:

a memory control circuit disposed on the volatile memory chip; and/or the storage control circuit is arranged on the interface chip;

a nonvolatile memory control circuit disposed on the nonvolatile memory chip; and/or the nonvolatile storage control circuit is arranged on the interface chip.

9. The nonvolatile three dimensional memory cell of claim 8 wherein the number of memory control circuits is greater than or equal to the sum of the number of communication protocol circuits and the number of logic circuits;

the number of the nonvolatile memory control circuits is greater than or equal to the sum of the number of the communication protocol circuits and the number of the logic circuits.

10. The non-volatile three-dimensional memory unit of any one of claims 1 to 9, wherein the communication protocol comprises at least one of a CXL protocol, a CCIX protocol, a GEN Z protocol, an OpenCPAI protocol, and an Nvlink protocol.

11. The nonvolatile three-dimensional memory cell of any one of claims 1 to 9, wherein the number of the volatile memory chips is at least two, and at least two of the volatile memory chips are connected by the three-dimensional heterogeneous integrated structure three-dimensional stack.

12. The nonvolatile three-dimensional memory cell according to any one of claims 1 to 9, wherein the number of the interface chips is at least two, and at least two of the interface chips are connected by three-dimensional stacking of the three-dimensional heterogeneous integrated structure; or the like, or, alternatively,

and at least two interface chips are respectively connected with the volatile memory chip in a three-dimensional stacking manner through the three-dimensional heterogeneous integrated structure.

13. The nonvolatile three dimensional memory cell of any one of claims 1 to 9 wherein the number of the nonvolatile memory chips is at least two, and at least two of the nonvolatile memory chips are connected by the three dimensional heterogeneous integrated structure three dimensional stack; or the like, or, alternatively,

at least two nonvolatile memory chips are respectively connected with the volatile memory chip and the interface chip in a three-dimensional stacking mode through the three-dimensional heterogeneous integrated structure.

14. The three-dimensional nonvolatile memory unit according to any one of claims 1 to 9, wherein the orthographic projection of the volatile memory chip, the orthographic projection of the interface chip and the orthographic projection of the nonvolatile memory chip are completely overlapped.

15. The non-volatile three-dimensional memory cell of any of claims 1 to 9, further comprising:

and the capacitor is electrically connected with the nonvolatile memory chip and used for supplying power to the nonvolatile memory chip.

16. A non-volatile three-dimensional memory chip assembly, comprising:

the non-volatile three-dimensional memory cell of any one of claims 1 to 15;

the substrate is electrically connected with the nonvolatile three-dimensional storage unit and used for packaging the nonvolatile three-dimensional storage unit.

17. An electronic device, comprising:

a processor;

the non-volatile three-dimensional memory chip assembly of claim 16, the non-volatile three-dimensional memory chip assembly being electrically connected to the processor.