CN116828866A

CN116828866A - Integrated circuit assembly, processor and system on chip

Info

Publication number: CN116828866A
Application number: CN202310673218.2A
Authority: CN
Inventors: 张喆; 李双辰; 许晗; 卓有为; 魏学超; 牛迪民; 郑宏忠
Original assignee: Alibaba Damo Institute Hangzhou Technology Co Ltd
Current assignee: Alibaba Damo Institute Hangzhou Technology Co Ltd
Priority date: 2023-06-07
Filing date: 2023-06-07
Publication date: 2023-09-29

Abstract

The embodiment of the invention provides an integrated circuit assembly, a processor and a system on chip, wherein the integrated circuit assembly comprises at least two wafer layers, each wafer layer comprises a front surface and a back surface, wherein in the at least two wafer layers, a first wafer layer and a second wafer layer are stacked front to front, the second wafer layer and the third wafer layer are stacked front to back in sequence, the second wafer layer is subjected to through hole silicon, a rerouting layer and hybrid bonding treatment, and the at least two wafer layers are connected with each other through the through hole silicon, the rerouting layer and the hybrid bonding of each layer. The integrated circuit assembly of the embodiment of the invention can provide larger on-chip storage capacity to meet the requirement of basic model calculation.

Description

Integrated circuit assembly, processor and system on chip

Technical Field

Embodiments of the present invention relate to the field of computer technologies, and in particular, to an integrated circuit assembly, a processor, and a system on a chip.

Background

The 3D wafer level package refers to a package technology in which two or more wafer layers are stacked in a vertical direction in the same package without changing the size of the package. The main characteristics of the 3D wafer level package include: multifunctional, high-efficiency, high-capacity and high-density. Therefore, the integrated circuit assembly of the 3D wafer level package can provide a larger on-chip memory capacity to meet the requirement of the basic model calculation, and the 3D wafer level package is a trend of current technology development.

Therefore, how to construct a data flow architecture for a 3D wafer level packaged integrated circuit device is a technical problem to be solved in the prior art.

Disclosure of Invention

Accordingly, embodiments of the present invention provide an integrated circuit assembly, a processor, and a system-on-a-chip to at least partially solve the above-mentioned problems.

According to a first aspect of an embodiment of the present invention, there is provided an integrated circuit assembly, including at least two wafer layers, each wafer layer including a front surface and a back surface, wherein, in the at least two wafer layers, a first wafer layer and a second wafer layer are stacked front to front, the second wafer layer and the third wafer layer are stacked front to back in sequence, the second wafer layer is processed through a through-silicon via, a rerouting layer and a hybrid bonding, and the at least two wafer layers are connected to each other through the through-silicon via, the rerouting layer and the hybrid bonding of each layer.

In another implementation manner of the present invention, the at least two wafer layers further include a third wafer layer, the second wafer layer and the third wafer layer are stacked front to back, and the other wafer layers except for the second wafer layer in the at least three wafer layers are subjected to at least one of through-silicon vias, rerouting layers and hybrid bonding treatment.

In another implementation of the present invention, the front side of the second wafer layer is subjected to a hybrid bonding process, and the back side of the second wafer layer is subjected to a through-silicon via, a redistribution layer, and a hybrid bonding process.

In another implementation of the present invention, the assembly includes three wafer layers, the front side of the first wafer layer being subjected to a hybrid bonding process, and the front side of the third wafer layer being subjected to a hybrid bonding process.

In another implementation of the present invention, pins are led out from the back surface of the first wafer layer or the back surface of the third wafer layer.

In another implementation of the present invention, the three wafer layers are all wafers; or the second wafer layer is a wafer, one of the first wafer layer and the third wafer layer is a chip, and the other wafer layer is a wafer; or, the second wafer layer is a chip.

In another implementation of the present invention, the data flow of the three wafer layers includes: the data flow from the first wafer layer to the second wafer layer is through: the data source point, the mixed bond metal medium of the first wafer layer, the mixed bond metal medium of the second wafer layer and the data target point; and/or the data flow from the second wafer layer to the first wafer layer is through: the data source point, the mixed bond metal medium of the second wafer layer, the mixed bond metal medium of the first wafer layer and the data target point; and/or the data flow from the second wafer layer to the third wafer layer is through: the method comprises the steps of data source points, through silicon via metal media of a second wafer layer, rerouting layer metal media of the second wafer layer, mixed bond metal media of a third wafer layer and data target points; and/or the data flow from the third wafer layer to the second wafer layer is through: the data source point, the mixed bond metal medium of the third wafer layer, the mixed bond metal medium of the second wafer layer, the rewiring layer metal medium of the second wafer layer, the through silicon via metal medium of the second wafer layer and the data target point; and/or the data flow from the first wafer layer to the second wafer layer to the third wafer layer is through: the method comprises the steps of a data source point, a mixed bond metal medium of a first wafer layer, a mixed bond metal medium of a front surface of a second wafer layer, a through silicon via metal medium of a back surface of the second wafer layer, a rewiring layer metal medium of a back surface of the second wafer layer, a mixed bond metal medium of a third wafer layer and a data target point; and/or the data flow from the third wafer layer to the second wafer layer and then to the first wafer layer is through: the method comprises the steps of data source points, mixed bond metal media of a third wafer layer, mixed bond metal media of the back surface of a second wafer layer, heavy wiring layer metal media of the back surface of the second wafer layer, through silicon via metal media of the back surface of the second wafer layer, mixed bond metal media of the front surface of the second wafer layer, mixed bond metal media of a first wafer layer and data target points.

In another implementation of the present invention, at least one of the three wafer layers is a logic layer, and the logic layer is connected to the pins.

In another implementation manner of the present invention, the wafer layer on the outer side of the three wafer layers is a logic layer, and the remaining wafer layers are storage layers.

In another implementation manner of the present invention, the wafer layers on two sides of the three wafer layers are all logic layers, and the wafer layer between the logic layers on two sides is a storage layer.

In another implementation of the present invention, the three wafer layers are all logic layers.

In another implementation of the present invention, the logic layer includes: at least one of a data flow logic unit, a calculation logic unit or a storage logic unit, wherein the data flow logic adopts a simplified instruction to collect flow of an artificial intelligence engine or a network on chip; the calculation logic adopts a resistance change type memory or a simplified instruction set; the storage logic adopts a resistance change type memory or a static random access memory; the storage layer adopts dynamic random access memory.

In another implementation of the present invention, if the logic layer includes the data flow logic unit, the configuring of the data flow logic unit includes: the type of domain-specific architecture, whether the storage architecture requires a register; if the logic layer includes the calculation logic unit, the configuration of the calculation logic unit includes: the fixed precision, the mixed precision and the calculated size of the storage array are matched with the bandwidth of the storage layer; if the logical layer includes the storage logical unit, the configuration of the storage logical unit includes: at least one of a storage array size and a storage array type; the configuration of the storage layer comprises: the number of memory blocks, the number of corresponding hybrid bond input and output ports, and whether the bandwidth can match the size of the compute storage array of the compute logic.

In another implementation of the present invention, when any one of the three wafer layers is a logic layer, at least two types of logic units are included.

In another implementation manner of the present invention, any one of the three wafer layers adjusts the correspondence between each unit in the wafer layer and each unit in the other wafer layers according to the yield of the other wafer layers.

In another implementation manner of the present invention, when any one of the three wafer layers is a logic layer, the logic layer configures logic units according to requirements.

In another implementation of the present invention, the configured logic layer of the three wafer layers multiplexes the other wafer layers.

In another implementation of the present invention, the number of hybrid bond metal dielectrics and the number of through silicon via metal dielectrics on the three wafer layers are configured independently.

According to a second aspect of an embodiment of the present invention, there is provided a processor including: an integrated circuit assembly according to the first aspect.

According to a third aspect of an embodiment of the present invention, there is provided a system on a chip, including: at least one processor, the processor is the processor of the second aspect.

In the scheme of the embodiment of the invention, the integrated circuit assembly comprises at least two wafer layers, each wafer layer comprises a front surface and a back surface, wherein in the at least two wafer layers, the first wafer layer and the second wafer layer are stacked from front to front, the second wafer layer and the third wafer layer are stacked from front to back in sequence, the second wafer layer is processed by through-silicon vias, rerouting layers and hybrid bonding, and the at least two wafer layers are connected with each other by the through-silicon vias, the rerouting layers and the hybrid bonding of each layer. At least two wafer layers in the embodiment of the invention are mutually connected through the silicon through holes, the rewiring layers and the hybrid bonding of each layer, so that the 3D wafer-level packaging of the multi-layer wafer layers is realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present invention, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.

Fig. 1a to 1h are schematic views of a wafer layer being processed.

FIG. 2a is a schematic diagram of an embodiment of an integrated circuit assembly according to the present invention.

Fig. 2b is a schematic diagram of another embodiment of an integrated circuit assembly according to the present invention.

Fig. 3 is a schematic diagram of a process for packaging an integrated circuit assembly according to another embodiment of the present invention.

Fig. 4a and 4b are schematic diagrams of two further embodiments of an integrated circuit assembly according to the invention.

Fig. 5a, 5b and 5c are schematic diagrams of still another embodiment of an integrated circuit assembly according to the present invention.

Fig. 6 is a schematic diagram of an integrated circuit assembly according to another embodiment of the present invention.

Fig. 7a and 7b are schematic diagrams of two further embodiments of an integrated circuit assembly according to the present invention.

Fig. 8 is a schematic diagram of an integrated circuit assembly according to another embodiment of the present invention.

Fig. 9a and 9b are schematic diagrams of yet another embodiment of an integrated circuit assembly according to the present invention.

Fig. 10 is a schematic diagram of an integrated circuit assembly according to another embodiment of the present invention.

Fig. 11 is a block diagram of a processor according to another embodiment of the present invention.

Fig. 12 is a schematic diagram of a system-on-chip according to another embodiment of the present invention.

Detailed Description

In order to make the technical solutions in the embodiments of the present invention better understood by those skilled in the art, the technical solutions in the embodiments of the present invention will be clearly and specifically described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the present invention, shall fall within the scope of protection of the embodiments of the present invention.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which illustrate exemplary embodiments. In addition, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that the directions and references (e.g., upper, lower, top, bottom, etc.) may be used merely to facilitate the description of the features in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and equivalents thereof.

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art that the embodiments herein may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments herein. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment herein. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment in any event that particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that two or more elements co-operate or interact with each other (e.g., as in a causal relationship).

The terms "above …," "below …," "between …," and "on …" as used herein refer to the relative position of one component or material with respect to other components or materials, wherein such physical relationships are notable. For example, in the context of materials, one material or materials disposed above or below another material may be in direct contact, or may have one or more intermediate materials. Also, one material disposed between two materials or materials may be in direct contact with both layers or may have one or more intermediate layers. In contrast, a first material or material "on" a second material or material is in direct contact with the second material/material. Similar distinction is made in the context of assembly of components.

As used throughout this description and in the claims, a list of items connected by the term "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "at least one of A, B or C" can mean a; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; or A, B and C.

The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "near," "approximately," "near," and "approximately" generally refer to within +/-10% of a target value.

The implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

The Wafer layer (Wafer) is composed of pure silicon (Si), including front and back sides. The front side of the wafer layer is the main working surface on which the chips are fabricated on the wafer. The front side typically has a specific orientation and lattice structure for growing or building transistors, circuits and other semiconductor devices thereon, i.e., the front side is provided with a wiring layer. The back side of the wafer layer, also referred to as the back side surface or backing, is opposite the front side. The back side is generally planar and free of crystalline structures to provide mechanical stability to support and handle the wafer. The back side is typically free of circuitry or devices and may be specially treated or coated to meet specific requirements, such as enhanced adhesion or improved heat transfer.

The 3D wafer level package refers to an integrated circuit assembly formed by more than two wafer level packages.

Hybrid Bonding (HB) is a method of achieving denser interconnection between chips stacked one on top of the other, and the Hybrid bonding process allows wafers to be stacked front-to-front.

The main function of Through-Silicon Vias (TSV) is the electrical extension and interconnection of the Z-axis (the axis perpendicular to the plane of the wafer layer).

The rewiring layer (RDL, re-distribution Layer) serves as an electrical extension and interconnection of the XY plane (the plane in which the wafer layer resides). In the FIWLP (Fan-In Wafer Level Package) of advanced packaging, FOWLP (Fan-Out Wafer Level Package), RDL is the most critical technology, and different types of wafer level packages are formed by fanning IO pads into Fan-In or fanout of Fan-Out by RDL.

Referring to fig. 1a to 1h, arrows indicate directions of front surfaces of wafer layers; 11 represents a Si medium; 12, a metallic medium for transmitting an electrical signal, comprising: metal layers, through silicon vias, rewiring layers, hybrid bonding, pins, etc.; the other part represents the insulating medium. Fig. 1a is an initial wafer layer, and fig. 1b is a wafer layer subjected to hybrid bonding. Referring to fig. 1c, an initial wafer layer is shown, and fig. 1d, a through-silicon via processed wafer layer is shown. Referring to fig. 1e, which is an initial wafer layer, fig. 1f is a wafer layer processed by rerouting layer pin out. Fig. 1g shows a wafer layer with a back side subjected to through-silicon vias, a redistribution layer, and hybrid bonding, and a front side subjected to hybrid bonding. Fig. 1h shows a wafer layer with backside through-silicon vias, redistribution layers, hybrid bonding processes.

Two different embodiments of the integrated circuit assembly will be described below in connection with fig. 2a and 2 b.

FIG. 2a illustrates an integrated circuit assembly of one embodiment, the integrated circuit assembly comprising at least two wafer layers, i.e., W1, W2, W3, … … Wn, n.gtoreq.2. Each wafer layer includes a front side (the outer surface of the substrate opposite to the outer surface of the substrate where Si is shown in the drawings) and a back side (the outer surface of the substrate where Si is shown in the drawings). The first wafer layer W1 and the second wafer layer W2 are stacked front to front, the second wafer layer W2 and the third wafer layer W3 are stacked front to back in sequence, the second wafer layer W2 is processed by through silicon vias, rerouting layers and hybrid bonding, and at least two wafer layers are connected with each other by the through silicon vias, the rerouting layers and the hybrid bonding of each layer.

In the embodiment of the invention, at least two wafer layers are mutually connected through the through silicon vias, the rewiring layers and the hybrid bonding of each layer, so that the 3D wafer-level packaging of the multi-layer wafer layers is realized.

That is, the front surface of the wafer layer is the side provided with the wiring layer, denser and reliable wiring is realized on the front surface of the wafer layer through hybrid bonding, data transmission delay of the front surface wiring of the wafer layer is reduced, data transmission efficiency is improved, and therefore larger on-chip storage capacity can be provided to meet the requirement of basic model calculation.

The back surface of the wafer layer is one side of the substrate, through-silicon via processing is performed on the back surface of the wafer layer, wiring is led to the back surface of the wafer layer, and through the re-wiring layer and the mixed bonding processing, the back surface of the wafer layer is fully utilized to realize denser and reliable wiring while related processes are compatible, particularly in 3D wafer packaging (an example of an integrated circuit assembly), the back surface of the wafer layer at the middle layer realizes denser and reliable wiring, and the back surface of the wafer layer serving as the back surface of the 3D wafer packaging realizes wiring leading out from the 3D wafer packaging through the through-silicon via. In addition, electrode PAD (Package Assembly Drawing, PAD) technology can also be used to fabricate the pins of the 3D package.

FIG. 2b illustrates another integrated circuit assembly provided by an embodiment of the present invention, which includes at least three wafer layers, namely W1, W2, W3, … … Wn, n.gtoreq.3. Wherein the first wafer layer W1 and the second wafer layer W2 are stacked front to front, and the second wafer layer W2 and the third wafer layer W3 are stacked front to back. The third wafer layer W3 and the fourth wafer layer W4 are stacked front to back, … …, and the N-1 wafer layer Wn-1 and the N-th wafer layer Wn are stacked front to back.

The second wafer layer is subjected to at least one of through-silicon vias, re-wiring layers and hybrid bonding processes, and the other wafer layers are subjected to at least one of through-silicon vias, re-wiring layers and hybrid bonding processes. In the embodiment of the invention, at least three wafer layers are mutually connected through the through silicon vias, the rewiring layers and the hybrid bonding of each layer, so that the 3D wafer-level packaging of the multi-layer wafer layers is realized. The front of the wafer layer is one side provided with the wiring layer, denser and reliable wiring is realized on the front of the wafer layer through hybrid bonding, data transmission delay of front wiring of the wafer layer is reduced, data transmission efficiency is improved, and therefore larger on-chip storage capacity can be provided to meet the requirement of basic model calculation.

In one embodiment of the present invention, the integrated circuit assembly includes three wafer layers, i.e., W1, W2, W3. Fig. 3a shows an initial first wafer layer W1. Fig. 3b shows the front surface of the first wafer layer W1 subjected to hybrid bonding. Fig. 3c shows the front surface of the second wafer layer W2 subjected to the hybrid bonding process and stacked front-to-front with the front surface of the first wafer layer W1 subjected to the hybrid bonding process. Fig. 3d shows the second wafer layer W2 of fig. 3c after the backside is subjected to through-silicon vias, re-wiring layers and hybrid bonding processes. Fig. 3e shows a third wafer layer W3 having a front surface subjected to hybrid bonding, and the front surface of the third wafer layer W3 is stacked with the back surface of the second wafer layer W2.

According to the embodiment of the invention, the first wafer layer and the third wafer layer are mutually connected through hybrid bonding, the second wafer layer is mutually connected through the through silicon via, the rewiring layer and hybrid bonding, the packaging process is simpler and more convenient, and the packaging cost is reduced.

In other words, denser and reliable wiring is realized on the front surface of the wafer layer through hybrid bonding, the front surface-to-front surface stacking process enhances the data transmission efficiency between the adjacent wafer layers, and reduces the delay between different wafer layers.

Accordingly, the related process is compatible, the processing efficiency and the mechanical performance of the 3D wafer can be ensured, and the stacking process from the front side to the back side fully utilizes the back side of the wafer layer to realize denser and reliable wiring. At this time, the adjacent wafer layers respectively serve as a logic layer and a storage layer to provide data reading and writing efficiency, and the adjacent wafer layers respectively serve as the logic layer or the storage layer to provide data transmission efficiency.

In a specific implementation of the present invention, referring to fig. 4a, a first pin D1 is led out from the back surface of the first wafer layer W1; referring to fig. 4b, the second lead D2 is led out from the back surface of the third wafer layer W3. The embodiment of the invention is convenient for realizing the pin design of the integrated circuit component.

In one embodiment of the present invention, the three wafer layers are wafers or the second wafer layer is a wafer, one of the first wafer layer and the third wafer layer is a chip, and the other is a wafer.

Specifically, referring to fig. 5a, the three wafer layers are all wafers; referring to fig. 5b, the first wafer layer W1 and the second wafer layer W2 are wafers, and the third wafer layer W3 is a chip; referring to fig. 5c, the first wafer layer W1 is a chip, and the second wafer layer W2 and the third wafer layer W3 are wafers.

The three wafer layers of the integrated circuit component have diversified implementation modes, and one of the first wafer layer and the third wafer layer can adopt chips.

It should be appreciated that in some examples, the three wafer layers are all wafers, reducing the alignment process requirements of the three wafer layers. In this case, the integrated circuit components are configured with consideration factors (e.g., efficacy metrics) other than alignment process requirements, such as mechanical performance, compatibility with conventional processes, electrical performance (e.g., data transfer delays), heat dissipation performance, and the like.

In other examples, the second wafer layer is a wafer, one of the first and third wafer layers is a chip, and the other is a wafer. That is, the chips are outside the integrated circuit assembly, reducing alignment process requirements between wafer layers compared to chips between wafers. The chip can be a wafer layer finished by packaging (for example, 2D or 2.5D packaging), so that the packaging mode is more flexible, and more diversified 3D integrated packaging design choices can be provided.

In other examples, the second wafer layer is a die. In the case where the first wafer layer and the third wafer layer are both wafers, although the process of aligning the chips between the wafer layers is more demanding than if the chips are on one side, if the chips are arranged as the middle wafer layer with the emphasis on other factors (for example, the chips are the storage layers, better heat dissipation performance is brought), other performance indexes are still ensured.

In the case that at least one of the first wafer layer and the third wafer layer is a chip, the wafer layer completed by packaging (for example, 2D or 2.5D packaging) is fully utilized, so that the packaging mode is more flexible, and more diversified 3D integrated packaging design choices can be provided.

Illustratively, referring to FIG. 3e, the flow of data through the three wafer layers is illustrated.

The data flow from the first wafer layer W1 to the second wafer layer W2 is through: the data source point, the mixed bond metal medium of the first wafer layer W1, the mixed bond metal medium of the second wafer layer W2 and the data target point. The time delay is small when the data flow direction is from the first wafer layer W1 to the second wafer layer W2.

The data flow from the second wafer layer W2 to the first wafer layer W1 is through: the data source point, the mixed bond metal medium of the second wafer layer W2, the mixed bond metal medium of the first wafer layer W1 and the data target point. The data flow direction is from the second wafer layer W2 to the first wafer layer W1, and the time delay is small.

That is, by employing hybrid bonding with front-to-front stacking arrangements, the delay between different wafer layers is reduced.

The data flow from the second wafer layer W2 to the third wafer layer W3 passes through: the method comprises the steps of data source points, through silicon via metal media of a second wafer layer W2, rerouting layer metal media of the second wafer layer W2, mixed bond metal media of a third wafer layer W3 and data target points. The data flow direction is in the delay from the second wafer layer W2 to the third wafer layer W3.

The data flow from the third wafer layer W3 to the second wafer layer W2 is through: the data source point, the mixed bond metal medium of the third wafer layer W3, the mixed bond metal medium of the second wafer layer W2, the rewiring layer metal medium of the second wafer layer W2, the through silicon via metal medium of the second wafer layer W2 and the data target point. The data flow direction is in the delay from the third wafer layer W3 to the second wafer layer W2.

That is, preprocessing the backside of the wafer layers based on the re-wiring layer and through-silicon via process, and then employing hybrid bonding through the front-to-back stacking arrangement, reduces the delay between different wafer layers.

Because the preprocessing of the re-wiring layer and the through silicon via process increases the delay compared with directly adopting hybrid bonding, but the processing efficiency and the mechanical property of the 3D wafer can be ensured while the related processes are compatible.

Accordingly, for the logic layer to logic layer, logic layer to storage layer, and storage layer to storage layer, there are different delay requirements for component application, and the application of the integrated circuit component can be optimized by matching the corresponding delay requirements with the delays of the different stacking modes.

Data flow from the first wafer layer W1 to the second wafer layer W2 to the third wafer layer W3 is through: the method comprises the steps of data source points, mixed bond metal media of a first wafer layer W1, mixed bond metal media of a front surface of a second wafer layer W2, through silicon via metal media of a back surface of the second wafer layer W2, heavy wiring layer metal media of a back surface of the second wafer layer W2, mixed bond metal media of a third wafer layer W3 and data target points. The data flow direction is from the first wafer layer W1 to the second wafer layer W2 and then to the third wafer layer W3, and the time delay is large.

The data flow from the third wafer layer W3 to the second wafer layer W2 to the first wafer layer W1 is as follows: the data source point, the mixed bond metal medium of the third wafer layer W3, the mixed bond metal medium of the back surface of the second wafer layer W2, the rewiring layer metal medium of the back surface of the second wafer layer W2, the through silicon via metal medium of the back surface of the second wafer layer W2, the mixed bond metal medium of the front surface of the second wafer layer W2, the mixed bond metal medium of the first wafer layer W1 and the data target point. The data flow direction is from the third wafer layer W3 to the second wafer layer W2, and then to the first wafer layer W1, and the time delay is large.

Without loss of generality, the delay between non-adjacent different wafer layers may be greater than the delay between adjacent different wafer layers.

The integrated circuit assembly of the embodiment of the invention realizes data flow among three wafer layers, and the embodiment of the invention can design the data flow among the three wafer layers according to the requirement, so that the delay of the data flow meets the requirement of data transmission.

In one embodiment of the present invention, at least one of the three wafer layers is a logic layer, the remaining wafer layers are memory layers, and the logic layer is connected to the pins.

In one example, the wafer layer at the outer side of the three wafer layers is a logic layer, the rest wafer layers are storage layers, and the heat dissipation requirement of the logic layer is higher than that of the storage layers, so that the heat dissipation performance of the integrated circuit assembly is ensured. Further, in this case, the logic layer has a large specific gravity, and is preferably configured as a DSA such as a CPU or other control flow which is relatively complicated.

For example, the first wafer layer is a logic layer, the second wafer layer is a memory layer, and the third wafer layer is a memory layer. For another example, the first wafer layer is a memory layer, the second wafer layer is a memory layer, and the third wafer layer is a logic layer.

As a more preferable example, the wafer layers on two sides of the three wafer layers are logic layers, and the wafer layer between the two logic layers is a storage layer, so that the heat dissipation performance of the integrated circuit assembly is optimized.

Alternatively, the wafer layers outside the three wafer layers are logic layers, the rest wafer layers are a storage layer and a logic layer, the heat dissipation requirement of the logic layer is higher than that of the storage layer, and meanwhile, the heat dissipation capability of the storage layer is higher than that of the logic layer, and the storage layer can be favorable for heat dissipation of the logic layer, so that the heat dissipation performance of the integrated circuit assembly is guaranteed to a certain extent. Further, in this case, the storage layer has a large specific gravity, is more suitable for being configured as DSA such as GPU or TPU, and has a high calculation requirement.

For another example, the chips are configured as logic layers, the wafers are configured as storage layers, the chips are positioned outside the integrated circuit assembly, the wafers are positioned in the middle layer of the assembly, heat dissipation performance is guaranteed, and process requirements such as alignment processes and the like are reduced compared with the case that the chips are positioned in the middle layer of the integrated circuit assembly.

For example, the first wafer layer is a logic layer, the second wafer layer is a logic layer, and the third wafer layer is a memory layer. For another example, the first wafer layer is a memory layer, the second wafer layer is a logic layer, and the third wafer layer is a logic layer.

Alternatively, the first wafer layer is a logic layer, the second wafer layer is a logic layer, and the third wafer layer is a logic layer. The three wafer layers are all logic layers, the heat dissipation performance is poorer than that of the example, but the low-delay interconnection between the logic layers is greatly improved, and the data processing capability and the flow control performance which are better than those of the example are realized.

Since the first pin D1 is led out from the back surface of the first wafer layer W1 and the second pin D2 is led out from the back surface of the third wafer layer W3, the pins (D1 or D2) connected to the logic layer are all located on the outer layer of the three wafer layers.

Specifically, referring to table one, the selection and heat dissipation conditions of the logic layer and the storage layer are shown in table one. The six options given in table one correspond to the above six embodiments, respectively, and in the embodiments corresponding to the respective table entries, the 1 st, 3 rd, and 6 th heat dissipation are excellent, the 2 nd and 5 th are excellent, and the 4 th is excellent.

List one

Sequence number	First wafer layer W1	Second wafer layer W2	Third wafer layer W3	Heat dissipation
					1	Logic layer (L)	Storage layer (M)	Storage layer (M)	Excellent quality
2	Logic layer (L)	Logic layer (L)	Storage layer (M)	Excellent (excellent)
					3	Logic layer (L)	Storage layer (M)	Logic layer (L)	Excellent quality
4	Logic layer (L)	Logic layer (L)	Logic layer (L)	Good quality
					5	Storage layer (M)	Logic layer (L)	Logic layer (L)	Excellent (excellent)
6	Storage layer (M)	Storage layer (M)	Logic layer (L)	Excellent quality

The integrated circuit assembly of the embodiment of the invention can design three wafer layers into a logic layer or a storage layer according to the heat dissipation requirement, and the embodiment of the invention provides a more flexible design scheme.

In one embodiment of the present invention, the logic layer includes: one of the data flow logic unit, the calculation logic unit or the storage logic unit, wherein the data flow logic adopts three-dimensional mixed data to bond a fifth generation simplified instruction current collection artificial intelligent engine (3D-Hybrid Bonding Powered RISC-V Dataflow AI Engine, THRIVE) or a network on chip; the calculation logic adopts a resistance change type memory (used for in-memory processing) or a high-performance fifth-generation simplified instruction set (High performance RISC-V, HP-RV); the storage logic adopts a resistance change type memory (used as a memory) or a static random access memory; the storage logic adopts RRAM-Memory or SRAM; the memory layer adopts a DRAM process.

It should be understood that THRIVE herein is merely an example of a DSA or network-on-chip or accelerator, and that it may be replaced with other DSA or accelerator data flow logic units. The HP-RV herein is merely an example of a CPU that may be substituted for the computational logic of various types of CPUs.

The memory layer adopts dynamic random access memory.

In a specific implementation of the present invention, when any one of the three wafer layers is a logic layer, the logic layer configures logic units according to requirements.

The embodiment of the invention can more flexibly configure the logic units of the logic layer, thereby enabling the integrated circuit assembly to provide more diversified memory forms. The embodiment of the invention can provide a special memory or a special Domain Special Architecture (DSA) engine for PE (Processing Element, processing unit) by configuring the logic units of the logic layer.

In one embodiment of the present invention, any one of the three wafer layers is configured as desired. Thus, embodiments of the present invention may provide various 3D integrated design choices for advanced artificial intelligence models (GPT/LLM).

In other examples, the three wafer layers include a first logic layer and a second logic layer, the first logic layer and the second logic layer being different ones of the data flow logic unit, the compute logic unit, and the store logic unit. The logic layers and the storage layers of different logics are integrated into the integrated circuit assembly, so that the data reading and writing efficiency, the calculation efficiency and the overall data processing efficiency are improved. For example, the data flow logic unit and the calculation logic unit combine the advantages of parallel calculation and serial calculation, the data flow logic unit and the storage calculation unit combine the advantages of data reading and writing, the calculation logic unit and the storage calculation unit combine the advantages of data reading and writing, and so on.

More specifically, referring to table two, which gives four types of options as examples of three wafer layers, embodiments of the present invention are not limited to these four types.

Watch II

Example	First wafer layer W1	Second wafer layer W2	Third wafer layer W3	Type(s)
					1	THRIVE (or accelerator)	DRAM	RRAM-PIM	L-M-L
2	THRIVE	SRAM	DRAM	L-L-M
					3	THRIVE	DRAM	DRAM	L-M-M
4	THRIVE	DRAM	HP-RV (or CPU)	L-M-L

In one embodiment of the present invention, a specific description is given by way of example 1.

Referring to fig. 6, the first wafer layer W1 is threve-PE, the second wafer layer W2 is DRAM, and the third wafer layer W3 is RRAM-PIM.

The first wafer layer W1 is THRIVE-PE, i.e., the first wafer layer W1 includes data flow logic. The configuration of the data flow logic unit comprises: the type of Domain-specific architecture (DSA), whether the storage architecture requires a register (scanchpad). Specifically, the types of domain-specific architecture include: video Processing Units (VPUs) or matrix multiplication of generic matrices (GEMMs), etc.

The second wafer level W2 is DRAM, i.e., the second wafer level W2 includes memory logic cells. The configuration of the storage logic unit includes: the number of Memory banks, the number of corresponding hybrid bond input output ports (HB IO) and whether the bandwidth can match the size of the compute Memory array of the compute logic.

The third wafer layer W3 is RRAM-PIM, i.e., the third wafer layer W3 includes computational logic. The configuration of the computational logic includes: the size of the fixed precision, the mixed precision and the computing storage Array (CIM Array) is matched with the bandwidth of the storage layer. Specifically, the fixing accuracy includes: fixed data type (INT), or fixed BF (brain float)/FP (floating point); the mixing precision comprises: fixed data types (INT) and BF/FB.

The number of the mixed bond metal media and the number of the through silicon via metal media on the three wafer layers are independently configured. Therefore, the first wafer layer W1, the second wafer layer W2, and the third wafer layer W3 do not have to be in one-to-one correspondence with each other. Referring to fig. 7a and 7b, fig. 7a is a schematic diagram of a one-to-one correspondence between a first wafer layer W1, a second wafer layer W2, and a third wafer layer W3; fig. 7b is a schematic diagram showing the relationship among the first wafer layer W1, the second wafer layer W2, and the third wafer layer W3.

In a specific implementation of the present invention, when any one of the three wafer layers is a logic layer, at least two types of logic units are included.

Illustratively, referring to FIG. 8, a heterogeneous schematic diagram between the first wafer level W1, the second wafer level W2, and the third wafer level W3, i.e., the first wafer level W1 includes two types of logic cells, RRAM-PIM, and SRAM.

In a specific implementation of the present invention, any one of the three wafer layers adjusts the correspondence between each unit in the wafer layer and each unit in the other wafer layers according to the yield of the other wafer layers. Referring to fig. 9a, in example 1, since the yield of RRAM-PIM of the third wafer layer W3 is low, there may be a bad block 1, and referring to fig. 9b, when the second wafer layer W2 performs the rerouting layer, it may be more flexible to select, through the rerouting layer, a non-bad block 2 between RRAM-PIM of the third wafer layer W3 to correspond to the bad block 1.

In a specific implementation of the present invention, when any one of the three wafer layers is a logic layer, the logic layer may perform configuration of logic units according to the requirement based on the requirement. The logic layer configured in the three wafer layers multiplexes the other wafer layers. Illustratively, after the first wafer layer W1 and the second wafer layer W2 have been completed, different third wafer layers W3, i.e., third wafer layers W3, are customized according to different needs, and a self-customized Domain Specific Architecture (DSA) is configured. Referring specifically to fig. 10, the customized third wafer level W3 may multiplex the completed first wafer level W1 and second wafer level W2. That is, the completed first wafer layer W1 and second wafer layer W2 can be reused regardless of the Domain Specific Architecture (DSA) of the third wafer layer W3.

Embodiments of the present invention are non-von neumann architectures, thereby reducing the memory bottleneck problem associated with data movement. The multi-layer 3D heterogeneous data stream architecture provided by the embodiment of the invention provides a 3D memory so as to improve the memory of a system on a chip and meet the large memory requirement of a basic model. The diversified configuration of the logic layer of the embodiment of the invention provides various 3D integrated design choices for the advanced artificial intelligence model (GPT/LLM).

Fig. 11 is a block diagram of a processor according to another embodiment of the present invention. The processor 1100 of the present embodiment includes: processor core 1101 and integrated circuit component 1102.

Fig. 12 is a schematic diagram of a system-on-chip according to another embodiment of the present invention. The system on chip 1200 of the present embodiment includes a plurality of processors 1210.

In addition, the specific implementation of each step in the program may refer to the corresponding steps and corresponding descriptions in the units in the above method embodiments, which are not repeated herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and modules described above may refer to corresponding procedure descriptions in the foregoing method embodiments, which are not repeated herein.

It should be noted that, according to implementation requirements, each component/step described in the embodiments of the present invention may be split into more components/steps, or two or more components/steps or part of operations of the components/steps may be combined into new components/steps, so as to achieve the objects of the embodiments of the present invention.

The above-described methods according to embodiments of the present invention may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium downloaded through a network, so that the methods described herein may be stored on such software processes on a recording medium using a general purpose computer, special purpose processor, or programmable or special purpose hardware such as an ASIC or FPGA. It is understood that a computer, processor, microprocessor controller, or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by a computer, processor, or hardware, performs the methods described herein. Furthermore, when a general purpose computer accesses code for implementing the methods illustrated herein, execution of the code converts the general purpose computer into a special purpose computer for performing the methods illustrated herein.

Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present invention.

The above embodiments are only for illustrating the embodiments of the present invention, but not for limiting the embodiments of the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the embodiments of the present invention, so that all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the scope of the embodiments of the present invention should be defined by the claims.

Claims

1. The integrated circuit assembly comprises at least two wafer layers, wherein each wafer layer comprises a front surface and a back surface, the front surfaces of the first wafer layer and the second wafer layer are stacked in the at least two wafer layers, the second wafer layer and the third wafer layer are stacked in the front surfaces and the back surfaces in sequence, the second wafer layer is processed through a through hole, a rerouting layer and a hybrid bonding, and the at least two wafer layers are connected with each other through the through hole, the rerouting layer and the hybrid bonding of each layer.

2. The assembly of claim 1, wherein the at least two wafer layers further comprise a third wafer layer, the second wafer layer being stacked front-to-back with the third wafer layer, other wafer layers of the at least three wafer layers than the second wafer layer being subjected to at least one of a through-silicon via, a re-routing layer, and a hybrid bonding process.

3. The assembly of claim 2, wherein the front side of the second wafer layer is subjected to a hybrid bonding process and the back side of the second wafer layer is subjected to a through-silicon via, a re-routing layer, and a hybrid bonding process.

4. The assembly of claim 3, wherein the assembly comprises three wafer layers, the front side of the first wafer layer being subjected to a hybrid bonding process and the front side of the third wafer layer being subjected to a hybrid bonding process.

5. The assembly of claim 4, wherein the back side of the first wafer layer or the back side of the third wafer layer leads out pins.

6. The assembly of claim 5, wherein the three wafer layers are each wafers;

or alternatively, the process may be performed,

the second wafer layer is a wafer, one of the first wafer layer and the third wafer layer is a chip, and the other wafer layer is a wafer;

Or, the second wafer layer is a chip.

7. The assembly of claim 6, wherein the data flow of the three wafer layers comprises:

the data flow from the first wafer layer to the second wafer layer is through: the data source point, the mixed bond metal medium of the first wafer layer, the mixed bond metal medium of the second wafer layer and the data target point; and/or

The data flow from the second wafer layer to the first wafer layer is through: the data source point, the mixed bond metal medium of the second wafer layer, the mixed bond metal medium of the first wafer layer and the data target point; and/or

The data flow from the second wafer layer to the third wafer layer is through: the method comprises the steps of data source points, through silicon via metal media of a second wafer layer, rerouting layer metal media of the second wafer layer, mixed bond metal media of a third wafer layer and data target points; and/or

The data flow from the third wafer layer to the second wafer layer is through: the data source point, the mixed bond metal medium of the third wafer layer, the mixed bond metal medium of the second wafer layer, the rewiring layer metal medium of the second wafer layer, the through silicon via metal medium of the second wafer layer and the data target point; and/or

The data flow from the first wafer layer to the second wafer layer and then to the third wafer layer is as follows: the method comprises the steps of a data source point, a mixed bond metal medium of a first wafer layer, a mixed bond metal medium of a front surface of a second wafer layer, a through silicon via metal medium of a back surface of the second wafer layer, a rewiring layer metal medium of a back surface of the second wafer layer, a mixed bond metal medium of a third wafer layer and a data target point; and/or

The data flow from the third wafer layer to the second wafer layer and then to the first wafer layer is as follows: the method comprises the steps of data source points, mixed bond metal media of a third wafer layer, mixed bond metal media of the back surface of a second wafer layer, heavy wiring layer metal media of the back surface of the second wafer layer, through silicon via metal media of the back surface of the second wafer layer, mixed bond metal media of the front surface of the second wafer layer, mixed bond metal media of a first wafer layer and data target points.

8. The assembly of claim 7, wherein at least one of the three wafer layers is a logic layer, the logic layer being connected to the pins.

9. The assembly of claim 8, wherein an outer wafer layer of the three wafer layers is a logic layer and the remaining wafer layers are storage layers.

10. The assembly of claim 8, wherein the wafer layers on both sides of the three wafer layers are logic layers, and the wafer layer between the logic layers on both sides is a storage layer.

11. The assembly of claim 8, wherein the three wafer layers are each logic layers.

12. The component of any of claims 8-11, wherein the logic layer comprises: at least one of a data flow logic unit, a calculation logic unit or a storage logic unit, wherein the data flow logic adopts a simplified instruction to collect flow of an artificial intelligence engine or a network on chip; the calculation logic adopts a resistance change type memory or a simplified instruction set; the storage logic adopts a resistance change type memory or a static random access memory;

the storage layer adopts dynamic random access memory.

13. The assembly of claim 12, wherein if the logical layer includes the data flow logic, the configuration of the data flow logic comprises: the type of domain-specific architecture, whether the storage architecture requires a register;

If the logic layer includes the calculation logic unit, the configuration of the calculation logic unit includes: the fixed precision, the mixed precision and the calculated size of the storage array are matched with the bandwidth of the storage layer;

if the logical layer includes the storage logical unit, the configuration of the storage logical unit includes: at least one of a storage array size and a storage array type;

the configuration of the storage layer comprises: the number of memory blocks, the number of corresponding hybrid bond input and output ports, and whether the bandwidth can match the size of the compute storage array of the compute logic.

14. The assembly of claim 12, wherein any one of the three wafer layers, when a logic layer, comprises at least two types of logic cells.

15. The assembly of claim 12, wherein any one of the three wafer layers adjusts the correspondence of each cell in the wafer layer to each cell of the other wafer layers according to the yield of the other wafer layers.

16. The assembly of claim 12, wherein when any one of the three wafer layers is a logic layer, the logic layer configures logic units according to requirements.

17. The assembly of claim 12, wherein a configured logic layer of the three wafer layers multiplexes the other wafer layers.

18. The assembly of claim 12, wherein the number of hybrid bond metal dielectrics and the number of through silicon via metal dielectrics on the three wafer layers are independently configured.

19. A processor, comprising:

an integrated circuit assembly according to any of claims 1-18.

20. A system on a chip, comprising:

at least one processor, the processor being in accordance with claim 19.