WO2023231234A1 - Fcbga封装基板的制备方法 - Google Patents

Fcbga封装基板的制备方法 Download PDF

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Publication number
WO2023231234A1
WO2023231234A1 PCT/CN2022/120239 CN2022120239W WO2023231234A1 WO 2023231234 A1 WO2023231234 A1 WO 2023231234A1 CN 2022120239 W CN2022120239 W CN 2022120239W WO 2023231234 A1 WO2023231234 A1 WO 2023231234A1
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layer
packaging substrate
interconnection
preparing
fcbga
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PCT/CN2022/120239
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English (en)
French (fr)
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杨威
徐文龙
杜玲玲
庄爱东
宋景勇
付海涛
查晓刚
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上海美维科技有限公司
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Publication of WO2023231234A1 publication Critical patent/WO2023231234A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326

Definitions

  • the invention belongs to the technical field of semiconductor integrated circuits and relates to a method for preparing an FCBGA packaging substrate.
  • FCBGA Flip Chip Ball Grid Array
  • flip chip ball grid array packaging is currently the main method of high-end chip packaging.
  • the density of patterns on FCBGA packaging substrates continues to increase, and more and smaller blind holes need to be made, or trenches of various sizes and shapes need to be made according to product requirements. groove.
  • laser drilling has its limitations, which mainly include:
  • the price of laser drilling machines is very high.
  • the cost of laser drilling also increases rapidly.
  • the cost of laser drilling in order to ensure the high-density wiring design of the product, there are a large number of blind holes on the FCBGA package substrate. Hole design, and the number of blind holes continues to increase, which significantly increases the cost of laser drilling.
  • UV laser is a high-energy laser beam.
  • most of the laser energy is used for photochemical effects. It belongs to the principle of photochemical cracking and etching. Its energy is large and it can directly cut metal and glass fibers. It is suitable for small aperture processing. , but it requires precise control of laser drilling parameters, otherwise it will easily cause the problem of burn-through at the bottom of the blind hole;
  • CO 2 laser drilling has an operating wavelength of 9300 to 10600 nm, and the CO 2 laser is based on the copper layer and dielectric layer of the copper-clad laminate. The difference in absorption rate means that CO 2 laser can only form laser holes in the dielectric layer, while the copper layer at the bottom is not easily damaged.
  • CO 2 laser drilling has become an important method for making blind holes, but CO 2 laser drilling
  • the basic principle of the hole is that the material being processed absorbs the low-energy laser and melts or vaporizes the organic plate with strong heat in a very short time, causing it to be continuously removed to form a blind hole. This is an interaction between the laser and the material.
  • the process including reflection, absorption, vaporization, re-radiation, thermal diffusion and other different energy conversion processes, belongs to the principle of photothermal ablation. In actual work, this method has been found to easily produce excessive carbonization on the surface of the product, and even burn the board surface. Scorch will easily leave glue residue, which will affect the electrical performance of the product.
  • the laser light source is a very powerful and highly directional electromagnetic wave. Its wavelength is mostly in the range of ultraviolet, visible light and infrared.
  • the time of laser beam irradiation or laser pulse is limited.
  • a powerful laser beam irradiates When reaching the surface of a substance, the electrons in the substance will absorb electromagnetic waves, accelerate their motion, and violently collide with other electrons or ions. These laser collisions will rapidly heat up until the area irradiated by the beam is melted, vaporized, and ionized, thus Material is removed to form holes.
  • the laser beam irradiation or laser pulse time is long, that is, when these laser pulses collide for a long time or the number of laser shocks is less than 1 million times per second, a lot of energy is conducted and diffused to the surroundings.
  • the area forms a "heat-affected zone” (HAZ), whose thickness can range from tens to hundreds of microns.
  • Thermal damage or damage, such as melting and deformation will occur at the interface between the thickness of this "heat-affected zone” and its surrounding areas. , wrinkles, roughness, cracks or delamination, etc.
  • FCBGA packaging substrate it is necessary to provide a method for preparing an FCBGA packaging substrate to effectively solve the quality and cost problems encountered in the preparation of blind holes or trenches in the FCBGA packaging substrate.
  • the purpose of the present invention is to provide a method for preparing an FCBGA packaging substrate to solve the above series of preparation problems faced in the preparation of the FCBGA packaging substrate in the prior art.
  • the present invention provides a method for preparing an FCBGA packaging substrate, which includes the following steps:
  • the core board including a dielectric layer and core board copper foil layers located on opposite sides of the dielectric layer;
  • a patterned metal connection layer electrically connected to the core layer structure is formed based on the connection hole, and the metal connection layer includes a seed layer and a metal layer.
  • the shape of the connection hole formed includes one or a combination of a circle, an ellipse, and a polygon.
  • the lower limit of the width dimension of the formed connection hole is 40 ⁇ m or less.
  • the material of the built-up layer includes ABF material or PP material.
  • a mixed gas of carbon tetrafluoride and oxygen is used to perform the inductively coupled plasma etching; the radiofrequency bias of the inductively coupled plasma etching is 10V-30V, and the etching time is 80min-120min.
  • the formed seed layer of the metal connection layer includes a copper seed layer formed by electroless plating or a titanium/copper seed stack formed by sputtering.
  • the steps of forming the metal layer of the metal connection layer include film attaching, exposure, development, electroplating, film removal and etching.
  • a method of forming the interconnect holes includes mechanical drilling or laser drilling.
  • the interconnection conductive layer is formed to fill the interconnection hole; or the interconnection conductive layer is formed to cover only the sidewalls of the interconnection hole and fill the interconnection hole by forming an insulating layer.
  • the steps after preparing the core layer structure are repeated until the required number of stacked layers is completed to prepare a multi-layer FCBGA packaging substrate.
  • the preparation method of the FCBGA package substrate of the present invention can effectively reduce the size of the connection holes by using inductively coupled plasma etching, produce connection holes with a lower limit of width size below 40 ⁇ m, and can form multiple holes with different sizes and dimensions at one time.
  • connection holes with different shapes which can effectively reduce costs and increase the wiring density of FCBGA packaging substrates; inductively coupled plasma etching and layering are chemical reactions, which can avoid edge blackening and heat-affected zones caused by thermal ablation Therefore, the present invention can prepare an FCBGA packaging substrate with good reliability and electrical properties based on inductively coupled plasma etching.
  • Figure 1 shows a process flow chart for preparing an FCBGA packaging substrate based on inductively coupled plasma etching according to the present invention.
  • Figure 2 shows a schematic structural diagram of the core board in the embodiment of the present invention.
  • FIG. 3 shows a schematic structural diagram after interconnection holes are formed in an embodiment of the present invention.
  • FIG. 4a shows a schematic structural diagram after forming an interconnection conductive layer in an embodiment of the present invention.
  • FIG. 4b shows another structural schematic diagram after the interconnection conductive layer is formed in the embodiment of the present invention.
  • Figure 5 shows a schematic structural diagram of the core layer structure prepared in the embodiment of the present invention.
  • FIG. 6 shows a schematic structural diagram after forming a build-up layer and a copper foil layer in an embodiment of the present invention.
  • FIG. 7 shows a schematic structural diagram after forming an etching window in an embodiment of the present invention.
  • FIG. 8 shows a schematic structural diagram after inductively coupled plasma etching is performed to form connection holes in an embodiment of the present invention.
  • FIG. 9 shows a schematic structural diagram after removing the copper foil layer in an embodiment of the present invention.
  • FIG. 10a shows a schematic structural diagram after forming a metal connection layer in an embodiment of the present invention.
  • Figure 10b shows another structural schematic diagram after the metal connection layer is formed in the embodiment of the present invention.
  • spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element or element shown in the drawings.
  • a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • “between” means including both endpoint values.
  • structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, as well as may include additional features formed between the first and second features. Embodiments between second features such that the first and second features may not be in direct contact.
  • illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.
  • this embodiment provides a method for preparing an FCBGA packaging substrate, which includes the following steps:
  • S1 Provide a core board, which includes a dielectric layer and core copper foil layers located on opposite sides of the dielectric layer;
  • the metal connection layer includes a seed layer and a metal layer.
  • the preparation method of the FCBGA package substrate in this embodiment uses the inductively coupled plasma etching to produce both sides of the substrate at the same time to improve production efficiency; it can effectively reduce the size of the connection holes, and multiple moldings can be formed at one time. Having the connection holes of different sizes and/or different shapes can effectively reduce costs and increase the wiring density of the FCBGA packaging substrate; the inductively coupled plasma etching and the layer addition are chemical reactions, which can avoid thermal Ablation causes blackening of the edges and the generation of heat-affected zones, and the metal connection layer with good bonding force can be formed without the need for slag removal operations; thus the FCBGA packaging substrate with good reliability and electrical properties can be prepared .
  • step S1 is performed to provide a core board, which includes a dielectric layer 101 and core copper foil layers 102 located on opposite sides of the dielectric layer 101 .
  • the core board has a three-layer structure in which the core board copper foil layer 102, the dielectric layer 101 and the core board copper foil layer 102 are stacked in sequence, wherein the dielectric layer 101 can be Insulating materials with a glass transition temperature of 260 degrees and a deformation amount in the XY direction of less than 10 ppm/°C or less than 6 ppm/°C.
  • the thickness of the core plate copper foil layer 102 can be 12 ⁇ m, etc., but the structure of the core plate is not limited to this.
  • step S2 is performed: forming interconnection holes 103 penetrating the core board.
  • mechanical drilling or laser drilling can be used.
  • the mechanical drilling can be drilled using a mechanical drill.
  • the holes formed by mechanical drilling can be
  • the aperture of the interconnection hole 103 may be 150 ⁇ m as shown in Figure 3, but is not limited thereto; the laser drilling may be performed on both sides of the core board using a laser drill, and the aperture may be 40 ⁇ m to 200 ⁇ m. Such as 40 ⁇ m, 50 ⁇ m, 150 ⁇ m, 200 ⁇ m, etc.
  • step S3 is performed to form an interconnection conductive layer covering the interconnection holes 103 and the core copper foil layer 102.
  • the interconnection conductive layer includes a copper seed layer 104 of the interconnection conductive layer and a copper metal layer 105 of the interconnection conductive layer.
  • the copper metal layer 105 of the interconnect conductive layer covers the copper seed layer 104 of the interconnect conductive layer.
  • the slag removal operation can be performed first on the core board that has been mechanically drilled or laser drilled in order to improve the bonding force between the interconnection conductive layer and the core board, and then electroless plating can be used.
  • the copper seed layer 104 of the interconnection conductive layer is first formed, and then the copper metal layer 105 of the interconnection conductive layer is formed by electroplating to complete the production of the interconnection conductive layer.
  • the interconnection conductive layer may be formed to fill the interconnection holes 103, as shown in FIG. 4b; or the interconnection conductive layer may only cover the sidewalls of the interconnection holes 103, and fill the interconnection holes 103 by forming the insulating layer 106. Interconnect hole 103, Figure 4a.
  • the aperture of the interconnection hole 103 formed is larger than the aperture of the interconnection hole 103 formed by laser drilling.
  • the interconnect hole 103 may be filled by forming the insulating layer 106 .
  • mechanical drilling is used to form the interconnection hole 103.
  • the interconnection conductive layer only covers the side walls of the interconnection hole 103, and the interconnection hole is filled with the insulating layer 106.
  • the insulating layer 106 may be made of resin, but is not limited thereto.
  • the interconnection hole 103 can be filled only by the formed interconnection conductive layer, as shown in FIG. 4b, regarding The method of forming the interconnection conductive layer can be specifically selected according to needs, and is not overly limited here.
  • step S4 is performed to pattern the interconnection conductive layer and the core copper foil layer 102 to expose the dielectric layer 101 to prepare the core layer structure 100 .
  • the method of patterning the interconnection conductive layer and the core plate copper foil layer 102 may include forming a dry film, exposing, developing, forming an etching window, and then performing etching on the interconnection conductive layer and the core plate copper layer.
  • the foil layer 102 is etched, and finally the dry film removal step is performed to prepare the core layer structure 100.
  • the size and layout of the formed etching window can be selected according to needs, and are not overly limited here.
  • the core layer structure 100 includes a dielectric layer 101, a core copper foil layer 102, an interconnection conductive layer and an insulating layer 106.
  • step S5 is performed to form a build-up layer 201 and a copper foil layer 202 stacked from the inside out on two opposite sides of the core structure 100 using a lamination method.
  • the material of the build-up layer 201 may include ABF material or PP material.
  • the built-up layer 201 can be made of ABF material containing silicon oxide and epoxy resin, or PP material containing glass fiber and epoxy resin, etc.
  • the types of the built-up layer 201 and the copper foil layer 202 can be based on Specific choices need to be made, and there are no excessive restrictions here.
  • the lamination method may adopt a method such as vacuum lamination to form the build-up layer 201 and the copper foil layer with good bonding force and stacked from the inside out on the opposite sides of the core layer structure 100 202. There is no excessive restriction on the thickness of the build-up layer 201 and the copper foil layer 202.
  • step S6 is performed to pattern the copper foil layer 202 to form an etching window 203 .
  • the etching window 203 can be formed in the copper foil layer 202 through the steps of film attaching, exposure, development, etching and film removal, so that the etching window 203 can be patterned based on the etching window 203.
  • step S7 is performed to perform inductively coupled plasma etching based on the etching window 203 to form a connection hole 204 penetrating the build-up layer 201 .
  • a mixed gas of carbon tetrafluoride and oxygen can be used to perform the inductively coupled plasma etching, wherein the radio frequency bias voltage of the inductively coupled plasma etching can be 10V to 30V, such as 10V, 15V, 20V, 30V, etc. , the etching time can be between 80min and 120min, such as 80min, 100min, 120min, etc., and according to the thickness of the built-up layer 201, multiple cycles of the inductively coupled plasma etching can be performed to form a layer that penetrates the built-up layer 201.
  • the connecting hole 204 of 201 can be used to perform the inductively coupled plasma etching, wherein the radio frequency bias voltage of the inductively coupled plasma etching can be 10V to 30V, such as 10V, 15V, 20V, 30V, etc. , the etching time can be between 80min and 120min, such as 80min, 100min, 120min, etc.
  • connection hole 204 may include one or a combination of circles, ellipses, and polygons, such as circles, squares, trapezoids, etc., and the lower limit of the width of the connection holes 204 may be 40 ⁇ m. Below, such as 40 ⁇ m, 30 ⁇ m, 20 ⁇ m, etc., and multiple connection holes 204 with different sizes and/or different morphologies can be formed at one time, such as small blind holes, large blind holes, small trenches, and large trenches can be prepared at one time. slots, etc., which can effectively reduce costs and increase wiring density.
  • connection holes 204 since the inductively coupled plasma etching and the build-up layer 201 are chemically reacted, the problem of edge blackening and heat-affected zones caused by thermal ablation when forming the connection holes 204 can be avoided.
  • step S8 is performed to remove the copper foil layer 202 , for example, using an etching method to remove the copper foil layer 202 to expose the build-up layer 201 .
  • step S9 is performed to form a patterned metal connection layer electrically connected to the core layer structure 100 based on the connection hole 204 .
  • the metal connection layer includes a seed layer and a metal layer.
  • the seed layer may include a copper seed layer formed by electroless plating or a titanium/copper seed stack formed by sputtering.
  • the seed layer in this embodiment is the copper seed layer 205 of the metal connection layer formed by electroless plating.
  • sputtering may also be used to form the titanium seed layer 207 of the metal connection layer and the copper seed layer 205 of the metal connection layer.
  • /Copper seed stack which can be selected according to needs.
  • the slag residue caused by ablation can be avoided when etching the build-up layer 201, thereby reducing the number of slag residues before forming the seed layer.
  • the steps of removing slag are used to reduce the process flow and reduce costs.
  • the copper metal layer 206 of the metal connection layer with a smaller size can be formed through the steps of film attaching, exposure, development, electroplating, film removal and etching.
  • it may also include repeating the steps after preparing the core layer structure 100 until the required number of stacked layers is completed to prepare a multi-layer FCBGA packaging substrate.
  • the above-mentioned steps S5 to S9 can be repeated until the required number of stacked layers is completed, such as 2 layers, 4 layers, 6 layers, etc., to prepare a multi-layer FCBGA packaging substrate.
  • the specific number of layers is not overly limited here. .
  • the preparation method of the FCBGA package substrate of the present invention can effectively reduce the size of the connection holes by using inductively coupled plasma etching, produce connection holes with a lower limit of width size below 40 ⁇ m, and can form multiple holes with different features at one time.
  • Connection holes of different sizes and/or shapes can effectively reduce costs and increase the wiring density of FCBGA packaging substrates; inductively coupled plasma etching and layering are chemical reactions, which can avoid edge blackening and thermal effects caused by thermal ablation. Therefore, the present invention can prepare an FCBGA packaging substrate with good reliability and electrical properties based on inductively coupled plasma etching.

Abstract

本发明提供一种FCBGA封装基板的制备方法，通过采用感应耦合等离子刻蚀，可有效降低连接孔的尺寸，制作宽度尺寸下限为40μm以下的连接孔，并且可以一次成型多个具有不同尺寸和/或不同形貌的连接孔，从而可有效降低成本，提升FCBGA封装基板的布线密度；感应耦合等离子刻蚀与增层为化学反应，可避免热烧蚀导致边缘发黑以及产生热影响区的问题，且无需进行除渣操作即可形成具有良好结合力的金属连接层；从而本发明基于感应耦合等离子刻蚀可制备具有良好可靠性及电性能的FCBGA封装基板。

Description

FCBGA封装基板的制备方法 技术领域
本发明属于半导体集成电路技术领域，涉及一种FCBGA封装基板的制备方法。
背景技术
FCBGA(Flip Chip Ball Grid Array)这种被称为倒装芯片球栅格阵列封装是目前高端芯片封装的主要方式。随着电子产品的集成度越来越高，FCBGA封装基板上的图形密度不断增加，需要制作更多、更小的盲孔，或者根据产品的要求，需要制作各种不同尺寸、不同形状的沟槽。
现在批量制作盲孔和沟槽的主要方法是采用UV激光钻机或者CO 2激光钻机在FCBGA封装基板上钻盲孔或铣沟槽，但采用激光钻孔有其局限性，主要包括：
一方面，激光钻机的价格非常高，随着基板上盲孔数量的大量增加，导致激光钻孔的成本也迅速增加，例如，为保证产品的高密度布线设计，FCBGA封装基板上有大量的盲孔设计，且盲孔的数量也在持续增加，使得激光钻孔成本大幅增加。
另一方面，UV激光是一种高能激光束，钻孔时大部分激光能量被用于光化学作用，属于光化学裂蚀刻原理，且其能量大，可以直接切割金属和玻璃纤维，适用于小孔径加工，但是其需要精确控制激光钻孔参数，否则极易造成盲孔底部烧穿的问题；CO 2激光钻孔由于其工作波长在9300～10600nm，基于覆铜板铜层和介电层对CO 2激光吸收率的不同，从而CO 2激光可仅在介电层中形成激光孔，而位于底部的铜层则不易被损坏，因此CO 2激光钻孔成为盲孔制作的重要方法，但CO 2激光钻孔的基本原理是被加工的材料吸收低能量的激光，在极短的时间将有机板材以强热熔化或汽化，使之被持续移除而形成盲孔，这是一个激光与物质相互作用的过程，包括反射、吸收、汽化、再辐射、热扩散等不同的能量转换过程，属于光热烧蚀原理，这种方法在实际工作中被发现容易在产品表面产生过度碳化，甚至将板面烧焦，易残留胶渣，影响产品的电气性能。
再者，激光光源是一束非常强大和高度定向性的电磁波，其波长大多在紫外、可见光和红外的范围内，而激光束照射或激光脉冲的时间是有限定的，当强大的激光束照射到物质的表面时，物质中的电子会吸收电磁波而加速运动，并与其他电子或离子发生激烈的碰撞，这些激光碰撞会迅速加热，直到被光束照射区域产生熔化、气化和离子化，从而除去物质而形成孔洞。在这个碰撞和熔化的过程中，如果激光光束照射或激光脉冲时间长，即当这些激光脉冲碰撞时间长或者激光冲击次数每秒少于100万次时，就有很多能量被传导和扩散到周围 区域形成“热影响区”(HAZ)，其厚度可以从几十微米到几百微米，而在这个“热影响区”厚度及其周围区域的界面处会形成热损伤或破坏，如熔化、变形、起皱、粗糙、裂缝或分层等等。
因此，提供一种FCBGA封装基板的制备方法，以有效解决FCBGA封装基板盲孔或沟槽制备所遇到的质量及成本问题，实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种FCBGA封装基板的制备方法，用于解决现有技术中FCBGA封装基板在制备中所面临的上述一系列的制备问题。
为实现上述目的及其他相关目的，本发明提供一种FCBGA封装基板的制备方法，包括以下步骤：
提供芯板，所述芯板包括介电层及位于所述介电层相对两面的芯板铜箔层；
形成贯穿所述芯板的互联孔；
形成覆盖所述互联孔及芯板铜箔层的互联导电层；
图形化所述互联导电层及所述芯板铜箔层，显露所述介电层，制备芯层结构；
采用压合法，于所述芯层结构的相对两面形成自内而外叠置的增层及铜箔层；
图形化所述铜箔层，形成刻蚀窗口；
基于所述刻蚀窗口，进行感应耦合等离子刻蚀，形成贯穿所述增层的连接孔；
去除所述铜箔层；
基于所述连接孔形成与所述芯层结构电连接的图形化的金属连接层，所述金属连接层包括种子层及金属层。
可选地，形成的所述连接孔的形貌包括圆形、椭圆形及多边形中的一种或组合。
可选地，形成的所述连接孔的宽度尺寸的下限为40μm以下。
可选地，所述增层的材质包括ABF材质或PP材质。
可选地，采用四氟化碳和氧气的混合气体进行所述感应耦合等离子刻蚀；所述感应耦合等离子刻蚀的射频偏压为10V～30V，刻蚀时间为80min～120min。
可选地，形成的所述金属连接层的种子层包括采用化学镀形成的铜种子层或采用溅射法形成的钛/铜种子叠层。
可选地，形成所述金属连接层的金属层的步骤包括贴膜、曝光、显影、电镀、去膜及刻蚀。
可选地，形成所述互联孔的方法包括机械钻孔或激光钻孔。
可选地，形成的所述互联导电层填充所述互联孔；或形成的所述互联导电层仅覆盖所述互联孔的侧壁，并通过形成绝缘层填充所述互联孔。
可选地，重复进行所述芯层结构制备后的步骤，直至完成所需的叠板层数以制备多层FCBGA封装基板。
如上所述本发明的FCBGA封装基板的制备方法，通过采用感应耦合等离子刻蚀，可有效降低连接孔的尺寸，制作宽度尺寸下限为40μm以下的连接孔，并且可以一次成型多个具有不同尺寸和/或不同形貌的连接孔，从而可有效降低成本，提升FCBGA封装基板的布线密度；感应耦合等离子刻蚀与增层为化学反应，可避免热烧蚀导致边缘发黑以及产生热影响区的问题，且无需进行除渣操作即可形成具有良好结合力的金属连接层；从而本发明基于感应耦合等离子刻蚀可制备具有良好可靠性及电性能的FCBGA封装基板。
附图说明
图1显示为本发明基于感应耦合等离子刻蚀制备FCBGA封装基板的工艺流程图。
图2显示为本发明实施例中芯板的结构示意图。
图3显示为本发明实施例中形成互联孔后的结构示意图。
图4a显示为本发明实施例中形成互联导电层后的一种结构示意图。
图4b显示为本发明实施例中形成互联导电层后的另一种结构示意图。
图5显示为本发明实施例中制备的芯层结构的结构示意图。
图6显示为本发明实施例中形成增层及铜箔层后的结构示意图。
图7显示为本发明实施例中形成刻蚀窗口后的结构示意图。
图8显示为本发明实施例中进行感应耦合等离子刻蚀形成连接孔后的结构示意图。
图9显示为本发明实施例中去除铜箔层后的结构示意图。
图10a显示为本发明实施例中形成金属连接层后的一种结构示意图。
图10b显示为本发明实施例中形成金属连接层后的另一种结构示意图。
元件标号说明
100               芯层结构
101               介电层
102               芯板铜箔层
103               互联孔
104               互联导电层的铜种子层
105               互联导电层的铜金属层
106               绝缘层
201               增层
202               铜箔层
203               刻蚀窗口
204               连接孔
205               金属连接层的铜种子层
206               金属连接层的铜金属层
207               金属连接层的钛种子层
S1～S9            步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。本文使用的“介于……之间”表示包括两端点值。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，其组件布局型态也可能更为复杂。
参阅图1，本实施例提供一种FCBGA封装基板的制备方法，包括以下步骤：
S1：提供芯板，所述芯板包括介电层及位于所述介电层相对两面的芯板铜箔层；
S2：形成贯穿所述芯板的互联孔；
S3：形成覆盖所述互联孔及芯板铜箔层的互联导电层；
S4：图形化所述互联导电层及所述芯板铜箔层，显露所述介电层，制备芯层结构；
S5：采用压合法，于所述芯层结构的相对两面形成自内而外叠置的增层及铜箔层；
S6：图形化所述铜箔层，形成刻蚀窗口；
S7：基于所述刻蚀窗口，进行感应耦合等离子刻蚀，形成贯穿所述增层的连接孔；
S8：去除所述铜箔层；
S9：基于所述连接孔形成与所述芯层结构电连接的图形化的金属连接层，所述金属连接层包括种子层及金属层。
本实施例的FCBGA封装基板的制备方法，通过采用所述感应耦合等离子刻蚀，可同时进行基板双面制作，以提高生产效率；可有效降低所述连接孔的尺寸，并且可以一次成型多个具有不同尺寸和/或不同形貌的所述连接孔，从而可有效降低成本，提升所述FCBGA封装基板的布线密度；所述感应耦合等离子刻蚀与所述增层为化学反应，可避免热烧蚀导致边缘发黑以及产生热影响区的问题，且无需进行除渣操作即可形成具有良好结合力的所述金属连接层；从而可制备具有良好可靠性及电性能的所述FCBGA封装基板。
以下结合附图2～图10b，对FCBGA封装基板的制备方法进行进一步的介绍，具体包括：
首先，参阅图2，执行步骤S1，提供芯板，所述芯板包括介电层101及位于所述介电层101相对两面的芯板铜箔层102。
具体的，所述芯板为依次叠置所述芯板铜箔层102、所述介电层101及所述芯板铜箔层102的三层结构，其中，所述介电层101可为玻璃化转变温度为260度、XY方向变形量小于10ppm/℃或小于6ppm/℃的绝缘材料，所述芯板铜箔层102的厚度可为12μm等，但所述芯板的结构并非局限于此。
接着，参阅图3，执行步骤S2：形成贯穿所述芯板的互联孔103。
具体的，当在所述芯板上进行所述互联孔103的制作时，可采用机械钻孔或激光钻孔，其中，所述机械钻孔可采用机械钻机进行钻孔，机械钻孔形成的所述互联孔103的孔径可为如图3所示的150μm，但并非局限于此；所述激光钻孔可采用激光钻机在所述芯板的两面进行对钻，孔径可为40μm～200μm，如40μm、50μm、150μm、200μm等。
接着，参阅图4a及图4b，执行步骤S3，形成覆盖所述互联孔103及芯板铜箔层102的 互联导电层。所述互联导电层包括互联导电层的铜种子层104和互联导电层的铜金属层105。作为示例，所述互联导电层的铜金属层105覆盖所述互联导电层的铜种子层104。
具体的，可在已经进行机械钻孔或激光钻孔的所述芯板上先进行除胶渣的操作，以便提高所述互联导电层与所述芯板的结合力，接着可采用如化学镀先形成所述互联导电层的铜种子层104，接着再采用电镀法形成所述互联导电层的铜金属层105，以完成所述互联导电层的制作。
作为示例，形成的所述互联导电层可填充所述互联孔103，如图4b；或形成的所述互联导电层仅覆盖所述互联孔103的侧壁，并通过形成绝缘层106填充所述互联孔103，如图4a。
具体的，当采用机械钻孔形成所述互联孔103时，其形成的所述互联孔103的孔径大于所述激光钻孔形成的所述互联孔103的孔径，为进一步提高其机械稳定性，可通过形成所述绝缘层106以填充所述互联孔103。本实施例中，如图4a所示，采用机械钻孔形成所述互联孔103，所述互联导电层仅覆盖所述互联孔103的侧壁，且通过所述绝缘层106填充所述互联孔103，其中，所述绝缘层106的材质可为树脂，但并非局限于此。在另一实施例中，若所述互联孔103的尺寸较小，如采用激光钻孔制备，则可仅通过形成的所述互联导电层即可填充所述互联孔103，如图4b，关于形成所述互联导电层的方法具体可根据需要进行选择，此处不作过分限制。
接着，参阅图5，执行步骤S4，图形化所述互联导电层及所述芯板铜箔层102，显露所述介电层101以制备芯层结构100。
具体的，图形化所述互联导电层及所述芯板铜箔层102的方法可包括形成干膜、曝光、显影，形成刻蚀窗口，而后进行对所述互联导电层及所述芯板铜箔层102的刻蚀，最后进行干膜去除的步骤，以制备所述芯层结构100，关于形成的所述刻蚀窗口的尺寸及布局可根据需要进行选择，此处不作过分限制。作为示例，所述芯层结构100包括介电层101、芯板铜箔层102、互联导电层和绝缘层106。
接着，参阅图6，执行步骤S5，采用压合法，于所述芯层结构100的相对两面各自形成自内而外叠置的增层201及铜箔层202。
作为示例，所述增层201的材质可包括ABF材质或PP材质。
具体的，所述增层201可采用含氧化硅及环氧树脂的ABF材质，或含玻璃纤维及环氧树脂的PP材质等，所述增层201及所述铜箔层202的种类可根据具体需要进行选择，此处不作过分限制。其中，所述压合法可采用如真空压合的方法，以于所述芯层结构100的相对两面形成具有良好结合力、自内而外叠置的所述增层201及所述铜箔层202，关于所述增层201 及所述铜箔层202的厚度此处不作过分限制。
接着，参阅图7，执行步骤S6，图形化所述铜箔层202，形成刻蚀窗口203。
具体的，可通过贴膜、曝光、显影、刻蚀和去膜的步骤，以在所述铜箔层202中形成所述刻蚀窗口203，从而可基于所述刻蚀窗口203图形化所述增层201。
接着，参阅图8，执行步骤S7，基于所述刻蚀窗口203，进行感应耦合等离子刻蚀，形成贯穿所述增层201的连接孔204。
具体的，可采用四氟化碳和氧气混合气体进行所述感应耦合等离子刻蚀，其中，所述感应耦合等离子刻蚀的射频偏压可为10V～30V，如10V、15V、20V、30V等，刻蚀时间可在80min～120min，如80min、100min、120min等，并根据所述增层201的厚度，可以进行所述感应耦合等离子刻蚀的多次循环操作，以形成贯穿所述增层201的所述连接孔204。
其中，形成的所述连接孔204的形貌可包括圆形、椭圆形及多边形中的一种或组合，如圆形、方形、梯形等，且所述连接孔204的宽度尺寸下限可在40μm以下，如40μm、30μm、20μm等，且可一次成型多个具有不同尺寸和/或不同形貌的所述连接孔204，如一次成型制备小盲孔、大盲孔、小沟槽、大沟槽等，从而可有效降低成本，提升布线密度。
进一步的，由于所述感应耦合等离子刻蚀与所述增层201为化学反应，从而可避免在形成所述连接孔204时，因热烧蚀导致的边缘发黑以及产生热影响区的问题。
接着，参阅图9，执行步骤S8，去除所述铜箔层202，如采用刻蚀法去除所述铜箔层202，以显露所述增层201。
接着，参阅图10a及图10b，执行步骤S9，基于所述连接孔204形成与所述芯层结构100电连接的图形化的金属连接层，所述金属连接层包括种子层及金属层。
作为示例，所述种子层可包括采用化学镀形成的铜种子层或采用溅射法形成的钛/铜种子叠层。
具体的，参阅图10a，该实施例所述种子层为采用化学镀形成的所述金属连接层的铜种子层205，但并非局限于此，如参阅图10b，在另一实施例中，为进一步的提高所述金属连接层与所述芯层结构100的结合力，也可采用溅射法形成包括所述金属连接层的钛种子层207及所述金属连接层的铜种子层205的钛/铜种子叠层，具体可根据需要进行选择。本实施例中，由于采用所述感应耦合等离子刻蚀，从而在对所述增层201进行刻蚀时，可避免烧蚀导致的胶渣残留现象，从而在形成所述种子层前，可减少除胶渣的步骤，以减少工艺流程，降低成本。
接着，可在所述种子层的基础上通过贴膜、曝光、显影、电镀、去膜及刻蚀的步骤，形 成具有较小尺寸的所述金属连接层的铜金属层206。
作为示例，还可包括重复进行所述芯层结构100制备后的步骤，直至完成所需的叠板层数以制备多层FCBGA封装基板。
具体的，可重复进行上述步骤S5～步骤S9，直至完成所需的叠板层数，如2层、4层、6层等，以制备多层FCBGA封装基板，具体层数此处不作过分限定。
综上所述，本发明的FCBGA封装基板的制备方法，通过采用感应耦合等离子刻蚀，可有效降低连接孔的尺寸，制作宽度尺寸下限为40μm以下的连接孔，并且可以一次成型多个具有不同尺寸和/或不同形貌的连接孔，从而可有效降低成本，提升FCBGA封装基板的布线密度；感应耦合等离子刻蚀与增层为化学反应，可避免热烧蚀导致边缘发黑以及产生热影响区的问题，且无需进行除渣操作即可形成具有良好结合力的金属连接层；从而本发明基于感应耦合等离子刻蚀可制备具有良好可靠性及电性能的FCBGA封装基板。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. FCBGA封装基板的制备方法，其特征在于，包括以下步骤：
    提供芯板，所述芯板包括介电层及位于所述介电层相对两面的芯板铜箔层；
    形成贯穿所述芯板的互联孔；
    形成覆盖所述互联孔及芯板铜箔层的互联导电层；
    图形化所述互联导电层及所述芯板铜箔层，显露所述介电层，制备芯层结构；
    采用压合法，于所述芯层结构的相对两面形成自内而外叠置的增层及铜箔层；
    图形化所述铜箔层，形成刻蚀窗口；
    基于所述刻蚀窗口，进行感应耦合等离子刻蚀，形成贯穿所述增层的连接孔；
    去除所述铜箔层；
    基于所述连接孔形成与所述芯层结构电连接的图形化的金属连接层，所述金属连接层包括种子层及金属层。
  2. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：形成的所述连接孔的形貌包括圆形、椭圆形及多边形中的一种或组合。
  3. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：形成的所述连接孔的宽度尺寸的下限为40μm以下。
  4. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：所述增层的材质包括ABF材质或PP材质。
  5. 根据权利要求4所述的FCBGA封装基板的制备方法，其特征在于：所述增层的材质包括含氧化硅及环氧树脂的ABF材质或含玻璃纤维及环氧树脂的PP材质。
  6. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：所述压合法为真空压合法。
  7. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：采用四氟化碳和氧气的混合气体进行所述感应耦合等离子刻蚀；所述感应耦合等离子刻蚀的射频偏压为10V～30V，刻蚀时间为80min～120min。
  8. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：形成的所述种子层包 括采用化学镀形成的铜种子层或采用溅射法形成的钛/铜种子叠层。
  9. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：形成所述金属层的步骤包括贴膜、曝光、显影、电镀、去膜及刻蚀。
  10. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：形成所述互联孔的方法包括机械钻孔或激光钻孔。
  11. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：所述互联导电层包括互联导电层的铜种子层和互联导电层的铜金属层。
  12. 根据权利要求10所述的FCBGA封装基板的制备方法，其特征在于：形成覆盖所述互联孔及芯板铜箔层的互联导电层的方法包括：
    在所述芯板上进行除胶渣的操作；
    采用化学镀法形成所述互联导电层的铜种子层；
    采用电镀法形成所述互联导电层的铜金属层。
  13. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：形成的所述互联导电层填充所述互联孔；或形成的所述互联导电层仅覆盖所述互联孔的侧壁，并通过形成绝缘层填充所述互联孔。
  14. 根据权利要求1所述的FCBGA封装基板的制备方法，其特征在于：重复进行所述芯层结构制备后的步骤，直至完成所需的叠板层数以制备多层FCBGA封装基板。
  15. 一种FCBGA封装基板，其特征在于，所述FCBGA封装基板通过权利要求1-14任一项所述的制备方法制成。
PCT/CN2022/120239 2022-06-01 2022-09-21 Fcbga封装基板的制备方法 WO2023231234A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003218528A (ja) * 2002-01-21 2003-07-31 Hitachi Kokusai Electric Inc プリント基板の製造方法
TW200824065A (en) * 2006-11-28 2008-06-01 Advanced Semiconductor Eng Package substrate and fabricating method thereof
CN104185363A (zh) * 2014-08-19 2014-12-03 华进半导体封装先导技术研发中心有限公司 复合型超薄无芯基板及其制作方法
CN114068473A (zh) * 2020-07-31 2022-02-18 三星电子株式会社 半导体封装件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003218528A (ja) * 2002-01-21 2003-07-31 Hitachi Kokusai Electric Inc プリント基板の製造方法
TW200824065A (en) * 2006-11-28 2008-06-01 Advanced Semiconductor Eng Package substrate and fabricating method thereof
CN104185363A (zh) * 2014-08-19 2014-12-03 华进半导体封装先导技术研发中心有限公司 复合型超薄无芯基板及其制作方法
CN114068473A (zh) * 2020-07-31 2022-02-18 三星电子株式会社 半导体封装件

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