TW200824065A - Package substrate and fabricating method thereof - Google Patents

Abstract

A package substrate including a semiconductor substrate, an insulation layer, at least one plated through-hole structure, a first circuit lamination, and a second circuit lamination is provided. The semiconductor substrate has a first surface, a corresponding second surface, and at least one through hole connecting there between. The insulation layer covers the first surface, the second surface and the inner side of the through hole. The plated through-hole structure is disposed inside the through hole of the semiconductor substrate. The first and the second circuit lamination are respectively disposed on the first and the second surface and have their own solder pads thereon. The first circuit lamination and the second circuit lamination are electrically connected with each other via the plated through-hole structure. The fabricating method of the package substrate is also provided.

Description

200824065 ^ojdivi ^ j2-NEW-FINAL-TW-2006 1128 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and is not related to a package substrate and its fabrication method. /, [Prior Art] Flip chip technology has been widely used in the field of chip packaging due to its advantages of shrinking chip package area, shrinkage, and path. = Chip Scale Package (CSP), wafer direct attach package (Direct Chip Attached (DCA) and Multi-Chip Module (MCM) and other types of package modules can be used to achieve the purpose of packaging by flip chip technology. The conventional flip chip packaging process firstly fabricates a plurality of bumps (five) on the contacts of the wafer, and then prints them on the screen by a screen printing (such as a solder to form a solder to the contacts of the package substrate, Align the bumps on the wafer with the solder and attach the bumps to the material

The L process allows solder to be bonded to the bumps to mount the wafer on the substrate and electrically connect the wafer to the package substrate. In addition, the plate (four) - the side surface may be formed with solder balls, so that the wafer is connected to the solder ball through the package, and is connected to the external circuit by the solder ball, such as the corresponding bump of the printed cloth can not be sealed with the shock Peel off the substrate. In addition, the joint may cause the bump to be self-sealing on the substrate, and between the sealing substrate and the external circuit board.

200824065 Λ〇£ϋνι j j2-NEW-FINAL-TW-2006 1128 The problem of solder balls falling off due to different coefficients. As the integration of the integrated circuit increases, the thermal stress and warpage of the wafer, the package substrate and the external circuit board are mismatched. It is also becoming more and more serious, and as a result, the reliability between the wafer and the package substrate and between the package substrate and the external circuit board is lowered, and the reliability test is failed. SUMMARY OF THE INVENTION In view of the above, the present invention provides a package substrate which can be effectively reduced and can be used to improve the reliability of wafer packaging. The purpose is to provide a package of the above-mentioned county substrate. The purpose of the invention is as follows: the invention proposes a kind of sealing plate 'the first line to the right side - the first surface and the first material At least a through hole having an opposite face and a second surface. Insulation i cover 2 inner wall of the through hole, 纟 = brother, the line should be layered on the first surface = the first line of the first layer is laminated. According to the invention, the method for fabricating the ih-batch substrate is further mentioned, and the manufacturing method of the package base 200824065 AM^i”2-NEW_FINAL_TW2〇〇6ll28 board first provides a semiconductor substrate, and the semiconductor substrate has a phase ΐ—the first a surface and a second surface. Then, a through hole is formed in the semiconductor substrate, wherein the through hole penetrates the first surface and the second surface. Thereafter, an insulating layer is formed to cover the first surface of the semiconductor substrate, The second surface and the inner wall of the through hole. Then, a first conductive layer is formed on the insulating layer. Next, an insulating (four) is formed in the through hole, and the through-hole (10) first conductive layer and the insulator two are formed into a plated through hole structure. Forming a first line stack and (two second lines are laminated on both sides of the semiconductor substrate, such that the first line stack second line stack is electrically connected to each other via the plated through hole structure, wherein the first line layer surface has At least one first pad, and the second circuit stack surface has one second pad. In a preferred embodiment, the first line stack and/or the second line stack are respectively formed by at least one pattern. The circuit layer and at least one dielectric layer Stacked, wherein the patterned circuit layer may comprise a surface circuit layer, and the surface circuit layer is, for example, a titanium/nickel vanadium/copper alloy layer or a titanium/nickel vanadium/gold alloy layer. Further, the patterned circuit layer may further comprise at least one The inner circuit layer, wherein the inner circuit layer " is, for example, a copper layer, a titanium/copper alloy layer or a titanium/copper/titanium alloy layer. In addition, the dielectric material can be an organic material and the organic material is, for example, a poly. The above-mentioned plated through-hole structure may include a conductive wall and an insulating material, and the conductive wall is disposed on the insulating layer of the inner wall of the through hole, and the insulating material is filled in the through hole, wherein the conductive wall is, for example, a copper layer or a titanium. / Copper alloy layer or titanium / copper / titanium alloy layer 0 The above package substrate may further comprise at least one solder ball, arranged in the first welding 200824065 aoiijvi J J2-NEW-FINAL-TW-20061128 Yuxing / or Ding π limb The method of manufacturing the above-mentioned package substrate, the method of forming the through hole in the semiconductor substrate is, for example, laser drilling, The method of forming the insulating chips is, for example, a semi-conductive The substrate is subjected to a thermal oxidation process. "In a preferred embodiment, the first line stack is formed and/or the second == method comprises the following steps: (4) forming a second conductive layer in the semi-guide: side /b) patterning the second conductive layer to form - Figure 8, good road layer. (C) forming a dielectric layer on the patterned 绕μ 匕 dielectric layer ′ to expose a portion of the patterned line; This: and

The following steps are included: First, the layer is provided on the layer. Thereafter, the second conductive 2 factory was patterned by a patterned mask to remove the mask. Further, the second conductive layer of the pattern H is wet-type. For example, the method of using a photosensitive material to form a dielectric layer for the straw-money engraving liquid, for example, for the dielectric layer - micro-denier: 'the method of the dielectric layer = can include the following steps: first === External 'patterned dielectric layer. Thereafter, the patterned mask is removed by patterning the mask - patterning the mask behind, where the pattern is set to layer for the remainder. The method of patterning the metal layer f, for example, including the metal material, includes etching the dielectric layer by the dielectric layer to the dielectric layer 200824065 ... one... 2-NEW-FINAL-TW-20061128 The method for fabricating the substrate further comprises: forming at least a solder ball on the first solder fillet, wherein the method of forming the germanium surface may include: the middle of the circuit stack and/or the second circuit stack is exposed; Figure 4; Army = - opening, with ": welding rod material to form at least - solder balls. Next, move: The pattern in the middle can be turned into a “® cased photoresist layer”. In addition, 3 may contain (4), and after the mask, the 2 flux may be included and the reaction product of the auxiliary agent and the solder may be removed. A less-mineral via structure, a first including an insulating substrate, a wiring layer to the Victoria, and a second wiring stack. The hole structure is disposed on at least a through hole of the inner surface of the through hole. Plated through and the surface of the first-line laminate has a surface dead, s on the :: 面 face i' two-line laminated surface with cm conduction. The method for manufacturing the agricultural substrate with the circuit layer and the second circuit layer through the plated through hole structure, comprising the following: - the following: Correspondingly - wherein the through hole is formed through the first-table ^_, the through hole is in the insulating substrate, and the electric layer covers the semiconductor substrate: first, then forms a first guide, and then fills in - (4) Two surfaces and the inner wall of the through hole. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Finally, a first line layer and a second line are respectively formed on both sides of the insulating substrate, so that the first line stack and the second line stack are electrically connected to each other via the plated through hole structure, wherein the first line stack The layer surface has at least one first pad and the second line stack surface has at least one second pad. In a preferred embodiment, the first line stack and/or the second line stack are respectively superposed by at least one patterned circuit layer and at least one dielectric layer. The patterned circuit layer may include a surface layer. The circuit layer, for example, is a titanium/nickel vanadium/copper alloy layer or a titanium/nickel vanadium/gold alloy layer. In addition, the patterned circuit layer may further comprise at least one inner wiring layer, wherein the inner wiring layer is, for example, a copper layer, a titanium/copper alloy layer or a titanium/copper/titanium alloy layer. Further, the material of the dielectric layer may be an organic material, and the organic material is, for example, Polyimide. The above plated through hole structure may include a conductive wall and an insulating material, and the conductive wall is disposed on the insulating layer of the inner wall of the through hole, and the insulating material is filled in the through hole

The conductive substrate is, for example, a copper layer, a titanium/copper alloy layer, or a titanium/copper/titanium alloy layer 0. The package substrate may further include at least one solder ball disposed on the first solder joint and/or the second solder pad. Further, the material of the semiconductor substrate is, for example, a dioxygen price f (Si〇2). In addition, a method of forming a through hole in a semiconductor material of a semi-conducting county is laser drilling. The method of forming a first-line stack and/or a second turn (3) includes the steps of: (a) forming a second conductive layer on at least one side of the half-double substrate. (b) patterning the second conductive layer to form a wooden circuit layer. (e) forming a dielectric layer on (d) the patterned dielectric layer to expose the substrate. And forming a first-line stack and/or a second layer. In addition, the method of repeating steps (a) to (4) at least the "line" layer may further include the following steps: first, the == two conductive layer on the electrical layer. Thereafter, the wet mask is performed by patterning the mask 2 to the second conductive layer. The method is, for example, forming a dielectric layer by means of a pair of remnant pairs, and patterning the dielectric layer to form a dielectric layer. In addition, the first step is to provide a patterned mask: After the shift, the mask is applied to the dielectric layer. The method of forming a solder mask comprises: at least one solder ball in the first shape, wherein the solder ball is formed by the method of fabricating the dielectric layer. = Case: pad cover 2, 枓. Then 'reflow solder' to form at least a flux that can contain flux, and after removing the patterned mask, it can be packaged 12

200824065 ^^xvx^^2-NEW-FINAL-TW-20061128 includes removing the flux and removing the reaction product of the flux and the solder. The package substrate of the present invention can use a semiconductor substrate or an insulating substrate having a desired thermal expansion coefficient. Therefore, when the package substrate is used in a chip package, the difference in thermal expansion coefficient between the package substrate and the wafers carried therein can be reduced. Improve the reliability of the chip package. The above and other objects, features and advantages of the present invention will become more apparent. [Embodiment] M - A schematic cross-sectional view of a substrate of the present invention in the first embodiment of the present invention. The two 'package substrate just includes a semiconductor substrate ιΐ0, an insulation: a line crystal via structure 130, a first line stack 140, and a first 〇 having a corresponding first table first surface, nt and The semiconductor substrate 110 (7) has a uniform aperture through the body =112 and the second surface 114. 112. The second surface layer 120 covers the first surface of the semiconductor substrate 110 on the inner wall of the through hole ΰδ:1^116. The plated through hole structure 130 is disposed on the insulating layer 12 of the square, and the 14G is disposed on the first surface 112 of the pad 142. The surface of the circuit stack 14G has a first insulating layer 120 on the first surface 152 of the second surface Η4, and the surface of the first ohm-circuit layer 15G has a second pad structure 130. Mutual conduction: 14G and second line stack (9) via mine through hole junction 13 200824065 "One-NEW-FINAL - TW-20061128 Note that in this embodiment, consistent hole i 16 and one-clock via structure 130 For example, the sealing substrate 1 can also have a plurality of through holes ι6 and a plurality of plated through holes, which are not related to the present invention. In addition, in this embodiment, two or more first weldings are used. The first 142 and the second 塾 152 are exemplified by those skilled in the art. However, in practical applications, the number of the first pad 142 and the second pad 152 may be plural, and the present invention also Do not limit this.

Since the package substrate in the embodiment uses a semiconductor substrate, when the package substrate is used in the wafer county, the difference in thermal expansion between the wafer and the package substrate can be reduced, so that (9) the county does not expect the raw solder balls to fall off. Such problems, in turn, improve the reliability of the chip package. The material of the semiconductor substrate 110 is, for example, Silicium. Further, the material of the insulating layer 120 is, for example, SiO 2 (Si 2 ). The material of the conductor substrate 110 is cut through a thermal oxidation process: the surface of the substrate U is formed - the insulating layer of the layer of the material of the silica oxide is 12U. The line wiring layer 140 is patterned by two or more layers. The circuit layer 144 is alternately laminated with the media board 146.

= 50 is formed by two or more patterned circuit layers 154 and dielectric layers i56 J 璺 5, but the invention is not limited thereto. For example, the first (10) may also include only - the patterned circuit layer 144 and - The dielectric layer i46, g & line layer (9) may include only - the patterned circuit layer 154 and the layer, in other words, the patterned circuit layer 144 may include - surface line 2-NEW-FINAL-TW-20061128 200824065

The material f of the surface wiring layer 144a is, for example, titanium/nickel/copper five or titanium/nickel/gold alloy. Further, if the first wiring stack (10) is formed by alternately laminating two or more patterned wiring layers 144 and dielectric layers 146, the patterned wiring layer 144 may further include a plurality of inner wiring layers! She, while the inner layer 1 is, for example, a copper layer, a titanium/copper alloy layer or a chin/copper/champ alloy layer, the material of the dielectric layer 146 may be an organic material, such as polyimide. . The patterned circuit layer 154 may also be a surface layer 154a, or a surface layer (10) and a plurality of inner layer layers (10), and the material layer of the surface layer (10) may be the same material as the surface layer 144a. The material of the inner wiring layer (10) may be the same as the inner wiring layer 144b. It is worth noting that 'in this implementation, a plurality of inner layer layer layers and an inner layer layer layer 154b are taken as an example', but those skilled in the art may also only set one (10) secret layer 144b, or only configure The circuit layer 154b' is not limited by the present invention. In addition, the plated through hole structure 130 may include a conductive wall 132 and an insulating material 134, and the conductive wall 132 is disposed on the inner layer of the through hole 116, and the insulating material 134 is filled in the through hole 116, wherein the conductive wall 13j is, for example, a copper layer, a titanium/copper alloy layer or a titanium/copper/titanium alloy layer. When the package substrate is applied to the wafer package, the package substrate 1 may further include solder balls 160. The solder ball 160 may be disposed on one of the first pad 142 or the second pad 152, or may be disposed on the first pad and the second pad 152 at the same time. The material of the solder ball 16 turns is, for example, tin. It is worth noting that since the surface layer _ and the surface layer 1Ma material f can be titanium / record 15 (S ) 200824065 • ------- -2-NEW-FINAL-TW-20061128 / copper alloy Or titanium/nickel hunger/gold alloy, which has the effect of a metal layer such as a ball bottom, and the knife is used as an adhesive layer/barrier layer/wetting layer to enhance the first The bonding effect between the pad 142 and the second pad 152 and the solder ball 160. The method of manufacturing the package substrate 100 will be described below. 2A to 2B are flow charts showing a method of fabricating the package substrate of FIG. 1. What needs to be Newming is that the material and configuration of the following parts are detailed in the above, so I won't repeat them.吞月麦麦耻图2Α to Figure 2Ε, first, as shown in Figure 2Α =^1〇# semiconductor substrate U〇 has a corresponding - d d face it, a younger two surface 114. Next, as shown in Fig. 26_, the hole 116 is formed in the semiconductor substrate u, into the shell 112 and the second surface 114. The above (4) holes 116 are penetrated through the first table® hole, mechanical iron hole or sensation ===., _ Plasma, ICP). 'UC lvely Couplec substrate (10) «Semiconductor The inner wall of the insulating layer (10) is formed as described above. Yi chemical gas accumulation), 妓 _ _ fresh: product (such as plasma to increase the conductor substrate 11G material cut, i + for example, if the surface of the semi-material (10) produces a layer of dioxide, the process is used in the semiconductor base and then As shown in FIG. 2D, the insulating layer 120 is formed on the layer 120. The above-mentioned forming conductive layer 136 is insulative electroplating, etc., and the material thereof may be steel, silver enamel, etc., having plating or no 16 200824065 ~1...2-NEW-FINAL-TW-20061128 Next, as shown in FIG. 2E, an insulating material 丨 34 is filled in the through hole 116, and the first conductive layer 136 in the through hole 116 (ie, the above conductive wall) 132) and the insulating material 134 constitutes a clock through hole structure 13 〇. When the insulating material 134 is filled, the stencii printing method can be used to align the screen and the package substrate 100 first, and then manually on the screen. A large amount of plug hole glue is placed, and a plug hole is coated with a squeegee to form an insulating material 134.

Then, referring to ffi 2F to FIG. 2Q, a first line stack 40 and a second line stack 15G are respectively formed on both sides of the semiconductor substrate iiq, and the first line stack 14G and the second line are laminated. 15() is electrically connected to each other via a mine via structure, wherein the first line laminate has a surface having at least 142' and the second line laminate 15G has at least one second field for convenience of description. The method of layer 150 is only exemplified by the first-layer laminate 14 〇. The method of referring to the invention of the invention is to refer to the method of the invention. The following method can be used to form the first Two line stack 150. More specifically, the first-line stack (10) can be subjected to a step of forming a two-conducting layer j ° U2 (as shown in Fig. 2F). Among them, the taxi, ~ 曰 弟 一 一 一 表面 表面 表面 表面 表面 嫂 嫂 嫂 表面 表面 表面 表面 表面 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 二 二 二 二 二 二 二 2008 2008 2008 2008 2008 2008 2008 2008 2008 Show).

The method of drying the second conductive layer 148 is, for example, first, as shown in FIG. 2G, a patterned mask 17a is applied to the second conductive layer Μ 2G, and the patterned mask 17Ga can be a patterned photoresist layer. Next, the method of performing the second conductive layer 148 on the second conductive layer 148 as shown in the middle of the medium-to-small single-screen 17〇a is, for example, by using a re-environment. Thereafter, as shown in Fig. 21, the pattern Li is shifted: the action of patterning the second conductive layer 148 is completed. #144h... The ordering step (4)' forms a dielectric layer 146 on the inner layer line (shown in Figure 2J). The above method of forming the dielectric layer 146 on the inner layer line S is, for example, coating, printing, or the like. The material of the dielectric layer I46 may be a crucible material such as polyacrylonitrile (P〇1yimide) or the like. Next, step (4) is performed to pattern the dielectric layer 146 to expose the core-patterned wiring layer 144 (as shown in Figures 2K-2P). The method of patterning the dielectric layer 146 is performed, for example, by forming a pattern mask 17Gb' on the dielectric layer 146 and thereby patterning the mask layer to the side of the dielectric layer 146. The actual conversion can be a patterned metal layer, and the material of the patterned metal layer is, for example, Ming. The above method of forming the patterned mask 17b is as shown in Fig. 2κ, and a metal layer mb is formed on the tantalum layer 146. Next, as shown in Fig. 2L, a patterned mask 17cc is formed on the metal layer 172b, and the patterned mask 17c is, for example, a patterned photoresist layer. Then, as shown in Fig. 2M, the metal layer U2b is etched so that the metal layer is formed into a patterned mask 170b. Finally, the removal of the patterned mask 170c as shown in the ' 2N completes the fabrication of the patterned mask 18 200824065 . 2-NEW-FINAL-TW-20061128 Curtain 170b. Thereafter, as shown in FIG. 2A, the dielectric layer 146 is etched by patterning the mask 174, wherein the dielectric layer 146 is dry etched by plasma, for example, by plasma. It is worth noting that the snaps formed in the dielectric layer H6 in this way have vertical side walls. Then, the action of patterning the dielectric layer 146 is completed by removing the patterned mask as shown in Fig. 2P. Through the above steps, an inner wiring layer 144b and a dielectric layer 146 are formed on the semiconductor substrate 11, and then only the above steps are performed, and (a) to (4)' can be used to form the upper patterned circuit layer. (4) 舁 dielectric layer 146. The first wiring stack 14 shown in Fig. 2Q has a plurality of inner wiring layers 144b and two or more dielectric layers. Further, as shown in Fig. 2R, the above steps (&) to (d), the surface wiring layer 144a of the 1-shaped outer layer, and the surface wiring layer - 146 may be repeated. The method for forming the above-mentioned package substrate 100 is as follows: For the convenience of description, the following method for forming the solder ball 160 is to form the solder ball 160 only on the first solder fillet 142. For example, the artisan can apply the method of forming the solder 60 on the first pad 142 to form the solder ball 16 on the second pad 152. The method of forming a ball can include the following steps: First, no, provided on the line-layer stack (10) - the patterned pattern mask 170d has at least one opening σ ^ 煜 μ μ 1 for exposing After the second 'as shown in FIG. 2A, fill a hole 172d with a 19 200824065

AiSbKi332-NEW-FINAL-TW-2〇〇6l 128 Solder 162. Then, solder 162 is reflowed as shown in Fig. 2U to form solder balls 160. Next, remove the patterned mask md as shown in Figure i. The patterned mask 170d can be a patterned photoresist layer. In addition, in the solder 162 "J join help! (not shown), in the step of reflow solder M2, the chemical reaction of 'help_and solder 162' will cause the oxide in the solder (6) to be n贞π to the surface of the solder ball 16G so that the solder ball 16〇 It has a better electrical connection with the crystal # or other components carried by the package substrate 1GG. 1 flux can be rosin-based fluxing water-soluble flux. If the solder 162 is added (4), the removal of the flux after removing the patterned mask may include removing the flux and removing the reaction product of the flux and the solder 162. When the flux and the flux and the solder 162 are removed, for example, HCFC (hydrQehl, magnetic 丽·_) > monthly washing method, replenishing method, or a priori cleaning, water cleaning method, etc. may be used. . The package substrate of the present invention can also be used as the package substrate of the present invention. 3A to 3D are diagrams showing the formation of a hardened dielectric layer on a package substrate according to another embodiment of the present invention. For convenience of explanation, the patterned dielectric layer 146 is formed on the first surface m. For example, the exemplified person can use the method to form the patterned dielectric layer 156 on the second surface ι4. 3A to 3D', in another embodiment of the present invention, the package coating method may be the same as the package substrate 100 method before the step (4), and in the step (c)+, the dielectric layer 146, the material is photosensitive. The material, as shown in FIG. 3A, forms a dielectric layer on the first surface 112. The above method of forming the dielectric layer 146 is, for example, riding cloth or printing. 20 200824065 ^^xvx^2-NEW-FINAL.TW.20〇61128 Down' In step (4), the dielectric layer 146 is patterned by a lithography process. The patterning of the dielectric layer 146 may include the following steps: First, the patterned mask 170c is formed on the dielectric layer 146. < ' As shown in FIG. 3C, the dielectric layer 146 is patterned with a patterned mask 170c. The method of the f layer 146 is, for example, exposed to ultraviolet light and developed. Finally, 3D does not remove the patterned mask (10) to complete the patterned dielectric layer 146. The method for fabricating the package substrate after the step (d) can be the same as the method for fabricating the package substrate (10), and the second embodiment is not described herein. The second embodiment is the second embodiment of the present invention. Schematic diagram of the package base (four). Referring to Fig. 4, in the second embodiment and the first embodiment, the same reference numerals denote the same elements, and the second embodiment is substantially the same as the first embodiment. The differences between the two embodiments will be explained in detail below, and the same points will not be described. The wn sealing substrate comprises an insulating substrate 210, a plated through hole structure 0, a first-line laminate 14A, and a second wiring laminate 15A. The insulating material 210 has a corresponding first surface 212 and a second surface 214, and the insulating substrate 21 has a uniform hole 216 extending through the first surface 212 and the second surface 214. According to the above, the plated through hole structure 130 is disposed in the through hole 216. The first line = stack 140 has been placed on the first surface 212, and the first line stack 14 has a first pad 142 on its surface. The second line stack 15 is disposed on the surface 21 of the second 21 200824065 Λοηινι J J2-NEW-FINAL-TW-20061128, and the surface of the second line stack has a second pad 152, the first line stack The 140 and the second wiring stack 15 are electrically connected to each other via the plated through hole structure 130. The second embodiment is different from the first embodiment in that the package substrate 200 of the second embodiment uses the insulating substrate 210, so that the insulating layer 12 is not required, and the step of forming the insulating layer 120 can be omitted during fabrication. Simplifies the process and structure of the package substrate to improve the reliability of the package and reduce the fabrication rate

In the present embodiment, the insulating substrate 21 may be cerium oxide (SiO 2 ). Hereinafter, the manufacturing process of the package substrate 200 will be described with reference to the drawings. Hereinafter, a method of fabricating the package substrate 200 will be described. 5A to 5M are flowcharts showing a method of fabricating the package substrate of FIG. 4. It should be noted that the materials and configurations of the following components have been disclosed in detail, and therefore will not be repeated. Referring to Figures 5A through 5D, first, as shown in Figure 5A, an insulating substrate 210 is provided. The insulating substrate 21 has corresponding ones - a first 2 and a second surface 2H. Next, as shown in FIG. 5B, a uniform hole 216 is formed in the insulating substrate 210, wherein the through hole 216 extends through the first surface 212 and the second surface 214. The above-mentioned way of forming the through hole 21 (4) is, for example, a laser drill, a mechanical drill or an induction light balance plasma residue. As shown in Fig. 5C, a first conductive layer 136 is formed on the gas substrate 210. The method for forming the first conductive layer 136 may be electroplating, electric ore, etc., and the material thereof may be copper, silver or the like having good electrical conductivity. 22 200824065 3d2-NEW-FINAL-TW-2006 1128 Next, as shown in FIG. 5D, an insulating material 134 is filled in the through hole 216, and the first conductive layer 136 in the through hole 216 (ie, the above conductive wall 132) And the insulating material 134 forms a plated through hole structure 13A. For the method of filling the insulating material 134, refer to the manufacturing method of the above-mentioned package substrate 1 ,, and no further description is made here. Then, referring to FIGS. 5E to 5J, a first wiring layer 140 and a second wiring layer 15 are formed on both sides of the insulating substrate 21, respectively, so that the first wiring layer 140 and the second wiring layer are laminated. 15〇 is electrically connected to each other via a plated through hole structure 13〇, wherein the surface of the first line stack 140 has at least one first pad 142, and the surface of the second line stack 15 has at least one second pad 152. For convenience of description, the following method for forming the first line stack 140 and the second line layer/50 is only described by taking the first line stack 14〇 as an example, and those skilled in the art refer to the disclosure of the present invention. When it is possible to form a first line stack 140, the method should be a bribe-shaped wire line stack 15 〇. In detail, the first line stack 140 can be formed by the following steps. Step U) is performed to form - the second conductive layer 148 is not on the first surface. Next, step (b) is performed to pattern the second green to form a patterned wiring layer 144. Taking the first line stack (10) having a plurality of patterned I" 4 and dielectric layers 146 as an example, at this time 144 [, the patterned circuit layer 144 is, for example, lost as an inner layer circuit layer", + 5F). The above method of arranging the second conductive layer 148 can be "the method of making the substrate touch of the county, and no further description is made here. The layer 'top step (t formation - dielectric layer 146 back to the inner layer line). The dielectric layer 146 is formed on the inner layer line 23 200824065 ^.NEW.FINAL-TW-20061128

The method on the J layer 144b is, for example, coating, printing, or the like. The material of the dielectric layer 146 may be an organic material such as polyimide or the like. Next, performing step U, the dielectric layer 146 is patterned to expose a portion of the patterned wiring layer 144 (as shown in Figure 5H). For the method of patterning the dielectric layer 146, reference may be made to the above package substrate. By the above steps, an inner layer „ 1 her and the dielectric layer M6 have been formed on the insulating substrate 210, and then only the above steps u) to (4) are repeated, and the upper patterned circuit can be formed one after another. The layer 144 and the dielectric layer 146. The first wiring layer 140 shown in Fig. 51 has two or more inner wiring layers 144b and two or more dielectric layers (10). Further, as shown in Fig. 5J, The above steps are repeated ((1), the outermost surface layer 144a is formed, and the surface layer is covered by the electrical layer 146°, wherein the surface layer has, for example, a plurality of pads 142. L: Referring to FIG. 5K to FIG. 5, the above-mentioned package substrate 2 is used as a solder ball 16 〇. For convenience of description, the following forms a solder ball 1 (9) pad 142 to form a ball 160 as an example, cooked,: The method of forming _160 on the "'烊塾142 can be applied to the formation of the spheroid 160 on the second pad 152. The method of forming the solder ball 16. The τ column step can be included. First, as shown in Fig. 5 A patterned mask 170d is provided on the first line stack 140, and the back woodized mask 170d has at least one opening 172. d, for violent, a solder pad 142. Thereafter, as shown in Fig. 5L, a 24 200824065 Λοηινι ^ ji-NEW-FINAL-TW-20061128 solder 162 is filled in the opening coffee. Then, as shown in Fig. 5M The solder 162 is reflowed to form the solder ball 160. Next, the patterned mask 17d is removed, as shown in Fig. 4. The details of the method of forming the solder ball 16G can be referred to the mounting substrate. The manufacturing method is not described here. The 'encapsulated substrate of the present invention uses the material of the conductor substrate as the core (_), so that when the chip is packaged, the package substrate and the package can be reduced. The difference between the bulging of the lining between the wafers, and thus the reliability of the package Ϊ 2 2 2 invention can directly use the Er 2 Shouxian substrate with the appropriate thermal expansion coefficient to omit the formation of the insulating layer on the semi-conducting materials 4 The production cost of the low-counter substrate is exemplified. The π-Γΐΐ invention has been disclosed above in the preferred embodiment, but it is not used in any technical field, and it is not in the spirit! More movements and retouching, whichever is the case. [Description of the scope of the patent application] [Simplified description of the drawings] = the schematic diagram of the package substrate of the present invention. The flow chart of the method for fabricating the substrate is formed. The flow of the patterned dielectric layer is invented. Another embodiment of the package substrate shape of the second embodiment of the county substrate coffee diagram. [Main components = say ^] Figure 4 of the field of the production of the flow chart. 1〇〇: package substrate 25 110: semiconductor substrate 112: First surface 114: second surface 116: through hole 120: insulating layer 130: plated through hole structure 132: conductive wall 134: insulating material 136: first conductive layer 140: first wiring layer 150: second wiring layer 142: first pad 152: second pad 144, 154: patterned wiring layer 144a, 154a: surface wiring layer 144b, 154b: inner wiring layer 146, 146', 156, 156': dielectric layer 148, 158 : second conductive layer 160 : solder balls 162 : solders 170 a , 170 b , 170 c , 170 c , 170 d : patterned mask 172 b · metal layer 172 d : opening 200 : package substrate 210 : insulating substrate 26

Claims (2)

200824065 ^οι^ινι ^ j2-NEW-FINAL-TW-20061 128 X. Patent application scope: 1. A package substrate, comprising: a surface, and having a corresponding - first surface and - second table at least: Between the first surface and the second surface surface and the first surface of the semiconductor substrate, the second surface: the second plating: F upper structure, disposed in the through hole; And the second layer is disposed on the insulating layer above the first surface, and the second layer of the green layer is a first green pad; and the first and second pads are formed; 'Arranged on the insulating layer above the second surface, and the second, the line stack surface line stack and the second line stack two brother - 9 'by the bite Zhou, the field of the plated through hole structure Mutual conduction. 2. The stencil of the stencil of the stencil of the stencil of the second line and/or the layer of the slab of the second line and the at least one dielectric layer are superposed. ^目木化线3. As in the scope of the patent application, item 2 - the patterned circuit layer includes - the surface layer layer board, the at least 4 · as in the third line of the patent application scope, such as: 合金 alloy layer or The missing/nickel gold layer of the fm item f 3 Kawasaki Prefecture, wherein the at least the circuit layer further includes at least the inner layer circuit layer. The circuit layer is as described in the package substrate of the fifth item, wherein The inner layer comprises a copper layer, a titanium 7 copper alloy layer or a titanium/copper/titanium alloy layer. 27 200824065 j2-NEW-FINAL-TW-20061 128 7. As claimed in the second item of the special purpose item, The material of the dielectric layer includes organic materials. • 8. Please refer to the package substrate described in item 7 for the purpose of the dielectric layer. The material of the layer includes polyimine. The package substrate, wherein the keyhole structure comprises: a conductive wall disposed on the insulating layer on the inner wall of the through hole; and an insulating material filled in the through hole. 9. The package substrate of claim 9, wherein the conductive wall comprises a copper layer, a titanium/copper alloy layer or The package substrate according to the above-mentioned claim, wherein the material of the semiconductor substrate comprises a stone substrate. The material of the insulating layer includes the oxidized stone. 13. The package substrate as described in claim 1-3, further comprising at least one solder ball disposed on the first pad and/or the second pad. A package substrate comprising: an insulating substrate having a corresponding first surface and a second surface® and having at least a consistent aperture therethrough through the first surface and the second surface; a chain through-hole structure disposed in the through hole; a first line stack of the first line disposed on the first surface, and the surface of the first line has at least one first pad; and a second line Laminated, disposed on the second surface, and the second line 28 200824065 A fox liNEW-FINAL-TW-ZOi^l 128-way laminated surface has at least one first-悝埶兮荣^u田^一乐一Know the pad, the brother of a line laminate with the first line The package substrate according to Item 14, wherein the material of the insulating substrate comprises cerium oxide (si02). Please fully cover the package substrate of the 14th item, wherein the second And/or the second circuit stack is respectively formed by at least a patterned circuit layer and at least one dielectric layer. The package substrate according to claim 16, wherein the at least one pattern The circuit board layer comprises a surface layer. 18. The package substrate of claim 17, wherein the surface circuit layer comprises a titanium/nickel vanadium/copper alloy layer or a titanium/nickel vanadium/gold alloy layer. The package substrate of claim 17, wherein the at least one patterned circuit layer further comprises at least one inner wiring layer. 20. The package substrate of claim 19, wherein the inner wiring layer comprises a copper layer, a titanium/copper alloy layer or a titanium/copper/titanium alloy layer. 21. The county substrate as described in claim 16, wherein the material of the dielectric layer comprises an organic material. The package substrate of claim 21, wherein the material of the electrical layer comprises polyimine. The package substrate of the invention of claim 14, wherein the conductive wall is disposed on the insulating layer of the inner wall of the through hole; and an insulating material is filled in the through hole. The package substrate according to claim 23, wherein the guide wall 2008 20086565 ASbK n^2-NEW-FINAL-TW-20061128 the electric wall comprises a copper layer, a titanium/copper alloy layer or a titanium/copper/titanium alloy Floor. The package substrate of claim 14, further comprising at least one solder ball disposed on the first pad and/or the second pad. A method for fabricating a package substrate, comprising: providing a semiconductor substrate having a corresponding first surface and a second surface; forming a through hole in the semiconductor material of the semiconductor material The through hole penetrates the first surface and the second surface; forming an insulating layer covering the first surface of the semiconducting county line, the first surface and the inner wall of the through holes; forming a conductive layer On the insulating layer; "insulating material f is in the through hole, the through hole (4) the first conductive layer and the insulating material form a plated through hole structure 丨 and respectively form a first line stacking plate and a conductor substrate On both sides, the _th line=-the line-rich layer is electrically connected to each other by the through-hole structure of the mine, and the second line is laminated via the ^-die-weld' and the second line is laminated 27 · The method of claim 26, wherein the through hole is formed in the semi-conducting y j package substrate. (4) Substrate towel (4) pure laser drill 28 · as in the patent application range % method, wherein the The method of the insulating layer, the thermal oxidation process of the package substrate of the Xunxun. The semiconductor substrate is carried out according to the method of claim 26, wherein the sealing method described in claim 26, wherein the first-line laminate and/or the board are formed. The method includes: a method of flying a child-line stacking U) forming a second conductive layer on the semi-conductive (8) patterning the second conductive layer, j-side; (4) forming a dielectric layer on the patterned patterning (4) patterning the dielectric layer; on the layer; and layer. Christine Road out part of the patterned circuit method, 苴中开t into ^^ commits the package substrate described in item 29 The method includes the steps of: repeating the steps (4) to (4) at least one time; and the method for patterning the second layer of the package substrate of the package substrate according to claim 29 of the patent scope of claim 29, comprising: providing a patterned mask On the second conductive layer, the patterned mask removes the patterned mask from the second guide. The method of producing a sealing substrate according to the item 31 of the St. Patent No. 31, and the patterned mask comprises a patterned photoresist layer. 33. As described in claim 32, the method of borrowing, 34 Γ Γ 专利 专利 专利 专利 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 ® ® ® ® ® ® ® The mediation process includes performing a lithography process on the dielectric layer. (s) 31 200824065 ASEKl 552-NEW-FINAL-TW-20061128., 3=I: A method of fabricating a package substrate according to claim 29, wherein the method of wooding the dielectric layer comprises: providing A patterned mask is disposed on the dielectric layer; the dielectric layer is performed by the patterned mask to remove the patterned mask. The method of fabricating the package substrate of the method of claim 35 includes a patterned metal layer. The package substrate described in item 36 of the Farley range is manufactured by the material pool of the patterned metal layer. :3=In the production of the package substrate described in Item 35 of the patent scope, the method of manufacturing the dielectric layer includes (4) plasma processing of the dielectric layer, and the preparation of the 26th Lai Xuxian silk =. The method further includes forming at least one soldering method on the solder-on-weld and/or the second soldering pad, wherein the package substrate is fabricated or the second Wei (four) is provided with a picture= !=== having, at least, exposing a solder to the opening; reflowing the solder to form at least one solder ball; and removing the patterned mask. For example, the manufacturer of the package substrate described in the scope of application of the patent scope 32 200824065 332-NEW-FINAL-TW-20061128 Method 'The                     42. The sealing method of claim 4, wherein the solder contains a helper (four)', and after removing the ^^, further comprising removing the flux, and removing the station 2θ wood mask The reaction product. A method for fabricating a package substrate from the transfer, comprising: providing a surface to a second surface-insulating substrate, wherein the insulating substrate has a corresponding first surface, wherein the a hole penetrating the first forming-first conductive layer covering the first surface of the semiconductor substrate, the second surface and the inner walls of the through holes; filling an insulating material in the through hole, the first in the through hole a lead layer and the insulating material form a plated through hole structure; and a finely divided-first-scale stack and a second layer laminated on both sides of the insulating substrate to make the first line stack and the The second line stacker is electrically connected to each other by the plated through hole structure, wherein the first line stack surface has at least one first pad, and the second line stack surface has at least one second turn. The method of fabricating the package substrate of claim 43, wherein the method of forming the through hole in the insulating substrate comprises laser drilling. The method of fabricating a package substrate according to claim 43, wherein the material of the insulating substrate comprises sulphur dioxide. 46. The manufacturer of the package substrate as described in claim 43. 200824065 ASEK1552-NEW-FINAL-TW-20061128 The outer layer and/or the old method, wherein the formation comprises z ((blfi two fr conductive layer) At least 1; "two conductive layers" of the insulating substrate to form a "patterned line" (C) I into -, an electrical layer in the patterned circuit layer, a layer. (4) patterning the dielectric layer In order to expose the portion; the patterned circuit method, the manufacturer of the sealing plate as described in item 46 of the ^^^, further includes the method of co-reinforcing the layer, the production of the sealing plate described in the item The method of arranging the conductive layer - the conductive layer comprises: ί providing a patterned mask on the second conductive layer; hunting by the patterned mask removes the patterned mask from the second guide. (d), Μ and the law, 494: It is the fabrication of the cracked substrate described in item 48. The mask is made of -ffi. The 5::: the crack described in the 49th patent. The method of fabricating the second conductive layer comprises: wet etching the second conductive layer by a side liquid. The fabrication substrate of the package substrate described in item (8) is formed of a photosensitive material to form the dielectric layer, and the method of patterning the dielectric layer includes performing a lithography process on the dielectric layer. The method for fabricating a package substrate according to item 46 of the patent scope is disclosed in the method of 2008. s. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; Shielding the dielectric layer; etching the dielectric layer by the patterned mask; and removing the patterned mask. Method 53. Making a package substrate as described in claim 52 The method of fabricating a package substrate according to claim 53, wherein the material of the patterned metal layer comprises aluminum. The method for fabricating the package substrate of the package substrate of the above-mentioned item 52 includes dry dielectric etching of the dielectric layer by means of (4) mounting. Forming a ball of the sealing substrate on the first soldering pad and/or the second bonding pad At least one welding 5=the manufacturing method of the package substrate according to the item 5% of the patent application, the method for forming the croquet in the eighth method comprises: providing a picture on the line stack and/or the second line stack The patterned mask has at least an opening for exposing the mat and/or the second pad; filling a solder in the opening; reflowing the solder to form at least a solder ball; In addition to the patterned mask, the method of fabricating the package substrate of claim 57, wherein the patterned mask comprises a patterned photoresist layer. 35 200824065 J J2-NEW-FINAL-TW-20061128 59. The reaction product of the patterned mask is removed as described in the preparation of the package substrate 2: flux '. ...the agent' and the removal of the flux and the solder 36