WO2023231106A1 - 像素驱动电路和显示面板 - Google Patents

像素驱动电路和显示面板 Download PDF

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Publication number
WO2023231106A1
WO2023231106A1 PCT/CN2022/101521 CN2022101521W WO2023231106A1 WO 2023231106 A1 WO2023231106 A1 WO 2023231106A1 CN 2022101521 W CN2022101521 W CN 2022101521W WO 2023231106 A1 WO2023231106 A1 WO 2023231106A1
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WIPO (PCT)
Prior art keywords
transistor
boost
electrically connected
gate
voltage
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Application number
PCT/CN2022/101521
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English (en)
French (fr)
Inventor
胡亮
Original Assignee
Tcl华星光电技术有限公司
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Publication of WO2023231106A1 publication Critical patent/WO2023231106A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to the field of display panel manufacturing technology, and specifically to pixel driving circuits and display panels.
  • the light-emitting elements in self-luminous displays are current-driven, that is, the brightness of the light depends on the current flowing through the light-emitting element.
  • the luminous brightness of the light-emitting element is generally adjusted by adjusting the data voltage, and the gate-source voltage of the driving transistor does not change during the light-emitting stage, that is, the luminous brightness of the light-emitting element cannot be changed.
  • Embodiments of the present application provide a pixel driving circuit and a display panel to solve the technical problem that existing self-luminous displays have low luminous brightness due to the hardware influence of data driving chips.
  • Embodiments of the present application provide a pixel driving circuit, including:
  • a driving transistor is connected in series with the light-emitting element between the first power line and the second power line, and the source of the driving transistor is electrically connected to the light-emitting element;
  • the source of the data transistor is electrically connected to the data line
  • the drain of the data transistor is electrically connected to the gate of the driving transistor
  • the gate of the data transistor is loaded with a data control signal
  • a boost module the input end of the boost module is used to load a boost input signal, and the output end of the boost module is electrically connected to the gate of the drive transistor;
  • the boost module controls the gate of the driving transistor to rise from the first voltage in the first stage to the second voltage in the second stage, and the second stage is located after the first stage, and the The driving transistor is used to generate a driving current according to the second voltage to drive the light-emitting element to emit light.
  • the present application provides a pixel driving circuit and a display panel.
  • the pixel driving circuit includes: a driving transistor connected in series with a light-emitting element between a first power line and a second power line.
  • the source of the driving transistor is electrically connected to the light-emitting element.
  • the module controls the gate of the driving transistor to rise from the first voltage in the first stage to the second voltage in the second stage.
  • the second stage is located after the first stage.
  • the driving transistor is used to adjust the voltage according to the first stage.
  • the second voltage generates a driving current to drive the light-emitting element to emit light.
  • this application provides a boost module with an input end loaded with a boost input signal, and the output end of the boost module is electrically connected to the gate of the drive transistor, so as to modulate the gate voltage of the drive transistor to a level that can be changed by the first voltage.
  • the voltage rises to the second voltage, thereby increasing the driving current flowing through the light-emitting element to increase the brightness of the light-emitting element, thereby increasing the brightness of the display panel.
  • FIG. 1 is a circuit diagram of a first pixel driving circuit provided by an embodiment of the present application.
  • FIG. 2 is a circuit diagram of a second pixel driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a circuit diagram of a third pixel driving circuit provided by an embodiment of the present application.
  • FIG. 4 is a circuit diagram of a fourth pixel driving circuit provided by an embodiment of the present application.
  • FIG. 5 is a circuit diagram of a fifth pixel driving circuit provided by an embodiment of the present application.
  • FIG. 6 is a circuit diagram of a sixth pixel driving circuit provided by an embodiment of the present application.
  • Figure 7 is a waveform diagram of some signals provided by the embodiment of the present application.
  • first”, “second”, “third”, etc. in this application are used to distinguish different objects, rather than describing a specific sequence.
  • the terms “including” and “having” and any variations thereof are intended to cover non-exclusive inclusion.
  • the terms “source” and “drain” can be used interchangeably, as long as the corresponding transistor has at least one source and at least one drain.
  • a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally also includes steps or modules that are not listed, or optionally also includes Other steps or modules inherent to such processes, methods, products or devices.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Embodiments of the present application provide a pixel driving circuit, which includes but is not limited to the following embodiments and combinations of the following embodiments.
  • the pixel driving circuit 100 includes: a driving transistor T1 connected in series with the light-emitting element L between the first power line and the second power line.
  • the driving transistor T1 The source S of the data transistor T4 is electrically connected to the light-emitting element L; the data transistor T4 has a source electrically connected to the data line, and a drain of the data transistor T4 is electrically connected to the driving transistor T1
  • the gate G, the gate of the data transistor T4 is loaded with the data control signal Scan; the boost module 10, the input end of the boost module 10 is loaded with the boost input signal CK, and the output of the boost module 10
  • the terminal is electrically connected to the gate G of the driving transistor T1; wherein the boost module controls 10 the gate G of the driving transistor T1 to rise from the first voltage Vg1 of the first stage to the second The second voltage Vg2 of the stage is located after the first stage.
  • the driving transistor T1 is used to generate a driving current according to the second voltage Vg2
  • the first power line can be loaded with the first signal VSS
  • the second power line can be loaded with the second signal VDD.
  • the magnitude of the first signal VSS and the magnitude of the second signal VDD can be two respectively.
  • the voltage value corresponding to the first signal VSS may be smaller than the voltage value corresponding to the second signal VDD.
  • the driving transistor T1 may be an N-type transistor or a P-type transistor
  • the light-emitting element L may be, but is not limited to, an organic light-emitting semiconductor, a light-emitting diode, a micro-light-emitting diode, or a sub-millimeter light-emitting diode.
  • the driving transistor T1 is an N-type transistor as an example. Based on the above discussion, the drain D of the driving transistor T1 can be electrically connected to the second power line to be loaded.
  • the second signal VDD, the source S of the driving transistor T1 can be electrically connected to the anode of the light-emitting element L, and the cathode of the light-emitting element L can be electrically connected to the first power line to be loaded with the first signal VSS, such as the first signal VSS
  • the corresponding voltage value may be 0 volts, that is, the cathode of the light-emitting element L may be grounded.
  • the gate-source voltage Vgs between the gate G of the driving transistor T1 and the source S of the driving transistor T1 drives the light-emitting element L to emit light.
  • the driving transistor T1 When the driving transistor T1 is turned on, the first signal Under the action of VSS and the second signal VDD, a driving current flowing to the light-emitting element L can be generated, wherein the magnitude of the driving current is positively correlated with the gate-source voltage Vgs between the gate G of the driving transistor T1 and the source S of the driving transistor T1 , and the voltage loaded to the gate G of the driving transistor T1 can generally be determined according to the voltage value corresponding to the expected gray scale of the light-emitting element L, that is, it can be considered that the voltage value corresponding to the expected gray scale of the light-emitting element L determines the flow to the light-emitting element L
  • the size of the driving current determines the luminance of the light-emitting element L.
  • the source voltage Vs of the source S of the driving transistor T1 can be a relatively stable value, that is, it can be considered that this
  • the luminance of the light-emitting element L can be determined by the gate voltage Vg of the gate G of the driving transistor T1.
  • the gate voltage Vg applied to the gate G of the driving transistor T1 can generally be determined by the gate voltage Vg of the gate G of the driving transistor T1.
  • the voltage value corresponding to the expected gray scale is determined.
  • the boost module 10 is provided, and the input terminal of the boost module 10 is loaded with the boost input signal CK, and the output terminal of the boost module 10 is electrically connected to the gate G of the driving transistor T1.
  • the gate voltage Vg of the gate G of the driving transistor T1 can also be determined by the boost input signal CK; in the first stage, the gate G of the driving transistor T1 has the first voltage Vg1, combined with the above discussion , the first stage here can be considered as the "light-emitting stage" mentioned above, and the first voltage Vg1 can be at least determined by the voltage value corresponding to the expected gray scale of the light-emitting element L, which is loaded to the gate of the driving transistor T1 Determined by the voltage of electrode G, further, in this embodiment, the boost module 10 is configured to control the gate G of the driving transistor T1 to have a second voltage Vg2 related to the boost input signal CK in the second stage.
  • the second voltage Vg2 is greater than the first voltage Vg1.
  • the second stage here can be considered to be after the first stage, that is, the gate voltage Vg of the driving transistor T1 can be changed from the first voltage Vg1 under the action of the boost module 10 and the boost input signal CK. rises to the second voltage Vg2, thereby increasing the driving current flowing through the light-emitting element L to increase the luminous brightness of the light-emitting element L.
  • the specific structure of the boost module 10 and the waveform of the boost input signal CK can be reasonably set according to the actual situation, so as to better improve the luminous brightness of the light-emitting element L.
  • the boost module 10 includes: a first capacitor C1 , the first plate of the first capacitor C1 is electrically connected to all terminals of the drive transistor T1
  • the gate G serves as the output terminal of the boost module 10; a first boost transistor T2, the drain of the first boost transistor T2 is electrically connected to the second electrode of the first capacitor C1 board, the source of the first boost transistor T2 is electrically connected to the input end of the boost module 10, the gate of the first boost transistor T2 is loaded with the first boost control signal, and the The first boost transistor T2 is turned on in both the first phase and the second phase; wherein the boost input signal CK has a first boost input voltage Vcl in the first phase, and the boost input The signal CK has a second boost input voltage Vch in the second stage, and the second boost input voltage is greater than the first boost input voltage.
  • the first boost transistor T2 may be an N-type transistor or a P-type transistor.
  • the first boost transistor T2 is an N-type transistor and the second plate of the first capacitor C1 is electrically connected to the node A for illustration.
  • the gate of the first boost transistor T2 can be electrically connected to the gate G of the driving transistor T1 to obtain the gate voltage Vg of the gate G of the driving transistor T1 as the first boost control.
  • the gate voltage Vg of the gate G of the driving transistor T1 has a larger first voltage Vg1 to turn on the driving transistor T1, which can also be considered to turn on the first Boost transistor T2, so that the boost input signal CK is loaded to the second plate of the first capacitor C1 through the first boost transistor T2, so that the voltage of node A is equal to the first boost input voltage Vcl.
  • the first boost transistor T2 can still be driven to turn on by the gate voltage Vg of the gate G of the driving transistor T1, so that the boost input signal CK is loaded to the second voltage of the first capacitor C1 through the first boost transistor T2.
  • the plate is configured so that the voltage of node A is equal to the second boosted input voltage Vch, that is, the change value ⁇ Va of the voltage of node A can be positively correlated with (Vch-Vcl), or even equal to (Vch-Vcl).
  • the change value of the gate voltage Vg of the gate G of the driving transistor T1 electrically connected to the first plate of the first capacitor C1 is also positively correlated with (Vch-Vcl), or even equal to (Vch -Vcl), so that the gate voltage Vg of the gate G of the driving transistor T1 rises from the first voltage Vg1 to the second voltage Vg2, thereby increasing the driving current flowing through the light-emitting element L to increase the luminous brightness of the light-emitting element L.
  • the gate of the first boost transistor T2 can also be electrically connected to the boost control line to be loaded with the first boost control signal.
  • the first boost control signal can be but is not limited to lighting control.
  • Signal EM in which the waveform of the signal transmitted on the boost control line can be the same or different from the waveform of the gate voltage Vg of the gate G of the driving transistor T1, as long as the first stage and the second stage can be controlled.
  • the boost transistor T2 can be turned on.
  • the specific principle of the gate voltage Vg of the gate G of the driving transistor T1 can be the same as the above "The gate of the first boost transistor T2 can be electrically connected to the gate of the driving transistor T1 The principle of action of the gate G" on the gate voltage Vg of the gate G of the driving transistor T1.
  • the boost module 10 further includes: a second boost transistor T3, the drain of the second boost transistor T3 is electrically connected to the first The source of the boost transistor T2 and the source of the second boost transistor T3 are electrically connected to the input terminal of the boost module 10 , and the gate of the second boost transistor T3 loads the third Two boost control signals, the second boost transistor T3 is turned on in both the first phase and the second phase; wherein, the gate of the first boost transistor T2 is electrically connected to the Said gate G of drive transistor T1.
  • the gate of the first boost transistor T2 can be electrically connected to the gate G of the driving transistor T1 to obtain the gate voltage Vg of the gate G of the driving transistor T1 as the first boost "Control signal”
  • this embodiment is equivalent to adding a second boost transistor T3 whose opening is controlled by the second boost control signal and is connected in series between the input end of the boost module 10 and node A.
  • the second boost control signal may be, but is not limited to, a lighting control signal (such as a lighting control signal EM) generated by a lighting control circuit. That is, it can be considered that the first boost control signal and the second boost control signal jointly determine the boost input signal CK.
  • the second boost control signal and the second boost transistor T3 can also further control whether the boost input signal CK can be loaded to node A, thereby improving the accuracy of the operation of the boost module 10 .
  • the pixel driving circuit 100 further includes: a second capacitor C2, the first plate of the second capacitor C2 is electrically connected to the first capacitor C1 The second plate of the second capacitor C2 is electrically connected to the source S (as shown in Figure 4) or the drain D (as shown in Figure 5) of the driving transistor T1. Show).
  • the first capacitor C1 and the second capacitor C2 is connected in series between the gate G and the source S of the driving transistor T1, or between the gate G and the drain D of the driving transistor T1.
  • the gate G of the driving transistor T1 switches from loading the first voltage Vg1 to In the floating state, since the voltage difference between the two ends of the first capacitor C1 and the second capacitor C2 cannot suddenly change, the change in the gate voltage Vg of the gate G of the driving transistor T1 is equal to the voltage of the gate G of the driving transistor T1.
  • the change amount or the change amount of the voltage of the drain D in particular, within a period of time, when the change amount of the voltage of the gate G or the change amount of the voltage of the drain D of the driving transistor T1 is 0, it can be considered that
  • the gate voltage Vg of the gate G of the driving transistor T1 may be maintained equal to the first voltage Vg1.
  • the first plate based on the second capacitor C2 is electrically connected to the second plate of the first capacitor C1, and the second electrode of the second capacitor C2
  • the plate can also be set to ground to maintain the voltage of the second plate of the second capacitor C2 unchanged, so that the gate voltage Vg of the gate G of the driving transistor T1 can also be maintained equal to the first voltage Vg1; or, different from In the above embodiment, the second capacitor C2 can also be connected in series between the gate G of the driving transistor T1 and the ground. Similarly, since the second capacitor C2 is connected to the ground, the gate voltage Vg of the gate G of the driving transistor T1 can also be maintained as is equal to the first voltage Vg1.
  • the boost module 10 further includes: a third capacitor C3; a boost switch K, which is connected in series with the third capacitor C3 to the gate of the driving transistor T1. G and the source S of the driving transistor T1; wherein, in the first phase and the third phase before the first phase, the boost switch K is turned on to control the driving transistor
  • the gate G of T1 rises from the third voltage Vg3 of the third stage to the first voltage Vg1 of the first stage.
  • the gate G of the driving transistor T1 has the first voltage Vg1.
  • the first stage can be considered as the "light-emitting stage” mentioned above, and the first voltage Vg1 can be at least determined by "according to The voltage value applied to the gate G of the driving transistor T1 is determined by the voltage value corresponding to the expected gray scale of the light-emitting element L. That is, the first voltage Vg1 can be considered to be related to the voltage of the source S of the driving transistor T1.
  • the boost module 10 is also configured so that in the third stage, the gate G of the driving transistor T1 has the third voltage Vg3.
  • the third stage can be understood as the data writing stage before the light-emitting stage, that is, The third voltage Vg3 may be equal to the voltage loaded to the gate G of the driving transistor T1 "determined according to the voltage value corresponding to the expected gray scale of the light-emitting element L".
  • the source S of the driving transistor T1 has a lower voltage.
  • the voltage of the source S of the driving transistor T1 increases.
  • the driving The gate voltage Vg of the gate G of the transistor T1 can also be increased from the third voltage Vg3 to the first voltage Vg1, thereby increasing the driving current flowing through the light-emitting element L to increase the luminous brightness of the light-emitting element L.
  • the change amount of the gate voltage Vg of the gate G of the driving transistor T1 is related to the voltage of the source S of the driving transistor T1, specifically to the source S of the driving transistor T1.
  • the voltage in the third stage is related to the difference between the first stage.
  • the boost switch K in this embodiment can at least be closed in the third stage and the first stage so that the third capacitor C3 is electrically connected to the gate G and source of the driving transistor T1 between the electrodes S, so that the gate voltage Vg of the gate G of the driving transistor T1 changes following the change of the source voltage Vs of the source S of the driving transistor T1, and is turned off in the second stage to avoid the
  • the change in the gate voltage Vg of the gate G causes the source voltage Vs of the source S of the driving transistor T1 to change synchronously, causing the gate-source voltage Vgs to be unable to rise, so that the driving current flowing through the light-emitting element L cannot be increased.
  • the pixel driving circuit 100 further includes a reset transistor T5.
  • the source of the reset transistor T5 is electrically connected to the reset line, and the drain of the reset transistor T5 is electrically connected to the reset line.
  • the reset transistor T5 is electrically connected to the source of the driving transistor T1, and the reset control signal Sense Gate is loaded on the gate of the reset transistor T5.
  • the pixel driving circuit 100 in this application may include the boost module 10 and the driving transistor T1 as described above, and may further include a data writing module and a reset module electrically connected to the driving transistor T1.
  • the data writing module can be electrically connected to one of the gate G and the source S of the driving transistor T1
  • the reset module can be electrically connected to the other of the gate G and the source S of the driving transistor T1.
  • the data writing module is electrically connected to the gate G of the driving transistor T1
  • the reset module is electrically connected to the source S of the driving transistor T1
  • the data writing module includes the data transistor mentioned above.
  • T4 the reset module includes the reset transistor T5 mentioned above as an example.
  • the pixel driving circuit 100 may include a 3T1C circuit composed of a driving transistor T1, a data transistor T4, a reset transistor T5 and a second capacitor C2.
  • the circuits included in the pixel driving circuit 100 are not limited to 3T1C circuits, and may also include, for example, 6T1C circuits, 7T1C circuits, or other circuits.
  • the data control signal Scan can control the data transistor T4 to turn on at least in the third stage, so that the data signal Data on the data line is loaded to the gate G of the driving transistor T1 to Turning on the driving transistor T1
  • the reset control signal Sense Gate can control the reset transistor T5 to turn on at least in the stage before the third stage, so that the reset signal Vref on the reset line is loaded to the source S of the driving transistor T1 to reset the source of the driving transistor T1.
  • Embodiments of the present application provide a display panel, including a pixel driving circuit.
  • the pixel driving circuit includes: a first transistor connected in series with a light-emitting element between a first power line and a second power line.
  • the source of the first transistor Electrically connected to the light-emitting element, the gate-source voltage between the gate of the first transistor and the source of the first transistor drives the light-emitting element to emit light; the second transistor, the second transistor
  • the source of the second transistor is electrically connected to the first signal line, the drain of the second transistor is electrically connected to the gate of the first transistor, and the gate of the second transistor is electrically connected to the second signal line. line;
  • a first module the input terminal of the first module is electrically connected to the third signal line, the output terminal of the first module is electrically connected to the gate of the first transistor, the first The control terminal of the module is electrically connected to the fourth signal line.
  • the first transistor in this embodiment can refer to the above description about the driving transistor T1
  • the second transistor can refer to the above description about the data transistor T4
  • the first module Reference may be made to the relevant description of the boost module 10 above.
  • the first signal line may be the data line mentioned above
  • the second signal line may be loaded with the data control signal Scan mentioned above
  • the third signal line may be loaded with the data control signal Scan mentioned above.
  • the boost input signal mentioned above may be loaded
  • the fourth signal line may be loaded with at least one of the first boost control signal and the second boost control signal mentioned above.
  • the first module includes: a first capacitor, a first plate of the first capacitor is electrically connected to the gate of the driving transistor to serve as the first module. Output terminal; a third transistor, the drain of the third transistor is electrically connected to the second plate of the first capacitor, and the third transistor is electrically connected to the input terminal of the first module , the gate of the third transistor is electrically connected to the fourth signal line.
  • the third transistor in this embodiment may refer to the above related description of the first boost transistor T2. Based on this, the fourth signal line may be loaded with the above-mentioned third transistor. A boost control signal.
  • the first module further includes: a fourth transistor, a drain of the fourth transistor is electrically connected to the drain of the third transistor, and a source of the fourth transistor is electrically connected to the drain of the third transistor. is electrically connected to the input end of the first module, and the gate of the fourth transistor is electrically connected to a fifth signal line that is different from the gate of the driving transistor; wherein, the third transistor The gate electrode is electrically connected to the gate electrode of the driving transistor.
  • the fourth transistor in this embodiment can refer to the above related description of the second boost transistor T3. Based on this, the fourth signal line is directly connected to the driving transistor.
  • the gate can be loaded with a first boost control signal, and the fifth signal line can be loaded with a second boost control signal.
  • the pixel driving circuit further includes: a second capacitor, the first plate of the second capacitor is electrically connected to the second plate of the first capacitor, the second capacitor The second plate is electrically connected to the source or drain of the first transistor.
  • the first module further includes: a third capacitor; a first switch, which is connected in series with the third capacitor to the gate of the first transistor and the source of the first transistor. between the poles; wherein, in the first stage and the third stage located before the first stage, the first switch is turned on to control the gate of the first transistor by the third stage.
  • the third voltage rises to the first voltage of the first stage.
  • the third capacitor in this embodiment may refer to the above description about the third capacitor C3
  • the first switch may refer to the above description about the boost switch K.
  • it further includes: a fifth transistor, the source of the fifth transistor is electrically connected to the sixth signal line, and the drain of the fifth transistor is electrically connected to the first transistor.
  • the source electrode and the gate electrode of the fifth transistor are electrically connected to the seventh signal line.
  • the fifth transistor in this embodiment may refer to the relevant description of the reset transistor T5 above.
  • the sixth signal line may be the reset line mentioned above.
  • the seven signal lines can load the reset control signal Sense Gate.
  • Embodiments of the present application provide a driving method, as shown in FIGS. 1 to 6 , for driving the pixel driving circuit 100 as described in any one of the above, including: in the first stage, according to the operation of the driving transistor T1
  • the source voltage Vs of the source S configures the boost input signal CK; through the boost input signal CK and the boost module 10, the gate G of the driving transistor T1 is controlled to have the same voltage as the boost input signal CK.
  • a second voltage Vg2 related to the input signal CK is applied, and the second voltage Vg2 is greater than the first voltage Vg1 that the gate of the driving transistor T1 has in the first stage.
  • the size of the driving current flowing through the light-emitting element L is positively correlated with the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1.
  • the first stage is the light-emitting stage, and in the subsequent light-emitting element During the process of L emitting light, it can be considered that the source voltage Vs of the source S of the driving transistor T1 is approximately equal to its voltage in the first stage. Therefore, in this embodiment, in the first stage, the source voltage Vs of the source S of the driving transistor T1 is The voltage Vs configures the boost input signal CK such that the second voltage Vg2 is based on the source voltage Vs of the source S of the driving transistor T1.
  • the second boost input voltage Vch of the boost input signal CK in the second stage can be set larger. , so that the gate G of the driving transistor T1 has a larger second voltage Vg2 in the second stage, so that the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 in the second stage is appropriate. .
  • the working process of the pixel driving circuit 100 may include but is not limited to the following stages;
  • the data control signal Scan is equal to the corresponding high potential to control the data transistor T4 to turn on.
  • the data signal Data on the data line is equal to the corresponding low potential and is transmitted to the gate G of the driving transistor T1 through the data transistor T4 to reset the driving transistor T1.
  • gate G is transmitted to the gate G of the driving transistor T1 through the data transistor T4 to reset the driving transistor T1.
  • the reset control signal Sense Gate is equal to the corresponding high potential to control the reset transistor T5 to turn on.
  • the reset signal Vref on the reset line is equal to the corresponding low potential and is transmitted to the source S of the driving transistor T1 through the reset transistor T5.
  • the data control signal Scan maintains the corresponding high potential to keep the data transistor T4 turned on.
  • the data signal Data on the data line is equal to the corresponding high potential Vdata and is transmitted to the gate G of the driving transistor T1 through the data transistor T4, so that
  • the gate voltage Vg of the gate G of the driving transistor T1 is equal to Vdata, that is, the first boost control signal (that is, the gate voltage Vg of the gate G of the driving transistor T1) is equal to the high potential Vdata corresponding to the data signal Data to control the first boost.
  • the voltage transistor T2 is turned on, and at the same time, the second voltage boost control signal (such as the lighting control signal EM) is also equal to the corresponding high potential pass to control the second voltage boost transistor T3 to be turned on.
  • the voltage boost input signal on the input end of the voltage boost module 10 CK is equal to the corresponding low potential Vcl and is transmitted to node A through the first boost transistor T2 and the second boost transistor T3.
  • the reset control signal Sense Gate maintains the corresponding high potential to keep the reset transistor T5 on, and the reset on the reset line
  • the signal Vref is equal to the corresponding low potential and is transmitted to the source S of the driving transistor T1 through the reset transistor T5, keeping the light-emitting element L turned off;
  • the data control signal Scan is equal to the corresponding low potential to control the data transistor T4 to turn off
  • the reset control signal Sense Gate is equal to the corresponding low potential to control the reset transistor T5 to turn off.
  • the gate G of the driving transistor T1 is turned off at the initial moment.
  • the gate voltage Vg is still equal to Vdata, so that the first boost transistor T2 and the second boost transistor T3 are still kept on, so that the boost input signal CK is equal to the corresponding low potential Vcl to be transmitted to the node A, combined with the first capacitor C1 As a result, the gate voltage Vg of the gate G of the driving transistor T1 is still maintained at Vdata.
  • the second signal VDD on the second power line is always equal to the corresponding high potential.
  • the first signal VSS on the first power line is always equal to the corresponding low potential, and the reset transistor T5 is turned off, the light-emitting element L is turned on, the driving current I flows through the light-emitting element L at the first current value I1, and the source of the driving transistor T1
  • the source voltage Vs of S is equal to the conduction voltage drop VL of the light-emitting element L;
  • the source voltage Vs of the source S of the driving transistor T1 is still equal to the conduction voltage drop VL of the light-emitting element L, and the gate voltage Vg of the gate G of the driving transistor T1 is still equal to Vdata, so that The first boost transistor T2 still remains on, and the second boost control signal (such as the lighting control signal EM) still maintains a corresponding high potential, so that the second boost transistor T3 still remains on, so that the boost input signal CK is equal to the corresponding high potential Vch to be transmitted to node A, that is, the voltage of node A rises by ⁇ Va.
  • the second boost control signal such as the lighting control signal EM
  • the gate voltage Vg of the gate G of the driving transistor T1 also rises to (Vdata+ ⁇ Va) , at this time, the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 increases, so that the driving current I flowing through the light-emitting element L rises to the second current value I2, so that the source of the driving transistor T1
  • the source voltage Vs of pole S is also slightly increased.
  • the pixel driving circuit 100 has the above-mentioned "brightening stage".
  • the gate voltage Vg of the gate G of the driving transistor T1 increases, so that the gate-source voltage Vgs between the gate G and the source S of the driving transistor T1 increases, so that the driving current I flowing through the light-emitting element L It has also been improved, thereby increasing the luminous brightness of the light-emitting element L, thereby improving the brightness of the display panel.
  • the boost input signal CK can achieve other functions for other devices loaded with the boost input signal CK, that is, increase the boost input signal CK.
  • the multiplexing rate of the input signal CK is high, but the second boost control signal (such as the light emission control signal EM) is equal to the corresponding low potential, which can control the second boost transistor T3 to turn off so that the node A is suspended to end the operation of the driving transistor T1. Modulation of gate voltage Vg of gate G.
  • the second boost control signal (for example, the light emission control signal EM) can also be a corresponding low voltage during the reset phase t1 and the data writing phase t2 to control the second boost transistor T3 to turn off to save energy.
  • An embodiment of the present application provides a display panel, as shown in FIGS. 1 to 6 , including a plurality of pixel driving circuits 100 as described in any one of the above.
  • the display panel may include a display area and a non-display area surrounding the display area.
  • a plurality of the pixel driving circuits 100 may be provided in the display area.
  • at least part of the pixel driving circuits 100 may be arranged in an array.
  • the display panel further includes: a data generation chip located on at least one side of the plurality of pixel driving circuits 100 , and a plurality of the data lines are electrically connected to the The data generation chip obtains the data signal Data.
  • the data signal Data obtained by the corresponding data line can be loaded to the gate G of the driving transistor T1 through the data transistor T4 to turn on the driving transistor T1, and later combined with the second capacitor C2
  • the voltage stabilizing effect and the source voltage Vs of the driving transistor T1 can control the light-emitting element L to emit light at the first brightness.
  • the absolute value of the voltage value of the corresponding data signal Data is greater for the pixel driving circuit 100 that is far away from the data generating chip than for the pixel driving circuit 100 that is close to the data generating chip.
  • the data generating chip is disposed close to at least one side of the plurality of pixel driving circuits 100 , that is, the distances between the plurality of pixel driving circuits 100 and the data generating chips are different, resulting in data received by the pixel driving circuits 100 at different locations.
  • the attenuation degree of the signal Data is different. For example, if the data signal Data loaded to each data line is the same, it will cause the data signal Data to be loaded onto the pixel driving circuit 100 at different positions in different voltages, which will affect the uniformity of the screen display. .
  • the pixel driving circuit 100 that is far away from the data generating chip has a greater attenuation degree of the received data signal Data than the pixel driving circuit 100 that is close to the data generating chip.
  • the absolute value of the voltage value of the data signal Data loaded into the pixel driving circuit 100 that is far away from the data generating chip is larger to compensate for the excessively large data signal Data caused by the large distance from the data generating chip, thereby reducing the number of pixels at different positions.
  • the difference in attenuation of the data signal Data loaded by the driving circuit 100 improves the uniformity of the display image of the display panel.
  • the display panel further includes: a signal generation chip located on at least one side of the plurality of pixel driving circuits 100 , and the input terminal circuits of the plurality of boost modules 10 sexually connected to the signal generation chip to obtain the boost input signal CK; wherein the boost input signal has a first boost input voltage in the first stage, and the boost input signal has a first boost input voltage in the first stage.
  • the second stage has a second boost input voltage, and the second boost input voltage is greater than the first boost input voltage; wherein the pixel driving circuit 100 that is far away from the data generating chip is relatively close to the data generating chip.
  • the difference between the corresponding second boosted input voltage and the corresponding first boosted input voltage is relatively large.
  • both the signal generation chip and the data generation chip can pass but are not limited to COF (Chip On Film, chip on film), COG (Chip On Glass, chip on glass substrate), COP (Chip On Pi, chip on flexible substrate) or other packaging technology is fixed on the front non-display area or back side of the display panel.
  • both the signal generating chip and the data generating chip can be disposed close to at least one side of the plurality of pixel driving circuits 100, that is, the distances between the pixel driving circuits 100 at different positions and the signal generating chips can be different, and the pixel driving circuits at different positions can be different.
  • the distance between 100 and the data generating chip can also vary.
  • the distance between the pixel driving circuit 100 and the data generation chip at different locations is different, which will lead to different attenuation degrees of the data signal Data received by the pixel driving circuit 100 at different locations.
  • the voltages of the pixel driving circuit 100 loaded at different positions by the data signals Data will be different, which will affect the uniformity of the screen display. Different attenuation degrees of the data signals Data will also cause corresponding The size of the first voltage is different.
  • the pixel driving circuit 100 that is far away from the data generating chip has a greater attenuation degree of the received data signal Data than the pixel driving circuit 100 that is close to the data generating chip.
  • the boosted input signal CK loaded on the pixel driving circuit 100 away from the data generation chip is set to a point where the difference between the second boosted input voltage Vch and the corresponding first boosted input voltage Vcl is larger, that is, the difference between the voltage of node A and
  • the change value ⁇ Va (positively related to (Vch-Vcl)) can also be larger to compensate for the loss of the first brightness that is too small due to the too small first voltage caused by the large distance from the data generation chip.
  • the large ⁇ Va reduces the difference between the second voltage and the first voltage in the pixel driving circuit 100 at different positions, so that the difference in the second brightness of the light-emitting elements L at different positions can be smaller, improving the display of the display panel.
  • the uniformity of the picture By setting a smaller The large ⁇ Va reduces the difference between the second voltage and the first voltage in the pixel driving circuit 100 at different positions, so that the difference in the second brightness of the light-emitting elements L at different positions can be smaller, improving the display of the display panel.
  • the uniformity of the picture is described in this specification.
  • the present application provides a pixel driving circuit and a display panel.
  • the pixel driving circuit includes: a driving transistor connected in series with a light-emitting element between a first power line and a second power line.
  • the source of the driving transistor is electrically connected to the light-emitting element.
  • the module controls the gate of the driving transistor to rise from the first voltage in the first stage to the second voltage in the second stage.
  • the second stage is located after the first stage.
  • the driving transistor is used to adjust the voltage according to the first stage.
  • the second voltage generates a driving current to drive the light-emitting element to emit light.
  • this application provides a boost module with an input end loaded with a boost input signal, and the output end of the boost module is electrically connected to the gate of the drive transistor, so as to modulate the gate voltage of the drive transistor to a level that can be changed by the first voltage.
  • the voltage rises to the second voltage, thereby increasing the driving current flowing through the light-emitting element to increase the brightness of the light-emitting element, thereby increasing the brightness of the display panel.

Abstract

像素驱动电路（100）和显示面板，包括连接于数据线的数据晶体管（T4）、与发光元件（L）串联于第一电源线（VDD）和第二电源线（VSS）之间的驱动晶体管（T1）、输入端加载升压输入信号（CK）的升压模块（10），驱动晶体管（T1）的源极、栅极分别电性连接于发光元件（L）、数据晶体管（T4），升压模块（10）的输出端电性连接于驱动晶体管（T1）的栅极使其由第一电压上升至第二电压。

Description

像素驱动电路和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及显示面板制造技术领域，具体涉及像素驱动电路和显示面板。
 背景技术
自发光显示器相比较液晶显示器，具有高色域、高对比度、响应时间短以及可弯折等优点，被业界公认为在新一代显示领域拥有巨大的发展潜力。
目前，自发光显示器中的发光元件均为电流驱动型，即发光亮度取决于流经发光元件的电流大小。其中，面板产出后一般通过调整数据电压的大小调整发光元件的发光亮度，并且在发光阶段驱动晶体管的栅源电压不会变化，即发光元件的发光亮度无法改变，然而，受限于数据驱动芯片的硬件影响，并且考虑到阈值电压和画面均匀性等方面补偿的影响，导致在发光阶段驱动晶体管的栅源电压较小，以至于流经发光元件的电流较小，造成发光元件及其形成的自发光显示器的亮度较低。
因此，现有的自发光显示器受限于数据驱动芯片的硬件影响而发光亮度较低，急需改进。
 技术问题
本申请实施例提供像素驱动电路和显示面板，以解决现有的自发光显示器受限于数据驱动芯片的硬件影响而发光亮度较低的技术问题。
 技术解决方案
本申请实施例提供像素驱动电路，包括：
驱动晶体管，与发光元件串联于第一电源线和第二电源线之间，所述驱动晶体管的源极电性连接于所述发光元件；
数据晶体管，所述数据晶体管的源极电性连接于数据线，所述数据晶体管的漏极电性连接于所述驱动晶体管的所述栅极，所述数据晶体管的栅极加载数据控制信号；
升压模块，所述升压模块的输入端用于加载升压输入信号，所述升压模块的输出端电性连接于所述驱动晶体管的所述栅极；
其中，所述升压模块控制所述驱动晶体管的所述栅极由第一阶段的第一电压上升至第二阶段的第二电压，所述第二阶段位于所述第一阶段之后，所述驱动晶体管用于根据所述第二电压产生驱动电流以驱动所述发光元件发光。
 有益效果
本申请提供了像素驱动电路和显示面板，像素驱动电路包括：驱动晶体管，与发光元件串联于第一电源线和第二电源线之间，所述驱动晶体管的源极电性连接于所述发光元件；数据晶体管，所述数据晶体管的源极电性连接于数据线，所述数据晶体管的漏极电性连接于所述驱动晶体管的所述栅极，所述数据晶体管的栅极加载数据控制信号；升压模块，所述升压模块的输入端用于加载升压输入信号，所述升压模块的输出端电性连接于所述驱动晶体管的所述栅极；其中，所述升压模块控制所述驱动晶体管的所述栅极由第一阶段的第一电压上升至第二阶段的第二电压，所述第二阶段位于所述第一阶段之后，所述驱动晶体管用于根据所述第二电压产生驱动电流以驱动所述发光元件发光。其中，本申请通过设置输入端加载升压输入信号的升压模块，且升压模块的输出端电性连接于驱动晶体管的栅极，以将驱动晶体管的栅极电压调制为可以由第一电压上升至第二电压，从而增加流经发光元件的驱动电流，以提高发光元件的发光亮度，从而提高显示面板的亮度。
 附图说明
下面通过附图来对本申请进行进一步说明。需要说明的是，下面描述中的附图仅仅是用于解释说明本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的第一种像素驱动电路的电路图。
图2为本申请实施例提供的第二种像素驱动电路的电路图。
图3为本申请实施例提供的第三种像素驱动电路的电路图。
图4为本申请实施例提供的第四种像素驱动电路的电路图。
图5为本申请实施例提供的第五种像素驱动电路的电路图。
图6为本申请实施例提供的第六种像素驱动电路的电路图。
图7为本申请实施例提供的部分信号的波形图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。此外，术语“源极”和“漏极”可以互换称呼，只需满足对应的晶体管具有至少一源极和至少一漏极即可。例如包含了一系列步骤或模块的过程、方法、系统、产品或设备没有限定于已列出的步骤或模块，而是可选地还包括没有列出的步骤或模块，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或模块。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请实施例提供了像素驱动电路，所述像素驱动电路包括但不限于以下实施例以及以下实施例的组合。
在一实施例中，如图1至图6所示，所述像素驱动电路100包括：驱动晶体管T1，与发光元件L串联于第一电源线和第二电源线之间，所述驱动晶体管T1的源极S电性连接于所述发光元件L；数据晶体管T4，所述数据晶体管T4的源极电性连接于数据线，所述数据晶体管T4的漏极电性连接于所述驱动晶体管T1的所述栅极G，所述数据晶体管T4的栅极加载数据控制信号Scan；升压模块10，所述升压模块10的输入端加载升压输入信号CK，所述升压模块10的输出端电性连接于所述驱动晶体管T1的所述栅极G；其中，所述升压模块控制10所述驱动晶体管T1的所述栅极G由第一阶段的第一电压Vg1上升至第二阶段的第二电压Vg2，所述第二阶段位于所述第一阶段之后，所述驱动晶体管T1用于根据所述第二电压Vg2产生驱动电流以驱动所述发光元件L发光。
其中，如图1至图6所示，第一电源线可以加载第一信号VSS，第二电源线可以加载第二信号VDD，第一信号VSS的大小和第二信号VDD的大小可以分别为两恒定的电压值，第一信号VSS对应的电压值可以小于第二信号VDD对应的电压值。其中，驱动晶体管T1可以为N型晶体管或者P型晶体管，发光元件L可以为但不限于有机发光半导体、发光二极管、微型发光二极管或者次毫米发光二极管。
具体的，如图1至图6所示，此处以驱动晶体管T1为N型晶体管为例进行说明，结合上文论述，驱动晶体管T1的漏极D可以电性连接于第二电源线以被加载第二信号VDD，驱动晶体管T1的源极S可以电性连接于发光元件L的阳极，发光元件L的阴极可以电性连接至第一电源线以被加载第一信号VSS，例如第一信号VSS对应的电压值可以为0伏特，即发光元件L的阴极可以接地。具体的，所述驱动晶体管T1的栅极G和所述驱动晶体管T1的所述源极S之间的栅源电压Vgs驱动所述发光元件L发光，当驱动晶体管T1开启时，在第一信号VSS和第二信号VDD的作用下可以产生流向发光元件L的驱动电流，其中，驱动电流的大小与驱动晶体管T1的栅极G和驱动晶体管T1的源极S之间的栅源电压Vgs呈正相关，而加载至驱动晶体管T1的栅极G的电压一般可以根据发光元件L的预期灰阶对应的电压值所确定，即可以认为发光元件L的预期灰阶对应的电压值决定了流向发光元件L的驱动电流的大小，从而决定了发光元件L的发光亮度。
需要注意的是，当像素驱动电路100处于发光阶段，由于发光元件L具有相对稳定的压降，导致驱动晶体管T1的源极S的源极电压Vs可以为一相对稳定的值，即可以认为此时发光元件L的发光亮度可以由驱动晶体管T1的栅极G的栅极电压Vg决定，结合上文论述可知，加载至驱动晶体管T1的栅极G的栅极电压Vg一般可以根据发光元件L的预期灰阶对应的电压值所确定，然而，受限于数据驱动芯片的硬件影响，并且考虑到阈值电压和画面均匀性等方面补偿的影响，导致“根据发光元件L的预期灰阶对应的电压值所确定”的加载至驱动晶体管T1的栅极G的电压实际较小，以至于流经发光元件L的驱动电流较小，造成发光元件L的发光亮度较低。
可以理解的，本实施例中通过设置升压模块10，且升压模块10的输入端加载升压输入信号CK，升压模块10的输出端电性连接于驱动晶体管T1的栅极G，相比较上文论述，即驱动晶体管T1的栅极G的栅极电压Vg还可以由升压输入信号CK决定；在第一阶段，驱动晶体管T1的栅极G具有第一电压Vg1，结合上文论述，此处的第一阶段可以认为上文提及的“发光阶段”，第一电压Vg1可以至少由“根据发光元件L的预期灰阶对应的电压值所确定”的加载至驱动晶体管T1的栅极G的电压决定，进一步的，本实施例中将升压模块10设置为可以控制驱动晶体管T1的栅极G在第二阶段具有与升压输入信号CK相关的第二电压Vg2，第二电压Vg2大于第一电压Vg1，此处的第二阶段可以认为处于第一阶段之后，即驱动晶体管T1的栅极电压Vg在升压模块10和升压输入信号CK的作用下可以由第一电压Vg1上升至第二电压Vg2，从而增加流经发光元件L的驱动电流，以提高发光元件L的发光亮度。其中，可以根据实际情况合理设置升压模块10的具体结构和升压输入信号CK的波形，以较好地提高发光元件L的发光亮度。
在一实施例中，如图2至图6所示，所述升压模块10包括：第一电容C1，所述第一电容C1的第一极板电性连接于所述驱动晶体管T1的所述栅极G以作为所述升压模块10的所述输出端；第一升压晶体管T2，所述第一升压晶体管T2的漏极电性连接于所述第一电容C1的第二极板，所述第一升压晶体管T2的源极电性连接至所述升压模块10的所述输入端，所述第一升压晶体管T2的栅极加载第一升压控制信号，所述第一升压晶体管T2在所述第一阶段和所述第二阶段均开启；其中，所述升压输入信号CK在所述第一阶段具有第一升压输入电压Vcl，所述升压输入信号CK在所述第二阶段具有第二升压输入电压Vch，所述第二升压输入电压大于所述第一升压输入电压。
其中，第一升压晶体管T2可以为N型晶体管或者P型晶体管，此处以第一升压晶体管T2为N型晶体管、第一电容C1的第二极板电性连接至节点A为例进行说明。具体的，如图2所示，第一升压晶体管T2的栅极可以电性连接至驱动晶体管T1的栅极G以获取驱动晶体管T1的栅极G的栅极电压Vg作为第一升压控制信号，结合上文论述，在第一阶段，即在发光阶段，驱动晶体管T1的栅极G的栅极电压Vg具有较大的第一电压Vg1以开启驱动晶体管T1，也可以认为同时开启第一升压晶体管T2，以使得升压输入信号CK通过第一升压晶体管T2加载至第一电容C1的第二极板以使得节点A的电压等于第一升压输入电压Vcl，在第二阶段，初始时刻第一升压晶体管T2仍然可以被驱动晶体管T1的栅极G的栅极电压Vg驱动以开启，以使得升压输入信号CK通过第一升压晶体管T2加载至第一电容C1的第二极板以使得节点A的电压等于第二升压输入电压Vch，即节点A的电压的变化值ΔVa可以与(Vch-Vcl)呈正相关，甚至等于(Vch-Vcl)，由于第一电容C1两端的电压差不能突变，故电性连接于第一电容C1的第一极板的驱动晶体管T1的栅极G的栅极电压Vg的变化值也与(Vch-Vcl)呈正相关，甚至等于(Vch-Vcl)，以使驱动晶体管T1的栅极G的栅极电压Vg由第一电压Vg1上升至第二电压Vg2，从而增加流经发光元件L的驱动电流，以提高发光元件L的发光亮度。
当然，如图3所示，第一升压晶体管T2的栅极也可以电性连接至升压控制线以被加载第一升压控制信号，第一升压控制信号可以为但不限于发光控制信号EM，其中，升压控制线上传输的信号的波形可以相同或者不同于驱动晶体管T1的栅极G的栅极电压Vg的波形，只需满足在第一阶段和第二阶段可以控制第一升压晶体管T2开启即可，具体对于驱动晶体管T1的栅极G的栅极电压Vg的作用原理，可以相同于上文中“第一升压晶体管T2的栅极可以电性连接至驱动晶体管T1的栅极G”对于驱动晶体管T1的栅极G的栅极电压Vg的作用原理。
特别的，当第一升压晶体管T2开启时，若升压输入信号CK的电压值保持不变，即节点A的电压保持不变，当驱动晶体管T1的栅极G由加载第一电压Vg1切换至悬空状态，由于第一电容C1两端的电压差不能突变，驱动晶体管T1的栅极G的栅极电压Vg也不会变化。
在一实施例中，如图4和图5所示，所述升压模块10还包括：第二升压晶体管T3，所述第二升压晶体管T3的漏极电性连接于所述第一升压晶体管T2的所述源极，所述第二升压晶体管T3的源极电性连接至所述升压模块10的所述输入端，所述第二升压晶体管T3的栅极加载第二升压控制信号，所述第二升压晶体管T3在所述第一阶段和所述第二阶段均开启；其中，所述第一升压晶体管T2的所述栅极电性连接至所述驱动晶体管T1的所述栅极G。
具体的，结合上文论述，基于“第一升压晶体管T2的栅极可以电性连接至驱动晶体管T1的栅极G以获取驱动晶体管T1的栅极G的栅极电压Vg作为第一升压控制信号”的这一实施例，本实施例相当于新增一由第二升压控制信号控制开启情况的第二升压晶体管T3串联于升压模块10的输入端和节点A之间，第二升压控制信号可以为但不限于有发光控制电路产生的发光控制信号（例如发光控制信号EM），即可以认为第一升压控制信号和第二升压控制信号共同决定升压输入信号CK是否可以加载至节点A，结合上文论述，即在通过第一升压控制信号控制第一升压晶体管T2在第一阶段和第二阶段开启的基础上，本实施例中通过新增的第二升压控制信号、第二升压晶体管T3还可以实现对于升压输入信号CK是否可以加载至节点A的进一步控制，提高了升压模块10工作的精准性。
在一实施例中，如图4和图5所示，所述像素驱动电路100还包括：第二电容C2，所述第二电容C2的第一极板电性连接于所述第一电容C1的所述第二极板，所述第二电容C2的第二极板电性连接于所述驱动晶体管T1的所述源极S（如图4所示）或者漏极D（如图5所示）。
需要注意的是，结合上文论述，在第一升压晶体管T2、第二升压晶体管T3中的至少一者关闭时，即节点A处于悬空状态下，此时第一电容C1和第二电容C2串联于驱动晶体管T1的栅极G和源极S之间，或者串联于驱动晶体管T1的栅极G和漏极D之间，当驱动晶体管T1的栅极G由加载第一电压Vg1切换至悬空状态，由于第一电容C1和第二电容C2两者整体的两端的电压差不能突变，故驱动晶体管T1的栅极G的栅极电压Vg的变化量等于驱动晶体管T1的栅极G的电压的变化量或者漏极D的电压的变化量；特别的，在一时间段内，当驱动晶体管T1的栅极G的电压的变化量或者漏极D的电压的变化量为0时，可以认为驱动晶体管T1的栅极G的栅极电压Vg可以维持为等于第一电压Vg1。
在其它的实施例中，结合上文分析，不同于以上实施例，基于第二电容C2的第一极板电性连接于第一电容C1的第二极板，第二电容C2的第二极板也可以设置为接地，以维持第二电容C2的第二极板的电压不变，从而驱动晶体管T1的栅极G的栅极电压Vg也可以维持为等于第一电压Vg1；或者，不同于以上实施例，第二电容C2也可以串联于驱动晶体管T1的栅极G和地之间，同理，由于第二电容C2接地，驱动晶体管T1的栅极G的栅极电压Vg也可以维持为等于第一电压Vg1。
在一实施例中，如图6所示，所述升压模块10还包括：第三电容C3；升压开关K，与所述第三电容C3串联于所述驱动晶体管T1的所述栅极G和所述驱动晶体管T1的所述源极S之间；其中，在所述第一阶段和位于所述第一阶段之前的第三阶段，所述升压开关K开启以控制所述驱动晶体管T1的所述栅极G由所述第三阶段的第三电压Vg3上升至所述第一阶段的所述第一电压Vg1。
同理，结合上文论述，在第一阶段，驱动晶体管T1的栅极G具有第一电压Vg1，第一阶段可以认为上文提及的“发光阶段”，第一电压Vg1可以至少由“根据发光元件L的预期灰阶对应的电压值所确定”的加载至驱动晶体管T1的栅极G的电压决定，即可以认为第一电压Vg1与驱动晶体管T1的源极S的电压相关。
具体的，本实施例中将升压模块10还设置为在第三阶段，驱动晶体管T1的栅极G具有第三电压Vg3，第三阶段可以理解为位于发光阶段之前的数据写入阶段，即第三电压Vg3可以等于“根据发光元件L的预期灰阶对应的电压值所确定”的加载至驱动晶体管T1的栅极G的电压，此时驱动晶体管T1的源极S具有较低的电压，进一步的，结合上文论述，在第三阶段之后的发光阶段，由于发光元件L导通，驱动晶体管T1的源极S的电压有所提升，由于第三电容C3两端的电压差不能突变，驱动晶体管T1的栅极G的栅极电压Vg也可以由第三电压Vg3提升至第一电压Vg1，从而增加流经发光元件L的驱动电流，以提高发光元件L的发光亮度。
因此，在第三电压Vg3一定的情况下，驱动晶体管T1的栅极G的栅极电压Vg的变化量即与驱动晶体管T1的源极S的电压相关，具体为与驱动晶体管T1的源极S的电压在第三阶段和第一阶段的差值相关。需要注意的是，结合上文论述，本实施例中的升压开关K可以至少满足在第三阶段和第一阶段闭合以使得第三电容C3电性连接于驱动晶体管T1的栅极G和源极S之间，以使得驱动晶体管T1的栅极G的栅极电压Vg跟随驱动晶体管T1的源极S的源极电压Vs的变化而变化，且在第二阶段断开以避免驱动晶体管T1的栅极G的栅极电压Vg变化引起驱动晶体管T1的源极S的源极电压Vs同步变化而造成栅源电压Vgs无法上升，以至于无法增加流经发光元件L的驱动电流。
在一实施例中，如图4至图6所示，所述像素驱动电路100还包括：复位晶体管T5，所述复位晶体管T5的源极电性连接于复位线，所述复位晶体管T5的漏极电性连接于所述驱动晶体管T1的所述源极，所述复位晶体管T5的栅极加载复位控制信号Sense Gate。
需要注意的是，本申请中的像素驱动电路100可以包括如上文所述的升压模块10和驱动晶体管T1，进一步的，还可以包括电性连接于驱动晶体管T1的数据写入模块和复位模块，数据写入模块可以电性连接于驱动晶体管T1的栅极G、源极S中的一者，复位模块可以电性连接于驱动晶体管T1的栅极G、源极S中的另一者。具体的，本实施例中以数据写入模块电性连接于驱动晶体管T1的栅极G、复位模块电性连接于驱动晶体管T1的源极S、数据写入模块包括上文提及的数据晶体管T4、复位模块包括上文提及的复位晶体管T5为例进行说明，即本实施例基于像素驱动电路100可以包括驱动晶体管T1、数据晶体管T4、复位晶体管T5和第二电容C2组成的3T1C电路为例进行说明，当然，像素驱动电路100包括的电路并不限于3T1C电路，例如还可以包括6T1C电路、7T1C电路或者其它电路。
可以理解的，结合上文论述，在本实施例中，数据控制信号Scan可以至少在第三阶段控制数据晶体管T4开启，以使数据线上的数据信号Data加载至驱动晶体管T1的栅极G以开启驱动晶体管T1，复位控制信号Sense Gate可以至少在第三阶段之前的阶段控制复位晶体管T5开启，以使复位线上的复位信号Vref加载至驱动晶体管T1的源极S以复位驱动晶体管T1的源极S。
本申请实施例提供了显示面板，包括像素驱动电路，所述像素驱动电路包括：第一晶体管，与发光元件串联于第一电源线和第二电源线之间，所述第一晶体管的源极电性连接于所述发光元件，所述第一晶体管的栅极和所述第一晶体管的所述源极之间的栅源电压驱动所述发光元件发光；第二晶体管，所述第二晶体管的源极电性连接于第一信号线，所述第二晶体管的漏极电性连接于所述第一晶体管的所述栅极，所述第二晶体管的栅极电性连接于第二信号线；第一模块，所述第一模块的输入端电性连接于第三信号线，所述第一模块的输出端电性连接于所述第一晶体管的所述栅极，所述第一模块的控制端电性连接于第四信号线。
进一步的，结合图1至图6所示，本实施例中的第一晶体管可以参考上文关于驱动晶体管T1的相关描述，第二晶体管可以参考上文关于数据晶体管T4的相关描述，第一模块可以参考上文关于升压模块10的相关描述，基于此，第一信号线可以为上文提及的数据线，第二信号线可以加载上文提及的数据控制信号Scan，第三信号线可以加载上文提及的升压输入信号，第四信号线可以加载上文提及的第一升压控制信号、第二升压控制信号中的至少一者。
在一实施例中，所述第一模块包括：第一电容，所述第一电容的第一极板电性连接于所述驱动晶体管的所述栅极以作为所述第一模块的所述输出端；第三晶体管，所述第三晶体管的漏极电性连接于所述第一电容的第二极板，所述第三晶体管的电性连接至所述第一模块的所述输入端，所述第三晶体管的栅极电性连接于所述第四信号线。
进一步的，结合图1至图6所示，本实施例中的第三晶体管可以参考上文关于第一升压晶体管T2的相关描述，基于此，第四信号线可以加载上文提及的第一升压控制信号。
在一实施例中，所述第一模块还包括：第四晶体管，所述第四晶体管的漏极电性连接于所述第三晶体管的所述漏极，所述第四晶体管的源极电性连接至所述第一模块的所述输入端，所述第四晶体管的栅极电性连接于不同于所述驱动晶体管的所述栅极的第五信号线；其中，所述第三晶体管的所述栅极电性连接至所述驱动晶体管的所述栅极。
进一步的，结合图1至图6所示，本实施例中的第四晶体管可以参考上文关于第二升压晶体管T3的相关描述，基于此，即为第四信号线直接连接于驱动晶体管的栅极以加载第一升压控制信号，第五信号线可以加载第二升压控制信号。
在一实施例中，所述像素驱动电路还包括：第二电容，所述第二电容的第一极板电性连接于所述第一电容的所述第二极板，所述第二电容的第二极板电性连接于所述第一晶体管的所述源极或者漏极。
进一步的，结合图1至图6所示，本实施例中的第二电容可以参考上文关于第二电容C2的相关描述。
在一实施例中，所述第一模块还包括：第三电容；第一开关，与所述第三电容串联于所述第一晶体管的所述栅极和所述第一晶体管的所述源极之间；其中，在所述第一阶段和位于所述第一阶段之前的第三阶段，所述第一开关开启以控制所述第一晶体管的所述栅极由所述第三阶段的第三电压上升至所述第一阶段的所述第一电压。
进一步的，如图6所示，本实施例中的第三电容可以参考上文关于第三电容C3的相关描述，第一开关可以参考上文关于升压开关K的相关描述。
在一实施例中，还包括：第五晶体管，所述第五晶体管的源极电性连接于第六信号线，所述第五晶体管的漏极电性连接于所述第一晶体管的所述源极，所述第五晶体管的栅极电性连接于第七信号线。
进一步的，结合图1至图6所示，本实施例中的第五晶体管可以参考上文关于复位晶体管T5的相关描述，基于此，第六信号线可以为上文提及的复位线，第七信号线可以加载复位控制信号Sense Gate。
本申请实施例提供了驱动方法，结合图1至图6所示，用于驱动如上文任一所述的像素驱动电路100，包括：在所述第一阶段根据所述驱动晶体管T1的所述源极S的源极电压Vs配置所述升压输入信号CK；通过所述升压输入信号CK和所述升压模块10，控制所述驱动晶体管T1的所述栅极G具有与所述升压输入信号CK相关的第二电压Vg2，所述第二电压Vg2大于在所述第一阶段所述驱动晶体管T1的所述栅极具有的第一电压Vg1。
具体的，结合上文分析，流经发光元件L驱动电流的大小与驱动晶体管T1的栅极G和源极S之间的栅源电压Vgs呈正相关，第一阶段作为发光阶段，在后续发光元件L发光的过程中，可以认为驱动晶体管T1的源极S的源极电压Vs近似等于其在第一阶段的电压，故本实施例中在第一阶段根据驱动晶体管T1的源极S的源极电压Vs配置升压输入信号CK，可以使得第二电压Vg2根据驱动晶体管T1的源极S的源极电压Vs，例如驱动晶体管T1的源极S的源极电压Vs越大，在对应的升压输入信号CK中在第一阶段的第一升压输入电压Vcl确定的情况下（例如等于0），可以将升压输入信号CK在第二阶段具有的第二升压输入电压Vch设置的较大，以使得动晶体管T1的栅极G在第二阶段具有的第二电压Vg2较大，从而使得在第二阶段中驱动晶体管T1的栅极G和源极S之间的栅源电压Vgs大小合适。
具体的，此处基于图4和图5所示的电路图，结合图7所示的时序图，像素驱动电路100的工作过程可以包括但不限于以下几个阶段；
复位阶段t1，数据控制信号Scan等于对应的高电位以控制数据晶体管T4开启，数据线上的数据信号Data等于对应的低电位通过数据晶体管T4传输至驱动晶体管T1的栅极G以复位驱动晶体管T1的栅极G，同时，复位控制信号Sense Gate等于对应的高电位以控制复位晶体管T5开启，复位线上的复位信号Vref恒等于对应的低电位通过复位晶体管T5传输至驱动晶体管T1的源极S以复位驱动晶体管T1的源极S；
数据写入阶段t2，数据控制信号Scan维持对应的高电位以维持数据晶体管T4开启，数据线上的数据信号Data等于对应的高电位Vdata通过数据晶体管T4传输至驱动晶体管T1的栅极G，使得驱动晶体管T1的栅极G的栅极电压Vg等于Vdata，即第一升压控制信号（即驱动晶体管T1的栅极G的栅极电压Vg）等于数据信号Data对应的高电位Vdata控制第一升压晶体管T2开启，同时，第二升压控制信号（例如发光控制信号EM）也等于对应的高电位通过以控制第二升压晶体管T3开启，升压模块10的输入端上的升压输入信号CK等于对应的低电位Vcl通过第一升压晶体管T2、第二升压晶体管T3传输至节点A，同时，复位控制信号Sense Gate维持对应的高电位以维持复位晶体管T5开启，复位线上的复位信号Vref恒等于对应的低电位通过复位晶体管T5传输至驱动晶体管T1的源极S，保持发光元件L截止；
发光阶段t3，数据控制信号Scan等于对应的低电位以控制数据晶体管T4关闭，复位控制信号Sense Gate等于对应的低电位以控制复位晶体管T5关闭，同理，初始时刻驱动晶体管T1的栅极G的栅极电压Vg仍然等于Vdata，使得第一升压晶体管T2、第二升压晶体管T3仍然维持为开启，使得升压输入信号CK等于对应的低电位Vcl以传输至节点A，结合第一电容C1的作用，驱动晶体管T1的栅极G的栅极电压Vg仍然维持为Vdata，此时由于第一电容驱动晶体管T1维持为开启，第二电源线上的第二信号VDD恒等于对应的高电位，第一电源线上的第一信号VSS恒等于对应的低电位，且复位晶体管T5关闭，发光元件L导通，驱动电流I以第一电流值I1流经发光元件L，驱动晶体管T1的源极S的源极电压Vs等于发光元件L的导通压降VL；
增亮阶段t4，初始时刻，驱动晶体管T1的源极S的源极电压Vs仍然等于发光元件L的导通压降VL，驱动晶体管T1的栅极G的栅极电压Vg仍然等于Vdata，以使得第一升压晶体管T2仍然维持为开启，第二升压控制信号（例如发光控制信号EM）仍然维持为对应的高电位，以使得第二升压晶体管T3仍然维持为开启，使得升压输入信号CK等于对应的高电位Vch以传输至节点A，即节点A的电压上升了ΔVa，结合第一电容C1的作用，驱动晶体管T1的栅极G的栅极电压Vg也上升至(Vdata+ΔVa)，此时驱动晶体管T1的栅极G和源极S之间的栅源电压Vgs有所提升，使得流经发光元件L的驱动电流I上升至第二电流值I2，以至于驱动晶体管T1的源极S的源极电压Vs也稍有提升。
可以理解的，结合上文论述，本申请中通过设置升压模块10和对应的升压输入信号CK使得像素驱动电路100具有上文提及的“增亮阶段”，在“增亮阶段”中驱动晶体管T1的栅极G的栅极电压Vg有所提升，以使驱动晶体管T1的栅极G和源极S之间的栅源电压Vgs有所提升，从而流经发光元件L的驱动电流I也有所提升，从而提升了发光元件L的发光亮度，以此提升了显示面板的亮度。
需要注意的是，在本帧的增亮阶段t4之后，即使升压输入信号CK维持一段时间为对应的高电位以对于其它的被加载升压输入信号CK的器件实现其它的功能，即提高升压输入信号CK的复用率，但是第二升压控制信号（例如发光控制信号EM）等于对应的低电位可以控制第二升压晶体管T3关闭以使节点A悬空，以结束对于驱动晶体管T1的栅极G的栅极电压Vg的调制。另外，结合上文论述，在某些帧中的复位阶段t1、数据写入阶段t2和发光阶段t3中由于不需要节点A的电压的变化以调制驱动晶体管T1的栅极G的栅极电压Vg，故第二升压控制信号（例如发光控制信号EM）在复位阶段t1、数据写入阶段t2也可以为对应的低电压以控制第二升压晶体管T3关闭以节能。
本申请实施例提供了显示面板，结合图1至图6所示，包括多个如上文任一所述的像素驱动电路100。具体的，显示面板可以包括显示区和围绕显示区的非显示区，多个所述像素驱动电路100可以设于所述显示区，进一步的，至少部分所述像素驱动电路100可以阵列排布。
在一实施例中，结合图1至图6所示，显示面板还包括：数据产生芯片，位于多个所述像素驱动电路100的至少一侧，多条所述数据线电性连接至所述数据产生芯片以获取数据信号Data。具体的，结合上文论述，在数据晶体管T4开启时，对应的数据线获取的数据信号Data可以通过数据晶体管T4加载至驱动晶体管T1的栅极G以开启驱动晶体管T1，后期结合第二电容C2的稳压作用和驱动晶体管T1的源极电压Vs，可以控制发光元件L发光为第一亮度。
在一实施例中，远离所述数据产生芯片的所述像素驱动电路100相对于靠近所述数据产生芯片的所述像素驱动电路100，对应的所述数据信号Data的电压值的绝对值较大。需要注意的是，数据产生芯片靠近多个像素驱动电路100的至少一侧而设置，即多个像素驱动电路100与数据产生芯片之间的距离不同，导致不同位置的像素驱动电路100接收的数据信号Data的衰减程度不同，例如加载至每一数据线的数据信号Data相同，则会造成数据信号Data最终加载在不同位置的像素驱动电路100上的电压的大小具有差异而影响画面显示的均匀性。
可以理解的，在本实施例中，远离数据产生芯片的像素驱动电路100相对于靠近数据产生芯片的像素驱动电路100而言，接收的数据信号Data的衰减程度更大，基于此，本实施例将远离数据产生芯片的像素驱动电路100所加载的数据信号Data的电压值的绝对值较大，以弥补由于与数据产生芯片距离较大带造成的数据信号Data过大，从而减少不同位置的像素驱动电路100加载的数据信号Data的衰减的差异，提高显示面板的显示画面的均匀性。
在一实施例中，结合图1至图6所示，显示面板还包括：信号产生芯片，位于多个所述像素驱动电路100的至少一侧，多个所述升压模块10的输入端电性连接至所述信号产生芯片以获取所述升压输入信号CK；其中，所述升压输入信号在所述第一阶段具有第一升压输入电压，所述升压输入信号在所述第二阶段具有第二升压输入电压，所述第二升压输入电压大于所述第一升压输入电压；其中，远离所述数据产生芯片的所述像素驱动电路100相对于靠近所述数据产生芯片的所述像素驱动电路100，对应的所述第二升压输入电压与对应的所述第一升压输入电压的差值较大。
具体的，信号产生芯片和数据产生芯片均可以通过但不限于COF(Chip On Film,芯片在膜上)、COG(Chip On Glass,芯片在玻璃基板上)、COP(Chip On Pi,芯片在柔性基板上)或者其它封装技术固定于显示面板的正面的非显示区或者背面。其中，信号产生芯片和数据产生芯片均可以靠近多个像素驱动电路100的至少一侧而设置，即不同位置的像素驱动电路100与信号产生芯片之间的距离可以不同，不同位置的像素驱动电路100与数据产生芯片之间的距离也可以不同。需要注意的是，结合上文论述，不同位置的像素驱动电路100与数据产生芯片之间的距离不同，会导致不同位置的像素驱动电路100接收的数据信号Data的衰减程度不同，例如加载至每一数据线的数据信号Data相同，则会造成数据信号Data最终加载在不同位置的像素驱动电路100的电压的大小具有差异而影响画面显示的均匀性，数据信号Data的衰减程度不同也会造成对应的第一电压的大小不同。
可以理解的，在本实施例中，远离数据产生芯片的像素驱动电路100相对于靠近数据产生芯片的像素驱动电路100而言，接收的数据信号Data的衰减程度更大，基于此，本实施例将远离数据产生芯片的像素驱动电路100所加载的升压输入信号CK设置为，第二升压输入电压Vch与对应的第一升压输入电压Vcl的差值较大，即节点A的电压的变化值ΔVa（与(Vch-Vcl)呈正相关）也可以较大，以弥补由于与数据产生芯片距离较大带造成的第一电压过小而造成的第一亮度过小的损失，通过设置较大的ΔVa，从而减少不同位置的像素驱动电路100中的第二电压与第一电压的差值的差异，使得不同位置的发光元件L的第二亮度的差异可以较小，提高显示面板的显示画面的均匀性。
本申请提供了像素驱动电路和显示面板，像素驱动电路包括：驱动晶体管，与发光元件串联于第一电源线和第二电源线之间，所述驱动晶体管的源极电性连接于所述发光元件；数据晶体管，所述数据晶体管的源极电性连接于数据线，所述数据晶体管的漏极电性连接于所述驱动晶体管的所述栅极，所述数据晶体管的栅极加载数据控制信号；升压模块，所述升压模块的输入端用于加载升压输入信号，所述升压模块的输出端电性连接于所述驱动晶体管的所述栅极；其中，所述升压模块控制所述驱动晶体管的所述栅极由第一阶段的第一电压上升至第二阶段的第二电压，所述第二阶段位于所述第一阶段之后，所述驱动晶体管用于根据所述第二电压产生驱动电流以驱动所述发光元件发光。其中，本申请通过设置输入端加载升压输入信号的升压模块，且升压模块的输出端电性连接于驱动晶体管的栅极，以将驱动晶体管的栅极电压调制为可以由第一电压上升至第二电压，从而增加流经发光元件的驱动电流，以提高发光元件的发光亮度，从而提高显示面板的亮度。
以上对本申请实施例所提供的像素驱动电路和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种像素驱动电路，其中，包括：
    驱动晶体管，与发光元件串联于第一电源线和第二电源线之间，所述驱动晶体管的源极电性连接于所述发光元件；
    数据晶体管，所述数据晶体管的源极电性连接于数据线，所述数据晶体管的漏极电性连接于所述驱动晶体管的所述栅极，所述数据晶体管的栅极加载数据控制信号；
    升压模块，所述升压模块的输入端用于加载升压输入信号，所述升压模块的输出端电性连接于所述驱动晶体管的所述栅极；
    其中，所述升压模块控制所述驱动晶体管的所述栅极由第一阶段的第一电压上升至第二阶段的第二电压，所述第二阶段位于所述第一阶段之后，所述驱动晶体管用于根据所述第二电压产生驱动电流以驱动所述发光元件发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述升压模块包括：
    第一电容，所述第一电容的第一极板电性连接于所述驱动晶体管的所述栅极以作为所述升压模块的所述输出端；
    第一升压晶体管，所述第一升压晶体管的漏极电性连接于所述第一电容的第二极板，所述第一升压晶体管的源极电性连接至所述升压模块的所述输入端，所述第一升压晶体管的栅极加载第一升压控制信号，所述第一升压晶体管在所述第一阶段和所述第二阶段均开启；
    其中，所述升压输入信号在所述第一阶段具有第一升压输入电压，所述升压输入信号在所述第二阶段具有第二升压输入电压，所述第二升压输入电压大于所述第一升压输入电压。
  3. 根据权利要求2所述的像素驱动电路，其中，所述升压模块还包括：
    第二升压晶体管，所述第二升压晶体管的漏极电性连接于所述第一升压晶体管的所述源极，所述第二升压晶体管的源极电性连接至所述升压模块的所述输入端，所述第二升压晶体管的栅极加载第二升压控制信号，所述第二升压晶体管在所述第一阶段和所述第二阶段均开启；
    其中，所述第一升压晶体管的所述栅极电性连接至所述驱动晶体管的所述栅极。
  4. 根据权利要求2所述的像素驱动电路，其中，所述第一升压晶体管的栅极电性连接至不同于所述驱动晶体管的所述栅极的升压控制线以被加载第一升压控制信号，所述第一升压控制信号为发光控制信号。
  5. 根据权利要求2所述的像素驱动电路，其中，还包括：
    第二电容，所述第二电容的第一极板电性连接于所述第一电容的所述第二极板，所述第二电容的第二极板电性连接于所述驱动晶体管的所述源极或者漏极。
  6. 根据权利要求1所述的像素驱动电路，其中，所述升压模块还包括：
    第三电容；
    升压开关，与所述第三电容串联于所述驱动晶体管的所述栅极和所述驱动晶体管的所述源极之间；
    其中，在所述第一阶段和位于所述第一阶段之前的第三阶段，所述升压开关开启以控制所述驱动晶体管的所述栅极由所述第三阶段的第三电压上升至所述第一阶段的所述第一电压。
  7. 根据权利要求1所述的像素驱动电路，其中，还包括：
    复位晶体管，所述复位晶体管的源极电性连接于复位线，所述复位晶体管的漏极电性连接于所述驱动晶体管的所述源极，所述复位晶体管的栅极加载复位控制信号。
  8. 一种显示面板，其中，包括多个如权利要求1所述的像素驱动电路。
  9. 根据权利要求8所述的显示面板，其中，还包括：
    数据产生芯片，位于多个所述像素驱动电路的至少一侧，多条所述数据线电性连接至所述数据产生芯片以获取数据信号。
  10. 根据权利要求9所述的显示面板，其中，远离所述数据产生芯片的所述像素驱动电路相对于靠近所述数据产生芯片的所述像素驱动电路，对应的所述数据信号的电压值的绝对值较大。
  11. 根据权利要求9所述的显示面板，其中，还包括：
    信号产生芯片，位于多个所述像素驱动电路的至少一侧，多个所述升压模块的输入端电性连接至所述信号产生芯片以获取所述升压输入信号；
    其中，所述升压输入信号在所述第一阶段具有第一升压输入电压，所述升压输入信号在所述第二阶段具有第二升压输入电压，所述第二升压输入电压大于所述第一升压输入电压；
    其中，远离所述数据产生芯片的所述像素驱动电路相对于靠近所述数据产生芯片的所述像素驱动电路，对应的所述第二升压输入电压与对应的所述第一升压输入电压的差值较大。
  12. 一种显示面板，其中，包括像素驱动电路，所述像素驱动电路包括：
    第一晶体管，与发光元件串联于第一电源线和第二电源线之间，所述第一晶体管的源极电性连接于所述发光元件；
    第二晶体管，所述第二晶体管的源极电性连接于第一信号线，所述第二晶体管的漏极电性连接于所述第一晶体管的所述栅极，所述第二晶体管的栅极电性连接于第二信号线；
    第一模块，所述第一模块的输入端电性连接于第三信号线，所述第一模块的输出端电性连接于所述第一晶体管的所述栅极，所述第一模块的控制端电性连接于第四信号线。
  13. 根据权利要求12所述的显示面板，其中，所述第一模块包括：
    第一电容，所述第一电容的第一极板电性连接于所述第一晶体管的所述栅极以作为所述第一模块的所述输出端；
    第三晶体管，所述第三晶体管的漏极电性连接于所述第一电容的第二极板，所述第三晶体管的源极电性连接至所述第一模块的所述输入端，所述第三晶体管的栅极电性连接于所述第四信号线。
  14. 根据权利要求13所述的显示面板，其中，所述第一模块还包括：
    第四晶体管，所述第四晶体管的漏极电性连接于所述第三晶体管的所述漏极，所述第四晶体管的源极电性连接至所述第一模块的所述输入端，所述第四晶体管的栅极电性连接于不同于所述第一晶体管的所述栅极的第五信号线；
    其中，所述第三晶体管的所述栅极电性连接至所述第一晶体管的所述栅极。
  15. 根据权利要求13所述的显示面板，其中，所述像素驱动电路还包括：
    第二电容，所述第二电容的第一极板电性连接于所述第一电容的所述第二极板，所述第二电容的第二极板电性连接于所述第一晶体管的所述源极或者漏极。
  16. 根据权利要求12所述的显示面板，其中，所述第一模块还包括：
    第三电容；
    第一开关，与所述第三电容串联于所述第一晶体管的所述栅极和所述第一晶体管的所述源极之间，所述第一开关用于控制所述第三电容电性连接于所述第一晶体管的所述栅极和所述第一晶体管的所述源极之间。
  17. 根据权利要求12所述的显示面板，其中，还包括：
    第五晶体管，所述第五晶体管的源极电性连接于第六信号线，所述第五晶体管的漏极电性连接于所述第一晶体管的所述源极，所述第五晶体管的栅极电性连接于第七信号线。
  18. 根据权利要求12所述的显示面板，其中，包括多个所述像素驱动电路，还包括：
    数据产生芯片，位于多个所述像素驱动电路的至少一侧，多条所述数据线电性连接至所述数据产生芯片以获取数据信号。
  19. 根据权利要求18所述的显示面板，其中，远离所述数据产生芯片的所述像素驱动电路相对于靠近所述数据产生芯片的所述像素驱动电路，对应的所述数据信号的电压值的绝对值较大。
  20. 根据权利要求18所述的显示面板，其中，还包括：
    信号产生芯片，位于多个所述像素驱动电路的至少一侧，多个所述升压模块的输入端电性连接至所述信号产生芯片以获取所述升压输入信号；
    其中，所述升压输入信号在所述第一阶段具有第一升压输入电压，所述升压输入信号在所述第二阶段具有第二升压输入电压，所述第二升压输入电压大于所述第一升压输入电压；
    其中，远离所述数据产生芯片的所述像素驱动电路相对于靠近所述数据产生芯片的所述像素驱动电路，对应的所述第二升压输入电压与对应的所述第一升压输入电压的差值较大。
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CN113421525A (zh) * 2021-06-21 2021-09-21 福州京东方光电科技有限公司 像素驱动电路、显示面板、显示设备和驱动控制方法

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JP2011107187A (ja) * 2009-11-12 2011-06-02 Sony Corp 表示装置、表示装置の駆動方法および電子機器
JP2013092681A (ja) * 2011-10-26 2013-05-16 Canon Inc 表示装置
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