WO2023230888A1 - 发光基板及其制备方法、发光装置 - Google Patents

发光基板及其制备方法、发光装置 Download PDF

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Publication number
WO2023230888A1
WO2023230888A1 PCT/CN2022/096384 CN2022096384W WO2023230888A1 WO 2023230888 A1 WO2023230888 A1 WO 2023230888A1 CN 2022096384 W CN2022096384 W CN 2022096384W WO 2023230888 A1 WO2023230888 A1 WO 2023230888A1
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WIPO (PCT)
Prior art keywords
electrode
layer
light
wiring
display area
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PCT/CN2022/096384
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English (en)
French (fr)
Inventor
张星
徐攀
韩影
罗程远
赵冬辉
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001570.5A priority Critical patent/CN117501841A/zh
Priority to PCT/CN2022/096384 priority patent/WO2023230888A1/zh
Publication of WO2023230888A1 publication Critical patent/WO2023230888A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of optoelectronic technology, and in particular to a light-emitting substrate, a preparation method thereof, and a light-emitting device.
  • OLED Organic Light Emitting Diode
  • the present disclosure provides a light-emitting substrate, which includes a display area and a frame area located on one side of the display area.
  • the light-emitting substrate includes: a base substrate, a functional layer provided on one side of the base substrate, and a stacked arrangement. a first insulating layer and a first electrode layer on the side of the functional layer facing away from the base substrate, the first insulating layer being located between the functional layer and the first electrode layer;
  • the functional layer includes: a first electrode wiring located in the display area, an electrode signal bus located in the frame area, and an electrode signal lead connecting the first electrode wiring and the electrode signal bus;
  • the first electrode layer and the first electrode trace are connected through a first via hole provided on the first insulation layer.
  • the functional layer further includes: data signal leads located in the frame area, and data traces located in the display area, the data signal leads are connected to the data traces ;
  • the orthographic projections of the data signal leads and the electrode signal leads respectively overlap on the base substrate, and the data signal leads and the electrode signal leads are respectively located on different film layers.
  • the functional layer includes a first wiring layer, a second insulation layer, a second wiring layer, a third insulation layer and a third wiring layer that are stacked in sequence.
  • An insulating layer is provided on the side of the third wiring layer facing away from the base substrate;
  • the data signal lead is located on the second wiring layer, and the electrode signal lead is located on the third wiring layer.
  • the electrode signal bus is located on the first wiring layer, and the third wiring layer further includes: a third wiring layer connected to one end of the electrode signal lead close to the electrode signal bus.
  • An adapter part, the first adapter part and the electrode signal bus are connected through a second via hole provided on the third insulating layer and the second insulating layer.
  • the second via hole includes a third via hole provided on the third insulating layer, and a fourth via hole provided on the second insulating layer;
  • the second wiring layer also includes a second transfer part located in the frame area, and the second transfer part is connected to the first transfer part through the third via hole.
  • the connecting portion is connected to the electrode signal bus through the fourth via hole.
  • the third wiring layer further includes: a third transfer part connected to one end of the electrode signal lead close to the first electrode wiring;
  • One end of the first electrode trace close to the electrode signal bus extends to the frame area and is connected to a fourth transfer part. Both the first electrode trace and the fourth transfer part are located on the The second wiring layer;
  • the third transfer part and the fourth transfer part are connected through a fifth via hole provided on the third insulation layer.
  • the functional layer includes a first thin film transistor located in the display area, and the data wiring and the source and drain of the first thin film transistor are located in the second wiring layer, the data wiring is connected to the source or drain of the first thin film transistor;
  • the extending direction of the data wiring is the same as the extending direction of the first electrode wiring.
  • the functional layer includes a second thin film transistor located in the display area
  • the first wiring layer also includes a gate wiring located in the display area
  • the second thin film The gate electrode of the transistor, the gate wiring is connected to the gate electrode of the second thin film transistor.
  • the functional layer includes a third thin film transistor located in the display area
  • the third wiring layer also includes a plurality of second electrodes located in the display area, the second electrodes are connected to The third thin film transistor is connected.
  • the first insulating layer is reused as a pixel defining layer, the pixel defining layer has a plurality of pixel openings, and the orthographic projection of the pixel openings on the base substrate is located at The second electrode is within the orthographic projection range on the base substrate;
  • the light-emitting substrate further includes: a light-emitting layer provided in the pixel opening, and the first electrode layer is provided on a side of the light-emitting layer facing away from the base substrate.
  • the data signal lead and the electrode signal bus are located on the same side of the display area.
  • the extension direction of the first electrode wire is different from the extension direction of the electrode signal bus; or, the extension direction of the first electrode wire is different from the extension direction of the electrode signal bus.
  • the extension directions are perpendicular to each other.
  • the functional layer further includes: data signal leads located in the frame area, and data traces located in the display area, the data signal leads are connected to the data traces ;
  • the orthographic projections of the data signal leads and the electrode signal leads on the base substrate do not overlap, and the data signal leads and the electrode signal leads are arranged on the same layer.
  • the data signal leads and the electrode signal bus are respectively located on different sides of the display area.
  • the first electrode layer and the electrode signal bus are connected through a sixth via hole provided on the first insulation layer.
  • the present disclosure provides a light-emitting device, including the light-emitting substrate described in any one of the above.
  • the present disclosure provides a method for preparing a light-emitting substrate.
  • the light-emitting substrate includes a display area and a frame area located on one side of the display area.
  • the preparation method includes:
  • a functional layer is formed on one side of the base substrate.
  • the functional layer includes: a first electrode trace located in the display area, an electrode signal bus located in the frame area, and a first electrode trace connected to the first electrode trace. and electrode signal leads of the electrode signal bus;
  • a first insulating layer and a first electrode layer are formed in sequence on the side of the functional layer facing away from the base substrate.
  • the first insulating layer is located between the functional layer and the first electrode layer.
  • An electrode layer is connected to the first electrode trace through a first via hole provided on the first insulation layer.
  • Figure 1 schematically shows a schematic plan view of a light-emitting substrate in the related art
  • Figure 2 schematically shows a schematic plan view of the first light-emitting substrate provided by the present disclosure
  • Figure 3 schematically shows a schematic cross-sectional structural view of the first light-emitting substrate provided by the present disclosure at the L1 position;
  • Figure 4 schematically shows a schematic cross-sectional structural view of the first light-emitting substrate provided by the present disclosure at the L2 position;
  • Figure 5 schematically shows a schematic cross-sectional structural view of the first light-emitting substrate provided by the present disclosure at the L3 position;
  • Figure 6 schematically shows a schematic cross-sectional structural view of the first light-emitting substrate provided by the present disclosure at the L4 position;
  • Figure 7 schematically shows a schematic plan view of the second light-emitting substrate provided by the present disclosure
  • FIG. 8 schematically shows a schematic cross-sectional structural view of the second light-emitting substrate provided by the present disclosure at position L5.
  • the cathode is usually made of materials with high transmittance, such as metal oxides such as indium zinc oxide. Due to the large resistance of metal oxides, severe IR drop occurs on the cathode, which affects display uniformity.
  • an auxiliary cathode made of metal is generally provided, and the auxiliary electrode and the cathode are connected through via holes.
  • FIG. 1 a schematic plan view of a light-emitting substrate in the related art is schematically shown.
  • the cathode signal input bus 11 is connected to the signal input terminal VSS, and the cathode signal input bus 11 and the cathode 12 pass through The hole 10 is connected, and the cathode 12 and the auxiliary cathode 13 are connected through the via hole 14 . Therefore, the transmission path of the voltage signal VSS on the auxiliary cathode 13 is: signal input terminal VSS ⁇ cathode signal input bus 11 ⁇ via hole 10 ⁇ cathode 12 ⁇ via hole 14 ⁇ auxiliary cathode 13.
  • the signal on the auxiliary cathode 13 comes from the cathode 12, and the cathode 12 itself has severe IR drop. Therefore, the signal transmission path shown in Figure 1 affects the effect of the auxiliary cathode 13 on improving IR drop.
  • the present disclosure provides a light-emitting substrate.
  • a schematic plan view of the light-emitting substrate provided by the present disclosure is schematically shown, as shown in Figure 2 or Figure 7.
  • the light-emitting substrate includes a display area and a frame area located on one side of the display area.
  • the light-emitting substrate includes: a base substrate 31 , a functional layer 32 disposed on one side of the base substrate 31 , and a first insulating layer laminated on a side of the functional layer 32 away from the base substrate 31 .
  • layer 33 and the first electrode layer 34 the first insulating layer 33 is located between the functional layer 32 and the first electrode layer 34 .
  • the functional layer 32 includes: a first electrode trace 21 located in the display area, an electrode signal bus 22 located in the frame area, and an electrode signal lead 23 connecting the first electrode trace 21 and the electrode signal bus 22 .
  • the first electrode layer 34 and the first electrode trace 21 are connected through the first via hole H1 provided on the first insulating layer 33 .
  • the material of the first electrode layer 34 can be, for example, transparent metal oxide materials such as indium tin oxide and indium zinc oxide, which can improve the light transmittance of the top-emission light-emitting substrate.
  • the material of the first electrode layer 34 can also be a metal material, which is not limited in this disclosure.
  • the material of the first electrode trace 21 may be a metal material with high conductivity, for example. Due to the high conductivity of metal materials, by arranging the first electrode trace 21 to connect to the first electrode layer 34, the IR drop on the first electrode layer 34 can be improved and the uniformity of the signal on the first electrode layer 34 can be improved, thereby Improve display uniformity.
  • the material of the first electrode trace 21 can also be a metal oxide material, which is not limited in this disclosure.
  • the electrode signal bus 22 can also be connected to the transparent electrode signal input terminal for transmitting the transparent electrode signal input from the transparent electrode signal input terminal.
  • the electrode signal bus 22 can directly transmit the transparent electrode signal to the first electrode trace 21, and then the electrode signal bus 22 can directly transmit the transparent electrode signal to the first electrode trace 21.
  • the first electrode trace 21 is transmitted to the first electrode layer 34 . Since the transparent electrode signal on the first electrode trace 21 is directly input from the electrode signal bus 22, and the impedance of the first electrode trace 21 is small, the IR drop of the transparent electrode signal transmitted on the first electrode trace 21 is small. , therefore, the uniformity of the transparent electrode signal on the first electrode trace 21 can be improved, thereby improving the uniformity of the transparent electrode signal on the first electrode layer 34, improving the display uniformity, and improving the IR drop effect of the auxiliary electrode.
  • the first electrode layer 34 may serve as a cathode layer, and accordingly, the first electrode wiring 21 may serve as an auxiliary cathode, which is not limited in this disclosure.
  • the first electrode layer 34 may be an integral structure connected over the entire surface, and the orthographic projection of the first electrode layer 34 on the base substrate 31 at least covers the display area and part of the frame area.
  • the contact resistance between 21 is large or even the contact fails, which further affects the transmission of the transparent electrode signal from the electrode signal bus 22 to the first electrode layer 34 and affects the uniformity of the transparent electrode signal on the first electrode layer 34 .
  • the first electrode layer 34 and the electrode signal bus 22 are connected through the sixth via hole H6 provided on the first insulation layer 33 .
  • the electrode signal bus 22 can directly transmit the transparent electrode signal to the first electrode layer 34, increasing the transmission of the transparent electrode signal to the first electrode layer 34. transmission channel, thereby further improving the uniformity of the transparent electrode signal on the first electrode layer 34 and improving the display uniformity.
  • the size of the sixth via hole H6 may be larger than the size of the first via hole H1 in the plane direction where the base substrate 31 is located. Since the size of the sixth via H6 is larger, the overlap area between the first electrode layer 34 and the electrode signal bus 22 can be increased, the contact resistance can be reduced, and the contact resistance between the first electrode layer 34 and the electrode signal bus 22 can be ensured. Valid connection.
  • the functional layer 32 may also include data signal leads 24 located in the frame area, and data traces 25 located in the display area.
  • the data signal lead 24 is connected to the data wiring 25.
  • the data signal lead 24 is used to provide a data signal to the data wiring 25.
  • the light-emitting device in the light-emitting substrate emits light driven by the data signal.
  • the data signal leads 24 may be distributed axially symmetrically.
  • the extension direction of the symmetry axis may be parallel to the extension direction of the data trace 25 .
  • the electrode signal leads 23 and the data signal leads 24 located in the frame area can be arranged in various ways. They can be arranged on the same layer, or they can be located on different film layers. This disclosure does not limit this.
  • the orthographic projections of the data signal leads 24 and the electrode signal leads 23 on the base substrate 31 overlap, that is, the data signal leads 24 are on the base substrate 31
  • the orthographic projection of the electrode signal lead 23 overlaps with the orthographic projection of the electrode signal lead 23 on the base substrate 31 .
  • the data signal leads 24 and the electrode signal leads 23 are respectively located on different film layers.
  • the data signal lead 24 and the electrode signal lead 23 are respectively located on different film layers, short circuits caused by overlapping can be avoided, and the lateral coupling capacitance between the data signal lead 24 and the electrode signal lead 23 can also be reduced, reducing the mutual interaction between the data signal lead 24 and the electrode signal lead 23. signal interference.
  • the data signal leads 24 and the electrode signal leads 23 are overlapped with each other in different film layers, which can reduce the space occupied in the frame area, thereby realizing a narrow frame light-emitting substrate.
  • the data signal lead 24 and the electrode signal bus 22 may be located on the same side of the display area.
  • the data signal lead 24 and the electrode signal bus 22 are both located on the lower side of the display area, that is, the lower frame area.
  • the data signal leads 24 and the electrode signal bus 22 can be located on different film layers and overlapped. As shown in FIG. 2 , the orthographic projection of the data signal lead 24 on the base substrate 31 overlaps with the orthographic projection of the electrode signal bus 22 on the base substrate 31 . The data signal lead 24 and the electrode signal bus 22 are located at different locations respectively. film layer.
  • the extension direction of the first electrode trace 21 and the extension direction of the electrode signal bus 22 may be different.
  • the extension direction of the first electrode trace 21 and the extension direction of the electrode signal bus 22 are perpendicular to each other.
  • the first electrode wiring 21 extends along the column direction
  • the electrode signal bus line 22 extends along the row direction.
  • first electrode wiring 21 extends along the column direction
  • the voltage drop in the column direction can be improved.
  • the electrode signal bus 22 extends along the row direction
  • multiple first electrode traces 21 can be arranged along the row direction and connected to the electrode signal bus 22 respectively, thereby improving the voltage drop in the row direction and increasing the transparent electrode signal.
  • the uniformity in all directions on the first electrode trace 21 improves the uniformity of the transparent electrode signal in all directions on the first electrode layer 34 and improves the display uniformity.
  • the functional layer 32 may include a first wiring layer 35 , a second insulation layer 36 , a second wiring layer 37 , a third insulation layer 38 and a third wiring layer that are stacked in sequence. 39.
  • the first insulating layer 33 is provided on the side of the third wiring layer 39 facing away from the base substrate 31.
  • the data signal leads 24 and the electrode signal leads 23 are arranged in different layers, optionally, the data signal leads 24 can be located on the second wiring layer 37 and the electrode signal leads 23 can be located on the third wiring layer 39 .
  • the electrode signal lead 23 is located on the side of the data signal lead 24 facing away from the first wiring layer 35, which can reduce the The coupling capacitance between the electrode signal lead 23 and the first wiring layer 35 prevents signal interference between the electrode signal lead 23 and the first wiring layer 35 .
  • the third insulating layer 38 may include a stacked passivation layer 381 and a planarization layer 382 , and the planarization layer 382 is provided on a side of the passivation layer 381 facing away from the base substrate 31 .
  • the flat layer 382 of organic material can be made with a larger thickness
  • the flat layer 382 with a larger thickness can further increase the longitudinal distance between the data signal lead 24 and the electrode signal lead 23 and further reduce the distance between the data signal lead 24 and the electrode signal lead 23 .
  • the material of the first wiring layer 35 may include one or more of metal materials and metal oxide materials.
  • the material of the second wiring layer 37 may include one or more of metal materials and metal oxide materials.
  • the material of the third wiring layer 39 may include one or more of metal materials and metal oxide materials.
  • including one or more of metal materials and metal oxide materials means including metal materials, or including metal oxide materials, or including metal materials and metal oxide materials.
  • metal materials include copper, aluminum, magnesium, molybdenum, gold, silver, etc.
  • metal oxide materials include indium tin oxide, etc.
  • the resistance of the electrode signal lead 23 can be reduced.
  • the electrode signal bus 22 may be located on the first wiring layer 35 .
  • the third wiring layer 39 can also include: an end of the electrode signal lead 23 close to the electrode signal bus 22
  • the connected first transfer part A1 is connected to the electrode signal bus 22 through the second via hole H2 provided on the third insulating layer 38 and the second insulating layer 36 .
  • the size of the second via hole H2 may be larger than the size of the first via hole H1 in the plane direction where the base substrate 31 is located. Since the size of the second via hole H2 is larger, the overlapping area between the first adapter part A1 and the electrode signal bus 22 can be increased, the contact resistance can be reduced, and the effective connection between the electrode signal lead 23 and the electrode signal bus 22 can be ensured. .
  • the second via hole H2 may include a third via hole H3 provided on the third insulating layer 38 and a fourth via hole H4 provided on the second insulating layer 36 .
  • the second wiring layer 37 may also include a second transfer part A2 located in the frame area. The second transfer part A2 is connected to the first transfer part A1 through the third via H3. The second transfer part A2 It is connected to the electrode signal bus 22 through the fourth via hole H4.
  • the second adapter part A2 and the first adapter part A1 and the electrode signal bus 22 located on both sides of the second adapter part A2 pass through respectively.
  • hole connection that is, the second transfer part A2 and the first transfer part A1 are connected through the third via hole H3
  • the second transfer part A2 and the electrode signal bus 22 are connected through the fourth via hole H4
  • the third via hole H3 is connected with
  • the depth of the fourth via hole H4 is smaller than the depth of the second via hole H2, which can reduce the process complexity of preparing the via hole, increase the effective contact area between the first transfer part A1 and the electrode signal bus 22, and reduce the contact resistance. .
  • the third wiring layer 39 may also include: close to the electrode signal lead 23 One end of the first electrode trace 21 is connected to the third adapter part A3.
  • one end of the first electrode trace 21 close to the electrode signal bus 22 extends to the frame area and is connected to the fourth transfer part A4.
  • the first electrode trace 21 and the fourth transfer part A4 are both located on the second trace. Layer 37.
  • the third transfer part A3 and the fourth transfer part A4 may be connected through the fifth via hole H5 provided on the third insulation layer 38.
  • the size of the fifth via hole H5 is larger than the size of the first via hole H1 in the plane direction of the base substrate 31 . Due to the larger size of the fifth via hole H5, the overlapping area of the third transfer part A3 and the fourth transfer part A4 can be increased, the contact resistance can be reduced, and the connection between the first electrode trace 21 and the electrode signal lead 23 can be ensured. effective connection between them.
  • the third adapter part A3 and the fourth adapter part A4 may be disposed in the packaging area close to the boundary line between the display area and the frame area.
  • the first via hole H1 can penetrate the first insulating layer 33 and the third insulating layer 38 to realize the connection between the first electrode layer 34 and the first insulating layer 38.
  • the via holes between the electrode traces 21 are connected.
  • the first via hole H1 is a deep hole.
  • a fifth transfer part A5 may be provided on the third wiring layer 39 , so that the first electrode layer 34 and the fifth transfer part A5 are connected through the first via hole H1 , and the fifth transfer part A5 is connected to the first electrode trace 21 through the seventh via hole H7 provided on the third insulating layer 38 .
  • the process complexity of preparing via holes can be reduced, the effective contact area between the first electrode layer 34 and the first electrode trace 21 can be increased, and the contact resistance can be reduced.
  • a light-emitting layer material may also be provided between the first insulating layer 33 and the first electrode layer 34 .
  • a groove may be first formed on the side of the fifth adapter part A5, and then a sputtering process may be used to form the first electrode layer 34, so that the first electrode layer 34 is formed in the side groove of the fifth adapter part A5, thereby realizing the first electrode layer 34.
  • the third wiring layer 39 includes a first conductive layer 391 and a second conductive layer 392, and the second conductive layer 392 is located on the A conductive layer 391 is on a side facing away from the base substrate 31 .
  • the material of the first conductive layer 391 may include metal oxides such as indium tin oxide, and the material of the second conductive layer 392 may include metal oxides such as indium tin oxide and metals.
  • the first electrode layer 34 and the electrode signal bus 22 are connected through the sixth via H6 provided on the first insulating layer 33 .
  • the first adapter part A1 and the second adapter part A2 are connected through the third via hole H3 provided on the third insulating layer 38 , the second transfer part A2 and the electrode signal bus 22 are connected through the fourth via hole H4 provided on the second insulation layer 36 .
  • the functional layer 32 may include a plurality of thin film transistors located in the display area. Thin film transistors are used to drive the light-emitting devices in the light-emitting substrate to emit light under the control of external signals.
  • the functional layer 32 includes a first thin film transistor (not shown in the figure) located in the display area.
  • the data wiring 25 and the source and drain of the first thin film transistor are located in the second wiring layer 37 .
  • Line 25 is connected to the source or drain of the first thin film transistor.
  • the data signal lead 24 , the data wiring 25 , the first electrode wiring 21 and the source and drain of the first thin film transistor are all located on the same film layer, that is, the second wiring layer 37 .
  • the extension direction of the data trace 25 is in line with the first electrode trace 21
  • the extending directions of the data traces 25 and the extending directions of the first electrode traces 21 may be parallel to each other.
  • extension direction of the data trace 25 and the extension direction of the first electrode trace 21 may also be different, as long as it is ensured that the data trace 25 and the first electrode trace 21 do not intersect.
  • the functional layer 32 includes a second thin film transistor (not shown in the figure) located in the display area, and the first wiring layer 35 may also include a gate line 26 located in the display area, and a gate of the second thin film transistor.
  • the gate trace 26 is connected to the gate of the second thin film transistor.
  • the electrode signal bus 22 , the gate wiring 26 and the gate of the second thin film transistor are all located on the same film layer, that is, the first wiring layer 35 .
  • the functional layer 32 includes a third thin film transistor (not shown in the figure) located in the display area, and the third wiring layer 39 may also include a plurality of second electrodes 27 located in the display area. The second electrode 27 is connected to the third thin film transistor.
  • the source and drain of the third thin film transistor may be located on the second wiring layer 37, the second electrode 27 is located on the third wiring layer 39, and the second electrode 27 is connected to the source or drain of the third thin film transistor.
  • the poles may be connected through vias provided on the third insulating layer 38 .
  • the first electrode layer 34 is a cathode layer
  • the second electrode 27 can be an anode, which is not limited in this disclosure.
  • the first electrode layer 34 may be an anode layer
  • the second electrode 27 may be a cathode.
  • the second electrode 27 and the electrode signal lead 23 are both located on the same film layer, that is, the third wiring layer 39 .
  • the first thin film transistor, the second thin film transistor and the third thin film transistor may be different from each other, or two of them may be the same thin film transistor, or three of them may be the same thin film transistor, which is not limited in this disclosure.
  • the third wiring layer 39 includes a first conductive layer 391 and a second conductive layer 392
  • the second conductive layer 392 is located on a side of the first conductive layer 391 away from the base substrate 31, and the material of the second conductive layer 392 includes metal.
  • the metal can be located on the side surface of the second conductive layer 392 facing away from the base substrate 31, which can improve the reflectivity of light incident on the metal surface, improve the reflectivity of the second electrode, and improve top-emission luminescence. The light extraction efficiency of the device.
  • the first insulating layer 33 can be reused as a pixel defining layer.
  • the pixel defining layer has a plurality of pixel openings.
  • the orthographic projection of the pixel openings on the base substrate 31 is located on the second electrode 27 on the base substrate 31 . within the orthographic projection range.
  • the light-emitting substrate may further include: at least a light-emitting layer 61 provided within the pixel opening, and the first electrode layer 34 is provided on a side of the light-emitting layer 61 facing away from the base substrate 31 .
  • the second electrode 27 , the light-emitting layer 61 and the first electrode layer 34 located in a pixel opening constitute a light-emitting device.
  • the light-emitting layer 61 may include one or more color light-emitting layers such as a white light-emitting layer, a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer.
  • the electrode signal bus line 22 and the gate wiring are insulated from each other.
  • the second transfer part A2 the data signal lead 24 and the fourth transfer part A4 located in the frame area are all insulated from each other, and the first electrode line 21 and the data line located in the display area are insulated from each other.
  • the wires 25 are insulated from each other.
  • the second electrode 27 and the electrode signal lead 23 are insulated from each other.
  • the orthographic projections of the data signal leads 24 and the electrode signal leads 23 on the base substrate 31 do not overlap, and the data signal leads 24 and the electrode signal leads 23 do not overlap.
  • Leads 23 are arranged on the same layer.
  • the data signal lead 24 and the electrode signal bus 22 may be located on different sides of the display area.
  • the data signal lead 24 is located on the lower side of the display area, and the electrode signal bus 22 is located on the upper, left, and right sides of the display area. That is, the data signal lead 24 is located on the lower frame area, and the electrode signal bus 22 is located on the upper, left, and right sides of the display area.
  • the bus 22 is located in the upper bezel area, the left bezel area and the right bezel area.
  • the electrode signal bus 22 since the electrode signal bus 22 is located on the upper, left and right sides of the display area, the electrode signal bus 22 forms a semi-closed structure, which can shield interference from external signals and improve the stability of the display image.
  • the data signal lead 24 and the electrode signal bus 22 may also be located on opposite sides of the display area.
  • the data signal lead 24 is located on the lower side of the display area
  • the electrode signal bus 22 is located on the upper side of the display area.
  • the orthographic projections of the data signal leads 24 and the electrode signal bus 22 on the base substrate 31 do not overlap.
  • the data signal leads 24 and the electrode signal bus 22 can be located on the same or different film layers. This disclosure is suitable for This is not a limitation.
  • the present disclosure provides a light-emitting device, including the light-emitting substrate provided in any one of the items.
  • the light-emitting device includes the above-mentioned light-emitting substrate, those skilled in the art can understand that the light-emitting device has the advantages of the light-emitting substrate provided by the present disclosure, which will not be described again here.
  • the light-emitting device in this embodiment can be: a display panel, electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a virtual reality device, an augmented reality device, an under-screen camera device, and a navigator. Any products or components with 2D or 3D display capabilities.
  • the data signal leads 24 in the light-emitting substrate and the leads connecting the electrode signal bus 22 can be extended to the binding area, and the transparent electrode signal input end is located in the binding area.
  • the binding area is used to bind the flexible circuit board, through which the driver chip can be connected.
  • the driver chip can provide data signals and transparent electrode signals, etc.
  • the display can be more significantly improved. uneven phenomenon.
  • the present disclosure provides a method for preparing a light-emitting substrate.
  • the light-emitting substrate includes a display area and a frame area located on one side of the display area.
  • the preparation method includes:
  • Step S01 Provide a base substrate.
  • Step S02 Form a functional layer on one side of the base substrate.
  • the functional layer includes: a first electrode trace located in the display area, an electrode signal bus located in the frame area, and an electrode signal connecting the first electrode trace and the electrode signal bus. lead.
  • Step S03 Form a first insulating layer and a first electrode layer in sequence on the side of the functional layer facing away from the base substrate.
  • the first insulating layer is located between the functional layer and the first electrode layer, and the first electrode layer and the first electrode are routed connected through a first via hole provided on the first insulating layer.
  • the light-emitting substrate provided by any one of the above can be prepared using the preparation method provided by the present disclosure.
  • a light-emitting substrate, a preparation method thereof, and a light-emitting device provided by the present disclosure have been introduced in detail above. Specific examples are used in this article to illustrate the principles and implementations of the present disclosure. The description of the above embodiments is only used to help understanding. The methods and core ideas of the present disclosure; at the same time, for those of ordinary skill in the field, there will be changes in the specific implementation methods and application scope based on the ideas of the present disclosure. In summary, the contents of this specification should not understood as limitations of this disclosure.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the element claim enumerating several means, several of these means may be embodied by the same item of hardware.
  • the use of the words first, second, third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

发光基板及其制备方法、发光装置，涉及显示技术领域。发光基板包括显示区域以及位于显示区域一侧的边框区域，发光基板包括：衬底基板，设置在衬底基板一侧的功能层，以及层叠设置在功能层背离衬底基板一侧的第一绝缘层和第一电极层，第一绝缘层位于功能层与第一电极层之间；其中，功能层包括：位于显示区域的第一电极走线，位于边框区域的电极信号总线，以及连接第一电极走线和电极信号总线的电极信号引线；第一电极层与第一电极走线通过设置在第一绝缘层上的第一过孔连接。

Description

发光基板及其制备方法、发光装置 技术领域
本公开涉及光电技术领域，特别是涉及一种发光基板及其制备方法、发光装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光器件，具有自发光、高对比度、低功耗、宽色域、轻薄化、可异形化等优点。
概述
本公开提供了一种发光基板，包括显示区域以及位于所述显示区域一侧的边框区域，所述发光基板包括：衬底基板，设置在所述衬底基板一侧的功能层，以及层叠设置在所述功能层背离所述衬底基板一侧的第一绝缘层和第一电极层，所述第一绝缘层位于所述功能层与所述第一电极层之间；
其中，所述功能层包括：位于所述显示区域的第一电极走线，位于所述边框区域的电极信号总线，以及连接所述第一电极走线和所述电极信号总线的电极信号引线；所述第一电极层与所述第一电极走线通过设置在所述第一绝缘层上的第一过孔连接。
在一种可选的实现方式中，所述功能层还包括：位于所述边框区域的数据信号引线，以及位于所述显示区域的数据走线，所述数据信号引线与所述数据走线连接；
其中，所述数据信号引线和所述电极信号引线分别在所述衬底基板上的正投影有交叠，所述数据信号引线和所述电极信号引线分别位于不同的膜层。
在一种可选的实现方式中，所述功能层包括依次层叠设置的第一走线层、第二绝缘层、第二走线层、第三绝缘层和第三走线层，所述第一绝缘层设置在所述第三走线层背离所述衬底基板的一侧；
其中，所述数据信号引线位于所述第二走线层，所述电极信号引线位于所述第三走线层。
在一种可选的实现方式中，所述电极信号总线位于所述第一走线层，所述第三走线层还包括：与所述电极信号引线靠近所述电极信号总线一端连接的第一转接部，所述第一转接部与所述电极信号总线通过设置在所述第三绝缘层和所述第二绝缘层上的第二过孔连接。
在一种可选的实现方式中，所述第二过孔包括设置在所述第三绝缘层上的第三过孔，以及设置在所述第二绝缘层上的第四过孔；
所述第二走线层还包括位于所述边框区域的第二转接部，所述第二转接部与所述第一转接部通过所述第三过孔连接，所述第二转接部与所述电极信号总线通过所述第四过孔连接。
在一种可选的实现方式中，所述第三走线层还包括：与所述电极信号引线靠近所述第一电极走线一端连接的第三转接部；
所述第一电极走线靠近所述电极信号总线的一端延伸至所述边框区域，且与第四转接部连接，所述第一电极走线和所述第四转接部均位于所述第二走线层；
其中，所述第三转接部与所述第四转接部通过设置在所述第三绝缘层上的第五过孔连接。
在一种可选的实现方式中，所述功能层包括位于显示区域的第一薄膜晶体管，所述数据走线以及所述第一薄膜晶体管的源极和漏极均位于所述第二走线层，所述数据走线与所述第一薄膜晶体管的源极或漏极连接；
其中，所述数据走线的延伸方向与所述第一电极走线的延伸方向相同。
在一种可选的实现方式中，所述功能层包括位于显示区域的第二薄膜晶体管，所述第一走线层还包括位于所述显示区域的栅极走线，以及所述第二薄膜晶体管的栅极，所述栅极走线与所述第二薄膜晶体管的栅极连接。
在一种可选的实现方式中，所述功能层包括位于显示区域的第三薄膜晶体管，所述第三走线层还包括位于显示区域内的多个第二电极，所述第二电极与所述第三薄膜晶体管连接。
在一种可选的实现方式中，所述第一绝缘层复用为像素界定层，所述像素界定层具有多个像素开口，所述像素开口在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影范围内；
所述发光基板还包括：设置在所述像素开口内的发光层，所述第一电极 层设置在所述发光层背离所述衬底基板的一侧。
在一种可选的实现方式中，所述数据信号引线与所述电极信号总线位于所述显示区域的同一侧。
在一种可选的实现方式中，所述第一电极走线的延伸方向与所述电极信号总线的延伸方向不同；或者，所述第一电极走线的延伸方向与所述电极信号总线的延伸方向相互垂直。
在一种可选的实现方式中，所述功能层还包括：位于所述边框区域的数据信号引线，以及位于所述显示区域的数据走线，所述数据信号引线与所述数据走线连接；
其中，所述数据信号引线和所述电极信号引线分别在所述衬底基板上的正投影无交叠，所述数据信号引线和所述电极信号引线同层设置。
在一种可选的实现方式中，所述数据信号引线与所述电极信号总线分别位于所述显示区域的不同侧。
在一种可选的实现方式中，所述第一电极层与所述电极信号总线通过设置在所述第一绝缘层上的第六过孔连接。
本公开提供了一种发光装置，包括任一项所述的发光基板。
本公开提供了一种发光基板的制备方法，所述发光基板包括显示区域以及位于所述显示区域一侧的边框区域，所述制备方法包括：
提供衬底基板；
在所述衬底基板的一侧形成功能层，所述功能层包括：位于所述显示区域的第一电极走线，位于所述边框区域的电极信号总线，以及连接所述第一电极走线和所述电极信号总线的电极信号引线；
在所述功能层背离所述衬底基板的一侧依次形成第一绝缘层和第一电极层，所述第一绝缘层位于所述功能层与所述第一电极层之间，所述第一电极层与所述第一电极走线通过设置在所述第一绝缘层上的第一过孔连接。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。需要说明的是，附图中的比例仅作为示意并不代表实际比例。
图1示意性地示出了相关技术中的一种发光基板的平面结构示意图；
图2示意性地示出了本公开提供的第一种发光基板的平面结构示意图；
图3示意性地示出了本公开提供的第一种发光基板在L1位置的剖面结构示意图；
图4示意性地示出了本公开提供的第一种发光基板在L2位置的剖面结构示意图；
图5示意性地示出了本公开提供的第一种发光基板在L3位置的剖面结构示意图；
图6示意性地示出了本公开提供的第一种发光基板在L4位置的剖面结构示意图；
图7示意性地示出了本公开提供的第二种发光基板的平面结构示意图；
图8示意性地示出了本公开提供的第二种发光基板在L5位置的剖面结构示意图。
详细描述
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在大尺寸顶发射OLED器件中，阴极通常采用透过率较高的材料，如氧化铟锌等金属氧化物。由于金属氧化物的阻抗较大，导致阴极存在严重的IR drop，进而影响显示均一性。为了解决这一问题，一般通过设置金属材质的辅助阴极，辅助电极与阴极之间通过过孔连接。
参照图1示意性地示出了相关技术中的一种发光基板的平面结构示意图， 如图1所示，阴极信号输入总线11与信号输入端VSS连接，阴极信号输入总线11与阴极12通过过孔10连接，阴极12与辅助阴极13通过过孔14连接。因此，辅助阴极13上的电压信号VSS的传输路径为：信号输入端VSS→阴极信号输入总线11→过孔10→阴极12→过孔14→辅助阴极13。由此可见，辅助阴极13上的信号来自于阴极12，而阴极12本身存在严重的IR drop，因此图1所示的信号传输路径影响辅助阴极13改善IR drop的效果。
为了提升辅助电极改善IR drop的效果，本公开提供了一种发光基板，参照图2和图7分别示意性地示出了本公开提供的发光基板的平面结构示意图，如图2或图7所示，该发光基板包括显示区域以及位于显示区域一侧的边框区域。
参照图3示意性地示出了图2所示发光基板在L1位置处的剖面结构示意图，参照图8示意性地示出了图7所示发光基板在L5位置处的剖面结构示意图。如图3或图8所示，该发光基板包括：衬底基板31，设置在衬底基板31一侧的功能层32，以及层叠设置在功能层32背离衬底基板31一侧的第一绝缘层33和第一电极层34，第一绝缘层33位于功能层32与第一电极层34之间。
其中，功能层32包括：位于显示区域的第一电极走线21，位于边框区域的电极信号总线22，以及连接第一电极走线21和电极信号总线22的电极信号引线23。
如图3或图8所示，第一电极层34与第一电极走线21通过设置在第一绝缘层33上的第一过孔H1连接。
第一电极层34的材料例如可以采用氧化铟锡、氧化铟锌等透明的金属氧化物材料，这样可以提高顶发射发光基板的光线透过率。
当然，第一电极层34的材料也可以采用金属材料，本公开对此不作限定。
第一电极走线21的材料例如可以采用导电率较高的金属材料。由于金属材料的导电率较高，通过设置第一电极走线21与第一电极层34连接，可以改善第一电极层34上的IR drop，提高第一电极层34上信号的均一性，从而提高显示均一性。
当然，第一电极走线21的材料也可以采用金属氧化物材料，本公开对此不作限定。
在具体实现中，电极信号总线22还可以连接透明电极信号输入端，用于传输透明电极信号输入端输入的透明电极信号。
本公开提供的发光基板，由于第一电极走线21通过电极信号引线23直接连接至电极信号总线22，因此，电极信号总线22可以将透明电极信号直接传输至第一电极走线21，进而由第一电极走线21传输至第一电极层34。由于第一电极走线21上的透明电极信号是由电极信号总线22直接输入，并且第一电极走线21的阻抗较小，透明电极信号在第一电极走线21上传输的IR drop较小，因此可以提高透明电极信号在第一电极走线21上的均一性，进而提高透明电极信号在第一电极层34上的均一性，提高显示均一性，提升辅助电极改善IR drop的效果。
示例性地，第一电极层34可以作为阴极层，相应地，第一电极走线21可以作为辅助阴极，本公开对此不作限定。其中，第一电极层34可以是整面连通的一体结构，第一电极层34在衬底基板31上的正投影至少覆盖显示区域和部分边框区域。
发明人发现，由于第一过孔H1位于显示区域，因此在衬底基板31所在的平面方向上，第一过孔H1的尺寸较小，这样可能导致第一电极层34与第一电极走线21之间接触电阻较大甚至接触失效，进而影响透明电极信号由电极信号总线22向第一电极层34的传输，影响透明电极信号在第一电极层34上的均一性。
可选地，如图3或图8所示，第一电极层34与电极信号总线22通过设置在第一绝缘层33上的第六过孔H6连接。
由于第一电极层34与电极信号总线22通过第六过孔H6直接连接，使得电极信号总线22可以将透明电极信号直接传输至第一电极层34，增加了透明电极信号向第一电极层34传输的通道，从而进一步提高透明电极信号在第一电极层34上的均一性，提高显示均一性。
另外，由于第六过孔H6位于边框区域，因此在衬底基板31所在的平面方向上，第六过孔H6的尺寸可以大于第一过孔H1的尺寸。由于第六过孔H6的尺寸较大，因此可以增大第一电极层34与电极信号总线22之间的搭接面积，降低接触电阻，确保第一电极层34与电极信号总线22之间的有效连接。
如图2或图7所示，功能层32还可以包括位于边框区域的数据信号引线 24，以及位于显示区域的数据走线25。数据信号引线24与数据走线25连接，数据信号引线24用于向数据走线25提供数据信号，发光基板中的发光器件在数据信号的驱动下发光。
在衬底基板31所在的平面内，数据信号引线24可以呈轴对称分布。对称轴的延伸方向可以平行于数据走线25的延伸方向。
在具体实现中，位于边框区域内的电极信号引线23与数据信号引线24的设置方式可以有多种，二者可以同层设置，也可以分别位于不同的膜层，本公开对此不作限定。
在一种可选的实现方式中，如图2所示，数据信号引线24和电极信号引线23分别在衬底基板31上的正投影有交叠，即数据信号引线24在衬底基板31上的正投影和电极信号引线23在衬底基板31上的正投影有交叠。数据信号引线24和电极信号引线23分别位于不同的膜层。
由于数据信号引线24和电极信号引线23分别位于不同的膜层，因此可以避免交叠引起的短路，还可以降低数据信号引线24与电极信号引线23之间的侧向耦合电容，减少相互之间的信号干扰。
另外，数据信号引线24和电极信号引线23在不同的膜层相互交叠设置，可以减小对边框区域的空间占用，从而实现窄边框的发光基板。
示例性地，如图2所示，数据信号引线24与电极信号总线22可以位于显示区域的同一侧。在图2中，数据信号引线24与电极信号总线22均位于显示区域的下侧，即下边框区域。
这种情况下，为了进一步减小对边框区域的空间占用，数据信号引线24和电极信号总线22可以分别位于不同的膜层且交叠设置。如图2所示，数据信号引线24在衬底基板31上的正投影和电极信号总线22在衬底基板31上的正投影有交叠，数据信号引线24和电极信号总线22分别位于不同的膜层。
本实现方式中，为了实现多条第一电极走线21与电极信号总线22之间的连接，第一电极走线21的延伸方向与电极信号总线22的延伸方向可以不同。
示例性地，如图2所示，第一电极走线21的延伸方向与电极信号总线22的延伸方向相互垂直。在图2中，第一电极走线21沿列方向延伸，电极信号总线22沿行方向延伸。
由于第一电极走线21沿列方向延伸，因此可以改善列方向上压降。另外，由于电极信号总线22沿行方向延伸，因此可以沿行方向排布多条第一电极走线21，且分别与电极信号总线22连接，从而可以改善行方向上的压降，提高透明电极信号在第一电极走线21上各个方向的均一性，提高透明电极信号在第一电极层34上各个方向的均一性，提高显示均一性。
可选地，如图3所示，功能层32可以包括依次层叠设置的第一走线层35、第二绝缘层36、第二走线层37、第三绝缘层38和第三走线层39，第一绝缘层33设置在第三走线层39背离衬底基板31的一侧。
为了实现数据信号引线24和电极信号引线23不同层设置，可选地，数据信号引线24可以位于第二走线层37，电极信号引线23可以位于第三走线层39。
由于第三走线层39位于第二走线层37背离第一走线层35的一侧，因此电极信号引线23位于数据信号引线24背离第一走线层35的一侧，这样可以减小电极信号引线23与第一走线层35之间的耦合电容，避免电极信号引线23与第一走线层35之间产生信号干扰。
如图3至图5所示，第三绝缘层38可以包括层叠设置的钝化层381和平坦层382，平坦层382设置在钝化层381背离衬底基板31的一侧。
由于有机材料的平坦层382可以制作较大的厚度，较大厚度的平坦层382可以进一步增大数据信号引线24与电极信号引线23之间的纵向距离，进一步降低数据信号引线24与电极信号引线23之间的耦合电容，减少相互之间的信号干扰。
在具体实现中，第一走线层35的材料可以包括金属材料和金属氧化物材料中的一种或多种。
第二走线层37的材料可以包括金属材料和金属氧化物材料中的一种或多种。
第三走线层39的材料可以包括金属材料和金属氧化物材料中的一种或多种。
其中，包括金属材料和金属氧化物材料中的一种或多种是指，包括金属材料，或者包括金属氧化物材料，或者包括金属材料和金属氧化物材料。
其中，金属材料包括铜、铝、镁、钼、金、银等；金属氧化物材料包括 氧化铟锡等。
由于电极信号引线23位于第三走线层39，并且金属材料的阻抗较小，因此可以降低电极信号引线23的电阻。
可选地，如图3所示，电极信号总线22可以位于第一走线层35。
为了实现电极信号引线23与电极信号总线22之间的连接，可选地，如图2至图4所示，第三走线层39还可以包括：与电极信号引线23靠近电极信号总线22一端连接的第一转接部A1，第一转接部A1与电极信号总线22通过设置在第三绝缘层38和第二绝缘层36上的第二过孔H2连接。
由于第二过孔H2位于边框区域，因此在衬底基板31所在的平面方向上，第二过孔H2的尺寸可以大于第一过孔H1的尺寸。由于第二过孔H2的尺寸较大，因此可以增大第一转接部A1与电极信号总线22的搭接面积，降低接触电阻，确保电极信号引线23与电极信号总线22之间的有效连接。
如图3或图4所示，第二过孔H2可以包括设置在第三绝缘层38上的第三过孔H3，以及设置在第二绝缘层36上的第四过孔H4。相应地，第二走线层37还可以包括位于边框区域的第二转接部A2，第二转接部A2与第一转接部A1通过第三过孔H3连接，第二转接部A2与电极信号总线22通过第四过孔H4连接。
通过在第一转接部A1与电极信号总线22之间设置第二转接部A2，使得第二转接部A2与位于其两侧的第一转接部A1和电极信号总线22分别通过过孔连接，即第二转接部A2与第一转接部A1通过第三过孔H3连接，第二转接部A2与电极信号总线22通过第四过孔H4连接，第三过孔H3与第四过孔H4的深度小于第二过孔H2的深度，这样可以降低制备过孔的工艺复杂度，增大第一转接部A1与电极信号总线22之间的有效接触面积，降低接触电阻。
为了实现电极信号引线23与第一电极走线21之间的连接，可选地，如图2、图3和图5所示，第三走线层39还可以包括：与电极信号引线23靠近第一电极走线21一端连接的第三转接部A3。
相应地，第一电极走线21靠近电极信号总线22的一端延伸至边框区域，且与第四转接部A4连接，第一电极走线21和第四转接部A4均位于第二走线层37。
其中，第三转接部A3与第四转接部A4可以通过设置在第三绝缘层38上 的第五过孔H5连接。
由于第五过孔H5位于边框区域，因此在衬底基板31所在的平面方向上，第五过孔H5的尺寸大于第一过孔H1的尺寸。由于第五过孔H5的尺寸较大，因此可以增大第三转接部A3与第四转接部A4的搭接面积，降低接触电阻，确保第一电极走线21与电极信号引线23之间的有效连接。
如图2所示，第三转接部A3和第四转接部A4可以在封装区域内靠近显示区域与边框区域的交界线设置。
本实现方式中，由于第一电极走线21位于第二走线层37，因此，第一过孔H1可以贯穿第一绝缘层33和第三绝缘层38，实现第一电极层34与第一电极走线21之间的过孔连接，这种情况下第一过孔H1为深孔。
或者，如图3所示，可以在第三走线层39设置第五转接部A5，使得第一电极层34与第五转接部A5通过第一过孔H1连接，第五转接部A5与第一电极走线21通过设置在第三绝缘层38上的第七过孔H7连接。这种方式中，可以降低制备过孔的工艺复杂度，增大第一电极层34与第一电极走线21之间的有效接触面积，降低接触电阻。
在图3中，在显示区域，在第一绝缘层33与第一电极层34之间还可以设置有发光层材料，为了实现第一电极层34与第一电极走线21之间的连接，可以首先在第五转接部A5的侧面形成凹槽，然后采用溅射工艺形成第一电极层34，使得第一电极层34形成在第五转接部A5的侧面凹槽内，从而实现第一电极层34与第一电极走线21之间的搭接。
为了在第五转接部A5的侧面形成凹槽，可选地，如图5所示，第三走线层39包括第一导电层391和第二导电层392，第二导电层392位于第一导电层391背离衬底基板31的一侧。其中，第一导电层391的材料可以包括氧化铟锡等金属氧化物，第二导电层392的材料包括氧化铟锡等金属氧化物和金属。
如图3和图4所示，为了实现第一电极层34与电极信号总线22通过设置在第一绝缘层33上的第六过孔H6连接，可选地，第一电极层34与第一转接部A1通过设置在第一绝缘层33上的第六过孔H6连接，第一转接部A1与第二转接部A2通过设置在第三绝缘层38上的第三过孔H3连接，第二转接部A2与电极信号总线22通过设置在第二绝缘层36上的第四过孔H4连接。
在具体实现中，功能层32可以包括位于显示区域的多个薄膜晶体管。薄膜晶体管用于在外部信号的控制下，驱动发光基板中的发光器件发光。
可选地，功能层32包括位于显示区域的第一薄膜晶体管(图中未示出)，数据走线25以及第一薄膜晶体管的源极和漏极均位于第二走线层37，数据走线25与第一薄膜晶体管的源极或漏极连接。
如图2所示，数据信号引线24、数据走线25、第一电极走线21以及第一薄膜晶体管的源极和漏极均位于同一膜层，即第二走线层37。
由于数据走线25与第一电极走线21位于同一膜层内，为了确保数据走线25与第一电极走线21不会发生短路，数据走线25的延伸方向与第一电极走线21的延伸方向可以相同，即数据走线25的延伸方向与第一电极走线21的延伸方向相互平行。
当然，数据走线25的延伸方向与第一电极走线21的延伸方向也可以不相同，只要确保数据走线25与第一电极走线21不相交即可。
可选地，功能层32包括位于显示区域的第二薄膜晶体管(图中未示出)，第一走线层35还可以包括位于显示区域的栅极走线26，以及第二薄膜晶体管的栅极，栅极走线26与第二薄膜晶体管的栅极连接。
如图2所示，电极信号总线22、栅极走线26以及第二薄膜晶体管的栅极均位于同一膜层，即第一走线层35。
可选地，如图2示，功能层32包括位于显示区域的第三薄膜晶体管(图中未示出)，第三走线层39还可以包括位于显示区域内的多个第二电极27，第二电极27与第三薄膜晶体管连接。
在具体实现中，第三薄膜晶体管的源极和漏极可以位于第二走线层37，第二电极27位于第三走线层39，第二电极27与第三薄膜晶体管的源极或漏极可以通过设置在第三绝缘层38上的过孔连接。
示例性地，第一电极层34为阴极层，第二电极27可以为阳极，本公开对此不作限定。也可以第一电极层34为阳极层，第二电极27可以为阴极。
如图2所示，第二电极27与电极信号引线23均位于同一膜层，即第三走线层39。
其中，第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管可以互不相同，或者其中的两个为同一个薄膜晶体管，或者三个为同一个薄膜晶体管， 本公开对此不作限定。
当第三走线层39包括第一导电层391和第二导电层392，第二导电层392位于第一导电层391背离衬底基板31的一侧，且第二导电层392的材料包括金属氧化物和金属时，金属可以位于第二导电层392背离衬底基板31的一侧表面，这样可以提高入射至该金属表面的光线的反射率，提高第二电极的反射率，提高顶发射发光器件的出光效率。
如图6所示，第一绝缘层33可以复用为像素界定层，像素界定层具有多个像素开口，像素开口在衬底基板31上的正投影位于第二电极27在衬底基板31上的正投影范围内。
可选地，发光基板还可以包括：至少设置在像素开口内的发光层61，第一电极层34设置在发光层61背离衬底基板31的一侧。
如图6所示，位于一个像素开口内的第二电极27、发光层61以及第一电极层34构成一个发光器件。发光层61可以包括白光发光层、红色发光层、绿色发光层和蓝色发光层等颜色发光层中的一种或多种。
需要说明的是，在第一走线层35内，电极信号总线22与栅极走线之间相互绝缘。在第二走线层37内，位于边框区域的第二转接部A2、数据信号引线24以及第四转接部A4之间均相互绝缘，位于显示区域的第一电极走线21和数据走线25之间相互绝缘。在第三走线层39内，第二电极27与电极信号引线23相互绝缘。
在另一种可选的实现方式中，如图7和图8所示，数据信号引线24和电极信号引线23分别在衬底基板31上的正投影无交叠，数据信号引线24和电极信号引线23同层设置。
可选地，数据信号引线24与电极信号总线22可以分别位于显示区域的不同侧。
示例性地，如图7所示，数据信号引线24位于显示区域的下侧，电极信号总线22位于显示区域的上侧、左侧和右侧，即数据信号引线24位于下边框区域，电极信号总线22位于上边框区域、左边框区域和右边框区域。
本示例中，由于电极信号总线22位于显示区域的上侧、左侧和右侧，电极信号总线22形成半封闭结构，从而可以屏蔽外部信号的干扰，提高显示画面的稳定性。
示例性地，数据信号引线24与电极信号总线22还可以分别位于显示区域相对的两侧，例如，数据信号引线24位于显示区域的下侧，电极信号总线22位于显示区域的上侧。
如图7所示，数据信号引线24和电极信号总线22分别在衬底基板31上的正投影无交叠，数据信号引线24和电极信号总线22可以位于相同或不同的膜层，本公开对此不作限定。
本公开提供了一种发光装置，包括任一项提供的发光基板。
由于该发光装置包括上述的发光基板，本领域技术人员可以理解，该发光装置具有本公开提供的发光基板的优点，这里不再赘述。
需要说明的是，本实施例中的发光装置可以为：显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、虚拟现实设备、增强现实设备、屏下摄像头设备以及导航仪等任何具有2D或3D显示功能的产品或部件。
在具体实现中，如图2或图7所示，发光基板中的数据信号引线24以及连接电极信号总线22的引线可以延伸至绑定区，透明电极信号输入端位于绑定区。绑定区用于绑定柔性电路板，通过柔性电路板可以连接驱动芯片。驱动芯片可以提供数据信号以及透明电极信号等。
发明人发现，当发光基板的尺寸较大时，第一电极层34上的压降更加明显，当本公开提供的发光基板应用于电视或显示器等大尺寸发光装置时，可以更加显著地改善显示不均的现象。
本公开提供了一种发光基板的制备方法，该发光基板包括显示区域以及位于显示区域一侧的边框区域，制备方法包括：
步骤S01：提供衬底基板。
步骤S02：在衬底基板的一侧形成功能层，功能层包括：位于显示区域的第一电极走线，位于边框区域的电极信号总线，以及连接第一电极走线和电极信号总线的电极信号引线。
步骤S03：在功能层背离衬底基板的一侧依次形成第一绝缘层和第一电极层，第一绝缘层位于功能层与第一电极层之间，第一电极层与第一电极走 线通过设置在第一绝缘层上的第一过孔连接。
采用本公开提供的制备方法可以制备得到上述任一项提供的发光基板。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的一种发光基板及其制备方法、发光装置进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全 指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (17)

  1. 一种发光基板，包括显示区域以及位于所述显示区域一侧的边框区域，所述发光基板包括：衬底基板，设置在所述衬底基板一侧的功能层，以及层叠设置在所述功能层背离所述衬底基板一侧的第一绝缘层和第一电极层，所述第一绝缘层位于所述功能层与所述第一电极层之间；
    其中，所述功能层包括：位于所述显示区域的第一电极走线，位于所述边框区域的电极信号总线，以及连接所述第一电极走线和所述电极信号总线的电极信号引线；所述第一电极层与所述第一电极走线通过设置在所述第一绝缘层上的第一过孔连接。
  2. 根据权利要求1所述的发光基板，其中，所述功能层还包括：位于所述边框区域的数据信号引线，以及位于所述显示区域的数据走线，所述数据信号引线与所述数据走线连接；
    其中，所述数据信号引线和所述电极信号引线分别在所述衬底基板上的正投影有交叠，所述数据信号引线和所述电极信号引线分别位于不同的膜层。
  3. 根据权利要求2所述的发光基板，其中，所述功能层包括依次层叠设置的第一走线层、第二绝缘层、第二走线层、第三绝缘层和第三走线层，所述第一绝缘层设置在所述第三走线层背离所述衬底基板的一侧；
    其中，所述数据信号引线位于所述第二走线层，所述电极信号引线位于所述第三走线层。
  4. 根据权利要求3所述的发光基板，其中，所述电极信号总线位于所述第一走线层，所述第三走线层还包括：与所述电极信号引线靠近所述电极信号总线一端连接的第一转接部，所述第一转接部与所述电极信号总线通过设置在所述第三绝缘层和所述第二绝缘层上的第二过孔连接。
  5. 根据权利要求4所述的发光基板，其中，所述第二过孔包括设置在所述第三绝缘层上的第三过孔，以及设置在所述第二绝缘层上的第四过孔；
    所述第二走线层还包括位于所述边框区域的第二转接部，所述第二转接部与所述第一转接部通过所述第三过孔连接，所述第二转接部与所述电极信号总线通过所述第四过孔连接。
  6. 根据权利要求3所述的发光基板，其中，所述第三走线层还包括：与 所述电极信号引线靠近所述第一电极走线一端连接的第三转接部；
    所述第一电极走线靠近所述电极信号总线的一端延伸至所述边框区域，且与第四转接部连接，所述第一电极走线和所述第四转接部均位于所述第二走线层；
    其中，所述第三转接部与所述第四转接部通过设置在所述第三绝缘层上的第五过孔连接。
  7. 根据权利要求3所述的发光基板，其中，所述功能层包括位于显示区域的第一薄膜晶体管，所述数据走线以及所述第一薄膜晶体管的源极和漏极均位于所述第二走线层，所述数据走线与所述第一薄膜晶体管的源极或漏极连接；
    其中，所述数据走线的延伸方向与所述第一电极走线的延伸方向相同。
  8. 根据权利要求3所述的发光基板，其中，所述功能层包括位于显示区域的第二薄膜晶体管，所述第一走线层还包括位于所述显示区域的栅极走线，以及所述第二薄膜晶体管的栅极，所述栅极走线与所述第二薄膜晶体管的栅极连接。
  9. 根据权利要求3所述的发光基板，其中，所述功能层包括位于显示区域的第三薄膜晶体管，所述第三走线层还包括位于显示区域内的多个第二电极，所述第二电极与所述第三薄膜晶体管连接。
  10. 根据权利要求9所述的发光基板，其中，所述第一绝缘层复用为像素界定层，所述像素界定层具有多个像素开口，所述像素开口在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影范围内；
    所述发光基板还包括：设置在所述像素开口内的发光层，所述第一电极层设置在所述发光层背离所述衬底基板的一侧。
  11. 根据权利要求2至10任一项所述的发光基板，其中，所述数据信号引线与所述电极信号总线位于所述显示区域的同一侧。
  12. 根据权利要求2至11任一项所述的发光基板，其中，所述第一电极走线的延伸方向与所述电极信号总线的延伸方向不同；或者，所述第一电极走线的延伸方向与所述电极信号总线的延伸方向相互垂直。
  13. 根据权利要求1所述的发光基板，其中，所述功能层还包括：位于所述边框区域的数据信号引线，以及位于所述显示区域的数据走线，所述数 据信号引线与所述数据走线连接；
    其中，所述数据信号引线和所述电极信号引线分别在所述衬底基板上的正投影无交叠，所述数据信号引线和所述电极信号引线同层设置。
  14. 根据权利要求13所述的发光基板，其中，所述数据信号引线与所述电极信号总线分别位于所述显示区域的不同侧。
  15. 根据权利要求1至14任一项所述的发光基板，其中，所述第一电极层与所述电极信号总线通过设置在所述第一绝缘层上的第六过孔连接。
  16. 一种发光装置，包括权利要求1至15任一项所述的发光基板。
  17. 一种发光基板的制备方法，所述发光基板包括显示区域以及位于所述显示区域一侧的边框区域，所述制备方法包括：
    提供衬底基板；
    在所述衬底基板的一侧形成功能层，所述功能层包括：位于所述显示区域的第一电极走线，位于所述边框区域的电极信号总线，以及连接所述第一电极走线和所述电极信号总线的电极信号引线；
    在所述功能层背离所述衬底基板的一侧依次形成第一绝缘层和第一电极层，所述第一绝缘层位于所述功能层与所述第一电极层之间，所述第一电极层与所述第一电极走线通过设置在所述第一绝缘层上的第一过孔连接。
PCT/CN2022/096384 2022-05-31 2022-05-31 发光基板及其制备方法、发光装置 WO2023230888A1 (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700675A (zh) * 2013-12-31 2014-04-02 京东方科技集团股份有限公司 Amoled阵列基板及显示装置
CN107342370A (zh) * 2017-07-06 2017-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN109713012A (zh) * 2018-12-27 2019-05-03 厦门天马微电子有限公司 一种显示面板和显示装置
CN110751922A (zh) * 2019-10-31 2020-02-04 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN111584610A (zh) * 2020-06-10 2020-08-25 京东方科技集团股份有限公司 一种显示面板及显示装置
CN113284921A (zh) * 2020-02-19 2021-08-20 合肥鑫晟光电科技有限公司 阵列基板及显示装置
WO2021248489A1 (zh) * 2020-06-12 2021-12-16 京东方科技集团股份有限公司 显示基板及显示装置
CN114335114A (zh) * 2019-11-15 2022-04-12 京东方科技集团股份有限公司 阵列基板及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700675A (zh) * 2013-12-31 2014-04-02 京东方科技集团股份有限公司 Amoled阵列基板及显示装置
CN107342370A (zh) * 2017-07-06 2017-11-10 武汉天马微电子有限公司 显示面板及显示装置
CN109713012A (zh) * 2018-12-27 2019-05-03 厦门天马微电子有限公司 一种显示面板和显示装置
CN110751922A (zh) * 2019-10-31 2020-02-04 上海天马有机发光显示技术有限公司 显示面板及显示装置
CN114335114A (zh) * 2019-11-15 2022-04-12 京东方科技集团股份有限公司 阵列基板及显示装置
CN113284921A (zh) * 2020-02-19 2021-08-20 合肥鑫晟光电科技有限公司 阵列基板及显示装置
CN111584610A (zh) * 2020-06-10 2020-08-25 京东方科技集团股份有限公司 一种显示面板及显示装置
WO2021248489A1 (zh) * 2020-06-12 2021-12-16 京东方科技集团股份有限公司 显示基板及显示装置

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